Array substrate and display panel
By setting up pixel circuits in the array substrate of the OLED display panel and using overlapping via design, the problem of tight layout space under high pixel density is solved, and higher pixel density and better usage performance is achieved.
CN119677328APending Publication Date: 2025-03-21HEFEI VISIONOX TECH CO LTD
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Patent Information
- Application Number
- CN202510126308.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-24
- Publication Date
- 2025-03-21
AI Technical Summary
Technical Problem
There is room for improvement in the performance of existing OLED display panels, especially under high pixel density, layout space design leads to high production difficulty, increased cost or decreased product yield.
Method used
By providing a pixel circuit in the array substrate, including a storage capacitor and a compensation transistor, and partially overlapping with the first capacitor plate with the first via hole, the space occupied by the pixel circuit is reduced, thereby improving pixel density and usage performance.
Benefits of technology
It is achieved to increase the pixel density of the display panel without increasing the process, reduce the preparation cost, and ensure that the width and spacing of the traces meet the needs.
✦ Generated by Eureka AI based on patent content.
Abstract
The invention discloses an array substrate and a display panel. A pixel circuit is arranged in the array substrate, and the pixel circuit comprises a storage capacitor and a compensation transistor; the storage capacitor comprises a first capacitor plate; the array substrate comprises a substrate, a first conductive layer, a first active layer and a first connecting line, the first conductive layer is located on one side of the substrate; the first capacitor plate is located on the first conductive layer. The first active layer is located on the side, away from the substrate, of the first conductive layer and comprises a first active part of the compensation transistor; the first connecting line is located on the side, away from the substrate, of the first active layer; the first active part is connected with a first connecting line through a first via hole, and the first connecting line is connected with a first capacitor plate; the orthographic projection of the first via hole on the substrate is at least partially overlapped with the orthographic projection of the first capacitor plate on the substrate. According to the technical scheme, the use performance of the display panel is improved.
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