Solar cell, photovoltaic module and semiconductor substrate

Abstract

The present invention discloses a solar cell, a photovoltaic module, and a semiconductor substrate, which relate to the field of photovoltaic technology. The invention aims to enable a passivation layer to have a good passivation effect on the semiconductor substrate; at the same time, the contact performance between the doped semiconductor layer and the electrode, as well as the shaping of the electrode, are improved, thereby increasing the conversion efficiency of the solar cell. The solar cell comprises a semiconductor substrate and a passivation layer. The semiconductor substrate has a first surface and a second surface relative to each other. At least one of the first surface and the second surface is a target surface. The passivation layer is arranged on the target surface. The side of the passivation layer facing away from the semiconductor substrate has a plurality of tower-like texture structures recessed into the passivation layer. A single tower-like texture structure is surrounded by a polygon-like bottom surface and side surfaces. In the same tower-like texture structure, at least one corner of the polygon-like bottom surface has a plurality of raised portions that rise along the extension direction of the side ridgeline, and the plurality of raised portions on the same corner have an undulating morphology extending in a direction parallel to the polygon-like bottom surface.

Description

Technical Field

[0001] The present invention relates to the field of photovoltaic technology, and in particular to a solar cell, a photovoltaic module and a semiconductor substrate. Background Art

[0002] As a green energy source, solar cells play a positive role in energy conservation and emission reduction. With the development of the photovoltaic industry, solar cell technology has become increasingly mature. Photovoltaic solar cells are devices that convert sunlight into electrical energy. Specifically, solar cells utilize the photovoltaic principle to generate charge carriers and then use electrodes to extract these charge carriers, thereby facilitating the efficient use of electrical energy. As an environmentally friendly and renewable energy source, solar energy has garnered increasing attention in recent years. Consequently, the application range of photovoltaic solar cells, which are based on the photoelectric effect, has also expanded.

[0003] However, existing solar cells have difficulty in achieving both good passivation effects and good electrode contact performance and shaping, which is not conducive to improving the conversion efficiency of solar cells. Summary of the Invention

[0004] The object of the present invention is to provide a solar cell, a photovoltaic module and a semiconductor substrate, which are used to ensure that the passivation layer has a good passivation effect on the semiconductor substrate, while increasing the surface roughness of the passivation layer on the side away from the semiconductor substrate by providing a raised portion on at least one corner of the polygonal bottom surface, thereby increasing the specific surface area of ​​the doped semiconductor layer in the passivation layer or formed on the side of the passivation layer close to the semiconductor substrate, improving the contact performance between the doped semiconductor layer and the electrode, and the shaping of the electrode, thereby improving the conversion efficiency of the solar cell.

[0005] In order to achieve the above-mentioned objectives, in a first aspect, the present invention provides a solar cell, which comprises: a semiconductor substrate and a passivation layer. The semiconductor substrate has a first surface and a second surface relative to each other. At least one of the first surface and the second surface is a target surface. The passivation layer is arranged on the target surface. The side of the passivation layer facing away from the semiconductor substrate has a plurality of tower-like texture structures recessed into the passivation layer. A single tower-like texture structure is surrounded by a polygon-like bottom surface and side surfaces. In the same tower-like texture structure, at least one corner of the polygon-like bottom surface has a plurality of raised portions climbing along the extension direction of the side ridge line, and the plurality of raised portions on the same corner have an undulating morphology extending in a direction parallel to the polygon-like bottom surface.

[0006] When the above technical solution is adopted, the passivation layer is arranged on the target surface of the semiconductor substrate, which can passivate the target surface side of the semiconductor substrate and reduce the carrier recombination rate. In addition, the side of the passivation layer facing away from the semiconductor substrate has multiple tower-like texture structures that are recessed into the passivation layer. Under the same conditions, compared with texture structures with a large degree of undulation, such as pyramid-shaped velvet structures, the tower-like texture structures without tower spires have a relatively small degree of undulation, making the surface of the side of the passivation layer facing away from the semiconductor substrate relatively flat from a macroscopic perspective. In addition, in the actual manufacturing process, the passivation layer is formed on the target surface of the semiconductor substrate through processes such as deposition. The surface undulation of the passivation layer on the side facing away from the semiconductor substrate will also be affected by the surface undulation of the target surface. Accordingly, the surface undulation of the passivation layer on the side facing away from the semiconductor substrate can also reflect the surface undulation of the target surface of the semiconductor substrate to a certain extent. Based on this, when the surface of the passivation layer facing away from the semiconductor substrate is relatively flat on a macroscopic scale, the target surface of the semiconductor substrate is also roughly a relatively flat surface, which is conducive to improving the formation quality and film thickness of the passivation layer on the target surface, and then conducive to improving the passivation effect of the passivation layer on the semiconductor substrate and improving the conversion efficiency of the solar cell.

[0007] In addition, in the tower-like texture structure formed on the side of the passivation layer facing away from the semiconductor substrate, at least one corner of the polygonal bottom surface has a plurality of raised portions climbing along the extension direction of the side ridge line, and the plurality of raised portions on the same corner have an undulating morphology extending in a direction parallel to the polygonal bottom surface. At this time, compared with the conventional tower-like texture structure with flat sides, the side of the tower-like texture structure in the present invention has the above-mentioned raised portions, so that the surface of the passivation layer facing away from the semiconductor substrate has a relatively larger surface roughness at the microscopic level than the conventional polished surface, which is beneficial to increase the doped semiconductor layer included in the passivation layer, or the doped semiconductor layer formed between the passivation layer and the semiconductor substrate has a larger specific surface area, thereby increasing the contact area between the doped semiconductor layer and the electrode, improving the contact performance between the doped semiconductor layer and the electrode, and the adhesion and shaping of the electrode on the doped semiconductor layer, which is beneficial to improving the conversion efficiency of solar cells.

[0008] As a possible implementation, the plurality of tower-base-like texture structures include a first-type tower-base-like texture structure and a second-type tower-base-like texture structure. The first-type tower-base-like texture structure is recessed deeper into the passivation layer than the second-type tower-base-like texture structure. The first-type tower-base-like texture structure has a greater number of raised portions than the second-type tower-base-like texture structure.

[0009] When adopting the above technical solution, the multiple tower-like texture structures also include a first-type tower-like texture structure with a larger concave depth and a larger number of protrusions, which can further increase the surface roughness of the passivation layer on the side away from the semiconductor substrate, further improve the contact performance between the above-mentioned doped semiconductor layer and the electrode, as well as the adhesion and shaping of the electrode on the doped semiconductor layer, improve the structural stability of the solar cell, and reduce the transmission loss between the doped semiconductor layer and the electrode.

[0010] As a possible implementation, in at least one of the tower-base-like texture structures, at least one pair of corners of the polygonal bottom surface each has a plurality of protrusions, and the at least one pair of corners is two corners of the polygonal bottom surface that are diagonally distributed.

[0011] When the above technical solution is adopted, in at least one tower-base-like texture structure, compared with having only one protrusion on a polygon-like bottom surface, when at least one pair of corners of the polygon-like bottom surface have multiple protrusions, at least one of the same tower-base-like texture structures is provided with a greater number of protrusions, which is beneficial to further increase the degree of undulation of the passivation layer away from the semiconductor substrate side, and at the same time, it is beneficial to make different protrusions distributed along the diagonal direction on different diagonals of the polygon-like bottom surface, rather than concentrated on a single corner, and further beneficial to make different areas along the diagonal direction in the same tower-base-like texture structure have higher surface roughness, which is beneficial to make different areas of the doped semiconductor layer and the electrode have good contact performance, and the electrode has strong adhesion and good shaping on different areas of the doped semiconductor layer.

[0012] As a possible implementation solution, the plurality of raised portions on the same corner have a broken line undulating shape or a wavy line undulating shape extending along the direction of the polygonal bottom surface.

[0013] When the above technical solution is adopted, compared with single convex or concave undulating morphologies such as arcs, the broken line undulating morphologies and the wavy line undulating morphologies both have continuous undulating morphologies of convex, concave, convex, concave..., which can further increase the surface roughness of the tower base-like texture structure, which is beneficial to increase the contact area between the above-mentioned doped semiconductor layer and the electrode, improve the contact performance between the doped semiconductor layer and the electrode, and the adhesion and shaping of the electrode on the doped semiconductor layer.

[0014] As a possible implementation, at least one raised portion may be shaped like a triangular prism, a cone, or a cylinder. In this case, the raised portion has a variety of morphologies, which helps improve the applicability of the solar cell provided by the present invention in different application scenarios. Furthermore, the difficulty of manufacturing a tower-like texture structure can be reduced.

[0015] As a possible implementation solution, the protrusion on at least one corner is in a triangular prism-like shape, and the ridgeline of the protrusion is in an arc shape that is concave toward the direction approaching the semiconductor substrate.

[0016] When the above technical solution is adopted, when the raised portion on at least one corner is in the shape of a triangular prism, compared with the ridge line of the raised portion being parallel to the side ridge line, when the ridge line of the raised portion is in the shape of an arc that is concave toward the direction close to the semiconductor substrate, the part of the raised portion corresponding to the concave arc ridge line also has a concave undulating morphology, which can further increase the surface roughness of the tower base-like texture structure in the area where the raised portion is provided, which is conducive to further increasing the specific surface area of ​​the above-mentioned doped semiconductor layer, and then increasing the contact area between the doped semiconductor layer and the electrode, improving the contact performance between the doped semiconductor layer and the electrode, and the adhesion and shaping of the electrode on the doped semiconductor layer, thereby improving the conversion efficiency of the solar cell.

[0017] As a possible implementation, the height of a single protrusion is greater than its width. The height direction of the protrusion is parallel to the thickness direction of the semiconductor substrate, and the width direction of the protrusion is parallel to the extension direction of the polygonal bottom surface of the tower-like texture structure.

[0018] When the above technical solution is adopted, compared with the "short and fat" protrusion whose height is smaller than its width, when the height of a single protrusion is greater than the width of the protrusion, the "tall and thin" single protrusion has a greater degree of undulation, and is conducive to forming a larger number of protrusions per unit area, further increasing the surface roughness of the passivation layer away from the semiconductor substrate side, and is conducive to increasing the contact area between the above-mentioned doped semiconductor layer and the electrode, further improving the contact performance between the doped semiconductor layer and the electrode, as well as the adhesion and shaping of the electrode on the doped semiconductor layer, thereby improving the conversion efficiency of the solar cell.

[0019] As a possible implementation solution, the height of a single protrusion is greater than or equal to 0.2 μm and less than or equal to 0.8 μm.

[0020] When the above technical solution is adopted, the height of the raised portion is within the above range, which helps prevent the surface roughness of the passivation layer on the side facing away from the semiconductor substrate from being smaller due to the smaller height of the raised portion, ensuring that the contact area between the doped semiconductor layer and the electrode can be increased by the raised portion, improving the contact performance between the doped semiconductor layer and the electrode, as well as the adhesion and shaping of the electrode on the doped semiconductor layer, thereby improving the conversion efficiency of the solar cell. In addition, it also helps prevent the surface roughness of the passivation layer on the side facing away from the semiconductor substrate from being larger due to the height of the raised portion being too large, ensuring that the target surface of the semiconductor substrate is relatively flat, and helping to improve the formation quality of the passivation layer on the target surface, improving the passivation effect of the passivation layer, and helping to achieve a balance between the passivation effect of the passivation layer, the contact performance between the doped semiconductor layer and the electrode, and the adhesion and shaping of the electrode, thereby ensuring that the solar cell has high operating performance and structural reliability.

[0021] As a possible implementation, the width of a single protrusion is greater than or equal to 0.1 μm and less than or equal to 0.8 μm. The application principle of the beneficial effect in this case is similar to the application principle of the beneficial effect of the height of a single protrusion being greater than or equal to 0.2 μm and less than or equal to 0.8 μm described above, and will not be repeated here.

[0022] As a possible implementation scheme, in at least one tower-base-like texture structure, at least one corner of the polygonal bottom surface has at least two groups of protrusions distributed in a stepped manner along the extension direction of the side ridges, and each group of protrusions includes multiple protrusions extending along the direction of the polygonal bottom surface.

[0023] When the above technical solution is adopted, at least two groups of raised portions distributed in a stepped manner can further increase the degree of undulation of the side surface of the tower-like texture structure along the direction of extension of the ridge line, further increase the surface roughness of the passivation layer on the side away from the semiconductor substrate, which is beneficial to increase the contact area between the above-mentioned doped semiconductor layer and the electrode, further improve the contact performance between the doped semiconductor layer and the electrode, as well as the adhesion and shaping of the electrode on the doped semiconductor layer, and improve the conversion efficiency of the solar cell.

[0024] As one possible implementation, the passivation layer further comprises a linear texture on the side facing away from the semiconductor substrate, with at least one side of the linear texture having multiple raised portions intersecting the direction in which the linear texture extends. In this case, the presence of the linear texture can further increase the surface roughness of the passivation layer on the side facing away from the semiconductor substrate, thereby increasing the contact area between the doped semiconductor layer and the electrode, further improving the contact performance between the doped semiconductor layer and the electrode, as well as the adhesion and shaping of the electrode on the doped semiconductor layer, thereby increasing the conversion efficiency of the solar cell.

[0025] As a possible implementation scheme, one of the first and second surfaces is the target surface. The passivation layer includes a first doped semiconductor portion and a second doped semiconductor portion of opposite conductivity types. At least a portion of the first doped semiconductor portion and at least a portion of the second doped semiconductor portion are spaced apart. The surface of the passivation layer corresponding to the first doped semiconductor portion on the side facing away from the semiconductor substrate is the first sub-surface, and the surface of the passivation layer corresponding to the second doped semiconductor portion on the side facing away from the semiconductor substrate is the second sub-surface. The number of protrusions on the first sub-surface is different from the number of protrusions on the second sub-surface; and / or the height of the protrusions on the first sub-surface is different from the height of the protrusions on the second sub-surface.

[0026] When adopting the above-mentioned technical solution, the number and height of the protrusions on the first sub-surface and the second sub-surface can be set respectively according to the requirements for different passivation effects of the first doped semiconductor part and the second doped semiconductor part in the actual application scenario, and the requirements for the contact performance between the two and the corresponding electrodes, so that the two parts of the passivation layer corresponding to the first doped semiconductor part and the second doped semiconductor part respectively have different passivation effects on the semiconductor substrate, and are conducive to making the first doped semiconductor part and the second doped semiconductor part have different surface morphologies, thereby helping to reduce the passivation difference between the two parts of the passivation layer corresponding to the first doped semiconductor part and the second doped semiconductor part respectively, and helping to reduce the difference in contact performance between the first doped semiconductor part and the second doped semiconductor part and the corresponding electrodes respectively.

[0027] As a possible implementation, the first doped semiconductor portion is a P-type doped semiconductor portion, and the second doped semiconductor portion is an N-type doped semiconductor portion. The raised portions are distributed only on the first sub-surface; the second sub-surface has a pyramid-like texture structure without raised portions.

[0028] When the above technical solution is adopted, due to the limitations of the doping solid concentration and the doping concentration, the dopant concentration of the dopant in the N-type doped semiconductor part is greater than the doping concentration of the dopant in the P-type doped semiconductor part, and the passivation characteristics and contact characteristics of the P-type doped semiconductor part with the positive electrode are relatively worse. Based on this, when the protrusions are distributed only on the first sub-surface, and the second sub-surface has a tower base-like texture structure without protrusions, it is beneficial to make the first sub-surface rougher than the second sub-surface, which is beneficial to increase the contact area between the P-type doped semiconductor part and the positive electrode, and reduce the difference in contact performance between the N-type doped semiconductor part and the P-type doped semiconductor part in the battery and the corresponding electrodes.

[0029] As a possible implementation solution, the target surface has a plurality of tower-like texture structures recessed into the semiconductor substrate, and the protrusions in the tower-like texture structures on the target surface are in a triangular prism-like shape.

[0030] When the above technical solution is adopted, compared with a texture structure with a large undulating morphology such as a pyramid-shaped velvet structure, when the target surface has multiple tower-like texture structures that are recessed into the semiconductor substrate, the target surface of the semiconductor substrate is relatively flat, which is beneficial to improving the formation quality and film thickness of the passivation layer formed on the target surface, and improving the passivation effect of the passivation layer. Secondly, when the tower-like texture structure on the target surface has a raised portion, and the raised portion is in the shape of a triangular prism, the presence of the triangular prism-like raised portion can increase the surface roughness of the target surface, which is beneficial for the doped semiconductor layer formed on the target surface by deposition and other processes to also have a relatively large specific surface area, thereby increasing the contact area between the doped semiconductor layer and the electrode, improving the contact performance between the doped semiconductor layer and the electrode, and the adhesion and shaping of the electrode on the doped semiconductor layer.

[0031] In a second aspect, the present invention provides a photovoltaic module, which includes the solar cell provided by the first aspect and various implementations thereof.

[0032] The beneficial effects of the second aspect of the present invention and its various implementations can be analyzed with reference to the beneficial effects of the first aspect and its various implementations, and will not be repeated here.

[0033] In a third aspect, the present invention provides a semiconductor substrate having a first surface and a second surface relative to each other. At least one of the first surface and the second surface is a target surface. The target surface has a plurality of tower-like texture structures that are recessed into the semiconductor substrate. A single tower-like texture structure is surrounded by a polygon-like bottom surface and side surfaces. In the same tower-like texture structure, at least one corner of the polygon-like bottom surface has a plurality of raised portions that rise along the extension direction of the side ridge line, and the plurality of raised portions on the same corner have an undulating morphology extending in a direction parallel to the polygon-like bottom surface. The beneficial effects in this case can be referred to above and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0035] Figure 1 This is a SEM image of a local surface of a passivation layer facing away from a semiconductor substrate in the related art;

[0036] Figure 2 A schematic longitudinal cross-sectional view of a first structure of a solar cell provided by an embodiment of the present invention;

[0037] Figure 3A schematic longitudinal cross-sectional view of a second structure of a solar cell provided by an embodiment of the present invention;

[0038] Figure 4 A schematic longitudinal cross-sectional view of a third structure of a solar cell provided by an embodiment of the present invention;

[0039] Figure 5 This is a SEM image of a local surface of the passivation layer facing away from the semiconductor substrate in an embodiment of the present invention. Figure 1 ;

[0040] Figure 6 This is a SEM image of a local surface of the passivation layer facing away from the semiconductor substrate in an embodiment of the present invention. Figure 2 ;

[0041] Figure 7 SEM image of the local surface of the target surface in the embodiment of the present invention Figure 1 ;

[0042] Figure 8 A schematic longitudinal cross-sectional view of a fourth structure of a solar cell provided by an embodiment of the present invention;

[0043] Figure 9 A schematic longitudinal cross-sectional view of a fifth structure of a solar cell provided by an embodiment of the present invention;

[0044] Figure 10 A schematic longitudinal cross-sectional view of a sixth structure of a solar cell provided by an embodiment of the present invention;

[0045] Figure 11 This is a SEM image of a local surface of the passivation layer facing away from the semiconductor substrate in an embodiment of the present invention. Figure 3 ;

[0046] Figure 12 This is a SEM image of a local surface of the passivation layer facing away from the semiconductor substrate in an embodiment of the present invention. Figure 4 ;

[0047] Figure 13 This is a SEM image of a local surface of the passivation layer facing away from the semiconductor substrate in an embodiment of the present invention. Figure 5 ;

[0048] Figure 14 A schematic longitudinal cross-sectional view of a seventh structure of a solar cell provided by an embodiment of the present invention;

[0049] Figure 15 SEM image of the local surface of the target surface in the embodiment of the present invention Figure 2 .

[0050] Figure numerals: 11 is a semiconductor substrate, 12 is a first surface, 13 is a second surface, 14 is a passivation layer, 15 is a tower-like texture structure, 16 is a raised portion, 17 is a linear texture structure, 18 is a first doped semiconductor portion, 19 is a second doped semiconductor portion, 20 is a doped semiconductor layer, 21 is an interface passivation layer, and 22 is a surface passivation layer. DETAILED DESCRIPTION

[0051] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely exemplary and are not intended to limit the scope of the present invention. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessary confusion of the concepts of the present invention.

[0052] The accompanying drawings illustrate various structural schematics according to embodiments of the present invention. These figures are not drawn to scale; certain details are exaggerated and may be omitted for clarity. The shapes of the various regions and layers shown in the figures, as well as their relative sizes and positions, are merely exemplary and may deviate in practice due to manufacturing tolerances or technical limitations. Those skilled in the art may design regions / layers with different shapes, sizes, and relative positions as needed.

[0053] In the context of the present invention, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element, or an intervening layer / element may exist between them. Furthermore, if a layer / element is "on" another layer / element in one orientation, it may be "below" the other layer / element when the orientation is reversed. To further clarify the technical problems, technical solutions, and beneficial effects of the present invention, the present invention is further described below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are intended solely to illustrate the present invention and are not intended to limit the present invention.

[0054] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Thus, a feature specified as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, "plurality" means two or more, unless otherwise specifically defined. "Several" means one or more, unless otherwise specifically defined.

[0055] In the description of the present invention, it should be noted that, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood in a broad sense. For example, they may refer to fixed, detachable, or integral connections; mechanical or electrical connections; direct or indirect connections through an intermediate medium; and may encompass internal communication between two components or interaction between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on specific circumstances.

[0056] As a green energy source, solar cells play a positive role in energy conservation and emission reduction. With the development of the photovoltaic industry, solar cell technology has become increasingly mature. Photovoltaic solar cells are devices that convert sunlight into electrical energy. Specifically, solar cells utilize the photovoltaic principle to generate charge carriers and then use electrodes to extract these charge carriers, thereby facilitating the efficient use of electrical energy. As an environmentally friendly and renewable energy source, solar energy has garnered increasing attention in recent years. Consequently, the application range of photovoltaic solar cells, which are based on the photoelectric effect, has also expanded.

[0057] Specifically, existing solar cells generally include a semiconductor substrate and a passivation layer formed on the semiconductor substrate. The passivation layer may include a doped semiconductor layer with a field passivation effect, or an interface passivation layer and / or a surface passivation layer with a chemical passivation effect. Figure 1 As shown, the surface of the semiconductor substrate on which the passivation layer is formed can be a simple polished surface. In this case, the surface has a relatively flat morphology, which is conducive to improving the formation quality of the passivation layer and enhancing the passivation effect of the passivation layer on the semiconductor substrate. However, the passivation layer formed on a semiconductor substrate with a flat surface also tends to be flat. This results in poor shaping and adhesion of the electrode material on the flat surface when forming an electrode for conducting carriers on the passivation layer, thereby reducing the selection and matching of electrode materials. At the same time, it also leads to a smaller contact area between the formed electrode and the doped semiconductor layer formed on the flat surface, increasing contact loss. Although the undulating suede surface has a larger surface roughness, which is conducive to improving the electrical contact performance between the electrode and the doped semiconductor layer, as well as the shaping and adhesion of the electrode, the formation quality of the doped semiconductor layer on the suede surface is poor, and its passivation effect is reduced. Therefore, existing solar cells cannot achieve both good passivation effect and good electrode contact performance and shaping, which is not conducive to improving the conversion efficiency of solar cells.

[0058] In order to solve the above technical problems, in the first aspect, an embodiment of the present invention provides a solar cell. Figures 2 to 6As shown, the solar cell provided by the embodiment of the present invention includes: a semiconductor substrate 11 and a passivation layer 14. The semiconductor substrate 11 has a first surface 12 and a second surface 13 relative to each other. At least one of the first surface 12 and the second surface 13 is a target surface. The passivation layer 14 is arranged on the target surface. The side of the passivation layer 14 facing away from the semiconductor substrate 11 has a plurality of tower-like texture structures 15 recessed into the passivation layer 14. Among them, a single tower-like texture structure 15 is surrounded by a polygon-like bottom surface and a side surface. In the same tower-like texture structure 15, at least one corner of the polygon-like bottom surface has a plurality of raised portions 16 climbing along the extension direction of the side ridge line, and the plurality of raised portions 16 on the same corner have an undulating morphology extending in a direction parallel to the polygon-like bottom surface.

[0059] When the above technical solution is adopted, Figures 2 to 6 As shown, a passivation layer 14 is disposed on the target surface of a semiconductor substrate 11, passivating the target surface side of the semiconductor substrate 11 and reducing the carrier recombination rate. Furthermore, the side of the passivation layer 14 facing away from the semiconductor substrate 11 has multiple pyramid-like texture structures 15 recessed into the passivation layer 14. With other factors remaining the same, compared to texture structures with greater undulation, such as pyramid-shaped velvet structures, the pyramid-like texture structures 15 lacking spires have relatively less undulation, resulting in a relatively flat surface on the side of the passivation layer 14 facing away from the semiconductor substrate 11 from a macroscopic perspective. Furthermore, during the actual manufacturing process, the passivation layer 14 is formed on the target surface of the semiconductor substrate 11 through processes such as deposition. The surface undulation of the passivation layer 14 facing away from the semiconductor substrate 11 is also affected by the surface undulation of the target surface. Accordingly, the surface undulation of the passivation layer 14 facing away from the semiconductor substrate 11 can, to a certain extent, reflect the surface undulation of the target surface of the semiconductor substrate 11. Based on this, when the surface of the passivation layer 14 facing away from the semiconductor substrate 11 is relatively flat on a macroscopic scale, the target surface of the semiconductor substrate 11 is also generally a relatively flat surface, which is conducive to improving the formation quality and film thickness of the passivation layer 14 on the target surface, thereby improving the passivation effect of the passivation layer 14 on the semiconductor substrate 11 and improving the conversion efficiency of the solar cell. In addition, if Figures 2 to 6As shown, in the tower-like texture structure 15 formed on the side of the passivation layer 14 facing away from the semiconductor substrate 11, at least one corner of the polygonal bottom surface has a plurality of raised portions 16 rising along the extension direction of the side ridge line, and the plurality of raised portions 16 on the same corner have an undulating morphology extending in a direction parallel to the polygonal bottom surface. At this time, compared with the conventional tower-like texture structure with a flat side, the side of the tower-like texture structure 15 in the embodiment of the present invention has the above-mentioned raised portions 16, so that the surface of the passivation layer 14 facing away from the semiconductor substrate 11 has a relatively larger surface roughness at the microscopic level than the conventional polished surface, which is beneficial to increase the doped semiconductor layer included in the passivation layer 14, or the doped semiconductor layer formed between the passivation layer 14 and the semiconductor substrate 11 has a larger specific surface area, thereby increasing the contact area between the doped semiconductor layer and the electrode, improving the contact performance between the doped semiconductor layer and the electrode, and the adhesion and shaping of the electrode on the doped semiconductor layer, which is beneficial to improving the conversion efficiency of the solar cell.

[0060] In actual applications, the solar cell provided by the embodiments of the present invention can be a double-sided contact cell, that is, one of the positive electrode and the negative electrode of the solar cell is arranged on the front side of the cell, and the other is arranged on the back side of the cell. Alternatively, the solar cell provided by the embodiments of the present invention can also be a back-contact cell, that is, both the positive electrode and the negative electrode of the solar cell are arranged on the back side of the cell.

[0061] Secondly, the solar cell provided by the embodiment of the present invention may be a cell having a tunneling passivation contact structure or a heterogeneous contact structure, or may be a conventional cell without the interface passivation layer included in the above structure.

[0062] Specifically, the embodiment of the present invention does not impose any specific limitation on the material of the semiconductor substrate. For example, the semiconductor substrate can be a substrate made of any semiconductor material, such as a silicon substrate, a silicon-germanium substrate, a germanium substrate, or a gallium arsenide substrate.

[0063] Regarding the first and second surfaces of the semiconductor substrate, the first surface of the semiconductor substrate can correspond to the front surface of the solar cell, in which case the second surface of the semiconductor substrate can correspond to the back surface of the solar cell; alternatively, the first surface of the semiconductor substrate can correspond to the back surface of the solar cell, in which case the second surface of the semiconductor substrate corresponds to the front surface of the solar cell. Whether the first and second surfaces are target surfaces can be determined based on the type of solar cell and the corresponding relationship between the first and second surfaces and the front and back surfaces of the solar cell, respectively, and is not specifically limited here.

[0064] For example, in the case where the solar cell is a double-sided contact cell, of the first and second surfaces of the semiconductor substrate, only the first surface may be the target surface, only the second surface may be the target surface, or both the first and second surfaces may be the target surface.

[0065] For example, in the case where the solar cell is a back-contact cell, one of the first surface and the second surface of the semiconductor substrate corresponding to the back surface of the cell is the target surface.

[0066] As for the surface topography of the target surface of the semiconductor substrate, as previously described, the surface topography of the passivation layer facing away from the semiconductor substrate can, to a certain extent, reflect the surface topography of the target surface of the semiconductor substrate. Therefore, the surface topography of the target surface can be referenced to the surface topography of the passivation layer facing away from the semiconductor substrate. Specifically, because the surface topography of the passivation layer facing away from the semiconductor substrate is a flat surface having multiple pyramid-like texture structures 15, the surface topography of the target surface is also relatively flat.

[0067] For example, Figure 7 As shown, the target surface may have a plurality of tower-like texture structures 15 that are recessed into the semiconductor substrate 11, and the tower-like texture structures 15 on the target surface may have a raised portion 16. In this case, compared with a texture structure having a large undulating morphology such as a pyramid-shaped velvet structure, when the target surface has a plurality of tower-like texture structures 15 that are recessed into the semiconductor substrate, the target surface of the semiconductor substrate is relatively flat, which is beneficial to improving the formation quality and film thickness of the passivation layer formed on the target surface, and improving the passivation effect of the passivation layer. Secondly, when the tower-like texture structures 15 on the target surface have a raised portion 16, the surface roughness of the target surface can be increased, which is beneficial for the doped semiconductor layer formed on the target surface by deposition and other processes to also have a relatively large specific surface area, thereby increasing the contact area between the doped semiconductor layer and the electrode, improving the contact performance between the doped semiconductor layer and the electrode, and the adhesion and shaping of the electrode on the doped semiconductor layer. The specific morphology of the tower-like texture structure 15 and the raised portions 16 on the target surface, as well as the number and distribution of the raised portions 16 and the dimensions of the raised portions 16, can be found in the following information regarding the specific morphology, number and distribution of the raised portions 16 and the dimensions of the raised portions 16 on the side of the passivation layer 14 facing away from the semiconductor substrate, and will not be further described here. For example, the raised portions 16 on the target surface may be shaped like a triangular prism, a cone, or a cylinder.

[0068] For the aforementioned passivation layer, the surface of the passivation layer facing away from the semiconductor substrate serves as the front and / or back surface of the solar cell. Regarding the formation location, the passivation layer can be disposed within the target surface or on the target surface, or a portion of the passivation layer can be disposed within the target surface and another portion disposed on the target surface. The formation location of the passivation layer on the target surface can be determined based on the structure of the passivation layer and is not specifically limited herein.

[0069] In terms of structure and materials, the specific structure of the passivation layer can be determined according to the type of solar cell and the actual application scenario, and is not specifically limited here. For example, the passivation layer can include at least one of an interface passivation layer, a doped semiconductor layer, a surface passivation layer, an anti-reflection layer, and a transparent conductive layer.

[0070] like Figures 2 to 4 As shown, when the passivation layer 14 is only a doped semiconductor layer, the passivation layer 14 can be disposed on the target surface or within the target surface. In this case, the tower-like texture structure and the protrusions are both formed on the side of the doped semiconductor layer facing away from the semiconductor substrate. When the passivation layer 14 is disposed on the target surface, the material of the passivation layer 14 can include any semiconductor material such as silicon, silicon germanium, or germanium. The crystalline phase of the passivation layer 14 can be single crystal, polycrystalline, microcrystalline, nanocrystalline, or amorphous.

[0071] like Figure 9 and Figure 10 As shown, when the passivation layer 14 only includes at least one of a surface passivation layer 22, an anti-reflection layer, and a transparent conductive layer, the passivation layer 14 is disposed on the target surface. In this case, the tower-like texture structure and the raised portion are both formed on the outermost layer of the film layer included in the passivation layer 14 (i.e., the layer with the largest distance from the semiconductor substrate 11 along the thickness direction of the cell), on the side of the surface facing away from the semiconductor substrate 11. For example, when the passivation layer 14 only includes the surface passivation layer 22, the tower-like texture structure and the raised portion are both formed on the side of the surface passivation layer 22 facing away from the semiconductor substrate. In addition, the solar cell provided by the embodiment of the present invention also includes a doped semiconductor layer 20 disposed within or on the target surface (when the doped semiconductor layer 20 is disposed on the target surface, the material of the doped semiconductor layer 20 can be referred to above and will not be repeated here). The passivation layer is located on the side of the doped semiconductor layer 20 facing away from the semiconductor substrate 11. Furthermore, the materials of the surface passivation layer, anti-reflection layer, and transparent conductive layer can be set according to actual needs. Exemplarily, the material of the surface passivation layer may include any passivating material such as silicon oxide, aluminum oxide, silicon nitride, or silicon oxynitride. The material of the antireflection layer may include silicon nitride or silicon oxynitride. The material of the transparent conductive layer may include at least one of fluorine-doped tin oxide, aluminum-doped zinc oxide, tin-doped indium oxide, tungsten-doped indium oxide, molybdenum-doped indium oxide, cerium-doped indium oxide, and indium hydroxide.

[0072] When the passivation layer includes at least one of a surface passivation layer, an anti-reflection layer, and a transparent conductive layer in addition to the doped semiconductor layer, the tower-like texture structure and the raised portion are both formed on the outermost layer of the film layer included in the passivation layer 14 (i.e., the one with the largest distance from the semiconductor substrate along the thickness direction of the battery), and on the side of the surface facing away from the semiconductor substrate. For example, when the passivation layer only includes a doped semiconductor layer and a transparent conductive layer, and the transparent conductive layer is arranged on the side of the doped semiconductor layer facing away from the semiconductor substrate, the tower-like texture structure and the raised portion are both formed on the side of the transparent conductive layer facing away from the semiconductor substrate. In addition, the formation position of the doped semiconductor layer in the solar cell, as well as the materials of the surface passivation layer, the anti-reflection layer, the transparent conductive layer, and the doped semiconductor layer can be referred to above and will not be repeated here.

[0073] It should be noted that, when the solar cell provided in the embodiment of the present invention is a double-sided contact cell and the passivation layer includes a doped semiconductor layer, the doped semiconductor layer in the same passivation layer is an N-type doped semiconductor layer or a P-type doped semiconductor layer. When the solar cell is a back contact cell and the passivation layer includes a doped semiconductor layer, as Figure 14 As shown, along a direction parallel to the target surface, the doped semiconductor layer in the passivation layer 14 includes alternating first doped semiconductor portions 18 and second doped semiconductor portions 19 of opposite conductivity types, and at least portions of the first doped semiconductor portions 18 are spaced apart from at least portions of the second doped semiconductor portions 19. Specifically, at least portions of the first doped semiconductor portions 18 and at least portions of the second doped semiconductor portions 19 can be spaced apart along a direction parallel to the target surface, or can be spaced apart along the thickness direction of the semiconductor substrate 11 by a dielectric layer made of an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride.

[0074] In addition, when the doped semiconductor layer is disposed on the target surface, as Figure 9 As shown, the doped semiconductor layer 20 may be in direct contact with the semiconductor substrate 11; or Figure 8 As shown, the solar cell may further include an interface passivation layer 21 positioned between the semiconductor substrate 11 and the doped semiconductor layer 20. The material and thickness of the interface passivation layer 21 can be determined based on the material of the doped semiconductor layer 20 and are not specifically limited herein. For example, when the doped semiconductor layer comprises a doped polycrystalline silicon layer, the interface passivation layer is a tunneling oxide layer. For another example, when the doped semiconductor layer comprises a doped amorphous silicon layer, the interface passivation layer is an intrinsic amorphous silicon layer.

[0075] In terms of surface morphology, the side of the passivation layer facing away from the semiconductor substrate has multiple tower-like texture structures that are recessed into the passivation layer. A single tower-like texture structure is surrounded by a polygon-like bottom surface and side surfaces. The polygon-like bottom surface can be a regular polygonal bottom surface (in this case, the polygon can be a regular quadrilateral, pentagon, hexagon or octagon, etc.; the corners of the polygon can be regular sharp corners or rounded corners; the polygon can be a regular polygon with the same side length or a polygon with different side lengths), or the polygon-like bottom surface can also be a polygonal bottom surface with at least one side having an irregular morphology such as an arc (it can be a quadrilateral, pentagon, hexagon or octagon, etc.; the corners of the polygon can be sharp corners or rounded corners).

[0076] As for the size of the tower-like texture structure, it can be determined based on the surface roughness requirements of the passivation layer on the side away from the semiconductor substrate in the actual application scenario, and no specific limitation is made here.

[0077] For example, the side length of the polygonal bottom surface in the tower-like base-shaped texture structure may be greater than or equal to 5 μm and less than or equal to 30 μm. For example, the side length of the polygonal bottom surface in the tower-like base-shaped texture structure may be 5 μm, 5.5 μm, 6 μm, 6.5 μm, 7 μm, 7.5 μm, 8 μm, 8.5 μm, 9 μm, 9.5 μm, 10 μm, 15 μm, 20 μm, 25 μm, or 30 μm.

[0078] For example, the concave depth of the tower-like base-shaped texture structure may be greater than or equal to 0.1 μm and less than or equal to 2 μm. For example, the concave depth of the tower-like base-shaped texture structure may be 0.1 μm, 0.5 μm, 0.8 μm, 1 μm, 1.2 μm, 1.5 μm, 1.8 μm or 2 μm.

[0079] Secondly, if Figure 5 and Figure 6 As shown, in the same type of tower base-shaped texture structure 15, at least one corner of the polygonal bottom surface has a plurality of raised portions 16 climbing along the extension direction of the side ridges, and the plurality of raised portions 16 on the same corner have an undulating morphology extending in a direction parallel to the polygonal bottom surface. Specifically, the raised portion climbs on the side of the tower base-shaped texture structure, and its climbing direction is roughly parallel to the extension direction of the side ridges. At this time, the inclination angle of the raised portion relative to the polygonal bottom surface can range from 30° to 60°. In addition, in the same type of tower base-shaped texture structure 15, it is possible that only one corner of the polygonal bottom surface has a plurality of raised portions 16. Or, as Figure 11 As shown, in at least one tower base-like texture structure 15, at least two corners of the polygonal bottom surface have multiple protrusions 16; at this time, in this case, the distribution relationship between different corners of the same polygonal bottom surface having multiple protrusions 16 thereon can be determined according to the actual manufacturing process.

[0080] For example, Figure 5 As shown, in at least one of the tower-like base-shaped texture structures 15, at least one pair of corners of the polygon-like base surface each have multiple raised portions 16. The at least one pair of corners can be two diagonally distributed corners of the polygon-like base surface. In this case, compared to having raised portions 16 on only one corner of the polygon-like base surface, when at least one of the tower-like base-shaped texture structures 15 has multiple raised portions 16 on at least one pair of corners, more raised portions 16 are provided in at least one of the same tower-like base-shaped texture structures 15. This further increases the undulation of the passivation layer on the side facing away from the semiconductor substrate. It also helps to distribute different raised portions 16 diagonally at different corners of the polygon-like base surface, rather than concentrating them on a single corner. This further helps to achieve high surface roughness in different diagonal regions of the same tower-like base-shaped texture structure 15, thereby ensuring good contact between different regions of the doped semiconductor layer and the electrode, and ensuring strong adhesion and good shaping of the electrode on different regions of the doped semiconductor layer.

[0081] In addition, as mentioned above, the presence of the protrusion is beneficial to increasing the surface roughness of the side of the passivation layer facing away from the semiconductor substrate at the microscopic level, and thus helps to increase the contact area between the doped semiconductor layer and the electrode, improve the contact performance between the doped semiconductor layer and the electrode, and the adhesion and shaping of the electrode on the doped semiconductor layer. However, if the size of the protrusion is too large, it will affect the formation quality of the passivation layer on the target surface. Therefore, the size of the protrusion can be determined based on the requirements for the passivation effect of the passivation layer, the contact performance between the doped semiconductor layer and the electrode, and the adhesion and shaping of the electrode on the doped semiconductor layer in the actual application scenario, and no specific limitation is made here.

[0082] Exemplarily, the height of a single raised portion may be greater than or equal to 0.2 μm and less than or equal to 0.8 μm. For example, the height of the raised portion may be 0.2 μm, 0.3 μm, 0.4 μm, 0.5 μm, 0.6 μm, 0.7 μm, or 0.8 μm. In this case, the height of the raised portion is within the above range, which helps prevent the surface roughness of the passivation layer facing away from the semiconductor substrate from being smaller due to the smaller height of the raised portion, ensuring that the contact area between the doped semiconductor layer and the electrode can be increased by the raised portion, improving the contact performance between the doped semiconductor layer and the electrode, as well as the adhesion and shaping of the electrode on the doped semiconductor layer, thereby improving the conversion efficiency of the solar cell. In addition, it also helps prevent the surface roughness of the passivation layer on the side facing away from the semiconductor substrate from being greater due to the height of the raised portion being too large, ensuring that the target surface of the semiconductor substrate is relatively flat, and helping to improve the formation quality of the passivation layer on the target surface, improving the passivation effect of the passivation layer, and facilitating achieving a balance between the passivation effect of the passivation layer, the contact performance between the doped semiconductor layer and the electrode, and the adhesion and shaping of the electrode, thereby ensuring that the solar cell has high operating performance and structural reliability. In the extension direction of the side edge line, a single raised portion can climb from a corner of the quasi-polygonal bottom surface to the top of the side surface, or a single raised portion can climb from a corner of the quasi-polygonal bottom surface only to the height of a portion of the side surface.

[0083] When a single raised portion rises from one corner of the polygonal base only to the height of the side portion, such as Figure 12 As shown, the corner may have only one set of protrusions 16 along the extending direction of the side ridge line, and in this case, part of the side surface of the tower base-like texture structure 15 is exposed. Figure 13 As shown, at least one corner of the polygonal bottom surface of at least one tower-like base-shaped texture structure 15 may also have at least two groups of raised portions 16 distributed in a stepped manner along the direction of the side ridges, with each group of raised portions 16 including multiple raised portions 16 extending along the direction of the polygonal bottom surface. In this case, the at least two groups of raised portions 16 distributed in a stepped manner can further increase the degree of undulation of the side surface of the tower-like base-shaped texture structure 15 along the direction of the ridges, further increasing the surface roughness of the side of the passivation layer facing away from the semiconductor substrate, thereby increasing the contact area between the doped semiconductor layer and the electrode, further improving the contact performance between the doped semiconductor layer and the electrode, as well as the adhesion and shaping of the electrode on the doped semiconductor layer, and improving the conversion efficiency of the solar cell.

[0084] For example, the width of a single raised portion can be greater than or equal to 0.1 μm and less than or equal to 0.8 μm. For example, the width of the raised portion can be 0.1 μm, 0.2 μm, 0.3 μm, 0.4 μm, 0.5 μm, 0.6 μm, 0.7 μm, or 0.8 μm. The application principle of the beneficial effect in this case is similar to the application principle of the beneficial effect of the height of a single raised portion greater than or equal to 0.2 μm and less than or equal to 0.8 μm described above, and will not be repeated here.

[0085] Specifically, in the actual application process, such as Figure 7 As shown, the height of a single protrusion can be greater than the width of the protrusion. The height direction of the protrusion 16 is parallel to the thickness direction of the semiconductor substrate, and the width direction of the protrusion 16 is parallel to the extension direction of the polygonal bottom surface of the tower-like texture structure 15. In this case, compared with the "short and fat" protrusion whose height is less than its width, when the height of a single protrusion 16 is greater than the width of the protrusion 16, the "thin and tall" single protrusion 16 has a greater degree of undulation, and is conducive to forming a larger number of protrusions 16 per unit area, further increasing the surface roughness of the side of the passivation layer away from the semiconductor substrate, and facilitating the increase of the contact area between the above-mentioned doped semiconductor layer and the electrode, further improving the contact performance between the doped semiconductor layer and the electrode, as well as the adhesion and shaping of the electrode on the doped semiconductor layer, thereby improving the conversion efficiency of the solar cell. Of course, there can also be at least one protrusion whose height is less than or equal to the width of the protrusion.

[0086] As for the shape of the raised portion and the undulating shape of multiple raised portions on the same corner extending along the polygonal bottom surface, they can be determined according to the recessed depth of the tower base-like texture structure and the actual application scenario, and no specific limitation is given here.

[0087] For example, Figure 12 and Figure 13 As shown, the multiple raised portions 16 on the same corner can have a zigzag or wavy undulation extending along the polygonal base. In this case, compared to a single convex or concave undulation such as an arc, the zigzag and wavy undulations both have a continuous undulation of convex, concave, convex, concave, etc., which can further increase the surface roughness of the tower-like texture structure 15, thereby increasing the contact area between the doped semiconductor layer and the electrode, improving the contact performance between the doped semiconductor layer and the electrode, and the adhesion and shaping of the electrode on the doped semiconductor layer.

[0088] For example, Figure 6 、 Figure 7 、 Figure 12 and Figure 13As shown, at least one raised portion 16 can be shaped like a triangular prism, a cone, or a cylinder. In this case, the morphology of the raised portion 16 can be varied, which helps improve the applicability of the solar cell provided by the embodiment of the present invention in different application scenarios. Furthermore, the manufacturing process difficulty of the tower-base-like texture structure 15 can be reduced.

[0089] It should be noted that the aforementioned quasi-triangular prism shape may be a regular triangular prism shape, the ridges of which are roughly parallel to the side ridges of the tower-shaped texture structure; or the quasi-triangular prism shape may be a quasi-triangular prism shape with irregular morphologies such as arc-shaped ridges or side surfaces. For example: Figure 12 and Figure 13 As shown, the raised portion 16 on at least one corner is in a triangular prism-like shape, and the ridgeline of the raised portion 16 can be in an arc shape that is concave toward the semiconductor substrate. In this case, when the raised portion 16 on at least one corner is in a triangular prism-like shape, compared to when the ridgeline of the raised portion 16 is a straight line, when the ridgeline of the raised portion 16 is in an arc shape that is concave toward the semiconductor substrate, the portion of the raised portion 16 corresponding to the concave arc-shaped ridgeline also has a concave undulating morphology, which can further increase the surface roughness of the tower-like base-like texture structure 15 in the area where the raised portion 16 is provided, which is conducive to further increasing the specific surface area of ​​the above-mentioned doped semiconductor layer, thereby increasing the contact area between the doped semiconductor layer and the electrode, improving the contact performance between the doped semiconductor layer and the electrode, and the adhesion and shaping of the electrode on the doped semiconductor layer, thereby improving the conversion efficiency of the solar cell. It should be noted that the arc-shaped ridgeline in the raised portion 16 that is concave toward the semiconductor substrate refers to the top ridgeline of the triangular prism-like structure.

[0090] The above-mentioned conical and cylindrical shapes can be regular conical or regular cylindrical shapes respectively (a part of the side of the regular conical or regular cylindrical shape can be integrated with the side of the tower base-like texture structure); or the conical and cylindrical shapes can also be irregular conical or cylindrical shapes with concave or convex microstructures on the side.

[0091] In addition, when the concave depth of the base-like texture structure is relatively small (e.g., the concave depth is less than 0.4 μm), the morphology of the raised portion can be cylindrical or conical. When the concave depth of the base-like texture structure is relatively large (e.g., greater than or equal to 0.4 μm), the morphology of the raised portion can be triangular prism-like. It can be seen that when the concave depth of the base-like texture structure is different, the morphology of the raised portion may also be different.

[0092] Specifically, the depths of the multiple tower-like texture structures on the side of the passivation layer facing away from the semiconductor substrate may be substantially the same, and the numbers of the different tower-like texture structures formed thereon are also substantially the same.

[0093] Alternatively, the above-mentioned multiple tower-base-like texture structures may include a first-type tower-base-like texture structure and a second-type tower-base-like texture structure. The depth of the first-type tower-base-like texture structure recessed into the passivation layer is greater than the depth of the second-type tower-base-like texture structure recessed into the passivation layer. Moreover, the number of raised portions in the first-type tower-base-like texture structure is greater than the number of raised portions in the second-type tower-base-like texture structure. In this case, the multiple tower-base-like texture structures also include a first-type tower-base-like texture structure with a larger recessed depth and a larger number of raised portions, which can further increase the surface roughness of the passivation layer away from the semiconductor substrate, further improve the contact performance between the above-mentioned doped semiconductor layer and the electrode, as well as the attachment and shaping of the electrode on the doped semiconductor layer, improve the structural stability of the solar cell, and reduce the transmission loss between the doped semiconductor layer and the electrode.

[0094] Among them, when the above-mentioned multiple tower-base-like texture structures can include a first-type tower-base-like texture structure and a second-type tower-base-like texture structure with different recessed depths and different numbers of protrusions, the distribution of the first-type tower-base-like texture structure and the second-type tower-base-like texture structure on the side of the passivation layer away from the semiconductor substrate can be set according to the structure of the passivation layer and actual needs, and no specific limitation is made here.

[0095] For example, in the case where the solar cell is a double-sided contact cell, the first type of tower-shaped texture structure and the second type of tower-shaped texture structure can be evenly distributed on the side of the passivation layer facing away from the semiconductor substrate; or, one of the first type of tower-shaped texture structure and the second type of tower-shaped texture structure is evenly distributed on the side of the passivation layer facing away from the semiconductor substrate, and the other is only randomly distributed in a local area on the side of the passivation layer facing away from the semiconductor substrate.

[0096] For example, Figure 14As shown, one of the first and second surfaces is the target surface. The passivation layer 14 includes a first doped semiconductor portion 18 and a second doped semiconductor portion 19 of opposite conductivity types. At least portions of the first doped semiconductor portion 18 and at least portions of the second doped semiconductor portion 19 are spaced apart. The surface of the passivation layer 14 corresponding to the first doped semiconductor portion 18 facing away from the semiconductor substrate 11 is a first sub-surface, and the surface of the passivation layer 14 corresponding to the second doped semiconductor portion 19 facing away from the semiconductor substrate 11 is a second sub-surface. The number of protrusions on the first sub-surface is different from the number of protrusions on the second sub-surface; and / or the height of the protrusions on the first sub-surface is different from the height of the protrusions on the second sub-surface. In this case, it can be understood that the first doped semiconductor portion 18 and the second doped semiconductor portion 19 of opposite conductivity types are spaced apart and spaced apart on the same side of the semiconductor substrate 11. In this case, the solar cell is a back-contact cell, which improves the cell's light utilization efficiency. In addition, when the number and / or height of the protrusions on the first sub-surface and the second sub-surface are different, the number and height of the protrusions on the first sub-surface and the second sub-surface can be set respectively according to the requirements for different passivation effects of the first doped semiconductor portion 18 and the second doped semiconductor portion 19 in the actual application scenario, and the requirements for the contact performance between the two and the corresponding electrodes, so that the two parts of the passivation layer 14 corresponding to the first doped semiconductor portion 18 and the second doped semiconductor portion 19 have different passivation effects on the semiconductor substrate 11, and are conducive to making the first doped semiconductor portion 18 and the second doped semiconductor portion 19 have different surface morphologies, thereby helping to reduce the passivation difference between the two parts of the passivation layer 14 corresponding to the first doped semiconductor portion 18 and the second doped semiconductor portion 19, and helping to reduce the difference in contact performance between the first doped semiconductor portion 18 and the second doped semiconductor portion 19 and the corresponding electrodes.

[0097] The formation positions of the first doped semiconductor portion and the second doped semiconductor portion included in the passivation layer on the target surface can be determined with reference to the formation position of the doped semiconductor layer included in the passivation layer on the target surface as described above. Specifically, the first doped semiconductor portion and the second doped semiconductor portion included in the passivation layer can both be formed in the target surface, or both be formed on the target surface, or one of the first doped semiconductor portion and the second doped semiconductor portion can be arranged in the target surface and the other can be arranged on the target surface. As for the specific conductivity type of the first doped semiconductor portion and the second doped semiconductor portion, it can be set according to actual needs, as long as it can help reduce the passivation difference between the two parts of the passivation layer corresponding to the first doped semiconductor portion and the second doped semiconductor portion, and help reduce the difference in contact performance between the first doped semiconductor portion and the second doped semiconductor portion and the corresponding electrodes.

[0098] It is understandable that due to the limitations of doping solid concentration and doping concentration, the dopant concentration of the dopant in the N-type doped semiconductor portion is greater than the doping concentration of the dopant in the P-type doped semiconductor portion, and the passivation characteristics and contact characteristics with the positive electrode of the P-type doped semiconductor portion are relatively worse. Based on this, if the number of raised portions on the first sub-surface is greater than the number of raised portions on the second sub-surface, and / or the height of the raised portions on the first sub-surface is greater than the height of the raised portions on the second sub-surface, in one case, the conductivity type of the first doped semiconductor portion can be P-type, the conductivity type of the second doped semiconductor portion is N-type, and the surface of the P-type doped semiconductor portion is rougher than that of the N-type doped semiconductor portion, so as to increase the contact area between the P-type doped semiconductor portion and the positive electrode and reduce the difference in contact performance between the corresponding N-type doped semiconductor portion and the P-type doped semiconductor portion in the battery and the corresponding electrode. In this case, the N-type doped semiconductor portion can be provided with a raised portion to further increase the contact area between the N-type doped semiconductor portion and the negative electrode and reduce the contact performance between the N-type doped semiconductor portion and the negative electrode; the N-type doped semiconductor portion can also be provided with no raised portion. In another embodiment, the conductivity type of the first doped semiconductor portion can be N-type, and the conductivity type of the second doped semiconductor portion can be P-type. The P-type doped semiconductor portion has a smoother surface than the N-type doped semiconductor portion, thereby improving the passivation effect of the P-type doped semiconductor portion on the semiconductor substrate 11 and reducing the passivation difference between the two parts of the battery corresponding to the N-type doped semiconductor portion and the P-type doped semiconductor portion. In this case, the N-type doped semiconductor portion can be provided with a raised portion to increase the contact area between the N-type doped semiconductor portion and the cathode and reduce the contact performance between the N-type doped semiconductor portion and the cathode; the N-type doped semiconductor portion can also be provided without a raised portion.

[0099] In addition, the first sub-surface and the second sub-surface may both have the above-mentioned tower-base-like texture structure. In this case, at least one of the first sub-surface and the second sub-surface may also have at least one tower-base-like texture structure without a raised portion. Alternatively, only one of the first sub-surface and the second sub-surface may have the above-mentioned tower-base-like texture structure, while the other may have a tower-base-like texture structure without a raised portion. For example: when the first doped semiconductor portion is an N-type doped polysilicon layer and the second doped semiconductor portion is a P-type doped amorphous silicon layer, only the first sub-surface may have the above-mentioned tower-base-like texture structure, while the second sub-surface may have a tower-base-like texture structure without a raised portion, and a velvet structure may be provided. For another example: the conductivity type of the first doped semiconductor part can be P-type, the conductivity type of the second doped semiconductor part can be N-type, and the above-mentioned tower-like texture structure is present only on the first sub-surface, while the tower-like texture structure without raised portions is present on the second sub-surface. At this time, the first sub-surface is rougher than the second sub-surface, which is conducive to making the surface of the P-type doped semiconductor part rougher than that of the N-type doped semiconductor part, so as to increase the contact area between the P-type doped semiconductor part and the positive electrode, and reduce the difference in contact performance between the N-type doped semiconductor part and the P-type doped semiconductor part in the battery and the corresponding electrodes. Among them, the bottom surface morphology and one-dimensional size of the tower-like texture structure without raised portions on the second sub-surface can refer to the bottom surface morphology and one-dimensional size of the tower-like texture structure with raised portions described above, and will not be repeated here. In addition, the one-dimensional size of the tower-like texture structure on the second sub-surface can be the same as or different from the one-dimensional size of the tower-like texture structure on the first sub-surface. When the one-dimensional size of the tower-like texture structure on the second sub-surface is different from the one-dimensional size of the tower-like texture structure on the first sub-surface, the recessed depth of the tower-like texture structure on the first sub-surface may be greater than the recessed depth of the tower-like texture structure on the second sub-surface, and / or the bottom side length (and / or bottom diagonal length) of the tower-like texture structure on the first sub-surface is smaller than the bottom side length (and / or bottom diagonal length) of the tower-like texture structure on the second sub-surface, so as to further increase the surface roughness of the first sub-surface and further improve the contact performance between the P-type doped semiconductor part and the positive electrode.

[0100] In one example, Figure 11 As shown, the passivation layer may further have a linear texture structure 17 on the side facing away from the semiconductor substrate, with at least one side of the linear texture structure 17 having a plurality of raised portions intersecting the extension direction of the linear texture structure 17. In this case, the presence of the linear texture structure 17 can further increase the surface roughness of the passivation layer on the side facing away from the semiconductor substrate, thereby increasing the contact area between the doped semiconductor layer and the electrode, further improving the contact performance between the doped semiconductor layer and the electrode, as well as the adhesion and shaping of the electrode on the doped semiconductor layer, thereby increasing the conversion efficiency of the solar cell.

[0101] Specifically, the linear texture structure can be a linear protrusion extending in a single direction. This linear texture structure can be a cutting line formed when cutting a semiconductor substrate during the actual manufacturing process. After polishing and cleaning, this linear texture structure remains and imparts a substantially similar morphology to the surface of the passivation layer disposed on the target surface. Therefore, the size and extension direction of the linear texture structure can be determined based on the size of the cutting line and the specific manufacturing process of polishing and cleaning, and are not specifically limited here.

[0102] Exemplarily, the passivation layer may further have a boss-type structure on the side facing away from the semiconductor substrate. The boss-type structure may be the boss-type structure remaining after the top of the pyramid-type structure is eliminated. The application principle of the beneficial effects in this case can refer to the application principle of the beneficial effects of the passivation layer also having a linear texture structure on the side facing away from the semiconductor substrate as described above, which will not be repeated here. Secondly, the surface of the boss-type structure may also have a plurality of raised portions that intersect with the extension direction of the side edges of the boss-type structure, so as to further increase the microscopic surface roughness of the passivation layer on the side facing away from the semiconductor substrate. Among them, the embodiment of the present invention does not specifically limit the size of the boss-type structure, as long as it can be applied to the solar cell provided in the embodiment of the present invention.

[0103] In a second aspect, an embodiment of the present invention provides a photovoltaic module, which includes the solar cell provided by the first aspect and various implementations thereof.

[0104] The beneficial effects of the second aspect and its various implementations in the embodiments of the present invention can be analyzed with reference to the beneficial effects of the first aspect and its various implementations, and will not be repeated here.

[0105] In a third aspect, an embodiment of the present invention provides a semiconductor substrate. Figure 15 As shown, the semiconductor substrate has a first surface and a second surface facing each other. At least one of the first surface and the second surface is a target surface. The target surface has multiple tower-like texture structures 15 that are recessed into the semiconductor substrate. Each tower-like texture structure 15 is surrounded by a polygonal bottom surface and side surfaces. Within each tower-like texture structure 15, at least one corner of the polygonal bottom surface has multiple raised portions 16 that rise along the extension direction of the side ridgeline. The multiple raised portions 16 at the same corner have an undulating topography extending parallel to the polygonal bottom surface.

[0106] For example, the multiple tower-like texture structures on the target surface of the semiconductor substrate may include a first-type tower-like texture structure and a second-type tower-like texture structure. The first-type tower-like texture structure is recessed deeper into the semiconductor substrate than the second-type tower-like texture structure. Furthermore, the first-type tower-like texture structure has a greater number of raised portions than the second-type tower-like texture structure.

[0107] For example, in at least one tower-base-like texture structure on the target surface, at least one pair of corners of the polygonal bottom surface each have a plurality of protrusions, and the at least one pair of corners are two corners of the polygonal bottom surface that are diagonally distributed.

[0108] For example, in the target surface, a plurality of protrusions on the same corner may have a broken line undulating shape or a wavy line undulating shape extending along the direction of the polygonal bottom surface.

[0109] Exemplarily, in the target surface, at least one protrusion is in a triangular prism-like, conical-like, or cylindrical-like shape.

[0110] For example, in the target surface, the protrusion on at least one corner may be in the shape of a triangular prism, and the ridgeline of the protrusion may be in the shape of an arc that is concave toward the direction approaching the semiconductor substrate.

[0111] For example, in the target surface, the height of a single protrusion may be greater than its width. The height direction of the protrusion is parallel to the thickness direction of the semiconductor substrate, and the width direction of the protrusion is parallel to the extension direction of the polygonal bottom surface of the tower-like texture structure.

[0112] Exemplarily, in the target surface, the height of a single protrusion is greater than or equal to 0.2 μm and less than or equal to 0.8 μm.

[0113] Exemplarily, in the target surface, the width of a single protrusion is greater than or equal to 0.1 μm and less than or equal to 0.8 μm.

[0114] Exemplarily, in the target surface, in at least one tower-base-like texture structure, at least one corner of the polygonal bottom surface has at least two groups of protrusions distributed in a stepped manner along the extension direction of the side ridges, and each group of protrusions includes multiple protrusions extending along the direction of the polygonal bottom surface.

[0115] Exemplarily, the target surface further has a linear texture structure, and at least one side of the linear texture structure has a plurality of protrusions intersecting with an extension direction of the linear texture structure.

[0116] For example, the target surface may have a first region and a second region that do not overlap. The number of protrusions on the surface of the first region is different from the number of protrusions on the surface of the second region; and / or the height of the protrusions on the surface of the first region is different from the height of the protrusions on the surface of the second region.

[0117] It should be noted that the semiconductor substrate provided in the third aspect of the present invention is used to manufacture the solar cell provided in the first aspect. The morphology, size, and distribution of the multiple tower-like texture structures on the target surface of the semiconductor substrate, as well as the size and distribution of the raised portions, can be referenced to the morphology, size, and distribution of the multiple tower-like texture structures on the side of the passivation layer facing away from the semiconductor substrate in the first aspect.

[0118] The beneficial effects of the third aspect and its various implementations in the embodiments of the present invention can be analyzed with reference to the beneficial effects of the first aspect and its various implementations, and will not be repeated here.

[0119] While the above description does not provide detailed technical details regarding patterning and etching of each layer, those skilled in the art will appreciate that various technical means can be employed to form layers, regions, and the like in desired shapes. Furthermore, those skilled in the art may devise methods that differ from those described above to form the same structure. Furthermore, while each embodiment has been described separately, this does not mean that the measures in each embodiment cannot be advantageously combined.

[0120] The above describes the embodiments of the present invention. However, these embodiments are merely for illustrative purposes and are not intended to limit the scope of the present invention. The scope of the present invention is defined by the appended claims and their equivalents. Various substitutions and modifications may be made by those skilled in the art without departing from the scope of the present invention, and such substitutions and modifications are intended to fall within the scope of the present invention.

Claims

1. A solar cell, characterized in that: include: a semiconductor substrate having a first side and a second side opposite to each other; At least one of the first surface and the second surface is a target surface; and a passivation layer disposed on the target surface; The side of the passivation layer facing away from the semiconductor substrate has a plurality of tower-like texture structures recessed into the passivation layer; Among them, a single tower-base-like texture structure is surrounded by a polygon-like bottom surface and a side surface; in the same tower-base-like texture structure, at least one corner of the polygon-like bottom surface has multiple raised portions rising along the extension direction of the side ridge line, and the multiple raised portions on the same corner have an undulating morphology extending in a direction parallel to the polygon-like bottom surface.

2. The solar cell according to claim 1, wherein The plurality of tower base-like texture structures include a first-type tower base-like texture structure and a second-type tower base-like texture structure; Among them, the depth of the first type of tower base-shaped texture structure recessed into the passivation layer is greater than the depth of the second type of tower base-shaped texture structure recessed into the passivation layer; the number of the raised portions in the first type of tower base-shaped texture structure is greater than the number of the raised portions in the second type of tower base-shaped texture structure.

3. The solar cell according to claim 1, wherein In at least one of the tower base-like texture structures, at least one pair of the corners of the polygonal bottom surface has a plurality of the protrusions; and at least one pair of the corners are two corners diagonally distributed in the polygonal bottom surface.

4. The solar cell according to claim 1, wherein The plurality of raised portions on the same corner have a broken line undulating shape or a wavy line undulating shape extending along the direction of the polygonal bottom surface.

5. The solar cell according to claim 1, wherein At least one of the protrusions is in a triangular prism-like, conical-like or cylindrical-like shape.

6. The solar cell according to claim 1, wherein The protrusion on at least one of the corners is in a triangular prism-like shape, and the ridgeline of the protrusion is in an arc shape that is concave toward the direction close to the semiconductor substrate.

7. The solar cell according to claim 1, wherein The height of a single protrusion is greater than the width of the protrusion; the height direction of the protrusion is parallel to the thickness direction of the semiconductor substrate, and the width direction of the protrusion is parallel to the extension direction of the polygonal bottom surface of the tower-like texture structure; and / or, the height of a single protrusion is greater than or equal to 0.2 μm and less than or equal to 0.8 μm; And / or, the width of a single protrusion is greater than or equal to 0.1 μm and less than or equal to 0.8 μm.

8. The solar cell according to claim 1, wherein In at least one of the tower-base-like texture structures, at least one corner of the polygonal bottom surface has at least two groups of raised portions distributed in a stepped manner along the extension direction of the side ridges, and each group of raised portions includes multiple raised portions extending along the direction of the polygonal bottom surface.

9. The solar cell according to claim 5, characterized in that The passivation layer further has a linear texture structure on a side facing away from the semiconductor substrate, and at least one side of the linear texture structure has a plurality of protrusions intersecting with an extending direction of the linear texture structure.

10. The solar cell according to claim 1, wherein One of the first surface and the second surface is a target surface; the passivation layer includes a first doped semiconductor portion and a second doped semiconductor portion of opposite conductivity types; at least a portion of the first doped semiconductor portion and at least a portion of the second doped semiconductor portion are spaced apart; The surface of the passivation layer corresponding to the first doped semiconductor portion and facing away from the semiconductor substrate is a first sub-surface, and the surface of the passivation layer corresponding to the second doped semiconductor portion and facing away from the semiconductor substrate is a second sub-surface. The number of the protrusions on the first sub-surface is different from the number of the protrusions on the second sub-surface; and / or the height of the protrusions on the first sub-surface is different from the height of the protrusions on the second sub-surface.

11. The solar cell according to claim 10, characterized in that The first doped semiconductor portion is a P-type doped semiconductor portion, and the second doped semiconductor portion is an N-type doped semiconductor portion; The protrusions are only distributed on the first sub-surface; the second sub-surface has a tower base-like texture structure without the protrusions.

12. The solar cell according to claim 1, wherein The target surface has a plurality of the tower base-like texture structures recessed into the semiconductor substrate, and the protrusions in the tower base-like texture structures on the target surface are in a triangular prism-like shape.

13. A photovoltaic module, characterized in that: The solar cell comprises the solar cell according to any one of claims 1 to 12.

14. A semiconductor substrate, characterized in that: The semiconductor substrate has a first surface and a second surface opposite to each other; at least one of the first surface and the second surface is a target surface; the target surface has a plurality of tower-like texture structures recessed into the semiconductor substrate; Among them, a single tower-base-like texture structure is surrounded by a polygon-like bottom surface and a side surface; in the same tower-base-like texture structure, at least one corner of the polygon-like bottom surface has multiple raised portions rising along the extension direction of the side ridge line, and the multiple raised portions on the same corner have an undulating morphology extending in a direction parallel to the polygon-like bottom surface.

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