Solar cell, photovoltaic module and semiconductor substrate

Abstract

The present invention discloses a solar cell, a photovoltaic module and a semiconductor substrate, which relate to the field of photovoltaic technology, so that the passivation layer has a good passivation effect on the semiconductor substrate, and improves the contact performance between the doped semiconductor layer and the electrode, as well as the shaping of the electrode. The solar cell includes a semiconductor substrate and a passivation layer. At least one of the first surface and the second surface of the semiconductor substrate is a target surface. Part of the surface of the passivation layer on the side away from the semiconductor substrate has a plurality of tower-like texture structures that are concave toward the side close to the semiconductor substrate. The plurality of tower-like texture structures include a first-type tower-like texture structure and a second-type tower-like texture structure. The corners in the bottom surface of the first-type tower-like texture structure are all quasi-rounded corners, and the bottom surface of the second-type tower-like texture structure includes some corners that are quasi-rounded corners, and the remaining corners are quasi-sharp corners. In the bottom surface of the same second-type tower-like texture structure, the number of quasi-rounded corners is greater than or equal to the number of quasi-sharp corners.

Description

Technical Field

[0001] The present invention relates to the field of photovoltaic technology, and in particular to a solar cell, a photovoltaic module and a semiconductor substrate. Background Art

[0002] As a green energy source, solar cells play a positive role in energy conservation and emission reduction. With the development of the photovoltaic industry, solar cell technology has become increasingly mature. Photovoltaic solar cells are devices that convert sunlight into electrical energy. Specifically, solar cells utilize the photovoltaic principle to generate charge carriers and then use electrodes to extract these charge carriers, thereby facilitating the efficient use of electrical energy. As an environmentally friendly and renewable energy source, solar energy has garnered increasing attention in recent years. Consequently, the application range of photovoltaic solar cells, which are based on the photoelectric effect, has also expanded.

[0003] However, existing solar cells have difficulty in achieving both good passivation effects and good electrode contact performance and shaping, which is not conducive to improving the conversion efficiency of solar cells. Summary of the Invention

[0004] The object of the present invention is to provide a solar cell, a photovoltaic module and a semiconductor substrate, which are used to ensure that the passivation layer has a good passivation effect on the semiconductor substrate, while increasing the surface roughness of the passivation layer on the side away from the semiconductor substrate by arranging a second type of tower base-shaped texture structure with a sharp corner on the bottom surface, which is beneficial to increase the specific surface area of ​​the doped semiconductor layer in the passivation layer or formed between the passivation layer and the semiconductor substrate, improve the contact performance between the doped semiconductor layer and the electrode, and the shaping of the electrode, thereby improving the conversion efficiency of the solar cell.

[0005] In order to achieve the above-mentioned purpose, in a first aspect, the present invention provides a solar cell, which comprises: a semiconductor substrate and a passivation layer. The semiconductor substrate comprises a first surface and a second surface opposite to each other. At least one of the first surface and the second surface is a target surface. The passivation layer is arranged on the target surface. Part of the surface of the passivation layer on the side away from the semiconductor substrate has a plurality of tower-like texture structures that are recessed toward the side close to the semiconductor substrate. Among them, the plurality of tower-like texture structures include a first-type tower-like texture structure and a second-type tower-like texture structure. The corners in the bottom surface of the first-type tower-like texture structure are all quasi-rounded corners, and the bottom surface of the second-type tower-like texture structure includes some corners that are quasi-rounded corners and the remaining corners are quasi-sharp corners. In the bottom surface of the same second-type tower-like texture structure, the number of quasi-rounded corners is greater than or equal to the number of quasi-sharp corners.

[0006] When adopting the above technical solution, the passivation layer is arranged on the target surface of the semiconductor substrate, and the target surface side of the semiconductor substrate can be passivated to reduce the carrier recombination rate. In addition, the side of the passivation layer facing away from the semiconductor substrate has multiple quasi-tower-shaped texture structures. Under the same conditions, compared with texture structures with a large degree of undulation, such as pyramid-shaped velvet structures, the degree of undulation of the quasi-tower-shaped texture structures without tower spires is relatively small. In addition, each corner in the bottom surface of the first type of tower-shaped texture structure included in the multiple quasi-tower-shaped texture structures, and most of the corners in the bottom surface of the second type of tower-shaped texture structure are quasi-rounded corners. Compared with the quasi-pointed corners, the quasi-rounded corner transition of the bottom surface is smoother and flatter, making the boundary transition of the quasi-tower-shaped texture structure at the quasi-rounded corner more relaxed and blurred, thereby making the surface of the side of the passivation layer facing away from the semiconductor substrate relatively flat from a macroscopic perspective. Furthermore, during the actual manufacturing process, the passivation layer is formed on the target surface of the semiconductor substrate through processes such as deposition. The surface undulation of the passivation layer on the side facing away from the semiconductor substrate is also affected by the surface undulation of the target surface. Accordingly, the surface undulation of the passivation layer on the side facing away from the semiconductor substrate can also, to a certain extent, reflect the surface undulation of the target surface of the semiconductor substrate. Therefore, when the surface of the passivation layer facing away from the semiconductor substrate is relatively flat on a macroscopic scale, the target surface of the semiconductor substrate is also generally relatively flat, which is beneficial for improving the formation quality and film thickness of the passivation layer on the target surface, thereby improving the passivation effect of the passivation layer on the semiconductor substrate and improving the conversion efficiency of the solar cell.

[0007] In addition, the bottom surface of the second type of tower base-shaped texture structure also includes sharp corners. Compared with rounded corners, the transition of the sharp corners is relatively obvious, and its undulation is greater, which is conducive to increasing the specific surface area of ​​the side of the passivation layer away from the semiconductor substrate. Moreover, in the bottom surface of the same second type of tower base-shaped texture structure, the number of sharp corners is greater than or equal to the number of rounded corners, ensuring that the side of the passivation layer away from the semiconductor substrate is macroscopically flat, while making the side of the passivation layer away from the semiconductor substrate have a relatively large surface roughness at the microscopic level, so that the doped semiconductor layer included in the passivation layer, or the doped semiconductor layer formed between the passivation layer and the semiconductor substrate has a larger specific surface area, thereby increasing the contact area between the doped semiconductor layer and the electrode, improving the contact performance between the doped semiconductor layer and the electrode, and the adhesion and shaping of the electrode on the doped semiconductor layer, which is conducive to improving the conversion efficiency of the solar cell.

[0008] As a possible implementation solution, on the side of the same passivation layer facing away from the semiconductor substrate, the distribution density of the first type of tower-shaped texture structures is greater than the distribution density of the second type of texture structures.

[0009] When the above technical solution is adopted, all corners in the bottom surface of the first type of tower base-shaped texture structure are quasi-rounded corners, and the proportion of quasi-rounded corners in its bottom surface is relatively large compared to the proportion of quasi-rounded corners in the second type of tower base-shaped texture structure. Moreover, as mentioned above, compared with the quasi-pointed corners, the quasi-rounded corner transitions on the bottom surface are smoother and flatter. Therefore, when the distribution density of the first type of tower base-shaped texture structure is greater than the distribution density of the second type of texture structure, it is beneficial to further improve the macroscopic surface flatness of the surface of the passivation layer facing away from the semiconductor substrate, and further improve the formation quality of the passivation layer and the passivation effect.

[0010] As a possible implementation, within the surface of the passivation layer facing away from the semiconductor substrate, where both the first-type tower-shaped texture and the second-type tower-shaped texture are present, the distribution density of the first-type tower-shaped texture within a 1 cm x 1 cm area is greater than or equal to 80% and less than or equal to 99%. In this case, each corner has a first-type tower-shaped texture with a relatively small rounded corner, and its distribution density is higher on the side of the passivation layer facing away from the semiconductor substrate. This further improves the macroscopic surface smoothness of the passivation layer on the side facing away from the semiconductor substrate, further enhancing the formation quality of the passivation layer and the passivation effect.

[0011] As a possible implementation, on the side of the passivation layer facing away from the semiconductor substrate, the number of remaining first-type tower-shaped structures adjacent to a single first-type tower-shaped structure is greater than the number of second-type tower-shaped structures. In this case, the distribution density of the first-type tower-shaped structures on the side of the passivation layer facing away from the semiconductor substrate is increased, further improving the macroscopic surface smoothness of the surface of the passivation layer facing away from the semiconductor substrate, and further enhancing the formation quality and passivation effect of the passivation layer.

[0012] As a possible implementation scheme, the surface of the passivation layer facing away from the semiconductor substrate is a quasi-rectangular surface. In the quasi-rectangular surface, the areas corresponding to the four corners are the four corner areas, the areas corresponding to the four contour edges are the peripheral areas, and the area located inside the four corner areas and the peripheral areas is the central area. The concave depth of the quasi-pyramid-like texture structure in the peripheral areas is greater than the concave depth of the quasi-pyramid-like texture structure in the central area; and / or the concave depth of the quasi-pyramid-like texture structure in the four corner areas is less than the concave depth of the quasi-pyramid-like texture structure in the central area.

[0013] When the above technical solution is adopted, in the actual manufacturing process, when the passivation layer is deposited on the semiconductor substrate to form the passivation layer, the growth rate of the passivation layer in the peripheral area of ​​the semiconductor substrate is relatively fast, which easily makes the deposition thickness of the passivation layer in the peripheral area larger. In this case, compared with the four corner areas and the middle area of ​​the passivation layer, the concave depth of the tower-like texture structure located in the peripheral area is larger, which is conducive to increasing the specific surface area of ​​the passivation layer located in the peripheral area, and the corresponding target surface of the semiconductor substrate corresponding to the above-mentioned peripheral area also has a relatively large specific surface area. The deposited film thickness of the passivation layer is inversely proportional to the specific surface area of ​​the target surface. Therefore, increasing the specific surface area of ​​the portion of the target surface corresponding to the above-mentioned peripheral area can prevent the thickness of the passivation layer in the peripheral area from being too large due to the high deposition rate, which is conducive to improving the thickness uniformity of different areas of the passivation layer. In addition, due to the influence of operations such as crystal pulling or cutting, the number of defects in the corresponding four corner areas of the semiconductor substrate is relatively large. Secondly, the recessed depth of the tower-like texture structure located in the four corner areas is relatively small, which is beneficial to reducing the surface roughness of the passivation layer in the four corner areas. The target surface of the corresponding semiconductor substrate corresponding to the above-mentioned four corner areas also has a relatively small surface roughness. There is no need to increase the etching depth of the four corner areas in order to obtain the tower-like texture structure with a larger recessed depth. Correspondingly, the number of defects exposed by etching in the corresponding four corner areas of the semiconductor substrate can be reduced, and it is beneficial to improve the formation quality and film thickness of the passivation layer in the four corner areas, and improve the passivation effect of the passivation layer in the four corner areas. The concave depth of the tower-like texture structure in the middle area of ​​the passivation layer is moderate, which can prevent the passivation effect of the passivation layer in the middle area from being affected by the excessive concave depth of the tower-like texture structure in the middle area. It can also prevent the contact area between the part of the doped semiconductor layer corresponding to the middle area and the electrode from being too small due to the excessive concave depth of the tower-like texture structure in the middle area. It further improves the contact performance between the doped semiconductor layer and the electrode, as well as the adhesion and shaping of the electrode on the doped semiconductor layer, so that the passivation effect and contact performance in the middle area are balanced, which is beneficial to improving the conversion efficiency of the solar cell.

[0014] As a possible implementation, the width of the four corner regions along the direction from the four corner vertices of the quasi-rectangular surface to the geometric center of the quasi-rectangular surface is less than or equal to 2 cm. In this case, the four corner regions can be prevented from being too large, which would result in an excessively small contact area between the portion of the doped semiconductor layer near the four corner regions and the electrode, thereby ensuring good contact performance between the doped semiconductor layer and the electrode, and ensuring that the electrode has strong adhesion and good shaping on the portion of the doped semiconductor layer near the four corner regions.

[0015] As a possible implementation, the width of the peripheral region along the direction from the edge of the quasi-rectangular surface to the geometric center is less than or equal to 3 cm. In this case, the width of the peripheral region can be prevented from being too wide, which would result in the passivation layer being deposited too thinly in the central region where the deposition rate is relatively low, thereby ensuring that the passivation layer in the central region has a higher passivation effect.

[0016] As a possible implementation solution, along a direction parallel to the target surface, the concave depth of one side of at least one of the tower base-like texture structures is smaller than the concave depth of the other side thereof.

[0017] When the above technical solution is adopted, in the actual application process, the passivation layer will include a surface passivation layer such as aluminum oxide with a chemical passivation effect, or the above surface passivation layer will be arranged between the passivation layer and the semiconductor substrate to passivate the surface defects of the doped semiconductor layer away from the semiconductor substrate by hydrogen injection, thereby improving the conversion efficiency of the solar cell. Secondly, in order to ensure the passivation effect of the surface passivation layer, the hydrogen content therein is relatively high, which easily leads to the hydrogen in the surface passivation layer overflowing during subsequent high-temperature operations such as sintering of the electrode material, thereby causing the film to burst, and the surface passivation layer at the bursting point is difficult to play a passivation role. In this case, when the concave depth of at least one side of the tower-like texture structure is smaller than the concave depth of the other side, the hydrogen overflowing from the surface passivation layer can escape to other parts through the side with a smaller concave depth of the tower-like texture structure, reducing the risk of film bursting. At the same time, the hydrogen escaping to other parts can also passivate the surface of other parts of the doped semiconductor layer, so that the surface passivation layer has a higher passivation effect, further improving the conversion efficiency of the solar cell.

[0018] As a possible implementation solution, the ratio of the concave depth on one side of at least one pyramid-like texture structure to the concave depth on the other side thereof is greater than or equal to 1.01 and less than 2. In this case, a large ratio of the concave depth on one side of the pyramid-like texture structure to the concave depth on the other side thereof can be prevented, thereby preventing the surface of the passivation layer facing away from the semiconductor substrate from having a large degree of surface undulation. This ensures that the side of the passivation layer facing away from the semiconductor substrate is relatively flat on a macroscopic scale, correspondingly making the target surface relatively flat, thereby improving the formation quality and film thickness of the passivation layer.

[0019] As a possible implementation, at least one quasi-pointed corner is the angle formed by two intersecting straight line segments. In this case, the transition at the quasi-pointed corner is sharper, which helps increase the surface undulation at the quasi-pointed corner, further increasing the specific surface area of ​​the passivation layer facing away from the semiconductor substrate, thereby increasing the contact area between the doped semiconductor layer and the electrode, further improving the contact performance between the doped semiconductor layer and the electrode, as well as the adhesion and shaping of the electrode on the doped semiconductor layer, thereby improving the conversion efficiency of the solar cell.

[0020] As a possible implementation scheme, at least one quasi-sharp corner is a corner with a smooth transition, and the fillet radius corresponding to the quasi-sharp corner is less than or equal to half of the fillet radius corresponding to the quasi-fillet corner. In this case, another example is provided for the morphology of the quasi-sharp corner, which improves the applicability of the solar cell provided by the present invention in different application scenarios and helps to reduce the difficulty of the manufacturing process. In addition, when the quasi-sharp corner is an angle with a relatively small fillet radius, the macroscopic flatness of the passivation layer on the side away from the semiconductor substrate can be further increased, thereby improving the formation quality of the passivation layer on the target surface and the passivation effect.

[0021] As a possible implementation scheme, one of the first surface and the second surface is the target surface. The passivation layer includes a first doped semiconductor layer and a second doped semiconductor layer that are alternately distributed and have opposite conductivity types, and at least a portion of the first doped semiconductor layer and at least a portion of the second doped semiconductor layer are spaced apart. The surface of the passivation layer corresponding to the portion of the first doped semiconductor layer that is away from the semiconductor substrate is the first sub-surface, and the surface of the passivation layer corresponding to the portion of the second doped semiconductor layer that is away from the semiconductor substrate is the second sub-surface. The first type of tower-base-shaped texture structure and the second type of tower-base-shaped texture structure are both distributed on the first sub-surface. The tower-base-shaped texture structure also includes a third type of tower-base-shaped texture structure distributed on the second sub-surface, and the bottom surface of the third type of tower-base-shaped texture structure is a surface with an arc-shaped contour.

[0022] When the above technical solution is adopted, the boundary of the third type of tower-shaped texture structure with an arc-shaped bottom surface is smoother and more blurred, so that the second sub-surface has a relatively higher flatness than the first sub-surface. The conductivity type of the first doped semiconductor layer and the second doped semiconductor layer can be set respectively according to the difference in surface roughness between the first sub-surface and the second sub-surface, the requirements for different passivation effects of the N-doped and P-doped semiconductor layers in actual application scenarios, and the requirements for contact performance between the two and the corresponding electrodes, so that the two parts of the passivation layer corresponding to the first doped semiconductor layer and the second doped semiconductor layer respectively have different passivation effects on the semiconductor substrate, and are conducive to making the first doped semiconductor layer and the second doped semiconductor layer have different surface morphologies, thereby facilitating reducing the passivation difference between the two parts of the passivation layer corresponding to the first doped semiconductor layer and the second doped semiconductor layer respectively, and facilitating reducing the difference in contact performance between the first doped semiconductor layer and the second doped semiconductor layer and the corresponding electrodes.

[0023] As a possible implementation, the tower-base-like texture structure also includes a fourth-type tower-base-like texture structure distributed on the second sub-surface, with the fourth-type tower-base-like texture structure having a polygonal bottom surface. In this case, the second sub-surface can have not only the third-type tower-base-like texture structure but also the fourth-type tower-base-like texture structure. This eliminates the need to strictly control etching conditions to obtain a second sub-surface with only the third-type tower-base-like texture structure, thus reducing the difficulty of the manufacturing process.

[0024] As a possible implementation solution, the conductivity type of the first doped semiconductor layer is P-type, and the conductivity type of the second doped semiconductor layer is N-type.

[0025] When the above technical solution is adopted, due to the limitations of the doping solid concentration (the doping solid concentration refers to the limit doping concentration) and the difficulty of doping, the doping concentration of the dopant in the N-type doped semiconductor layer is greater than the doping concentration of the dopant in the P-type doped semiconductor layer, and the contact performance between the P-type doped semiconductor layer and the positive electrode is relatively poor. Based on this, when the conductivity type of the first doped semiconductor layer is P-type, and the first sub-surface of the passivation layer corresponding to the first doped semiconductor layer on the side away from the semiconductor substrate is provided with a first type of tower-shaped texture structure and a second type of tower-shaped texture structure, the presence of the sharp corners in the bottom surface of the second type of tower-shaped texture structure is conducive to increasing the specific surface area of ​​the P-type doped semiconductor layer on the side away from the semiconductor substrate, increasing the contact area between the P-type doped semiconductor layer and the positive electrode, improving the contact performance between the P-type doped semiconductor layer and the positive electrode, and the adhesion and shaping of the positive electrode on the P-type doped semiconductor layer, which is conducive to improving the conversion efficiency of the solar cell.

[0026] As a possible implementation solution, the one-dimensional size of the bottom surface of the tower base-like texture structure on the first sub-surface is smaller than the one-dimensional size of the bottom surface of the tower base-like texture structure on the second sub-surface.

[0027] When adopting the above technical solution, it can be understood that the larger the one-dimensional size of the bottom surface of the tower-like base-shaped texture structure, the larger the bottom area of ​​the tower-like base-shaped texture structure. Within the same area, the fewer the number of tower-like base-shaped texture structures that can be set, and the lower the distribution density. Based on this, when the one-dimensional size of the bottom surface of the tower-like base-shaped texture structure located on the first sub-surface is small, it is beneficial to increase the surface roughness of the first sub-surface, further increase the contact area between the first doped semiconductor layer and the electrode, improve the contact performance between the first doped semiconductor layer and the electrode, and the adhesion and shaping of the electrode on the first doped semiconductor layer, which is beneficial to improve the conversion efficiency of the solar cell.

[0028] As a possible implementation solution, the one-dimensional size of the bottom surface of the tower base-like texture structure located on the first sub-surface is greater than or equal to 7 μm and less than or equal to 15 μm.

[0029] When using the above technical solution, the one-dimensional dimension of the bottom surface of the quasi-pyramid-shaped texture structure on the first sub-surface is within the above-mentioned range. This helps prevent the surface roughness of the passivation layer on the side facing away from the semiconductor substrate from being too large due to the one-dimensional dimension being too small, ensuring a macroscopically smooth surface on the target surface, further improving the formation quality and passivation effect of the passivation layer on the target surface. Furthermore, it can also prevent the surface roughness of the passivation layer on the side facing away from the semiconductor substrate from being too small due to the one-dimensional dimension being too large, ensuring a larger contact area between the doped semiconductor layer and the electrode, further improving the contact performance between the doped semiconductor layer and the electrode.

[0030] As a possible implementation, the one-dimensional size of the bottom surface of the tower-like base-shaped texture structure on the second sub-surface is greater than or equal to 5 μm and less than or equal to 30 μm. The application principle of the beneficial effect in this case can refer to the application principle of the beneficial effect of the one-dimensional size of the bottom surface of the tower-like base-shaped texture structure on the first sub-surface being greater than or equal to 7 μm and less than or equal to 15 μm described above, and will not be repeated here.

[0031] In a second aspect, the present invention provides a photovoltaic module, which includes the solar cell according to the first aspect and various implementations thereof.

[0032] The beneficial effects of the second aspect of the present invention and its various implementations can be analyzed with reference to the beneficial effects of the first aspect and its various implementations, and will not be repeated here.

[0033] In a third aspect, the present invention provides a semiconductor substrate comprising a first surface and a second surface relative to each other. At least one of the first surface and the second surface is a target surface. The target surface has a plurality of tower-like texture structures recessed into the semiconductor substrate. The plurality of tower-like texture structures include a first-type tower-like texture structure and a second-type tower-like texture structure. The corners in the bottom surface of the first-type tower-like texture structure are all quasi-rounded corners, and the bottom surface of the second-type tower-like texture structure includes some corners that are quasi-rounded corners and the remaining corners are quasi-sharp corners. In the bottom surface of the same second-type tower-like texture structure, the number of quasi-rounded corners is greater than the number of quasi-sharp corners.

[0034] The beneficial effects of the third aspect of the present invention and its various implementations can be analyzed with reference to the beneficial effects of the first aspect and its various implementations, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0036] Figure 1A schematic longitudinal cross-sectional view of a first structure of a solar cell provided by an embodiment of the present invention;

[0037] Figure 2 A schematic longitudinal cross-sectional view of a second structure of a solar cell provided by an embodiment of the present invention;

[0038] Figure 3 A schematic longitudinal cross-sectional view of a third structure of a solar cell provided by an embodiment of the present invention;

[0039] Figure 4 This is a SEM image of a local surface of the passivation layer facing away from the semiconductor substrate in an embodiment of the present invention. Figure 1 ;

[0040] Figure 5 This is a SEM image of a local surface of the passivation layer facing away from the semiconductor substrate in an embodiment of the present invention. Figure 2 ;

[0041] Figure 6 This is a SEM image of a local surface of the passivation layer facing away from the semiconductor substrate in an embodiment of the present invention. Figure 3 ;

[0042] Figure 7 A schematic longitudinal cross-sectional view of a fourth structure of a solar cell provided by an embodiment of the present invention;

[0043] Figure 8 A schematic longitudinal cross-sectional view of a fifth structure of a solar cell provided by an embodiment of the present invention;

[0044] Figure 9 A schematic longitudinal cross-sectional view of a sixth structure of a solar cell provided by an embodiment of the present invention;

[0045] Figure 10 A longitudinal SEM image of the local structure of a solar cell provided by an embodiment of the present invention Figure 1 ;

[0046] Figure 11 A longitudinal SEM image of the local structure of a solar cell provided by an embodiment of the present invention Figure 2 ;

[0047] Figure 12 A longitudinal SEM image of the local structure of a solar cell provided by an embodiment of the present invention Figure 3 ;

[0048] Figure 13 A longitudinal SEM image of the local structure of a solar cell provided by an embodiment of the present invention Figure 4 ;

[0049] Figure 14This is a SEM image of a local surface of the passivation layer facing away from the semiconductor substrate in an embodiment of the present invention. Figure 4 ;

[0050] Figure 15 This is a SEM image of a local surface of the passivation layer facing away from the semiconductor substrate in an embodiment of the present invention. Figure 5 .

[0051] Figure numerals: 11 is a semiconductor substrate, 12 is a first surface, 13 is a second surface, 14 is a passivation layer, 15 is a first type of tower-like texture structure, 16 is a second type of tower-like texture structure, 17 is a rounded corner, 18 is a sharp corner, 19 is a first doped semiconductor layer, 20 is a second doped semiconductor layer, 21 is a third type of tower-like texture structure, 22 is a fourth type of tower-like texture structure, 23 is a doped semiconductor layer, 24 is an interface passivation layer, 25 is a surface passivation layer, 26 is an anti-reflection layer, and 27 is a transparent conductive layer. DETAILED DESCRIPTION

[0052] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely exemplary and are not intended to limit the scope of the present invention. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessary confusion of the concepts of the present invention.

[0053] The accompanying drawings illustrate various structural schematics according to embodiments of the present invention. These figures are not drawn to scale; certain details are exaggerated and may be omitted for clarity. The shapes of the various regions and layers shown in the figures, as well as their relative sizes and positions, are merely exemplary and may deviate in practice due to manufacturing tolerances or technical limitations. Those skilled in the art may design regions / layers with different shapes, sizes, and relative positions as needed.

[0054] In the context of the present invention, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element, or an intervening layer / element may exist between them. Furthermore, if a layer / element is "on" another layer / element in one orientation, it may be "below" the other layer / element when the orientation is reversed. To further clarify the technical problems, technical solutions, and beneficial effects of the present invention, the present invention is further described below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are intended solely to illustrate the present invention and are not intended to limit the present invention.

[0055] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Thus, a feature specified as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, "plurality" means two or more, unless otherwise specifically defined. "Several" means one or more, unless otherwise specifically defined.

[0056] In the description of the present invention, it should be noted that, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood in a broad sense. For example, they may refer to fixed, detachable, or integral connections; mechanical or electrical connections; direct or indirect connections through an intermediate medium; and may encompass internal communication between two components or interaction between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on specific circumstances.

[0057] As a green energy source, solar cells play a positive role in energy conservation and emission reduction. With the development of the photovoltaic industry, solar cell technology has become increasingly mature. Photovoltaic solar cells are devices that convert sunlight into electrical energy. Specifically, solar cells utilize the photovoltaic principle to generate charge carriers and then use electrodes to extract these charge carriers, thereby facilitating the efficient use of electrical energy. As an environmentally friendly and renewable energy source, solar energy has garnered increasing attention in recent years. Consequently, the application range of photovoltaic solar cells, which are based on the photoelectric effect, has also expanded.

[0058] Specifically, existing solar cells typically include a semiconductor substrate and a passivation layer formed on the semiconductor substrate. The passivation layer may include a doped semiconductor layer with field passivation, or may include at least one of a surface passivation layer with chemical passivation, an anti-reflection layer, and a transparent conductive layer. The surface of the semiconductor substrate on which the passivation layer is formed may be polished, and the bottom surfaces of the textured structures on the polished surface may have a smooth, elliptical or other contoured bottom surface. In this case, the excessively flat surface morphology improves the formation quality of the passivation layer and enhances its passivation effect on the semiconductor substrate. However, a passivation layer formed on a flat semiconductor substrate also tends to have a flat surface. This results in poor shaping and adhesion of the electrode material to the flat surface when forming an electrode for carrier conduction on the passivation layer, thereby reducing the selection and matching of the electrode material. Furthermore, this reduces the contact area between the formed electrode and the doped semiconductor layer formed on the flat surface, increasing contact loss. Although the pyramid-shaped velvet surface with its undulating morphology has a relatively high surface roughness, which is beneficial for improving the electrical contact between the electrode and the doped semiconductor layer, as well as the shaping and adhesion of the electrode, the pyramid-shaped velvet surface has a large undulating surface morphology and is too sharp, resulting in poor formation of the doped semiconductor layer on the velvet surface, and its passivation effect is reduced. Therefore, existing solar cells cannot achieve both good passivation effect and good electrode contact performance and shaping, which is not conducive to improving the conversion efficiency of solar cells.

[0059] In order to solve the above technical problems, in the first aspect, an embodiment of the present invention provides a solar cell. Figures 1 to 6 As shown, the solar cell provided by the embodiment of the present invention includes: a semiconductor substrate 11 and a passivation layer 14. The semiconductor substrate 11 includes a first surface 12 and a second surface 13 opposite to each other. At least one of the first surface 12 and the second surface 13 is a target surface. The passivation layer 14 is arranged on the target surface. Part of the surface of the passivation layer 14 on the side facing away from the semiconductor substrate 11 has a plurality of tower-like texture structures that are concave toward the side close to the semiconductor substrate 11. Among them, the plurality of tower-like texture structures include a first-type tower-like texture structure 15 and a second-type tower-like texture structure 16. The corners in the bottom surface of the first-type tower-like texture structure 15 are all rounded corners 17, and the bottom surface of the second-type tower-like texture structure 16 includes some corners that are rounded corners 17 and the remaining corners are sharp corners 18. In the bottom surface of the same second-type tower-like texture structure 16, the number of rounded corners 17 is greater than or equal to the number of sharp corners 18.

[0060] When the above technical solution is adopted, Figures 1 to 6As shown, a passivation layer 14 is disposed on the target surface of the semiconductor substrate 11, passivating the target surface side of the semiconductor substrate 11 and reducing the carrier recombination rate. Furthermore, the side of the passivation layer 14 facing away from the semiconductor substrate 11 has multiple apex-like texture structures. With other factors remaining the same, compared to texture structures with greater undulation, such as pyramid-shaped velvet structures, apex-like texture structures without apex-like ridges have relatively less undulation. Furthermore, each corner on the bottom surface of the first-type apex-like texture structure 15, as well as most corners on the bottom surface of the second-type apex-like texture structure 16, are rounded corners 17. Compared to sharp corners 18, the rounded corners 17 on the bottom surface are smoother and flatter, resulting in a more gradual and blurred transition at the edges of the apex-like texture structures at the rounded corners 17. This results in a relatively flat surface from a macroscopic perspective on the side of the passivation layer 14 facing away from the semiconductor substrate 11. Furthermore, during the actual manufacturing process, the passivation layer 14 is formed on the target surface of the semiconductor substrate 11 through processes such as deposition. The surface undulation of the passivation layer 14 on the side facing away from the semiconductor substrate 11 is also affected by the surface undulation of the target surface. Accordingly, the surface undulation of the passivation layer 14 on the side facing away from the semiconductor substrate 11 can, to a certain extent, also reflect the surface undulation of the target surface of the semiconductor substrate 11. Therefore, when the surface of the passivation layer 14 on the side facing away from the semiconductor substrate 11 is relatively flat macroscopically, the target surface of the semiconductor substrate 11 is also generally flat, which helps improve the formation quality and film thickness of the passivation layer 14 on the target surface, thereby improving the passivation effect of the passivation layer 14 on the semiconductor substrate 11 and enhancing the conversion efficiency of the solar cell. Furthermore, the bottom surface of the second-type tower-shaped texture structure 16 also includes quasi-pointed corners 18. Compared to the quasi-rounded corners 17, the quasi-pointed corners 18 have a more pronounced transition and a greater degree of undulation, which helps increase the specific surface area of ​​the passivation layer 14 on the side facing away from the semiconductor substrate 11. Moreover, in the bottom surface of the same second-type tower-shaped texture structure 16, the number of sharp corners 18 is greater than or equal to the number of rounded corners 17, ensuring that the side of the passivation layer 14 facing away from the semiconductor substrate 11 is macroscopically flat, while making the side of the passivation layer 14 facing away from the semiconductor substrate 11 have a relatively large surface roughness at the microscopic level, so that the doped semiconductor layer included in the passivation layer 14, or the doped semiconductor layer formed between the passivation layer 14 and the semiconductor substrate 11 has a larger specific surface area, thereby increasing the contact area between the doped semiconductor layer and the electrode, improving the contact performance between the doped semiconductor layer and the electrode, and the adhesion and shaping of the electrode on the doped semiconductor layer, which is beneficial to improving the conversion efficiency of the solar cell.

[0061] In actual applications, the solar cell provided by the embodiments of the present invention can be a double-sided contact cell, that is, one of the positive electrode and the negative electrode of the solar cell is arranged on the front side of the cell, and the other is arranged on the back side of the cell. Alternatively, the solar cell provided by the embodiments of the present invention can also be a back-contact cell, that is, both the positive electrode and the negative electrode of the solar cell are arranged on the back side of the cell.

[0062] Secondly, the solar cell provided by the embodiment of the present invention may be a cell having a tunneling passivation contact structure or a heterogeneous contact structure; or it may be a conventional solar cell without the interface passivation layer included in the above structure.

[0063] Specifically, the embodiment of the present invention does not impose any specific limitation on the material of the semiconductor substrate. For example, the semiconductor substrate can be a substrate made of any semiconductor material, such as a silicon substrate, a silicon-germanium substrate, a germanium substrate, or a gallium arsenide substrate.

[0064] Regarding the first and second surfaces of the semiconductor substrate, the first surface of the semiconductor substrate can correspond to the front surface of the solar cell, in which case the second surface of the semiconductor substrate can correspond to the back surface of the solar cell; alternatively, the first surface of the semiconductor substrate can correspond to the back surface of the solar cell, in which case the second surface of the semiconductor substrate corresponds to the front surface of the solar cell. Whether the first and second surfaces are target surfaces can be determined based on the type of solar cell and the corresponding relationship between the first and second surfaces and the front and back surfaces of the solar cell, respectively, and is not specifically limited here.

[0065] For example, in the case where the solar cell is a double-sided contact cell, of the first and second surfaces of the semiconductor substrate, only the first surface may be the target surface, only the second surface may be the target surface, or both the first and second surfaces may be the target surface.

[0066] For example, in the case where the solar cell is a back-contact cell, one of the first surface and the second surface of the semiconductor substrate corresponding to the back surface of the cell is the target surface.

[0067] As for the surface topography of the target surface of the semiconductor substrate, as previously mentioned, the surface undulations of the passivation layer on the side facing away from the semiconductor substrate can, to a certain extent, reflect the surface undulations of the target surface of the semiconductor substrate. Therefore, the surface topography of the target surface can be referenced to the surface topography of the passivation layer on the side facing away from the semiconductor substrate. Specifically, because the surface topography of the passivation layer on the side facing away from the semiconductor substrate is a macroscopically flat surface with multiple pyramid-like texture structures, the surface topography of the target surface is also relatively flat macroscopically.

[0068] Exemplarily, the target surface may have a plurality of tower-base-like texture structures that are recessed into the semiconductor substrate. The plurality of tower-base-like texture structures include a first-type tower-base-like texture structure and a second-type tower-base-like texture structure. The corners in the bottom surface of the first-type tower-base-like texture structure are all quasi-rounded corners, and the bottom surface of the second-type tower-base-like texture structure includes some corners that are quasi-rounded corners, and the remaining corners are quasi-pointed corners. In the bottom surface of the same second-type tower-base-like texture structure, the number of quasi-rounded corners is greater than the number of quasi-pointed corners. In this case, compared with texture structures with a large degree of undulation, such as pyramid-type velvet structures, the degree of undulation of the tower-base-like texture structure without a spire is relatively small. Moreover, the corners in the bottom surface of the first-type tower-base-like texture structure included in the plurality of tower-base-like texture structures, and most of the corners in the bottom surface of the second-type tower-base-like texture structure are all quasi-rounded corners. Compared with the quasi-pointed corners, the quasi-rounded corner transition of the bottom surface is smoother and flatter, making the boundary transition of the quasi-rounded corners of the tower-like texture structure more gentle and blurred, so that the target surface of the semiconductor substrate is a relatively flat surface, which is conducive to improving the formation quality and film thickness of the passivation layer on the target surface, thereby improving the passivation effect of the passivation layer on the semiconductor substrate and improving the conversion efficiency of the solar cell. In addition, the bottom surface of the second type of tower-like texture structure also includes quasi-pointed corners. Compared with the quasi-rounded corners, the transition of the quasi-pointed corners is relatively obvious, and its undulation is greater, which is conducive to making the doped semiconductor layer formed on the target surface by deposition and other processes also have a relatively large specific surface area, thereby increasing the contact area between the doped semiconductor layer and the electrode, improving the contact performance between the doped semiconductor layer and the electrode, and the adhesion and shaping of the electrode on the doped semiconductor layer, which is conducive to improving the conversion efficiency of the solar cell. As for the specific morphology of the tower-like texture structure on the target surface, the distribution density and one-dimensional size of the first type of tower-like texture structure and the second type of tower-like texture structure, you can refer to the specific morphology of the tower-like texture structure on the side of the passivation layer away from the semiconductor substrate, the distribution density and one-dimensional size of the first type of tower-like texture structure and the second type of tower-like texture structure below, which will not be repeated here.

[0069] The passivation layer is disposed on the target surface, with the surface of the passivation layer facing away from the semiconductor substrate serving as the front and / or back surface of the solar cell. The specific structure and materials of the passivation layer can be determined based on the type of solar cell and the actual application scenario, and are not specifically limited here. Exemplarily, the passivation layer may include at least one of an interface passivation layer, a doped semiconductor layer, a surface passivation layer, an anti-reflection layer, and a transparent conductive layer.

[0070] Among them, Figures 1 to 3As shown, when the passivation layer 14 is merely a doped semiconductor layer, a pyramid-like texture structure is formed on the side of the doped semiconductor layer facing away from the semiconductor substrate 11. The material of the passivation layer 14 can include any semiconductor material such as silicon, silicon germanium, or germanium. The crystalline phase of the passivation layer 14 can be single crystal, polycrystalline, microcrystalline, nanocrystalline, or amorphous.

[0071] like Figures 4 to 7 As shown, when the passivation layer 14 includes only a surface passivation layer 25, an anti-reflection layer 26, and at least one of a transparent conductive layer, a tower-like texture structure is formed on the outermost layer of the passivation layer 14 (i.e., the layer with the greatest distance from the semiconductor substrate 11 along the thickness of the cell), on the side of the surface facing away from the semiconductor substrate 11. For example, when the passivation layer 14 includes only a surface passivation layer 25 and an anti-reflection layer 26, and the anti-reflection layer 26 is disposed on the side of the surface passivation layer 25 facing away from the semiconductor substrate 11, the tower-like texture structure is formed on the side of the anti-reflection layer 26 facing away from the semiconductor substrate 11. Furthermore, the materials of the surface passivation layer 25, anti-reflection layer 26, and transparent conductive layer can be configured according to actual needs. For example, the material of the surface passivation layer 25 can include any passivating material such as silicon oxide, aluminum oxide, silicon nitride, or silicon oxynitride. The material of the anti-reflection layer 26 can include silicon nitride or silicon oxynitride, etc. The material of the transparent conductive layer may include at least one of fluorine-doped tin oxide, aluminum-doped zinc oxide, tin-doped indium oxide, tungsten-doped indium oxide, molybdenum-doped indium oxide, cerium-doped indium oxide, and indium hydroxide. In the above case, the solar cell provided by the embodiment of the present invention further includes a doped semiconductor layer 23 disposed in or on the target surface (when the doped semiconductor layer 23 is disposed on the target surface, the material of the doped semiconductor layer 23 can be referred to above and will not be described again here), and the passivation layer 14 is located on the side of the doped semiconductor layer 23 facing away from the semiconductor substrate 11.

[0072] like Figures 4 to 6 ,as well as Figure 8 As shown, when the passivation layer 14 includes at least one of a surface passivation layer, an anti-reflection layer, and a transparent conductive layer 27 in addition to the doped semiconductor layer 23, the tower-like texture structure is formed on the outermost layer of the passivation layer 14 (i.e., the layer with the largest distance from the semiconductor substrate 11 along the thickness of the cell), on the surface facing away from the semiconductor substrate 11. For example, when the passivation layer 14 includes only the doped semiconductor layer 23 and the transparent conductive layer 27, and the transparent conductive layer 27 is disposed on the side of the doped semiconductor layer 23 facing away from the semiconductor substrate 11, the tower-like texture structure is formed on the side of the transparent conductive layer 27 facing away from the semiconductor substrate 11. Furthermore, the formation position of the doped semiconductor layer 23 in the above-mentioned solar cell, as well as the materials of the surface passivation layer, anti-reflection layer, transparent conductive layer 27, and doped semiconductor layer 23 can be referred to above and will not be repeated here.

[0073] It should be noted that, when the solar cell provided in the embodiment of the present invention is a double-sided contact cell and the passivation layer includes a doped semiconductor layer, the doped semiconductor layer in the same passivation layer is an N-type doped semiconductor layer or a P-type doped semiconductor layer. When the solar cell is a back contact cell and the passivation layer includes a doped semiconductor layer, as Figure 9 As shown, along a direction parallel to the target surface, the doped semiconductor layer in the passivation layer 14 includes alternating first doped semiconductor layers 19 and second doped semiconductor layers 20, and at least a portion of the first doped semiconductor layer 19 is spaced apart from at least a portion of the second doped semiconductor layer 20. Specifically, at least a portion of the first doped semiconductor layer 19 and at least a portion of the second doped semiconductor layer 20 can be spaced apart along a direction parallel to the target surface, or can be spaced apart along the thickness direction of the semiconductor substrate 11 by a dielectric layer made of an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride.

[0074] In addition, when the doped semiconductor layer is disposed on the target surface, as Figure 8 As shown, the doped semiconductor layer 23 may be in direct contact with the semiconductor substrate 11; or Figure 9 As shown, the solar cell may further include an interface passivation layer 24 positioned between the semiconductor substrate 11 and the doped semiconductor layer. The material and thickness of the interface passivation layer 24 can be determined based on the material of the doped semiconductor layer and are not specifically limited herein. For example, when the doped semiconductor layer comprises a doped polycrystalline silicon layer, the interface passivation layer is a tunneling oxide layer. For another example, when the doped semiconductor layer comprises a doped amorphous silicon layer, the interface passivation layer is an intrinsic amorphous silicon layer.

[0075] In terms of surface morphology, the bottom surfaces of the first type of tower-shaped texture structure and the second type of tower-shaped texture structure on the surface of the passivation layer facing away from the semiconductor substrate can be regular or irregular polygonal bottom surfaces (such as quadrilateral bottom surfaces, pentagonal bottom surfaces, hexagonal bottom surfaces or octagonal bottom surfaces, etc.). The polygons can be regular polygons with the same side lengths or polygons with different side lengths. Figures 4 to 6 As shown, the corners of the bottom surface of the first type of tower base-shaped texture structure 15 are all rounded corners 17. The corners of the bottom surface of the second type of tower base-shaped texture structure 16 are partly rounded corners 17, and the rest are sharp corners 18. Figure 4As shown, at least one quasi-tip corner 18 can be the angle formed by two intersecting straight line segments. In this case, the transition at the quasi-tip corner 18 is relatively sharp, which helps to increase the surface undulation at the quasi-tip corner 18, further increasing the specific surface area of ​​the side of the passivation layer facing away from the semiconductor substrate, thereby increasing the contact area between the doped semiconductor layer and the electrode, further improving the contact performance between the doped semiconductor layer and the electrode, as well as the adhesion and shaping of the electrode on the doped semiconductor layer, and thus improving the conversion efficiency of the solar cell.

[0076] Or, as Figures 4 to 6 As shown, at least one of the quasi-pointed corners 18 can also be a corner with a smooth transition and a smaller fillet radius. Specifically, the size of the fillet radius corresponding to the quasi-pointed corner in this case can be determined based on the requirements for the contact performance between the doped semiconductor layer and the electrode, as well as the adhesion and shaping of the electrode on the doped semiconductor layer in actual applications. For example, the fillet radius corresponding to the quasi-pointed corner 18 can be less than or equal to half of the fillet radius corresponding to the quasi-fillet 17 (such as the ratio between the fillet radius corresponding to the quasi-pointed corner 18 and the fillet radius corresponding to the above-mentioned quasi-fillet 17 can be one-half, one-third, one-quarter, one-fifth, one-sixth or one-seventh, etc.). In this case, another example is provided for the morphology of the quasi-pointed corner 18, which improves the applicability of the solar cell provided by the embodiment of the present invention in different application scenarios and helps to reduce the difficulty of the manufacturing process. In addition, when the quasi-pointed corner 18 is an angle with a relatively small fillet radius, the macroscopic flatness of the passivation layer on the side away from the semiconductor substrate can be further increased, thereby improving the formation quality and passivation effect of the passivation layer on the target surface. The sizes of the fillet radii corresponding to the sharp corners 18 and the rounded corners 17 can be determined according to the one-dimensional size of the bottom surfaces of the first and second tower base-shaped texture structures 15 and 16 and actual needs, and are not specifically limited here.

[0077] Specifically, the one-dimensional size and recessed depth of the bottom surfaces of the above-mentioned first-type tower-base-shaped texture structure and the second-type tower-base-shaped texture structure, as well as the distribution of the first-type tower-base-shaped texture structure and the second-type tower-base-shaped texture structure on the side of the passivation layer away from the semiconductor substrate, can be determined according to the requirements for the surface roughness of the passivation layer on the side away from the semiconductor substrate in the actual application scenario, as long as they can be applied to the solar cell provided in the embodiment of the present invention. Among them, the one-dimensional size of the bottom surfaces of the first-type tower-base-shaped texture structure and the second-type tower-base-shaped texture structure can be the bottom side length (bottom arc segment length), bottom diagonal length or fillet radius length corresponding to the fillet, etc. Secondly, the recessed depth of the first-type tower-base-shaped texture structure and the second-type tower-base-shaped texture structure is the recessed depth relative to the main surface of the passivation layer on the side away from the semiconductor substrate.

[0078] Exemplarily, the one-dimensional size of the bottom surface of the first type of tower-like texture structure and / or the second type of tower-like texture structure can be greater than or equal to 7μm and less than or equal to 15μm. For example, the one-dimensional size of the bottom surface of the tower-like texture structure can be 7μm, 7.5μm, 8μm, 9μm, 10μm, 11μm, 12μm, 13μm, 14μm, or 15μm, etc. In this case, the one-dimensional size of the bottom surface of the first type of tower-like texture structure and / or the second type of tower-like texture structure is within the above range, which helps prevent the surface roughness of the passivation layer on the side facing away from the semiconductor substrate from being too large due to the one-dimensional size being too small, ensuring that the target surface is a macroscopically flat surface, further improving the formation quality and passivation effect of the passivation layer on the target surface. In addition, it can also prevent the surface roughness of the passivation layer on the side facing away from the semiconductor substrate from being too small due to the large one-dimensional size, ensuring that the above-mentioned doped semiconductor layer has a large contact area with the electrode, further improving the contact performance between the doped semiconductor layer and the electrode.

[0079] As for the concave depth of the base-like texture structure, the concave depths of different regions of at least one base-like texture structure may be substantially the same along a direction parallel to the target surface. Figure 10 As shown, along the direction parallel to the target surface, the concave depth of at least one side of the tower-like texture structure can be smaller than the concave depth of the other side. In this case, in actual application, the passivation layer will include a surface passivation layer such as aluminum oxide with a chemical passivation effect, or the above-mentioned surface passivation layer will be arranged between the passivation layer and the semiconductor substrate to passivate the surface defects of the doped semiconductor layer away from the semiconductor substrate by hydrogen injection, thereby improving the conversion efficiency of the solar cell. Secondly, in order to ensure the passivation effect of the surface passivation layer, the hydrogen content therein is relatively high, which easily leads to the overflow of hydrogen in the surface passivation layer during subsequent high-temperature operations such as sintering of the electrode material, thereby causing the film to burst, and the surface passivation layer at the burst site is difficult to play a passivation role. In this case, when the concave depth of at least one side of the tower-like texture structure is smaller than the concave depth of the other side, hydrogen overflowing from the surface passivation layer can escape through the side of the tower-like texture structure with the smaller concave depth to other parts, reducing the risk of film explosion. While the hydrogen escaping to other parts can also passivate the surface of other parts of the doped semiconductor layer, the surface passivation layer has a higher passivation effect, further improving the conversion efficiency of the solar cell. As for the difference in concave depth on both sides of the same tower-like texture structure, it can be determined according to actual needs and is not subject to specific restrictions here.

[0080] For example, the ratio of the concave depth on one side of at least one of the tower-like base-shaped texture structures to the concave depth on the other side thereof can be greater than or equal to 1.01 and less than 2. For example, the ratio of the concave depth on one side of at least one of the tower-like base-shaped texture structures to the concave depth on the other side thereof can be 1.01, 1.1, 1.2, 1.3, 1.4, 1.5, 1.6, 1.7, 1.8, or 1.9, etc. In this case, a large ratio of the concave depth on one side of the tower-like base-shaped texture structure to the concave depth on the other side thereof can be prevented, thereby preventing the surface of the passivation layer facing away from the semiconductor substrate from having a large undulation. This ensures that the side of the passivation layer facing away from the semiconductor substrate is relatively flat on a macroscopic scale, correspondingly making the target surface relatively flat, thereby improving the formation quality and film thickness of the passivation layer.

[0081] Furthermore, the recessed depths in different regions of the passivation layer surface facing away from the semiconductor substrate may be the same or different. When the recessed depths in different regions of the passivation layer surface facing away from the semiconductor substrate are different, the relative depths of the pyramid-like texture structures in different regions may be determined based on the shape of the passivation layer surface facing away from the semiconductor substrate and actual needs.

[0082] For example, when the surface of the passivation layer facing away from the semiconductor substrate is a rectangular surface, the corresponding areas of the four corners in the rectangular surface are defined as the four corner areas, the corresponding areas of the four contour edges are defined as the peripheral areas, and the area located inside the four corner areas and the peripheral areas is defined as the middle area. Figure 11 and Figure 12 As shown, the concave depth of the tower-like base-shaped texture structure located in the peripheral area can be greater than the concave depth of the tower-like base-shaped texture structure located in the central area; and / or Figure 12 and Figure 13 As shown, the concave depth of the tower-like texture structure located in the four corner areas may be smaller than the concave depth of the tower-like texture structure located in the middle area.

[0083] When the above technical solution is adopted, in the actual manufacturing process, when the passivation layer is deposited on the semiconductor substrate to form the passivation layer, the growth rate of the passivation layer in the peripheral area of ​​the semiconductor substrate is relatively fast, which easily makes the deposition thickness of the passivation layer in the peripheral area larger. In this case, compared with the four corner areas and the middle area of ​​the passivation layer, the concave depth of the tower-like texture structure located in the peripheral area is larger, which is conducive to increasing the specific surface area of ​​the passivation layer located in the peripheral area, and the corresponding target surface of the semiconductor substrate corresponding to the above-mentioned peripheral area also has a relatively large specific surface area. The deposited film thickness of the passivation layer is inversely proportional to the specific surface area of ​​the target surface. Therefore, increasing the specific surface area of ​​the portion of the target surface corresponding to the above-mentioned peripheral area can prevent the thickness of the passivation layer in the peripheral area from being too large due to the high deposition rate, which is conducive to improving the thickness uniformity of different areas of the passivation layer. In addition, due to the influence of operations such as crystal pulling or cutting, the number of defects in the corresponding four corner areas of the semiconductor substrate is relatively large. Secondly, the recessed depth of the tower-like texture structure located in the four corner areas is relatively small, which is beneficial to reducing the surface roughness of the passivation layer in the four corner areas. The target surface of the corresponding semiconductor substrate corresponding to the above-mentioned four corner areas also has a relatively small surface roughness. There is no need to increase the etching depth of the four corner areas in order to obtain the tower-like texture structure with a larger recessed depth. Correspondingly, the number of defects exposed by etching in the corresponding four corner areas of the semiconductor substrate can be reduced, and it is beneficial to improve the formation quality and film thickness of the passivation layer in the four corner areas, and improve the passivation effect of the passivation layer in the four corner areas. The concave depth of the tower-like texture structure in the middle area of ​​the passivation layer is moderate, which can prevent the passivation effect of the passivation layer in the middle area from being affected by the excessive concave depth of the tower-like texture structure in the middle area. It can also prevent the contact area between the part of the doped semiconductor layer corresponding to the middle area and the electrode from being too small due to the excessive concave depth of the tower-like texture structure in the middle area. It further improves the contact performance between the doped semiconductor layer and the electrode, as well as the adhesion and shaping of the electrode on the doped semiconductor layer, so that the passivation effect and contact performance in the middle area are balanced, which is beneficial to improving the conversion efficiency of the solar cell.

[0084] Among them, the scope of the four corner areas, peripheral areas and central areas of the passivation layer facing away from the semiconductor substrate can be determined according to the formation quality of different areas of the semiconductor substrate in the actual application scenario, as well as the passivation effect and specific surface area requirements at different positions of the passivation layer. No specific limitation is made here.

[0085] For example, along the direction from the four corner vertices of the quasi-rectangular surface to the geometric center of the quasi-rectangular surface, the width of the four corner regions can be less than or equal to 2 cm. For example, the width of the four corner regions can be 0.5 cm, 0.8 cm, 1 cm, 1.2 cm, 1.5 cm, 1.8 cm, or 2 cm. In this case, it is possible to prevent the four corner regions from being too large, which would result in a small contact area between the doped semiconductor layer near the four corner regions and the electrode, thereby ensuring good contact performance between the doped semiconductor layer and the electrode, and ensuring that the electrode has strong adhesion and good shaping on the portion of the doped semiconductor layer near the four corner regions.

[0086] For example, the width of the peripheral area along the direction from the edge of the quasi-rectangular surface to the geometric center can be less than or equal to 3 cm. For example, the width of the peripheral area can be 0.5 cm, 0.8 cm, 1 cm, 1.2 cm, 1.5 cm, 1.8 cm, 2 cm, 2.2 cm, 2.5 cm, 2.8 cm, or 3 cm. In this case, it is possible to prevent the width of the peripheral area from being too large, which would result in the deposition thickness of the passivation layer being too small in the central area where the deposition rate is relatively low, thereby ensuring that the passivation layer in the central area has a higher passivation effect.

[0087] As for the distribution density of the first type of tower-shaped texture structure and the second type of tower-shaped texture structure on the side of the same passivation layer facing away from the semiconductor substrate, since the corners in the bottom surface of the first type of tower-shaped texture structure are all quasi-rounded corners, the proportion of quasi-rounded corners in its bottom surface is relatively large compared to the proportion of quasi-rounded corners in the second type of tower-shaped texture structure. Moreover, as mentioned above, compared with quasi-pointed corners, the quasi-rounded corner transition on the bottom surface is smoother and flatter, which helps to reduce the specific surface area of ​​the side of the passivation layer facing away from the semiconductor substrate. However, some of the corners in the bottom surface of the second type of tower-shaped texture structure are quasi-pointed corners, and the transition of the quasi-pointed corners is relatively obvious, and its undulation is greater, which helps to increase the specific surface area of ​​the side of the passivation layer facing away from the semiconductor substrate. In the above case, the distribution density of the first type of tower-shaped texture structure and the second type of tower-shaped texture structure, as well as the distribution number of quasi-rounded corners and quasi-pointed corners on the bottom surface of the second type of tower-shaped texture structure, can be determined according to the requirements for the specific surface area of ​​the passivation layer facing away from the semiconductor substrate in the actual application scenario.

[0088] For example, Figure 4 As shown, on the side of the same passivation layer facing away from the semiconductor substrate, the distribution density of the first type of tower-shaped texture structures 15 can be greater than the distribution density of the second type of texture structures. This arrangement further improves the macroscopic surface smoothness of the side of the passivation layer 14 facing away from the semiconductor substrate 11, further enhancing the formation quality and passivation effect of the passivation layer 14.

[0089] For example, in the surface of the area of ​​the passivation layer facing away from the semiconductor substrate having the first-type tower-shaped texture structure and the second-type tower-shaped texture structure, within an area of ​​1 cm×1 cm, the distribution density of the first-type tower-shaped texture structure can be greater than or equal to 80% and less than or equal to 99%. For example, the distribution density of the first-type tower-shaped texture structure can be 80%, 82%, 84%, 86%, 88%, 90%, 92%, 94%, 96%, 98%, or 99%, etc. In this case, each corner has the first-type tower-shaped texture structure of the rounded corner 17 with a smaller degree of undulation. The distribution density of the first-type tower-shaped texture structure is greater on the side of the passivation layer facing away from the semiconductor substrate, which is beneficial to further improve the macroscopic surface smoothness of the surface of the passivation layer facing away from the semiconductor substrate, further improving the formation quality of the passivation layer and the passivation effect.

[0090] Exemplarily, in the surface of the area where the passivation layer has a first type of tower-like texture structure and a second type of tower-like texture structure on the side facing away from the semiconductor substrate, and within the range of 1 cm × 1 cm, the distribution density of the first type of tower-like texture structure may be less than the distribution density of the second type of tower-like texture structure.

[0091] For example, Figure 4 As shown, on the side of the passivation layer facing away from the semiconductor substrate, the number of remaining first-type tower-shaped texture structures 15 adjacent to a single first-type tower-shaped texture structure 15 is greater than the number of second-type tower-shaped texture structures 16. This helps increase the distribution density of the first-type tower-shaped texture structures 15 on the side of the passivation layer facing away from the semiconductor substrate, further improving the macroscopic surface smoothness of the side of the passivation layer facing away from the semiconductor substrate, and further enhancing the formation quality and passivation effect of the passivation layer.

[0092] As for the distribution number of fillet-like corners and sharp corners in the bottom surface of the second type of tower base-shaped texture structure, it can be set according to the bottom surface morphology of the second type of tower base-shaped texture structure and actual needs. For example: when the bottom surface morphology of the second type of tower base-shaped texture structure is a regular or irregular quadrilateral, the number of fillet-like corners in the bottom surface of the second type of tower base-shaped texture structure can be 2 or 3. For another example: when the bottom surface morphology of the second type of tower base-shaped texture structure is a regular or irregular hexagon, the number of fillet-like corners in the bottom surface of the second type of tower base-shaped texture structure can be 3, 4 or 5.

[0093] Furthermore, in actual applications, the distribution densities of the first-type tower-shaped texture and the second-type tower-shaped texture in different regions of the passivation layer facing away from the semiconductor substrate may be approximately the same or different. Alternatively, in different regions of the passivation layer facing away from the semiconductor substrate, only some regions may have the first-type tower-shaped texture and the second-type tower-shaped texture, while the remaining regions may not have the first-type tower-shaped texture and the second-type tower-shaped texture.

[0094] Exemplarily, one of the first surface and the second surface is the target surface. Furthermore, the passivation layer includes a first doped semiconductor layer and a second doped semiconductor layer that are alternately distributed and have opposite conductivity types, and at least a portion of the first doped semiconductor layer and at least a portion of the second doped semiconductor layer are spaced apart. Based on this, the surface of the side of the passivation layer corresponding to the first doped semiconductor layer that is away from the semiconductor substrate is defined as the first sub-surface, and the surface of the side of the passivation layer corresponding to the second doped semiconductor layer that is away from the semiconductor substrate is defined as the second sub-surface. In the above case, the first type of tower-shaped texture structure and the second type of tower-shaped texture structure can be both distributed on the first sub-surface. The tower-shaped texture structure also includes a third type of tower-shaped texture structure distributed on the second sub-surface. As Figure 14 and Figure 15 As shown, the bottom surface of the third type of tower base-shaped texture structure 21 is a surface with an arc-shaped contour. In this case, the boundary of the third type of tower base-shaped texture structure 21 with an arc-shaped bottom surface is smoother and more blurred, so that the second sub-surface has a relatively higher flatness than the first sub-surface. The conductivity types of the first doped semiconductor layer and the second doped semiconductor layer can be set respectively according to the difference in surface roughness between the first sub-surface and the second sub-surface, the requirements for different passivation effects of the N-doped semiconductor layers and the P-doped semiconductor layers in actual application scenarios, and the requirements for the contact performance between the two and the corresponding electrodes, so that the two parts of the passivation layer corresponding to the first doped semiconductor layer and the second doped semiconductor layer respectively have different passivation effects on the semiconductor substrate, and are conducive to making the first doped semiconductor layer and the second doped semiconductor layer have different surface morphologies, thereby helping to reduce the passivation difference between the two parts of the passivation layer corresponding to the first doped semiconductor layer and the second doped semiconductor layer respectively (due to the limitation of the doping solid concentration of the N and P regions, the doping concentration of the P region is low. If the P region is formed on a relatively flat surface, it is conducive to improving the crystal quality and film thickness of the P region, which is conducive to improving the passivation effect of the P region, thereby reducing the passivation difference between the N and P regions.), and helping to reduce the difference in contact performance between the first doped semiconductor layer and the second doped semiconductor layer and the corresponding electrodes.

[0095] As for the conductivity type of the first and second doped semiconductor layers, due to limitations on doping concentration and doping difficulty, the doping concentration of the dopant in the N-type doped semiconductor layer is greater than the doping concentration of the dopant in the P-type doped semiconductor layer, resulting in relatively poor contact performance between the P-type doped semiconductor layer and the positive electrode. Furthermore, as previously described, the surface roughness of the first sub-surface provided with the first-type tower-shaped texture structure is relatively large, while the surface roughness of the second sub-surface provided with the second-type tower-shaped texture structure is relatively small. Therefore, the conductivity type of the first doped semiconductor layer can be set to P-type, and the conductivity type of the second doped semiconductor layer can be set to N-type. In this case, the presence of the quasi-pointed corners in the bottom surface of the second-type tower-shaped texture structure helps increase the specific surface area of ​​the P-type doped semiconductor layer on the side facing away from the semiconductor substrate, increasing the contact area between the P-type doped semiconductor layer and the positive electrode, improving the contact performance between the P-type doped semiconductor layer and the positive electrode, and the adhesion and shaping of the positive electrode on the P-type doped semiconductor layer, thereby improving the conversion efficiency of the solar cell.

[0096] Alternatively, the conductivity type of the first doped semiconductor layer can be set to N-type, and the conductivity type of the second doped semiconductor layer can be set to P-type. Based on this, N-type impurities are typically doped by substitutional diffusion, which is difficult to dope. Furthermore, the doping concentration of the N-type doped semiconductor layer is also relatively high, which can easily lead to a high number of defects within the N-type doped semiconductor layer after doping. In this case, the first sub-surface with greater surface roughness corresponds to the N-type doped semiconductor layer, which helps improve the contact performance between the N-type doped semiconductor layer and the cathode, as well as the adhesion and shaping of the cathode on the N-type doped semiconductor layer, thereby improving the conversion efficiency of the solar cell.

[0097] In addition, the bottom surface morphology of the third type of tower base-shaped texture structure on the second sub-surface can be a regular surface with an arc-shaped contour (such as an elliptical surface, a circular surface, etc.), or an irregular surface with an arc-shaped contour. Secondly, the second sub-surface can only have the third type of tower base-shaped texture structure. Or, as Figure 15 As shown, the tower base-like texture structure can also include a fourth type of tower base-like texture structure 22 distributed on the second sub-surface, and the bottom surface of the fourth type of tower base-like texture structure 22 is a polygonal bottom surface. In this case, the second sub-surface can not only have the third type of tower base-like texture structure 21, but also be provided with the fourth type of tower base-like texture structure 22. There is no need to strictly control the etching conditions in order to obtain a second sub-surface having only the third type of tower base-like texture structure 21, thereby reducing the difficulty of the manufacturing process. Among them, the bottom surface of the fourth type of tower base-like texture structure 22 can be a polygonal bottom surface such as a quadrilateral bottom surface, a pentagonal bottom surface, a hexagonal bottom surface or an octagonal bottom surface. The polygon can be a regular polygon with the same side length, or a polygon with different side lengths.

[0098] As for the size of the tower-like texture structure of the first sub-surface and the second sub-surface, the one-dimensional size and / or the recessed depth of the bottom surface of the tower-like texture structure located on the first sub-surface can be the same as the one-dimensional size and / or the recessed depth of the bottom surface of the tower-like texture structure located on the second sub-surface.

[0099] Alternatively, the one-dimensional size of the bottom surface of the tower-like texture structure located on the first sub-surface can be smaller than the one-dimensional size of the bottom surface of the tower-like texture structure located on the second sub-surface, and / or the recessed depth of the tower-like texture structure located on the first sub-surface can be greater than the recessed depth of the tower-like texture structure located on the second sub-surface. In this case, it can be understood that the larger the one-dimensional size of the bottom surface of the tower-like texture structure, the larger the bottom area of ​​the tower-like texture structure, and within the same area range, the fewer the number of tower-like texture structures that can be set, and the smaller the distribution density. Based on this, when the one-dimensional size of the bottom surface of the tower-like texture structure located on the first sub-surface is small, it is beneficial to increase the surface roughness of the first sub-surface, further increase the contact area between the first doped semiconductor layer and the electrode, improve the contact performance between the first doped semiconductor layer and the electrode, and the adhesion and shaping of the electrode on the first doped semiconductor layer, which is beneficial to improve the conversion efficiency of the solar cell. Secondly, the beneficial effect that the recessed depth of the tower-like texture structure located on the first sub-surface can be greater than the recessed depth of the tower-like texture structure located on the second sub-surface can be referred to above and will not be repeated here.

[0100] Among them, the one-dimensional size of the bottom surface of the tower-like texture structure of the first sub-surface can refer to the one-dimensional size of the bottom surface of the first type of tower-like texture structure and the second type of tower-like texture structure described above, which will not be repeated here.

[0101] As for the one-dimensional size of the bottom surface of the tower-base-like texture structure on the second sub-surface, illustratively, the one-dimensional size of the bottom surface of the tower-base-like texture structure on the second sub-surface can be greater than or equal to 5μm and less than or equal to 30μm. For example: the one-dimensional size of the bottom surface of the tower-base-like texture structure on the second sub-surface can be 5μm, 6μm, 8μm, 10μm, 15μm, 18μm, 20μm, 25μm or 30μm, etc. The application principle of the beneficial effect in this case can refer to the application principle of the beneficial effect of the one-dimensional size of the bottom surface of the first type of tower-base-like texture structure and / or the second type of tower-base-like texture structure being greater than or equal to 7μm and less than or equal to 15μm as described above, and will not be repeated here.

[0102] In a second aspect, an embodiment of the present invention provides a photovoltaic module, which includes the solar cell according to the first aspect and various implementations thereof.

[0103] The beneficial effects of the second aspect and its various implementations in the embodiments of the present invention can be analyzed with reference to the beneficial effects of the first aspect and its various implementations, and will not be repeated here.

[0104] In a third aspect, an embodiment of the present invention provides a semiconductor substrate comprising a first surface and a second surface relative to each other. At least one of the first surface and the second surface is a target surface. The target surface has a plurality of tower-like texture structures that are recessed into the semiconductor substrate. The plurality of tower-like texture structures include a first-type tower-like texture structure and a second-type tower-like texture structure. The corners in the bottom surface of the first-type tower-like texture structure are all quasi-rounded corners, and the bottom surface of the second-type tower-like texture structure includes some corners that are quasi-rounded corners and the remaining corners are quasi-sharp corners. In the bottom surface of the same second-type tower-like texture structure, the number of quasi-rounded corners is greater than the number of quasi-sharp corners.

[0105] In one example, in the same target surface, the distribution density of the first type of tower base-shaped texture structure is greater than the distribution density of the second type of texture structure.

[0106] In one example, in the area surface of the target surface having the first type of tower base-like texture structure and the second type of tower base-like texture structure, and within the range of 1cm×1cm, the distribution density of the first type of tower base-like texture structure is greater than or equal to 80% and less than or equal to 99%.

[0107] In one example, on the target surface, the number of remaining first-type tower-shaped texture structures adjacent to the single first-type tower-shaped texture structure is greater than the number of second-type tower-shaped texture structures.

[0108] In one example, the target surface is a quasi-rectangular surface; in the quasi-rectangular surface, the corresponding areas of the four corners are the four-corner areas, the corresponding areas of the four contour edges are the peripheral areas, and the area located inside the four-corner areas and the peripheral areas is the middle area; wherein the recessed depth of the tower-like texture structure located in the peripheral area is greater than the recessed depth of the tower-like texture structure located in the middle area; and / or the recessed depth of the tower-like texture structure located in the four-corner areas is less than the recessed depth of the tower-like texture structure located in the middle area.

[0109] In one example, in the target surface, along the direction from the four corner vertices of the quasi-rectangular surface to the geometric center of the quasi-rectangular surface, the width of the four corner regions is less than or equal to 2 cm.

[0110] In one example, in the target surface, along the direction from the edge of the quasi-rectangular surface to the geometric center, the width of the peripheral area is less than or equal to 3 cm.

[0111] In one example, in the target surface, along a direction parallel to the target surface, the concave depth of one side of at least one pyramid-like texture structure is smaller than the concave depth of the other side thereof.

[0112] In one example, in the target surface, a ratio between a concave depth on one side of at least one pyramid-like texture structure and a concave depth on the other side thereof is greater than or equal to 1.01 and less than 2.

[0113] In one example, in the target surface, at least one quasi-cusp angle is an angle formed by two intersecting straight line segments.

[0114] In one example, in the target surface, at least one quasi-sharp corner is a corner with a smooth transition, and the fillet radius corresponding to the quasi-sharp corner is less than or equal to one half of the fillet radius corresponding to the quasi-fillet corner.

[0115] In one example, one of the first surface and the second surface is a target surface; the target surface includes a first sub-surface and a second sub-surface that are alternately distributed; the first type of tower base-like texture structure and the second type of tower base-like texture structure are both distributed on the first sub-surface; the tower base-like texture structure also includes a third type of tower base-like texture structure distributed on the second sub-surface, and the bottom surface of the third type of tower base-like texture structure is a surface with an arc-shaped contour.

[0116] In one example, in the target surface, the tower base-like texture structure further includes a fourth-type tower base-like texture structure distributed on the second sub-surface, and the bottom surface of the fourth-type tower base-like texture structure is a polygonal bottom surface.

[0117] In one example, on the target surface, a one-dimensional size of a bottom surface of the pyramid-like texture structure on the first sub-surface is smaller than a one-dimensional size of a bottom surface of the pyramid-like texture structure on the second sub-surface.

[0118] In one example, on the target surface, a one-dimensional size of the bottom surface of the pyramid-like texture structure located on the first sub-surface is greater than or equal to 7 μm and less than or equal to 15 μm.

[0119] In one example, on the target surface, a one-dimensional size of the bottom surface of the pyramid-like texture structure located on the second sub-surface is greater than or equal to 5 μm and less than or equal to 30 μm.

[0120] It should be noted that the semiconductor substrate provided in the third aspect of the present invention is used to manufacture the solar cell provided in the first aspect. Information such as the morphology of the multiple tower-like texture structures, the size and distribution of the first and second tower-like texture structures, on the target surface of the semiconductor substrate can refer to the morphology of the multiple tower-like texture structures, the size and distribution of the first and second tower-like texture structures, on the side of the passivation layer facing away from the semiconductor substrate in the first aspect.

[0121] The beneficial effects of the third aspect and its various implementations in the embodiments of the present invention can be analyzed with reference to the beneficial effects of the first aspect and its various implementations, and will not be repeated here.

[0122] In a fourth aspect, an embodiment of the present invention provides a method for manufacturing a solar cell. The method for manufacturing a solar cell comprises the following steps:

[0123] First, a semiconductor substrate is provided; the semiconductor substrate includes a first surface and a second surface opposite to each other. At least one of the first surface and the second surface is a target surface. The material of the semiconductor substrate and whether the first surface and the second surface of the semiconductor substrate are target surfaces can be found in the previous section and are not further described here.

[0124] Next, a first polishing process is performed on the target surface of the semiconductor substrate to form a plurality of quasi-tower-shaped texture structures on the target surface. The plurality of quasi-tower-shaped texture structures include a first-type tower-shaped texture structure and a second-type tower-shaped texture structure. Each corner on the bottom surface of the first-type tower-shaped texture structure is a quasi-rounded corner, while the bottom surface of the second-type tower-shaped texture structure includes some quasi-rounded corners and the remaining quasi-pointed corners. Within the bottom surface of the same second-type tower-shaped texture structure, the number of quasi-rounded corners is greater than the number of quasi-pointed corners.

[0125] Specifically, the morphology, one-dimensional size and distribution of the tower-like texture structure on the target surface can refer to the morphology, one-dimensional size and distribution of the tower-like texture structure on the side of the passivation layer facing away from the semiconductor substrate in the solar cell provided by the first aspect described above, and will not be repeated here.

[0126] In an actual manufacturing process, a first alkaline solution containing sodium hydroxide or potassium hydroxide can be used to perform a first polishing treatment on the target surface of the semiconductor substrate. The first alkaline solution can be a solution containing sodium hydroxide or potassium hydroxide. The concentration and temperature of the first alkaline solution, as well as the treatment time of the first polishing treatment, can be determined based on the requirements for the morphology and one-dimensional dimensions of the tower-like texture structure in actual application scenarios, and are not specifically limited here.

[0127] Next, a passivation layer is formed on the target surface, wherein the passivation layer has a plurality of pyramid-like texture structures on a side facing away from the semiconductor substrate.

[0128] The specific formation process of the passivation layer can be determined based on the structure of the passivation layer and the distribution of the pyramid-like texture structure on the side of the passivation layer away from the semiconductor substrate.

[0129] For example, a process such as chemical vapor deposition can be used to form a passivation layer that is set as a whole layer on the target surface. If the passivation layer is only set in a local area of ​​the target surface, the passivation layer also needs to be patterned. If the passivation layer includes the first doped semiconductor layer and the second doped semiconductor layer of opposite conductivity types, after forming one of the first doped semiconductor layer and the second doped semiconductor layer, it is necessary to pattern the first doped semiconductor layer and the second doped semiconductor layer that are formed first; then, a process such as chemical vapor deposition is used to form the other of the first doped semiconductor layer and the second doped semiconductor layer that are set as a whole layer, and then the first doped semiconductor layer and the second doped semiconductor layer that are formed later are patterned.

[0130] The following describes the process of manufacturing the passivation layer by taking as an example a case where the passivation layer includes the first doped semiconductor layer and the second doped semiconductor layer of opposite conductivity types, and one of the first doped semiconductor layer and the second doped semiconductor layer is a P-type doped semiconductor layer formed first:

[0131] A first interface passivation layer and an intrinsic semiconductor layer are sequentially formed on the target surface using processes such as chemical vapor deposition. The intrinsic semiconductor layer is then doped using a doping process such as diffusion to form a P-type doped semiconductor layer. When the P-type doped semiconductor layer is made of silicon, a borosilicate glass layer is also formed on the side of the P-type doped semiconductor layer facing away from the semiconductor substrate after the P-type doped semiconductor layer is formed. The borosilicate glass layer is then locally heat-treated using a laser irradiation process, so that the untreated portion of the borosilicate glass layer forms a mask layer. A second alkaline solution is then used to selectively remove the portion of the P-type doped semiconductor layer exposed outside the mask layer. The second alkaline solution is used to etch the portion of the P-type doped semiconductor layer exposed outside the mask layer. Because the P-type impurity concentration in the first interface passivation layer is lower and the layer is more compact than the heat-treated portion of the borosilicate glass layer, the portion of the first interface passivation layer exposed outside the mask layer is preserved after etching with the second alkaline solution. Among them, the type, concentration, temperature and processing time of the above-mentioned second alkaline solution can be set according to actual needs and are not specifically limited here. Next, a third alkaline solution is used to remove the portion of the first interface passivation layer exposed outside the mask layer, and the portion of the semiconductor substrate exposed outside the mask layer is etched so that the surface of the portion of the semiconductor substrate exposed outside the mask layer is recessed inward relative to the surface of the portion of the semiconductor substrate covered with the mask layer, and a third type of tower base-shaped texture structure and / or a fourth type of tower base-shaped texture structure is formed. In addition, compared to the second alkaline solution, because the third alkaline solution corrodes the first interface passivation layer with higher density, the alkali concentration of the third alkaline solution is higher and the corresponding etching time is shorter. Specifically, the type, concentration, temperature and processing time of the third alkaline solution can be set according to actual needs and are not specifically limited here. Next, a process such as chemical vapor deposition can be used to sequentially form a second interface passivation layer and an N-type doped semiconductor layer on the P-type doped semiconductor layer and on the target surface. Then, a process such as chemical slurry or laser etching is used to remove the second interface passivation layer and the portion of the N-type doped semiconductor layer at least covering the local area of ​​the P-type doped semiconductor layer.

[0132] It should be noted that when the passivation layer includes the aforementioned N-type doped semiconductor layer and P-type doped semiconductor layer of opposite conductivity types, not only the P-type doped semiconductor layer can be formed first, but also the N-type doped semiconductor layer can be formed first. When the N-type doped semiconductor layer is formed first, the manufacturing process of the passivation layer can refer to the manufacturing process of the passivation layer when the P-type doped semiconductor layer is formed first, and will not be repeated here.

[0133] In addition, when the passivation layer includes the aforementioned N-type doped semiconductor layer and P-type doped semiconductor layer of opposite conductivity types, the solar cell may also not include the aforementioned first interface passivation layer and / or second interface passivation layer. When the solar cell does not include the aforementioned first interface passivation layer and / or second interface passivation layer, the aforementioned operations of forming and etching the first interface passivation layer and / or second interface passivation layer are not required.

[0134] In addition, when the N-type doped semiconductor layer and / or the P-type doped semiconductor layer does not include silicon material, and / or the N-type doped semiconductor layer and / or the P-type doped semiconductor layer is not formed using a diffusion process, a mask layer for performing patterning can be formed by combining chemical phase deposition and etching processes. The material of the mask layer can include materials such as silicon nitride or aluminum oxide.

[0135] While the above description does not provide detailed technical details regarding patterning and etching of each layer, those skilled in the art will appreciate that various technical means can be employed to form layers, regions, and the like in desired shapes. Furthermore, those skilled in the art may devise methods that differ from those described above to form the same structure. Furthermore, while each embodiment has been described separately, this does not mean that the measures in each embodiment cannot be advantageously combined.

[0136] The above describes the embodiments of the present invention. However, these embodiments are merely for illustrative purposes and are not intended to limit the scope of the present invention. The scope of the present invention is defined by the appended claims and their equivalents. Various substitutions and modifications may be made by those skilled in the art without departing from the scope of the present invention, and such substitutions and modifications are intended to fall within the scope of the present invention.

Claims

1. A solar cell, characterized in that: include: A semiconductor substrate comprising a first surface and a second surface opposite to each other; at least one of the first surface and the second surface is a target surface; a passivation layer, disposed on the target surface; A portion of the surface of the passivation layer on the side away from the semiconductor substrate has a plurality of tower-like texture structures formed by being concave toward the side close to the semiconductor substrate; The plurality of tower-base-like texture structures include a first-type tower-base-like texture structure and a second-type tower-base-like texture structure; each corner on the bottom surface of the first-type tower-base-like texture structure is a quasi-rounded corner, and the bottom surface of the second-type tower-base-like texture structure includes some quasi-rounded corners and the remaining corners are quasi-pointed corners; in the bottom surface of the same second-type tower-base-like texture structure, the number of quasi-rounded corners is greater than or equal to the number of quasi-pointed corners; The smoothness of the boundary transition of the passivation layer at the quasi-round corner is greater than the smoothness of the boundary transition of the passivation layer at the quasi-point corner.

2. The solar cell according to claim 1, wherein On a side of the same passivation layer facing away from the semiconductor substrate, the distribution density of the first type of tower-shaped texture structure is greater than the distribution density of the second type of tower-shaped texture structure; and / or, in a region of the surface of the passivation layer on a side facing away from the semiconductor substrate and having the first-type tower-shaped texture structure and the second-type tower-shaped texture structure, and within an area of ​​1 cm×1 cm, a distribution density of the first-type tower-shaped texture structure is greater than or equal to 80% and less than or equal to 99%; And / or, on the side of the passivation layer facing away from the semiconductor substrate, the number of the remaining first-type tower-shaped texture structures adjacent to a single first-type tower-shaped texture structure is greater than the number of the second-type tower-shaped texture structures.

3. The solar cell according to claim 1, wherein A surface of the passivation layer facing away from the semiconductor substrate is a substantially rectangular surface; in the substantially rectangular surface, regions corresponding to the four corners are referred to as four corner regions, regions corresponding to the four contour edges are referred to as peripheral regions, and a region located inside the four corner regions and the peripheral regions is referred to as a central region; Among them, the recessed depth of the tower-like texture structure located in the peripheral area is greater than the recessed depth of the tower-like texture structure located in the central area; and / or the recessed depth of the tower-like texture structure located in the four corner areas is less than the recessed depth of the tower-like texture structure located in the central area.

4. The solar cell according to claim 3, characterized in that Along the direction from the four corner vertices of the quasi-rectangular surface to the geometric center of the quasi-rectangular surface, the width of the four corner areas is less than or equal to 2 cm; And / or, along the direction from the edge of the quasi-rectangular surface to the geometric center, the width of the peripheral area is less than or equal to 3 cm.

5. The solar cell according to claim 1, wherein Along a direction parallel to the target surface, the concave depth of one side of at least one of the tower base-like texture structures is smaller than the concave depth of the other side thereof.

6. The solar cell according to claim 5, characterized in that The ratio of the concave depth on one side of at least one of the tower base-like texture structures to the concave depth on the other side thereof is greater than or equal to 1.01 and less than 2.

7. The solar cell according to claim 1, wherein At least one of the quasi-pointed angles is an angle formed by two intersecting straight line segments; Alternatively, at least one of the quasi-sharp corners is a corner with a smooth transition, and the fillet radius corresponding to the quasi-sharp corner is less than or equal to half of the fillet radius corresponding to the quasi-fillet corner.

8. The solar cell according to claim 1, wherein One of the first surface and the second surface is a target surface; the passivation layer includes first doped semiconductor layers and second doped semiconductor layers that are alternately distributed and have opposite conductivity types, and at least a portion of the first doped semiconductor layer and at least a portion of the second doped semiconductor layer are alternately distributed; A surface of the passivation layer corresponding to the first doped semiconductor layer and facing away from the semiconductor substrate is a first sub-surface, and a surface of the passivation layer corresponding to the second doped semiconductor layer and facing away from the semiconductor substrate is a second sub-surface; The first type of tower base-shaped texture structure and the second type of tower base-shaped texture structure are both distributed on the first sub-surface; The tower base-like texture structure further includes a third tower base-like texture structure distributed on the second sub-surface, and the bottom surface of the third tower base-like texture structure is a surface with an arc-shaped contour.

9. The solar cell according to claim 8, characterized in that The tower base-like texture structure further includes a fourth tower base-like texture structure distributed on the second sub-surface, and the bottom surface of the fourth tower base-like texture structure is a polygonal bottom surface.

10. The solar cell according to claim 8 or 9, characterized in that The conductivity type of the first doped semiconductor layer is P-type, and the conductivity type of the second doped semiconductor layer is N-type; and / or, a one-dimensional size of the bottom surface of the tower-base-like texture structure on the first sub-surface is smaller than a one-dimensional size of the bottom surface of the tower-base-like texture structure on the second sub-surface; And / or, a one-dimensional size of the bottom surface of the tower-base-like texture structure on the first sub-surface is greater than or equal to 7 μm and less than or equal to 15 μm; And / or, a one-dimensional size of the bottom surface of the tower base-like texture structure located on the second sub-surface is greater than or equal to 5 μm and less than or equal to 30 μm.

11. A photovoltaic module, characterized in that: The solar cell comprises the solar cell according to any one of claims 1 to 10.

12. A semiconductor substrate, characterized in that: include: The semiconductor substrate comprises a first surface and a second surface opposite to each other; at least one of the first surface and the second surface is a target surface; The target surface has a plurality of tower-like texture structures recessed into the semiconductor substrate; The plurality of tower-base-like texture structures include a first-type tower-base-like texture structure and a second-type tower-base-like texture structure; each corner on the bottom surface of the first-type tower-base-like texture structure is a quasi-rounded corner, and the bottom surface of the second-type tower-base-like texture structure includes some quasi-rounded corners and the remaining corners are quasi-pointed corners; in the bottom surface of the same second-type tower-base-like texture structure, the number of quasi-rounded corners is greater than the number of quasi-pointed corners; The smoothness of the boundary transition of the semiconductor substrate at the quasi-round corner is greater than the smoothness of the boundary transition of the semiconductor substrate at the quasi-point corner.

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