Hybrid passivated back contact cell and preparation method thereof

Abstract

The present application provides a hybrid passivation back contact battery and a preparation method thereof, the battery comprising a silicon wafer; a third tunneling oxide layer, a first amorphous silicon layer and a first anti-reflection layer are sequentially arranged on the front side of the silicon wafer; a first polishing area and a second polishing area are alternately arranged on the back side of the silicon wafer; at least a first semiconductor layer is arranged on the first polishing area; at least a second semiconductor layer is arranged on the second polishing area; a texturing area is arranged between the first polishing area and the adjacent second polishing area; a fourth tunneling oxide layer, a second amorphous silicon layer and a second anti-reflection layer are sequentially arranged on the first polishing area, the texturing area and the second polishing area; the refractive index of the first amorphous silicon layer is 2.2-4, and the refractive index of the first amorphous silicon layer gradually decreases from the third tunneling oxide layer to the first anti-reflection layer. The present application improves the passivation effect, thereby improving the battery efficiency. In addition, the passivation layers on the front and back sides can be deposited and formed in the same tubular PECVD, which simplifies the process steps and reduces the equipment cost.

Description

Technical Field

[0001] The present application relates to the technical field of back contact batteries, and in particular to a hybrid passivated back contact battery and a preparation method thereof. Background Art

[0002] Conventional back-contact cells usually have a passivation layer on both sides of the silicon wafer to achieve better photoelectric conversion efficiency and cell performance. The existing technology generally uses aluminum oxide and silicon nitride as passivation layers on the front and back sides of the silicon wafer, but the passivation effect of aluminum oxide and silicon nitride is poor, which will seriously affect the efficiency of the cell. In addition, the front and back sides need to be completed in three steps, which is complicated and has high equipment costs.

[0003] Therefore, there is an urgent need to provide a back contact battery to solve the above technical problems.

[0004] It should be noted that this part of the present invention only provides background technology related to the present invention and does not necessarily constitute prior art or known technology. Summary of the invention

[0005] In view of this, the purpose of the present application is to provide a hybrid passivated back contact battery and a preparation method thereof, so as to at least solve the problem that the prior art uses aluminum oxide and silicon nitride as passivation layers on the front and back sides of silicon wafers, the passivation effect is poor, and the process flow is complicated. The present application uses a tunneling oxide layer, an amorphous silicon layer, and an anti-reflection layer on the front and back sides of the battery to replace aluminum oxide and silicon nitride, thereby improving the passivation effect of the battery and thus improving the battery efficiency. In addition, the tunneling oxide layer, amorphous silicon layer, and anti-reflection layer on the front and back sides can be deposited and formed in the same tubular PECVD, which further simplifies the process steps and reduces the equipment cost.

[0006] In the first aspect, the present application provides a hybrid passivated back contact battery, including a silicon wafer, the silicon wafer having a front side and a back side; a third tunneling oxide layer, a first amorphous silicon layer and a first anti-reflection layer are sequentially arranged on the front side of the silicon wafer; along the X-axis direction of the back side of the silicon wafer, a first polishing area and a second polishing area are alternately arranged on the back side of the silicon wafer; along the Z-axis direction of the back side of the silicon wafer, at least a first semiconductor layer is arranged on the first polishing area; along the Z-axis direction of the back side of the silicon wafer, at least a second semiconductor layer is arranged on the second polishing area; a texturing area is arranged between the first polishing area and the adjacent second polishing area, and the texturing area isolates the first semiconductor layer from the second semiconductor layer; a fourth tunneling oxide layer, a second amorphous silicon layer and a second anti-reflection layer are sequentially arranged on the first polishing area, the texturing area and the second polishing area; the refractive index of the first amorphous silicon layer is 2.2-4, and the refractive index of the first amorphous silicon layer gradually decreases from the third tunneling oxide layer to the first anti-reflection layer.

[0007] In some embodiments, the thickness of the third tunnel oxide layer is 0.5-1.5 nm, and the thickness of the fourth tunnel oxide layer is 1-2 nm.

[0008] In some embodiments, a thickness ratio of the third tunnel oxide layer to the fourth tunnel oxide layer is 1:1-2.

[0009] In some embodiments, the thickness of the first anti-reflection layer is 65-120 nm, and the thickness of the second anti-reflection layer is 40-90 nm.

[0010] In some embodiments, the thickness ratio of the first anti-reflection layer to the second anti-reflection layer is 1:0.3-1.

[0011] In some embodiments, the thickness of the first amorphous silicon layer is 2-20 nm, and the thickness of the second amorphous silicon layer is 4-40 nm.

[0012] In some embodiments, a thickness ratio of the first amorphous silicon layer to the second amorphous silicon layer is 1:1.2-5.

[0013] In some embodiments, the refractive index of the second amorphous silicon layer is 2.2-4, and the refractive index of the second amorphous silicon layer gradually decreases from the fourth tunneling oxide layer to the second anti-reflection layer.

[0014] In some embodiments, the hybrid passivated back contact cell also includes a first electrode and a second electrode, the first electrode contacts the first semiconductor layer through a fourth tunneling oxide layer, a second amorphous silicon layer and a second anti-reflection layer; the second electrode contacts the second semiconductor layer through a fourth tunneling oxide layer, a second amorphous silicon layer and a second anti-reflection layer.

[0015] In some embodiments, the first semiconductor layer includes at least a first tunneling oxide layer and a first doped polycrystalline layer, the first tunneling oxide layer has a thickness of 1-2 nm, and the first doped polycrystalline layer has a thickness of 150-250 nm.

[0016] In some embodiments, the second semiconductor layer includes a second tunneling oxide layer and a second doped polycrystalline layer, the second tunneling oxide layer has a thickness of 1-2 nm, and the second doped polycrystalline layer has a thickness of 150-250 nm.

[0017] In a second aspect, the present application provides a method for preparing a hybrid passivated back contact battery, the preparation method comprising the following steps:

[0018] S101, polishing and cleaning the front and back sides of the silicon wafer in sequence;

[0019] S102, sequentially forming a first semiconductor layer and a first mask layer on the back side of the silicon wafer;

[0020] S103, performing a first etching on the first semiconductor layer and the first mask layer on the back surface obtained in S102 to form first opening areas distributed at intervals;

[0021] S104, removing the first semiconductor layer in the first opening area by polishing and cleaning to form a polishing surface;

[0022] S105, forming a second semiconductor layer and a second mask layer in sequence on the back surface obtained in S104;

[0023] S106, performing a second etching on the second mask layer on the back surface obtained in S105 to form a second opening area distributed at intervals, and performing a third etching on the second mask layer at the junction of the first semiconductor layer and the second semiconductor layer to form a third opening area distributed at intervals;

[0024] S107, removing the second semiconductor layer without the second mask layer, forming a textured surface in the area of ​​the first opening region without the second semiconductor layer, and forming a textured surface on the front side of the silicon wafer;

[0025] The area on the back of the silicon wafer that contacts the first semiconductor layer forms a first polishing area, the area on the back of the silicon wafer that contacts the second semiconductor layer forms a second polishing area, and the area on the first opening that does not have the second semiconductor layer forms a texturing area;

[0026] S108, cleaning and removing the first mask layer and the second mask layer exposed on the back side of the silicon wafer;

[0027] S109, forming a third tunneling oxide layer, a first amorphous silicon layer and a first anti-reflection layer in sequence on the front side of the silicon wafer by using tubular PECVD;

[0028] S110, forming a fourth tunnel oxide layer, a second amorphous silicon layer, and a second anti-reflection layer in sequence on the back side of the silicon wafer by using tubular PECVD;

[0029] The refractive index of the first amorphous silicon layer is 2.2-4, and the refractive index of the first amorphous silicon layer gradually decreases from the third tunneling oxide layer to the first anti-reflection layer.

[0030] In some embodiments, the width of the first opening region is 200-600 μm.

[0031] In some embodiments, the texturing area has a width of 10-50 μm.

[0032] In some embodiments, in S106 , there is a second mask layer or there is no second mask layer between the second opening region and the third opening region.

[0033] In some embodiments, when there is a second mask layer between the second opening region and the third opening region, the width of the second opening region is 100-500 μm, and the width of the third opening region is 40-150 μm.

[0034] In some embodiments, when there is no second mask layer between the second opening region and the third opening region, the second opening region and the third opening region together form a composite opening region, and the width of the composite opening region is 400-800 μm.

[0035] In some embodiments, the order of step S109 and step S110 may be interchanged.

[0036] In some embodiments, after S110 , the method further includes forming a first electrode and a second electrode respectively on the first semiconductor layer and the second semiconductor layer on the back side obtained in S110 .

[0037] The beneficial effects that this application can achieve are:

[0038] 1. Compared with the prior art which uses aluminum oxide and silicon nitride as passivation layers on the front and back sides of silicon wafers, the present application uses a tunneling oxide layer, an amorphous silicon layer, and an anti-reflection layer in the texturing area on the front and back sides of the battery to replace aluminum oxide and silicon nitride, thereby improving the passivation effect of the battery and thus improving the battery efficiency.

[0039] 2. Compared with the prior art which uses aluminum oxide and silicon nitride as passivation layers on the front and back sides of silicon wafers, the present application uses tunneling oxide layers, amorphous silicon layers, and anti-reflection layers to replace aluminum oxide and silicon nitride in the texturing areas on the front and back sides of the battery. These layers can be deposited in the same tubular PECVD, further simplifying the process steps and reducing equipment costs.

[0040] 3. The present application creatively adopts a gradient refractive index design in the amorphous silicon layer. The refractive index of the first amorphous silicon layer is 2.2-4, and the refractive index of the first amorphous silicon layer gradually decreases from the third tunneling oxide layer to the first anti-reflection layer. This structure can further enhance the optical performance of the battery, increase the light transmittance of the front side of the battery, reduce the reflectivity, and thus improve the short-circuit current of the battery.

[0041] 4. In the preferred solution of the present application, the second semiconductor layer remaining on the first semiconductor layer is removed, thereby reducing the parasitic absorption of the second semiconductor layer corresponding to the first semiconductor, thereby increasing the battery current.

[0042] 5. The present application creatively differentiates the thickness of the passivation layer structure on the front and back sides, corresponding to the different passivation requirements on the front and back sides, which can improve the passivation effect of the battery, thereby improving the battery efficiency. The present application also reasonably sets the thickness ratio of the front and back passivation layer structures, and further improves the passivation effect of the battery and the battery efficiency through the synergistic effect of the front and back sides. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0044] Figure 1 A schematic diagram of the structure of a hybrid passivated back contact cell in step S101 of Example 1 of the present application is shown;

[0045] Figure 2 A schematic diagram of the structure of a hybrid passivated back contact cell in step S102 of Example 1 of the present application is shown;

[0046] Figure 3 A schematic diagram of the structure of a hybrid passivated back contact cell in step S103 of Example 1 of the present application is shown;

[0047] Figure 4 A schematic diagram of the structure of a hybrid passivated back contact cell in step S104 of Example 1 of the present application is shown;

[0048] Figure 5 A schematic diagram of the structure of a hybrid passivated back contact cell in step S105 of Example 1 of the present application is shown;

[0049] Figure 6 A schematic diagram of the structure of a hybrid passivated back contact cell in step S106 of Example 1 of the present application is shown;

[0050] Figure 7 A schematic diagram of the structure of a hybrid passivated back contact cell in step S107 of Example 1 of the present application is shown;

[0051] Figure 8 A schematic diagram of the structure of a hybrid passivated back contact cell in step S108 of Example 1 of the present application is shown;

[0052] Fig. 9 A schematic diagram of the structure of a hybrid passivated back contact cell in step S109 of Example 1 of the present application is shown;

[0053] Fig.10 A schematic diagram of the structure of a hybrid passivated back contact cell in step S110 of Example 1 of the present application is shown;

[0054] Fig.11 A schematic diagram of the structure of a hybrid passivated back contact cell in step S111 of Example 1 of the present application is shown;

[0055] Fig.12 A schematic diagram of the structure of a hybrid passivated back contact cell in step S106 of Example 2 of the present application is shown;

[0056] Fig.13 A schematic diagram of the structure of a hybrid passivated back contact cell in step S107 of Example 2 of the present application is shown;

[0057] Fig.14 A schematic diagram of the structure of a hybrid passivated back contact cell in step S108 of Example 2 of the present application is shown;

[0058] Fig.15 A schematic diagram of the structure of a hybrid passivated back contact battery after step S109 and step S110 in Example 2 of the present application is shown;

[0059] Fig.16 A schematic diagram of the structure of a hybrid passivated back contact cell in step S111 of Example 2 of the present application is shown;

[0060] Fig.17 A schematic structural diagram of a back contact battery in Comparative Example 1 of the present application is shown.

[0061] Description of reference numerals:

[0062] 1. Silicon wafer; 2. First tunneling oxide layer; 3. P-type doped polycrystalline layer; 3A. Borosilicate glass (BSG) layer; 4. Second tunneling oxide layer; 5. N-type doped polycrystalline layer; 5A. Phosphorus silicon glass (PSG) layer; 6. Third tunneling oxide layer; 7. First amorphous silicon layer; 8. First anti-reflection layer; 9. Fourth tunneling oxide layer; 10. Second amorphous silicon layer; 11. Second anti-reflection layer; 12. First electrode; 13. Second electrode; 14. First aluminum oxide layer; 15. Second aluminum oxide layer. DETAILED DESCRIPTION

[0063] The term "comprising" in the specification and claims of the present application and the drawings is synonymous with "including", "containing" or "characterized by", and is inclusive or open-ended, and does not exclude additional undescribed elements or method steps. "Comprising" is a technical term used in the claim language, meaning that the elements are present, but other elements may also be added and still form a structure or method within the scope of the claim.

[0064] It should be noted that similar reference numerals and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further defined and explained in the subsequent drawings. In addition, the terms "first", "second", "third", etc. are only used to distinguish the description and cannot be understood as indicating or implying relative importance. The term "about" in this application means to include a small change (up to + / -10%) from the stated value.

[0065] In the first aspect, the present application provides a hybrid passivated back contact battery, including a silicon wafer, the silicon wafer having a front side and a back side; a third tunneling oxide layer, a first amorphous silicon layer and a first anti-reflection layer are sequentially arranged on the front side of the silicon wafer; along the X-axis direction of the back side of the silicon wafer, a first polishing area and a second polishing area are alternately arranged on the back side of the silicon wafer; along the Z-axis direction of the back side of the silicon wafer, at least a first semiconductor layer is arranged on the first polishing area; along the Z-axis direction of the back side of the silicon wafer, at least a second semiconductor layer is arranged on the second polishing area; a texturing area is arranged between the first polishing area and the adjacent second polishing area, and the texturing area isolates the first semiconductor layer from the second semiconductor layer; a fourth tunneling oxide layer, a second amorphous silicon layer and a second anti-reflection layer are sequentially arranged on the first polishing area, the texturing area and the second polishing area; the refractive index of the first amorphous silicon layer is 2.2-4, and the refractive index of the first amorphous silicon layer gradually decreases from the third tunneling oxide layer to the first anti-reflection layer.

[0066] The present invention uses a tunneling oxide layer, an amorphous silicon layer, and an anti-reflection layer to replace aluminum oxide and silicon nitride in the texturing area on the front and back of the battery, thereby improving the passivation effect of the battery and thus improving the battery efficiency. In addition, the tunneling oxide layer, amorphous silicon layer, and anti-reflection layer on the front and back sides can be deposited and formed in the same tubular PECVD, further simplifying the process steps and reducing the equipment cost.

[0067] The present application creatively adopts a gradient refractive index design in the amorphous silicon layer, the refractive index of the first amorphous silicon layer is 2.2-4, and the refractive index of the first amorphous silicon layer gradually decreases from the third tunneling oxide layer to the first anti-reflection layer. This structure can further enhance the optical performance of the battery, increase the light transmittance of the front side of the battery, reduce the reflectivity, and thus increase the short-circuit current of the battery.

[0068] In some embodiments, the thickness of the third tunnel oxide layer is 0.5-1.5 nm, and may be 0.5 nm, 0.7 nm, 1 nm, 1.2 nm, 1.5 nm, and any value therebetween. Preferably, the thickness of the third tunnel oxide layer is 0.9 nm.

[0069] In some embodiments, the thickness of the fourth tunnel oxide layer is 1-2 nm, which may be 1 nm, 1.2 nm, 1.4 nm, 1.6 nm, 1.8 nm, 2 nm, and any value therebetween. Preferably, the thickness of the fourth tunnel oxide layer is 1.2 nm.

[0070] In some embodiments, the thickness ratio of the third tunnel oxide layer and the fourth tunnel oxide layer is 1:1-2, which can be 1:1, 1:1.2, 1:1.4, 1:1.6, 1:1.8, 1:2 and any value therebetween. Preferably, the thickness ratio of the third tunnel oxide layer and the fourth tunnel oxide layer is 1:1.33.

[0071] The tunneling oxide layer can neutralize the unsaturated bonds at the interface and provide excellent surface chemical passivation effect. The presence of the tunneling oxide layer is crucial to reducing the recombination of carriers on the surface of the silicon wafer, thereby improving the efficiency of the battery. The present application makes differentiated settings for the thickness of the tunneling oxide layer on the front and back of the battery, corresponding to the different passivation requirements of the front and back sides, respectively, and at the same time reasonably sets the thickness ratio of the third tunneling oxide layer and the fourth tunneling oxide layer, which can further optimize the chemical passivation effect of the battery and improve the conversion efficiency of the battery. The present application reasonably sets the thickness of the third tunneling oxide layer and the fourth tunneling oxide layer, taking into account both the transmittance enhancement and anti-reflection and passivation effects on the front of the battery, and mainly considering the passivation effect on the back of the battery. The synergistic effect of the reasonable thickness ratio of the two is conducive to further improving the battery efficiency.

[0072] In some embodiments, the thickness of the first amorphous silicon layer is 2-20 nm, which may be 2 nm, 6 nm, 10 nm, 14 nm, 18 nm, 20 nm and any value therebetween. Preferably, the thickness of the first amorphous silicon layer is 5 nm.

[0073] In some embodiments, the thickness of the second amorphous silicon layer is 4-40nm, which can be 4nm, 10nm, 15nm, 20nm, 25nm, 30nm, 35nm, 40nm and any value therebetween. Preferably, the thickness of the second amorphous silicon layer is 10nm.

[0074] In some embodiments, the thickness ratio of the first amorphous silicon layer and the second amorphous silicon layer is 1:1.2-5, which can be 1:1.2, 1:2, 1:3, 1:4, 1:5 and any value therebetween. Preferably, the thickness ratio of the first amorphous silicon layer and the second amorphous silicon layer is 1:2.

[0075] The thickness of the amorphous silicon layer directly affects its passivation effect on the surface of the silicon wafer. The present application adopts a suitable thickness of the amorphous silicon layer, which can effectively passivate the dangling bonds on the surface of the silicon wafer, reduce defect recombination, and thus increase the minority carrier lifetime. At the same time, the appropriate thickness can ensure sufficient light transmittance while maintaining a good passivation effect. The present application makes differentiated settings for the thickness of the amorphous silicon layer on the front and back of the battery, corresponding to the different passivation requirements of the front and back, respectively, and reasonably sets the thickness ratio of the first amorphous silicon layer and the second amorphous silicon layer, which can effectively optimize the chemical passivation effect of the battery and improve the conversion efficiency of the battery. The present application reasonably sets the thickness of the first amorphous silicon layer and the second amorphous silicon layer, taking into account both the anti-reflection and passivation effects on the front of the battery, and mainly considering the passivation effect on the back of the battery. The synergistic effect of the reasonable thickness ratio of the two is conducive to further improving the battery efficiency.

[0076] In some embodiments, the thickness of the first anti-reflection layer is 65-120 nm, and can be 65 nm, 80 nm, 100 nm, 120 nm, and any value therebetween. Preferably, the thickness of the first anti-reflection layer is 75 nm.

[0077] In some embodiments, the thickness of the second anti-reflection layer is 40-90 nm, and can be 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, and any value therebetween. Preferably, the thickness of the second anti-reflection layer is 60 nm.

[0078] In some embodiments, the thickness ratio of the first anti-reflection layer and the second anti-reflection layer is 1:0.3-1, which can be 1:0.3, 1:0.4, 1:0.5, 1:0.6, 1:0.7, 1:0.8, 1:0.9, 1:1 and any value therebetween. Preferably, the thickness ratio of the first anti-reflection layer and the second anti-reflection layer is 1:0.8.

[0079] Preferably, the first anti-reflection layer and the second anti-reflection layer are both silicon dielectric films, more specifically, they can be one of silicon nitride, silicon oxynitride, and silicon oxide. Preferably, the first anti-reflection layer and the second anti-reflection layer are both silicon nitride layers.

[0080] Most of the back surface of the back contact battery is polished. To adapt to the reflection effect on the polished surface, the thickness of the second anti-reflection layer is set thinner in this application to adapt to the specific passivation requirements of the back surface. This application creatively differentiates the thickness of the passivation layer structure on the front and back sides, corresponding to the different passivation requirements of the front and back sides, which can further improve the passivation effect of the battery, thereby improving the battery efficiency.

[0081] In some embodiments, the refractive index of the second amorphous silicon layer is 2.2-4, and the refractive index of the second amorphous silicon layer gradually decreases from the fourth tunneling oxide layer to the second anti-reflection layer. The present application also adopts a gradient refractive index design on the amorphous silicon layer on the back of the battery. The gradient refractive index design of the second amorphous silicon layer is mainly conducive to improving the bifaciality of the battery (i.e., the amount of electricity generated by the battery after solar energy is reflected from the ground), thereby improving the battery conversion efficiency.

[0082] The gradient of the refractive index of the amorphous silicon layer can optimize the propagation path of light in the battery structure, thereby improving the efficiency of light absorption. This design can cause more reflection and refraction of light when entering the amorphous silicon layer, increase the interaction time between light and the material, and thus improve the efficiency of photogenerated carrier generation. The gradient of the refractive index of the amorphous silicon layer helps to reduce the loss of light in the amorphous silicon layer. Through the gradient design, the reflection loss of light at the interface can be reduced, so that more light energy can be absorbed and converted into electrical energy.

[0083] In some embodiments, the hybrid passivated back contact cell further includes a first electrode and a second electrode, the first electrode passes through the fourth tunneling oxide layer, the second amorphous silicon layer and the second anti-reflection layer to contact the first semiconductor layer; the second electrode passes through the fourth tunneling oxide layer, the second amorphous silicon layer and the second anti-reflection layer to contact the second semiconductor layer. It can be understood that the first electrode and the second electrode are divided into two polarities, and the polarities of the first electrode and the second electrode are different.

[0084] In some embodiments, the first semiconductor layer includes at least a first tunneling oxide layer and a first doped polycrystalline layer, the thickness of the first tunneling oxide layer is 1-2 nm; the thickness of the first doped polycrystalline layer is 150-250 nm. Those skilled in the art can select the effective doping concentration of the first doped polycrystalline layer according to actual needs, and the present application has no particular restrictions on this.

[0085] In some embodiments, the second semiconductor layer includes a second tunneling oxide layer and a second doped polycrystalline layer, the thickness of the second tunneling oxide layer is 1-2 nm; the thickness of the second doped polycrystalline layer is 150-250 nm. Those skilled in the art can select the effective doping concentration of the second doped polycrystalline layer according to actual needs, and this application has no particular restrictions on this.

[0086] In a second aspect, the present application provides a method for preparing a hybrid passivated back contact battery, the preparation method comprising the following steps:

[0087] S101, polishing and cleaning the front and back sides of the silicon wafer in sequence;

[0088] The silicon wafer is an N-type silicon wafer.

[0089] S102, sequentially forming a first semiconductor layer and a first mask layer on the back side of the silicon wafer;

[0090] The first semiconductor layer includes a first tunneling oxide layer and a first doped polycrystalline layer formed in sequence on the back side, the first doped polycrystalline layer is a P-type doped polycrystalline layer, and the first mask layer is a borosilicate glass (BSG) layer; the specific formation method of the first semiconductor layer and the first mask layer is: firstly depositing the first tunneling oxide layer and the intrinsic polycrystalline layer by LPCVD, and then performing boron diffusion on the intrinsic polycrystalline layer to form a P-type doped polycrystalline layer and a borosilicate glass (BSG) layer; after the boron diffusion, most of the bottom layer of the intrinsic polycrystalline layer is a P-type doped polycrystalline layer, and the top layer is a borosilicate glass (BSG) layer.

[0091] The thickness of the first tunneling oxide layer is 1-2 nm, the thickness of the first doped polycrystalline layer is 150-250 nm, and the thickness of the first mask layer is 20-80 nm.

[0092] S103, performing a first etching on the first semiconductor layer and the first mask layer on the back surface obtained in S102 to form first opening areas distributed at intervals;

[0093] The width of the first opening region is 200-600 μm.

[0094] The width of the first opening area accounts for 30-50% of Pitch. Pitch refers to the total width of the first opening area and the first semiconductor layer. A suitable proportion is beneficial to improving battery efficiency.

[0095] S104, removing the first semiconductor layer in the first opening area by polishing and cleaning to form a polishing surface;

[0096] S105, forming a second semiconductor layer and a second mask layer in sequence on the back surface obtained in S104;

[0097] The second semiconductor layer includes a second tunneling oxide layer and a second doped polycrystalline layer, the second doped polycrystalline layer is an N-type doped polycrystalline layer, and the second mask layer is a phosphosilicate glass (PSG) layer; the specific method for forming the second semiconductor layer and the second mask layer is: firstly depositing the second tunneling oxide layer and the intrinsic polycrystalline layer by LPCVD, and then performing phosphorus diffusion on the intrinsic polycrystalline layer to form an N-type doped polycrystalline layer and a phosphosilicate glass (PSG) layer; after the phosphorus diffusion, most of the bottom layer of the intrinsic polycrystalline layer is an N-type doped polycrystalline layer, and the top layer is a phosphosilicate glass (PSG) layer.

[0098] The thickness of the second tunneling oxide layer is 1-2 nm, the thickness of the second doped polycrystalline layer is 150-250 nm, and the thickness of the second mask layer is 20-80 nm.

[0099] S106, performing a second etching on the second mask layer on the back surface obtained in S105 to form a second opening area distributed at intervals, and performing a third etching on the second mask layer at the junction of the first semiconductor layer and the second semiconductor layer to form a third opening area distributed at intervals;

[0100] There is or there is no second mask layer between the second opening region and the third opening region.

[0101] When there is a second mask layer between the second opening region and the third opening region, the width of the second opening region is 100-500 μm, and the width of the third opening region is 40-150 μm.

[0102] When there is no second mask layer between the second opening region and the third opening region, the second opening region and the third opening region together form a composite opening region, and the width of the composite opening region is 400-800 μm.

[0103] A preferred solution is to form a composite opening area with the second opening area and the third opening area. When this solution is adopted, the second semiconductor layer remaining on the first semiconductor layer can be completely removed in the subsequent S107, reducing the parasitic absorption of the second semiconductor layer on the first semiconductor, thereby increasing the battery current.

[0104] S107, removing the second semiconductor layer without the second mask layer, forming a textured surface in the area of ​​the first opening region without the second semiconductor layer, and forming a textured surface on the front side of the silicon wafer;

[0105] The area on the back of the silicon wafer that contacts the first semiconductor layer forms a first polishing area, the area that contacts the second semiconductor layer forms a second polishing area, and the area in the first opening area that does not have the second semiconductor layer forms a texturing area; the width of the texturing area is 10-50μm.

[0106] The textured area is located in the third opening area, and the width of the third opening area: the width of the textured area = 1.1-6:1. If the width of the textured area is too narrow, it is easy to cause poor isolation effect and thus cause micro short circuit, thereby affecting parallel resistance and battery efficiency. If the width of the textured area is too wide, it is easy to increase the loss of lateral carrier transmission and thus increase the series resistance, thereby affecting battery efficiency. The present application can ensure the insulation effect while avoiding affecting battery efficiency by reasonably setting the width of the textured area.

[0107] S108, cleaning and removing the first mask layer and the second mask layer exposed on the back side of the silicon wafer;

[0108] S109, forming a third tunneling oxide layer, a first amorphous silicon layer and a first anti-reflection layer in sequence on the front side of the silicon wafer by using tubular PECVD;

[0109] The refractive index of the first amorphous silicon layer is 2.2-4, and the refractive index of the first amorphous silicon layer gradually decreases from the third tunneling oxide layer to the first anti-reflection layer. This structure can further improve the passivation effect of the battery and reduce the equipment cost.

[0110] S110, forming a fourth tunnel oxide layer, a second amorphous silicon layer, and a second anti-reflection layer in sequence on the back side of the silicon wafer by using tubular PECVD;

[0111] The second amorphous silicon layer may be designed with a gradient refractive index or a fixed refractive index.

[0112] Preferably, the refractive index of the second amorphous silicon layer is 2.2-4, and the refractive index of the second amorphous silicon layer gradually decreases from the fourth tunneling oxide layer to the second anti-reflection layer. The present application also adopts a gradient refractive index design on the amorphous silicon layer on the back of the battery. The gradient refractive index design of the second amorphous silicon layer is mainly conducive to improving the bifaciality of the battery (i.e., the amount of electricity generated by the battery after solar energy is reflected from the ground).

[0113] S111 , forming a first electrode and a second electrode respectively on the first semiconductor layer and the second semiconductor layer on the back side obtained in S110 .

[0114] The first electrode and the second electrode can be formed by printing, electroplating, or inkjet printing.

[0115] In some embodiments, the order of step S109 and step S110 can be interchanged, and the tunneling oxide layer, amorphous silicon layer, and anti-reflection layer on the front and back sides can be deposited in the same tubular PECVD. The order can be changed according to actual production needs, thereby expanding the adjustability of the deposition process.

[0116] The present application adopts a tunneling oxide layer, an amorphous silicon layer, and an anti-reflection layer to replace aluminum oxide and silicon nitride in the texturing area on the front and back of the battery, thereby improving the passivation effect of the battery and thus improving the battery efficiency. In addition, the tunneling oxide layer, amorphous silicon layer, and anti-reflection layer on the front and back sides can be deposited and formed in the same tubular PECVD, which further simplifies the process steps and reduces the equipment cost.

[0117] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0118] Example 1

[0119] like Figures 1 to 11 As shown, a method for preparing a hybrid passivated back contact battery comprises the following steps:

[0120] S101, such as Figure 1 As shown, the front and back sides of the silicon wafer 1 are polished and cleaned in sequence, and the silicon wafer 1 is an N-type silicon wafer.

[0121] S102, such as Figure 2 As shown, a first semiconductor layer and a borosilicate glass (BSG) layer 3A are sequentially formed on the back side of the silicon wafer 1;

[0122] The first semiconductor layer includes a first tunneling oxide layer 2 and a P-type doped polycrystalline layer 3 formed in sequence on the back side; the specific method for forming the first semiconductor layer and the borosilicate glass (BSG) layer 3A is: firstly deposit the first tunneling oxide layer 2 and the intrinsic polycrystalline layer by LPCVD, and then diffuse boron on the intrinsic polycrystalline layer to form the P-type doped polycrystalline layer 3 and the borosilicate glass (BSG) layer 3A; after the boron diffusion, most of the bottom layer of the intrinsic polycrystalline layer is the P-type doped polycrystalline layer 3, and the top layer is the borosilicate glass (BSG) layer 3A.

[0123] The thickness of the first tunnel oxide layer 2 is 1.8 nm, the thickness of the P-type doped polycrystalline layer 3 is 220 nm, and the thickness of the borosilicate glass (BSG) layer 3A is 30 nm.

[0124] S103, such as Figure 3 As shown, the first semiconductor layer and the borosilicate glass (BSG) layer 3A are first etched on the back surface obtained in S102 to form first opening areas distributed at intervals;

[0125] The width W1 of the first opening region is 400 μm.

[0126] S104, such as Figure 4 As shown, the first semiconductor layer is removed in the first opening region by polishing and cleaning to form a polishing surface;

[0127] S105, such as Figure 5 As shown, a second semiconductor layer and a phosphosilicate glass (PSG) layer 5A are sequentially formed on the back surface obtained in S104;

[0128] The second semiconductor layer includes a second tunneling oxide layer 4 and an N-type doped polycrystalline layer 5; the specific method for forming the second semiconductor layer and the phosphosilicate glass (PSG) layer 5A is as follows: firstly, the second tunneling oxide layer 4 and the intrinsic polycrystalline layer are deposited by LPCVD, and then phosphorus is diffused on the intrinsic polycrystalline layer to form an N-type doped polycrystalline layer 5 and a phosphosilicate glass (PSG) layer 5A; after the phosphorus diffusion, most of the bottom layer of the intrinsic polycrystalline layer is the N-type doped polycrystalline layer 5, and the top layer is the phosphosilicate glass (PSG) layer 5A.

[0129] The thickness of the second tunnel oxide layer 4 is 1.6 nm, the thickness of the N-type doped polycrystalline layer 5 is 200 nm, and the thickness of the phospho-silicate glass (PSG) layer 5A is 40 nm.

[0130] S106, such as Figure 6 As shown, the phosphosilicate glass (PSG) layer 5A on the back side of the first semiconductor layer obtained in S105 is subjected to a second etching to form a second opening area distributed at intervals, and at the same time, the phosphosilicate glass (PSG) layer 5A at the junction of the first semiconductor layer and the second semiconductor layer is subjected to a third etching to form a third opening area distributed at intervals; the second opening area and the third opening area together form a composite opening area, and the width W23 of the composite opening area is 600μm.

[0131] S107, such as Figure 7 As shown, the second semiconductor layer without the phosphosilicate glass (PSG) layer 5A is removed, a textured surface is formed in the area without the second semiconductor layer in the first opening area, and a textured surface is formed on the front side of the silicon wafer 1;

[0132] The area on the back of the silicon wafer 1 that contacts the first semiconductor layer forms a first polishing area, the area that contacts the second semiconductor layer forms a second polishing area, and the area in the first opening area that does not have the second semiconductor layer forms a texturing area; the width W4 of the texturing area is 50 μm.

[0133] S108, such as Figure 8 As shown, the borosilicate glass (BSG) layer 3A and the phosphosilicate glass (PSG) layer 5A exposed on the back side of the silicon wafer 1 are cleaned and removed;

[0134] S109, such as Fig. 9 As shown, a third tunnel oxide layer 6, a first amorphous silicon layer 7 and a first anti-reflection layer 8 are sequentially formed on the front side of the silicon wafer 1 by using tubular PECVD;

[0135] The thickness of the third tunnel oxide layer 6 is 0.9 nm, the thickness of the first amorphous silicon layer 7 is 5 nm, and the thickness of the first anti-reflection layer 8 is 75 nm. The first anti-reflection layer 8 is a silicon nitride layer.

[0136] The refractive index of the first amorphous silicon layer 7 is 2.2-4, and the refractive index of the first amorphous silicon layer 7 gradually decreases from the third tunneling oxide layer 6 to the first anti-reflection layer 8 .

[0137] S110, such as Fig.10 As shown, a fourth tunnel oxide layer 9, a second amorphous silicon layer 10 and a second anti-reflection layer 11 are sequentially formed on the back side of the silicon wafer 1 by using tubular PECVD;

[0138] The thickness of the fourth tunnel oxide layer 9 is 1.2 nm, the thickness of the second amorphous silicon layer 10 is 10 nm, and the thickness of the second anti-reflection layer 11 is 60 nm. The second anti-reflection layer 11 is a silicon nitride layer.

[0139] The refractive index of the second amorphous silicon layer 10 is 2.2-4, and the refractive index of the second amorphous silicon layer 10 gradually decreases from the fourth tunneling oxide layer 9 to the second anti-reflection layer 11 .

[0140] The thickness ratio of the third tunnel oxide layer to the fourth tunnel oxide layer is 1:1.33.

[0141] The thickness ratio of the first amorphous silicon layer to the second amorphous silicon layer is 1:2.

[0142] The thickness ratio of the first anti-reflection layer to the second anti-reflection layer is 1:0.8.

[0143] S111, such as Fig.11 As shown, a first electrode 12 and a second electrode 13 are respectively formed on the first semiconductor layer and the second semiconductor layer on the back side obtained in S110.

[0144] Example 2

[0145] The method of Example 1 is referred to, except that the second semiconductor layer on the first semiconductor layer is not completely removed. The process parameters that need to be adjusted to meet this condition are:

[0146] S106, such as Fig.12As shown, the phosphosilicate glass (PSG) layer 5A on the back side of the first semiconductor layer obtained in S105 is subjected to a second etching to form a second opening area distributed at intervals, and at the same time, the phosphosilicate glass (PSG) layer 5A at the junction of the first semiconductor layer and the second semiconductor layer is subjected to a third etching to form a third opening area distributed at intervals; the width W2 of the second opening area is 200μm, and the width W3 of the third opening area is 100μm.

[0147] S107, such as Fig.13 As shown, the second semiconductor layer without the phosphosilicate glass (PSG) layer 5A is removed, a textured surface is formed in the area without the second semiconductor layer in the first opening area, and a textured surface is formed on the front side of the silicon wafer 1;

[0148] The area on the back of the silicon wafer 1 that contacts the first semiconductor layer forms a first polishing area, the area that contacts the second semiconductor layer forms a second polishing area, and the area in the first opening area that does not have the second semiconductor layer forms a texturing area; the width W4 of the texturing area is 50 μm.

[0149] S108, such as Fig.14 As shown, the borosilicate glass (BSG) layer 3A and the phosphosilicate glass (PSG) layer 5A exposed on the back side of the silicon wafer 1 are cleaned and removed;

[0150] S109, such as Fig.15 As shown, a third tunnel oxide layer 6, a first amorphous silicon layer 7 and a first anti-reflection layer 8 are sequentially formed on the front side of the silicon wafer 1 by using tubular PECVD;

[0151] The thickness of the third tunnel oxide layer 6 is 0.9 nm, the thickness of the first amorphous silicon layer 7 is 5 nm, and the thickness of the first anti-reflection layer 8 is 75 nm. The first anti-reflection layer 8 is a silicon nitride layer.

[0152] The refractive index of the first amorphous silicon layer 7 is 2.2-4, and the refractive index of the first amorphous silicon layer 7 gradually decreases from the third tunneling oxide layer 6 to the first anti-reflection layer 8 .

[0153] S110, such as Fig.15 As shown, a fourth tunnel oxide layer 9, a second amorphous silicon layer 10 and a second anti-reflection layer 11 are sequentially formed on the back side of the silicon wafer 1 by using tubular PECVD;

[0154] The thickness of the fourth tunnel oxide layer 9 is 1.2 nm, the thickness of the second amorphous silicon layer 10 is 10 nm, and the thickness of the second anti-reflection layer 11 is 60 nm. The second anti-reflection layer 11 is a silicon nitride layer.

[0155] The refractive index of the second amorphous silicon layer 10 is 2.2-4, and the refractive index of the second amorphous silicon layer 10 gradually decreases from the fourth tunneling oxide layer 9 to the second anti-reflection layer 11 .

[0156] The thickness ratio of the third tunnel oxide layer to the fourth tunnel oxide layer is 1:1.33.

[0157] The thickness ratio of the first amorphous silicon layer to the second amorphous silicon layer is 1:2.

[0158] The thickness ratio of the first anti-reflection layer to the second anti-reflection layer is 1:0.8.

[0159] S111, such as Fig.16 As shown, a first electrode 12 and a second electrode 13 are respectively formed on the first semiconductor layer and the second semiconductor layer on the back side obtained in S110.

[0160] Example 3

[0161] The method of Example 1 is referred to, except that, in S110 , the refractive index of the second amorphous silicon layer 10 is designed to be a fixed refractive index, and the refractive index of the second amorphous silicon layer 10 is 3.2.

[0162] Example 4

[0163] The method of Example 1 is referred to, except that the third tunneling oxide layer 6 has a thickness of 1.2 nm, the first amorphous silicon layer 7 has a thickness of 8 nm, and the first anti-reflection layer 8 has a thickness of 100 nm, and the first anti-reflection layer 8 is a silicon nitride layer.

[0164] The thickness ratio of the third tunnel oxide layer to the fourth tunnel oxide layer is 1:1.

[0165] The thickness ratio of the first amorphous silicon layer to the second amorphous silicon layer is 1:1.25.

[0166] The thickness ratio of the first anti-reflection layer to the second anti-reflection layer is 1:0.6.

[0167] Example 5

[0168] The method of Example 1 is referred to, except that the thickness of the fourth tunnel oxide layer 9 is 1.5 nm, the thickness of the second amorphous silicon layer 10 is 15 nm, and the thickness of the second anti-reflection layer 11 is 75 nm, and the second anti-reflection layer 11 is a silicon nitride layer.

[0169] Wherein, the thickness ratio of the third tunnel oxide layer to the fourth tunnel oxide layer is 1:1.66.

[0170] The thickness ratio of the first amorphous silicon layer to the second amorphous silicon layer is 1:3.

[0171] The thickness ratio of the first anti-reflection layer to the second anti-reflection layer is 1:1.

[0172] Comparative Example 1

[0173] The method of Example 2 is carried out, except that the front and back sides of the silicon wafer are not tunnel oxide layers, such as amorphous silicon layers. Fig.17 As shown, specifically, it is replaced as follows: the front side of the silicon wafer 1 is a first aluminum oxide layer 14 , the back side of the silicon wafer 1 is a second aluminum oxide layer 15 , the first anti-reflection layer 8 is arranged on the first aluminum oxide layer 14 , and the second anti-reflection layer 11 is arranged on the second aluminum oxide layer 15 .

[0174] The process parameters that need to be adjusted to meet this condition are: in S109, the first aluminum oxide layer 14 and the second aluminum oxide layer 15 are formed simultaneously by ALD (atomic layer deposition), and then in S110, the first anti-reflection layer 8 and the second anti-reflection layer 11 are formed respectively by PECVD. It should be noted that the order of S109 and S110 cannot be reversed.

[0175] Comparative Example 2

[0176] The method of Example 1 is referred to, except that, in S109 , the refractive index of the first amorphous silicon layer 7 is designed to be a fixed refractive index, and the refractive index of the first amorphous silicon layer 7 is 3.2.

[0177] Comparative Example 3

[0178] The method of Example 1 is referred to, except that in S110, the thickness of the second anti-reflection layer 11 is 120 nm, and the thickness ratio of the first anti-reflection layer to the second anti-reflection layer is 1:1.6.

[0179] Comparative Example 4

[0180] The method of Example 1 is referred to, except that in S101, the silicon wafer 1 is a P-type silicon wafer.

[0181] Test Case

[0182] The back contact cells obtained in the above-mentioned embodiments and comparative examples were subjected to various performance tests, and the results are shown in Table 1. Among them, the short-circuit current and equipment cost of each embodiment and comparative example were converted using embodiment 1 as a reference benchmark, the data of embodiment 1 was normalized benchmark 1, and other examples were converted based on embodiment 1, such as the short-circuit current of comparative example 1 / the short-circuit current of embodiment 1 was 0.994.

[0183] Table 1

[0184]

[0185] It can be seen from the above results that, because the second semiconductor layer still remains on the first semiconductor layer in the current prior art, the basic structure of Comparative Example 1 is prepared by the method of Example 2. Comparison between Comparative Example 1 and Example 2 shows that the present application uses a tunneling oxide layer, an amorphous silicon layer, and an anti-reflection layer to replace aluminum oxide and silicon nitride in the texturing area on the front and back of the battery, thereby improving the short-circuit current of the battery, improving the passivation effect of the battery, and thus improving the battery efficiency. In addition, the tunneling oxide layer, amorphous silicon layer, and anti-reflection layer on the front and back sides can be deposited and formed in the same tubular PECVD, which further simplifies the process steps and reduces the equipment cost.

[0186] Furthermore, according to Example 1 and Comparative Example 2, the present application adopts a gradient refractive index design for the first amorphous silicon layer on the front side of the silicon wafer. This structure can further improve the passivation effect of the battery and reduce the equipment cost.

[0187] Furthermore, according to Example 1 and Comparative Example 3, most of the back side of the back-contact battery is a polished surface. In order to adapt to the reflection effect on the polished surface, the present application sets the thickness of the second anti-reflection layer to be thinner to adapt to the specific passivation requirements of the back side, which can further improve the passivation effect of the battery, thereby improving the battery efficiency.

[0188] Furthermore, according to Example 1 and Comparative Example 4, it can be seen that, compared with the use of P-type batteries, the N-type battery of the present application can obtain higher short-circuit current and battery conversion efficiency.

[0189] Furthermore, according to Example 1 and Example 2, compared with the second semiconductor layer on the first semiconductor layer not being completely removed, the preferred solution of the present application is to form a composite opening area with the second opening area and the third opening area. When this solution is adopted, the second semiconductor layer remaining on the first semiconductor layer can be completely removed in the subsequent S107, reducing the parasitic absorption of the corresponding second semiconductor layer on the first semiconductor, thereby increasing the battery current and further improving the battery conversion efficiency.

[0190] Furthermore, according to Example 1 and Example 3, it can be seen that compared with the second amorphous silicon layer having a fixed refractive index design, the second amorphous silicon layer in the preferred scheme of the present application has a gradient refractive index design. The gradient refractive index design of the second amorphous silicon layer is more conducive to improving the bifaciality of the battery (i.e., the amount of electricity absorbed by the battery after solar energy is reflected from the ground), which can increase the short-circuit current and thereby improve the battery conversion efficiency.

[0191] Furthermore, according to Example 1 and Example 4, by adopting the thickness of the third tunneling oxide layer, the first amorphous silicon layer and the first anti-reflection layer preferred in the present application and setting a suitable thickness ratio between the front and back sides, the passivation effect of the battery can be improved, the short-circuit current can be increased, and the battery efficiency can be thereby improved.

[0192] Furthermore, according to Example 1 and Example 5, by adopting the preferred thicknesses of the fourth tunnel oxide layer, the second amorphous silicon layer and the second anti-reflection layer of the present application and setting an appropriate thickness ratio between the front and back sides, the passivation effect of the battery can be improved, the short-circuit current can be increased, and the battery efficiency can be improved.

[0193] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0194] The embodiments of the present application are introduced in detail above. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method and core idea of ​​the present application. At the same time, for general technical personnel in this field, according to the idea of ​​the present application, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A hybrid passivated back contact cell, characterized in that: include: A silicon wafer, wherein the silicon wafer has a front side and a back side; a third tunneling oxide layer, a first amorphous silicon layer and a first anti-reflection layer are sequentially arranged on the front side of the silicon wafer; Along the X-axis direction of the back side of the silicon wafer, the back side of the silicon wafer is alternately arranged with a first polishing area and a second polishing area; Along the Z-axis direction of the back side of the silicon wafer, at least a first semiconductor layer is disposed on the first polishing area; At least a second semiconductor layer is disposed on the second polishing area along the Z-axis direction of the back side of the silicon wafer; A texturing area is provided between the first polishing area and the adjacent second polishing area, and the texturing area isolates the first semiconductor layer from the second semiconductor layer; A fourth tunneling oxide layer, a second amorphous silicon layer and a second anti-reflection layer are sequentially disposed on the first polishing area, the texturing area and the second polishing area; Among them, the refractive index of the first amorphous silicon layer is 2.2-4, and the refractive index of the first amorphous silicon layer gradually decreases from the third tunneling oxide layer to the first anti-reflection layer; the refractive index of the second amorphous silicon layer is 2.2-4, and the refractive index of the second amorphous silicon layer gradually decreases from the fourth tunneling oxide layer to the second anti-reflection layer.

2. The hybrid passivated back contact cell according to claim 1, characterized in that: The thickness of the third tunnel oxide layer is 0.5-1.5 nm, and the thickness of the fourth tunnel oxide layer is 1-2 nm; and / or, The thickness ratio of the third tunnel oxide layer to the fourth tunnel oxide layer is 1:(1-2).

3. The hybrid passivated back contact cell according to claim 1, characterized in that: The thickness of the first anti-reflection layer is 65-120 nm, and the thickness of the second anti-reflection layer is 40-90 nm; and / or, The thickness ratio of the first anti-reflection layer to the second anti-reflection layer is 1:(0.3-1).

4. The hybrid passivated back contact cell according to claim 1, characterized in that: The thickness of the first amorphous silicon layer is 2-20 nm, and the thickness of the second amorphous silicon layer is 4-40 nm; and / or, The thickness ratio of the first amorphous silicon layer to the second amorphous silicon layer is 1:(1.2-5).

5. The hybrid passivated back contact cell according to claim 1, characterized in that: The hybrid passivated back contact cell also includes: a first electrode, the first electrode passing through the fourth tunneling oxide layer, the second amorphous silicon layer and the second anti-reflection layer and contacting the first semiconductor layer; A second electrode is provided, wherein the second electrode passes through the fourth tunneling oxide layer, the second amorphous silicon layer and the second anti-reflection layer and contacts the second semiconductor layer.

6. The hybrid passivated back contact cell according to claim 1, characterized in that: The first semiconductor layer at least comprises: A first tunneling oxide layer, wherein the thickness of the first tunneling oxide layer is 1-2 nm; A first doped polycrystalline layer, wherein the thickness of the first doped polycrystalline layer is 150-250 nm; and / or, The second semiconductor layer comprises: A second tunneling oxide layer, wherein the thickness of the second tunneling oxide layer is 1-2 nm; The second doped polycrystalline layer has a thickness of 150-250 nm.

7. A method for preparing a hybrid passivated back contact battery, characterized in that: The preparation method is used to prepare a hybrid passivated back contact battery according to any one of claims 1 to 6, and the preparation method comprises the following steps: S101, polishing and cleaning the front and back sides of the silicon wafer in sequence; S102, sequentially forming a first semiconductor layer and a first mask layer on the back side of the silicon wafer; S103, performing a first etching on the first semiconductor layer and the first mask layer on the back surface obtained in S102 to form first opening areas distributed at intervals; S104, removing the first semiconductor layer in the first opening area by polishing and cleaning to form a polishing surface; S105, forming a second semiconductor layer and a second mask layer in sequence on the back surface obtained in S104; S106, performing a second etching on the second mask layer on the back surface obtained in S105 to form a second opening area distributed at intervals, and performing a third etching on the second mask layer at the junction of the first semiconductor layer and the second semiconductor layer to form a third opening area distributed at intervals; S107, removing the second semiconductor layer without the second mask layer, forming a textured surface in the area of ​​the first opening region without the second semiconductor layer, and forming a textured surface on the front side of the silicon wafer; The area on the back of the silicon wafer that contacts the first semiconductor layer forms a first polishing area, the area on the back of the silicon wafer that contacts the second semiconductor layer forms a second polishing area, and the area on the first opening that does not have the second semiconductor layer forms a texturing area; S108, cleaning and removing the first mask layer and the second mask layer exposed on the back side of the silicon wafer; S109, forming a third tunneling oxide layer, a first amorphous silicon layer and a first anti-reflection layer in sequence on the front side of the silicon wafer by using tubular PECVD; S110, forming a fourth tunnel oxide layer, a second amorphous silicon layer, and a second anti-reflection layer in sequence on the back side of the silicon wafer by using tubular PECVD; The refractive index of the first amorphous silicon layer is 2.2-4, and the refractive index of the first amorphous silicon layer gradually decreases from the third tunneling oxide layer to the first anti-reflection layer.

8. The preparation method according to claim 7, characterized in that: The width of the first opening area is 200-600 μm; and / or, The width of the texturing area is 10-50μm.

9. The preparation method according to claim 7, characterized in that: In S106 , a second mask layer is provided between the second opening region and the third opening region or no second mask layer is provided between the second opening region and the third opening region.

10. The preparation method according to claim 9, characterized in that: When there is a second mask layer between the second opening region and the third opening region, the width of the second opening region is 100-500 μm, and the width of the third opening region is 40-150 μm.

11. The preparation method according to claim 9, characterized in that: When there is no second mask layer between the second opening region and the third opening region, the second opening region and the third opening region together form a composite opening region, and the width of the composite opening region is 400-800 μm.

12. The preparation method according to claim 7, characterized in that: The order of step S109 and step S110 is interchanged.

13. The preparation method according to claim 7, characterized in that: After S110 , the method further includes forming a first electrode and a second electrode respectively on the first semiconductor layer and the second semiconductor layer on the back side obtained in S110 .

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