Three-dimensional integrated hafnium-based ferroelectric device and method of manufacturing the same

Abstract

The application provides a three-dimensional integrated hafnium-based ferroelectric device and a preparation method thereof, and comprises a substrate, a bottom electrode layer comprising a plurality of stacked structures, the bottom electrode layer comprising a plurality of parallel step structures, all the step structures being arranged on the substrate, each step structure comprising a first metal layer, a plurality of stacked structures and a first insulating layer, the first metal layer being arranged on the substrate, all the stacked structures being sequentially stacked on the first metal layer, and the first insulating layer being arranged on the top stacked structure, a ferroelectric material layer covering the bottom electrode layer, and a top electrode layer covering the ferroelectric material layer. The application has the advantages that the remanent polarization and the capacitance value can be improved without reducing the area of the planar device, and the performance of the ferroelectric memory is improved.

Description

Technical Field

[0001] This invention relates to the field of memory, and more particularly to a three-dimensional integrated hafnium-based ferroelectric device and its fabrication method. Background Technology

[0002] As integrated circuits continue to evolve towards higher densities and device sizes shrink, gate control capabilities are declining, and short-channel effects are severely impacting device performance. Compared to SiO2 (K ~ 3.9), HfO2, with its higher K value (relative permittivity, K ~ 25), effectively suppresses short-channel effects and improves gate control capabilities. Since Intel's 45nm process, it has been widely used as a gate dielectric material in CMOS devices. Furthermore, by doping HfO2 with different elements such as Si, Al, and Zr, its ferroelectric phase (O phase) can be obtained at room temperature. Compared to traditional ferroelectric materials, Hf-based ferroelectric materials maintain excellent ferroelectric properties even at very thin thicknesses (nm level), require lower fabrication temperatures, are environmentally friendly, and are highly compatible with traditional CMOS processes. Additionally, the two stable polarization states of ferroelectric materials can be maintained without an electric field, making them very promising for non-volatile memory (NVM) technology.

[0003] Currently, there are three main types of ferroelectric memories: Ferroelectric Random Access Memory (FeRAM), Ferroelectric Field Effect Transistor (FeFET), and Ferroelectric Tunneling Junction (FTJ). Among these, ferroelectric RAM and FTJ devices are typical metal-insulator-metal (MIM) capacitor structures. In the design of these two types of ferroelectric memories, the memory performance (such as the storage window, i.e., the ability to distinguish different data states) depends on the device's residual polarization (i.e., the polarization state retained by the ferroelectric material after the electric field is removed) and capacitance value. Residual polarization and capacitance value are positively correlated with the area of ​​the planar device, and the area of ​​the planar device cannot be effectively reduced. Summary of the Invention

[0004] The purpose of this invention is to provide a three-dimensional integrated hafnium-based ferroelectric device and its fabrication method. Without reducing the area of ​​the planar device, the invention achieves the goal of improving residual polarization and capacitance by setting a stepped structure on the bottom electrode and a matching ferroelectric material layer, thereby effectively improving the performance of the ferroelectric memory.

[0005] In a first aspect, a three-dimensional integrated hafnium-based ferroelectric device includes:

[0006] Substrate;

[0007] The bottom electrode layer includes a plurality of parallel stepped structures, all of which are disposed on the substrate; each stepped structure includes a first metal layer, a plurality of stacked structures and a first insulating layer; the first metal layer is disposed on the substrate, all of which are stacked sequentially on the first metal layer, and the first insulating layer is disposed on the top stacked structure.

[0008] A ferroelectric material layer, wherein the ferroelectric material layer covers the bottom electrode layer;

[0009] A top electrode layer, which covers the ferroelectric material layer.

[0010] The beneficial effects of this invention are as follows: by forming a stepped structure on a substrate by incorporating a metal layer, multiple stacked structures, and an insulating layer, the stepped structure design allows the bottom electrode layer to have different heights in the vertical direction. This results in the electric field being concentrated or enhanced at the stepped structure when an electric field is applied. The enhanced electric field facilitates more complete flipping and alignment of the electric dipoles in the ferroelectric material layer, thereby improving the remanent polarization intensity. Secondly, the stepped structure increases the contact area between the bottom electrode layer and the ferroelectric material layer, and a larger contact area means a larger capacitance value. In addition, the additional insulating layer on the multiple stacked structures further ensures the uniform distribution of the electric field in the ferroelectric material layer. The additional metal layer under the multiple stacked structures increases the total area of ​​the bottom electrode layer, further improving its capacitance performance. Furthermore, this invention simplifies the manufacturing process and improves production efficiency by directly covering the ferroelectric material layer with the top electrode layer, eliminating the need for drilling holes or reserving space in the ferroelectric material layer.

[0011] Optionally, the stacked structure includes a second metal layer and a second insulating layer; the second insulating layer is disposed on the first metal layer, and the second metal layer is disposed on the second insulating layer.

[0012] Optionally, a groove structure or a perforated structure is provided between every two adjacent stepped structures.

[0013] Optionally, the materials of the first metal layer, the second metal layer, and the top electrode layer all include W, or are doped with TiN, TaN, or Ru.

[0014] Optionally, both the first insulating layer and the second insulating layer are high-K dielectric materials; the high-K dielectric materials include HfO2 or Al2O3.

[0015] Optionally, the material of the ferroelectric material layer includes Hf-based ferroelectric materials, or Hf-based ferroelectric materials doped with Zr, Al, La, Y, or Si.

[0016] Secondly, the present invention also provides a method for fabricating a three-dimensional integrated hafnium-based ferroelectric device, used to fabricate the aforementioned three-dimensional integrated hafnium-based ferroelectric device, the method comprising:

[0017] Step 1: On the substrate, a consistent number of metal layers and insulating layers are alternately deposited using a thin film growth process to form the bottom electrode layer;

[0018] Step 2: A photoresist mask is formed on the bottom electrode layer by photolithography. Then, the photoresist mask is used as a protective layer to perform reactive ion etching on the bottom electrode layer not covered by the mask to form multiple trench structures or hole structures.

[0019] Step 3: By moving the photoresist mask and performing reactive ion etching, the bottom electrode layer is etched to form a stepped structure;

[0020] Step 4: Form a ferroelectric material layer on the bottom electrode layer by atomic deposition;

[0021] Step 5: The top electrode layer is formed on the ferroelectric material layer using a thin film growth process.

[0022] The beneficial effects of the fabrication method for the three-dimensional integrated hafnium-based ferroelectric device of the present invention are that, by adjusting the parameters of the stepped structure and the trench structure or the aperture structure, the performance of the capacitor can be customized to meet specific application requirements. For example, in memory applications requiring high storage density and fast read / write speeds, the performance of the capacitor can be improved by increasing the number of stepped structure layers and reducing the size of the trenches (apertures). Furthermore, by forming a ferroelectric material layer on the bottom electrode layer using atomic deposition, the thickness and composition of the ferroelectric material can be precisely controlled, thereby obtaining a high-performance ferroelectric material. In addition, the use of modern semiconductor manufacturing processes such as thin film growth, photolithography, and reactive ion etching simplifies the fabrication process and improves production efficiency. Simultaneously, these processes also ensure the precision and consistency of the capacitor structure.

[0023] Optionally, step four specifically includes the following steps:

[0024] Step A: Using a photoresist mask, etch the first insulating layer at the top to form the first step portion of the stepped structure, starting from the top.

[0025] Step B: Shift the photoresist mask by one step width and etch the stacked structure below it to form the (N+1)th step from the top, where N is a positive integer greater than or equal to 1;

[0026] Step C: Repeat step B until only the first metal layer remains beneath the stacked structure.

[0027] Optionally, the etching of the metal layer in step two uses a fluorine-based gas, including SF6 or CF4, and the etching of the metal layer in step two uses a chlorine-based gas, including BCl3 or CCl4.

[0028] Optionally, the etching rate of the metal layer in step two is consistent with the etching rate of the insulating layer.

[0029] Optionally, in step two: the etching gas flow rate of the insulating layer is 30 sccm for BCl3 and 20 sccm for Ar, the etching power is 120 W, and the chamber pressure is 3 Pa; the etching gas flow rate of the metal layer is 10 sccm for SF6, 30 sccm for Ar, and 3 sccm for O2, the chamber pressure is 1 Pa, the etching power is 60 W for SRF and 20 W for BRF. Attached Figure Description

[0030] Figure 1 The image shown is a three-dimensional view of a three-dimensional integrated hafnium-based ferroelectric device provided by the present invention after its fabrication is completed;

[0031] Figure 2 The image shown is a perspective view of step one of the fabrication methods of a three-dimensional integrated hafnium-based ferroelectric device provided by the present invention.

[0032] Figure 3 The image shown is a three-dimensional view of step two of the fabrication method of a three-dimensional integrated hafnium-based ferroelectric device provided by the present invention, when the photoresist mask is set without etching trench or hole structures.

[0033] Figure 4 The image shown is a three-dimensional view of the etching of trench or hole structures in step two of the fabrication method of a three-dimensional integrated hafnium-based ferroelectric device provided by the present invention.

[0034] Figure 5 The image shown is a three-dimensional view of the removal of the photoresist mask after etching the trench structure or hole structure in step two of the fabrication method of a three-dimensional integrated hafnium-based ferroelectric device provided by the present invention.

[0035] Figure 6 The image shown is a three-dimensional view of the first step portion after etching in step three of the fabrication method of a three-dimensional integrated hafnium-based ferroelectric device provided by the present invention.

[0036] Figure 7 The image shown is a three-dimensional view of the etched step portion in step three of the fabrication method of a three-dimensional integrated hafnium-based ferroelectric device provided by the present invention.

[0037] Figure 8 The image shown is a three-dimensional view of step four, forming the ferroelectric material layer, in a method for fabricating a three-dimensional integrated hafnium-based ferroelectric device provided by the present invention. Detailed Implementation

[0038] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. Unless otherwise defined, the technical or scientific terms used herein should have the ordinary meaning understood by those skilled in the art. The terms "comprising" and similar expressions used herein mean that the element or object preceding the word covers the element or object listed after the word and its equivalents, but does not exclude other elements or objects.

[0039] like Figure 1 As shown, an embodiment of the present invention provides a three-dimensional integrated hafnium-based ferroelectric device, comprising:

[0040] Substrate 1;

[0041] Bottom electrode layer 2 includes multiple parallel stepped structures 3, all of which are disposed on substrate 1; each stepped structure 3 includes a first metal layer (i.e., Figure 1 The lowest metal layer 212), multiple stacked structures 21 and the first insulating layer (i.e. Figure 1 The uppermost insulating layer 211); the first metal layer is disposed on the substrate 1, all the stacked structures 21 are stacked sequentially on the first metal layer, and the first insulating layer is disposed on the top stacked structure 21.

[0042] Ferroelectric material layer 4 covers the bottom electrode layer 2;

[0043] Top electrode layer 5, which covers ferroelectric material layer 4.

[0044] In some embodiments, such as Figure 1 As shown, the stacked structure 21 includes a second metal layer (i.e., Figure 1 The middle layer is the metal layer 212 included in the label 21) and the second insulating layer (i.e. Figure 1 The middle layer is the insulating layer 211 encompassed by the label 21; the second insulating layer is disposed on the first metal layer, and the second metal layer is disposed on the second insulating layer.

[0045] In some embodiments, such as Figure 1 As shown, a groove structure 22 or a hole structure is provided between every two adjacent step structures 3.

[0046] In some embodiments, substrate 1 may be a Si (silicon material) substrate. Due to its long history of development and wide industrial applications, Si substrate has a very mature manufacturing process, which can effectively reduce costs and has good compatibility with other semiconductor and metal materials.

[0047] In some embodiments, the materials of the metal layer 212 (including the first metal layer and the second metal layer) and the top electrode layer 5 both include W (tungsten), or doped with TiN (titanium nitride), TaN (tantalum nitride), or Ru (ruthenium). These materials are stable in high-temperature and oxidizing environments, contributing to improved long-term stability and reliability of the device. Furthermore, the electrode materials remain stable during annealing; thus simplifying the process and preventing chemical reactions between the metal layer and adjacent materials during the direct annealing of Hf-based ferroelectric materials to achieve ferroelectricity. Additionally, tungsten is a high-melting-point, high-hardness metal; TiN and TaN improve electrode adhesion; and Ru (ruthenium) exhibits good ductility and processability, facilitating its fabrication and integration into semiconductor devices. Therefore, the materials of the metal layer 212 and the top electrode layer 5 can be selected according to the specific needs of the electrodes in different scenarios.

[0048] In some embodiments, the insulating layer 211 may be made of a high-K dielectric material (a material with a dielectric constant higher than that of silicon dioxide); the selected high-K dielectric materials include HfO2 (hafnium dioxide) and Al2O3 (aluminum oxide); the above materials can have a higher dielectric constant than silicon dioxide while maintaining good insulation performance, so that they can provide a larger capacitance value at the same thickness, and can effectively reduce leakage current and increase breakdown voltage.

[0049] In some embodiments, the material of the ferroelectric material layer 4 includes an Hf-based ferroelectric material, or an Hf-based ferroelectric material doped with Zr, Al, La, Y, or Si. Zr (zirconium), Al (aluminum), La (lanthanum), Y (yttrium), and Si (silicon) are common doping elements. Doping with these elements can introduce lattice distortion, change the crystal structure and electronic structure of the material, and thus improve its ferroelectric properties, conductivity, dielectric constant, and other physical properties.

[0050] To facilitate understanding, this embodiment further illustrates a method for fabricating a three-dimensional integrated hafnium-based ferroelectric device according to the present invention, specifically including the following steps:

[0051] Step 1: On substrate 1, metal layers 212 and insulating layers 211 of the same number are alternately deposited using a thin film growth process to form the bottom electrode layer 2; specifically, as shown... Figure 2As shown, after cleaning substrate 1 using the RCA process (an industry-standard wet cleaning process that can remove organic and inorganic contaminants from the surface of silicon wafers), an 80 nm thick tungsten film is grown using physical vapor deposition (PVD), followed by a 20 nm thick alumina film grown using atomic layer deposition (ALD). This process is repeated four times, alternating between the tungsten film (i.e., metal layer 212) and the alumina film (i.e., insulating layer 211).

[0052] Step 2: A photoresist mask 51 is formed on the bottom electrode layer 2 using photolithography. Then, using this photoresist mask 51 as a protective layer, reactive ion etching is performed on the portion of the bottom electrode layer 2 not covered by the photoresist mask 51 to form multiple trench structures 22 or hole structures; specifically, as shown... Figures 3 to 5 As shown, a trench-type photoresist mask 51 is first formed by photolithography. Then, BCl3 (boron trichloride) and SF6 (sulfur hexafluoride) are used to etch the insulating layer 211 and the metal layer 212 respectively, and finally etched onto the Si substrate 1. Finally, the photoresist mask 51 is washed away. For specific steps, please refer to the following section on the etching process of trench structure 22 or hole structure.

[0053] Step 3: By moving the photoresist mask 52 and performing reactive ion etching, the bottom electrode layer 2 is etched to form a stepped structure 3; specifically, as shown... Figure 6 As shown, a photoresist mask 52 is formed by photolithography, and the top insulating layer 211 is etched using BCl3. Then, multiple stacked structures 21 are etched, and finally the bottom metal layer 212 is etched to form a stepped structure 3. In this process, the photoresist mask 52 needs to be moved according to the width of the step portion. For specific steps, please refer to the etching process of the stepped structure 3 below.

[0054] Step four: A ferroelectric material layer 4 is formed on the bottom electrode layer 2 using atomic layer deposition (ALD), allowing for precise control over the film thickness, excellent uniformity, and interface quality of the ferroelectric material layer 4. The ferroelectric material layer 4 is called a ferroelectric material because of its strong polarization. This polarization allows the material's polarization state to change reversibly under an applied electric field, thus enabling it to store electrical charge. This property makes ferroelectric materials very useful in the manufacture of memory devices, such as ferroelectric random access memory (FRAM).

[0055] Step 5: A top electrode layer 5 is formed on the ferroelectric material layer 4 using two thin film growth processes, including atomic layer deposition (ALD) and chemical vapor deposition (CVD). Since the top electrode layer 5 needs to fill the trench structure 22 or the porous structure, specific techniques or strategies may be required during deposition, such as tilted deposition or multiple filling operations, to ensure good step coverage. Furthermore, after the top electrode layer 5 is grown, post-processing such as annealing or oxidation may be necessary to improve the film's performance and stability.

[0056] For ease of understanding, this embodiment further illustrates the etching process of the trench structure 22 or the hole structure in the fabrication method of a three-dimensional integrated hafnium-based ferroelectric device of the present invention, including the following steps:

[0057] Step 1, Photoresist mask formation: A photoresist mask 51 is formed on the bottom electrode layer 2 using photolithography. This mask defines the area that needs to be etched to form the trench structure 22 or the aperture structure.

[0058] Step 2, Etching Gas Selection: To ensure etching selectivity, i.e., to ensure that only the target material is etched during the etching process without affecting other materials, primary etching gases with different etching selectivity for metal layer 212 (e.g., W, tungsten) and insulating layer 211 (e.g., Al2O3, aluminum oxide) were selected. BCl3 (or similar chlorine-based gases such as carbon tetrachloride, CCl4) and SF6 (or similar fluorine-based gases such as carbon tetrafluoride, CF4) were chosen as the primary etching gases for insulating layer 211 and metal layer 212, respectively.

[0059] Step 3, Alternating Etching: Since the bottom electrode layer 2 contains alternating metal layers 212 and insulating layers 211, it is necessary to use chlorine-based gas and fluorine-based gas alternately to etch the insulating layer 211 and the metal layer 212 respectively.

[0060] Step 4, Etching Parameter Control: To ensure that the etching rates of the metal layer 212 and the insulating layer 211 are consistent, a series of etching parameters need to be precisely controlled. These include gas flow rate, chamber pressure, etching power (SRF and BRF), etc. The advantage of consistent etching rates for the metal layer 212 and the insulating layer 211 is that when etching layers of different materials, consistent etching rates can avoid the formation of uneven surfaces or edges during the etching process and reduce lateral etching.

[0061] The specific etching parameters are as follows:

[0062] For etching the insulating layer 211 (such as Al2O3): when using BCl3, the gas flow rate is 30 sccm; when using Ar, the gas flow rate is 20 sccm; the etching power is set to 120W, and the chamber pressure is 3Pa.

[0063] For etching of metal layer 212 (e.g., W): when using SF6, the gas flow rate is 10 sccm; when using Ar, the gas flow rate is 30 sccm; when using O2, the gas flow rate is 3 sccm; the chamber pressure is 1 Pa.

[0064] The etching power was set to SRF 60W and BRF 20W. These parameters were set to reduce the etching rate of W, improve the anisotropy of etching, and reduce lateral etching, thereby ensuring the morphology and quality of the trench structure 22 or the hole structure.

[0065] Step 5, Etching Completion and Cleaning: After the trench structure 22 or the hole structure is etched, the photoresist mask is removed by chemical cleaning or other methods to obtain the required bottom electrode layer 2.

[0066] For ease of understanding, this embodiment further illustrates the etching process of the stepped structure 3 in the fabrication method of a three-dimensional integrated hafnium-based ferroelectric device of the present invention, including the following steps:

[0067] Step A, as Figure 6 As shown, the top insulating layer 211 is etched through the photoresist mask 52 to form the first step portion 31 of the stepped structure 3, starting from the top.

[0068] Step B: Shift the photoresist mask 52 by one step width and etch the underlying stacked structure 21 to form the N+1th step (32, 33, or 34) from the top, where N is a positive integer greater than or equal to 1; Step C: Repeat Step B until only one metal layer 212 remains under the stacked structure 21.

[0069] Step D, as follows Figure 7 As shown, the top metal layer 212 is etched through the photoresist mask 52 to form the last step portion 35 of the stepped structure 3, starting from the top.

[0070] Specifically, taking the second step 32 as an example, after the first step 31 is formed, the photoresist mask 52 is shifted by one step width through step B, and the underlying stacked structure 21 is etched to form the second step 32 starting from the top.

[0071] It should be understood that the three-dimensional integrated hafnium-based ferroelectric device described above can be applied not only in ferroelectric memories, but specifically in ferroelectric random access memories (FeRAM) or ferroelectric tunneling junction devices (FTJs). In FeRAM, the capacitor can serve as the basic structure of the memory cell, enabling non-volatile data storage. In FTJ devices, the capacitor can serve as part of the tunneling junction, utilizing the polarization characteristics of the ferroelectric material to modulate the tunneling current.

[0072] While embodiments of the present invention have been described in detail above, it will be apparent to those skilled in the art that various modifications and variations can be made to these embodiments. However, it should be understood that such modifications and variations fall within the scope and spirit of the invention as set forth in the claims. Furthermore, the invention described herein may have other embodiments and can be implemented or carried out in various ways.

Claims

1. A three-dimensional integrated hafnium-based ferroelectric device, characterized in that, include: Substrate; The bottom electrode layer includes a plurality of parallel stepped structures, all of which are disposed on the substrate; each stepped structure includes a first metal layer, a plurality of stacked structures and a first insulating layer; the first metal layer is disposed on the substrate, all of which are stacked sequentially on the first metal layer, and the first insulating layer is disposed on the top stacked structure. A ferroelectric material layer, wherein the ferroelectric material layer covers the bottom electrode layer; A top electrode layer, which covers the ferroelectric material layer.

2. The three-dimensional integrated hafnium-based ferroelectric device according to claim 1, characterized in that, The stacked structure includes a second metal layer and a second insulating layer; the second insulating layer is disposed on the first metal layer, and the second metal layer is disposed on the second insulating layer.

3. The three-dimensional integrated hafnium-based ferroelectric device according to claim 1, characterized in that, A groove structure or a hole structure is provided between every two adjacent stepped structures.

4. The three-dimensional integrated hafnium-based ferroelectric device according to any one of claims 2, characterized in that, The materials of the first metal layer, the second metal layer, and the top electrode layer all include W, or are doped with TiN, TaN, or Ru.

5. The three-dimensional integrated hafnium-based ferroelectric device according to claim 2, characterized in that, Both the first insulating layer and the second insulating layer are high-K dielectric materials; the high-K dielectric materials include HfO2 or Al2O3.

6. The three-dimensional integrated hafnium-based ferroelectric device according to claim 1, characterized in that, The ferroelectric material layer is made of Hf-based ferroelectric materials or Hf-based ferroelectric materials doped with Zr, Al, La, Y, or Si.

7. A method for fabricating a three-dimensional integrated hafnium-based ferroelectric device, characterized in that, The method for fabricating a three-dimensional integrated hafnium-based ferroelectric device according to any one of claims 1-6 includes: Step 1: On the substrate, a consistent number of metal layers and insulating layers are alternately deposited using a thin film growth process to form the bottom electrode layer; Step 2: A photoresist mask is formed on the bottom electrode layer by photolithography. Then, the photoresist mask is used as a protective layer to perform reactive ion etching on the bottom electrode layer not covered by the mask to form multiple trench structures or hole structures. Step 3: By moving the photoresist mask and performing reactive ion etching, the bottom electrode layer is etched to form a stepped structure; Step 4: Form a ferroelectric material layer on the bottom electrode layer by atomic deposition; Step 5: The top electrode layer is formed on the ferroelectric material layer using a thin film growth process.

8. The method for fabricating a three-dimensional integrated hafnium-based ferroelectric device according to claim 7, characterized in that, Step three specifically includes the following steps: Step A: Using a photoresist mask, etch the first insulating layer at the top to form the first step portion of the stepped structure, starting from the top. Step B: Shift the photoresist mask by one step width and etch the stacked structure below it to form the (N+1)th step from the top, where N is a positive integer greater than or equal to 1; Step C: Repeat step B until only the first metal layer remains beneath the stacked structure.

9. The method for fabricating a three-dimensional integrated hafnium-based ferroelectric device according to claim 7, characterized in that, In step two, the etching of the metal layer uses a fluorine-based gas, including SF6 or CF4, and the etching of the metal layer in step two uses a chlorine-based gas, including BCl3 or CCl4.

10. The method for fabricating a three-dimensional integrated hafnium-based ferroelectric device according to claim 7, characterized in that, In step two, the etching rate of the metal layer is consistent with the etching rate of the insulating layer.

11. The method for fabricating a three-dimensional integrated hafnium-based ferroelectric device according to claim 7, characterized in that, In step two: the etching gas flow rate of the insulating layer is 30 sccm for BCl3 and 20 sccm for Ar, the etching power is 120 W, and the chamber pressure is 3 Pa; the etching gas flow rate of the metal layer is 10 sccm for SF6, 30 sccm for Ar, and 3 sccm for O2, the chamber pressure is 1 Pa, the etching power is 60 W for SRF and 20 W for BRF.

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