Storage system, operation method of storage system, and computer readable storage medium

Abstract

The invention discloses a storage system, an operation method of the storage system and a computer readable storage medium, and relates to the technical field of storage. The storage system comprises a memory and a memory controller; the memory comprises a memory array, the memory array is coupled with n word lines, the n word lines are arranged according to a physical word line identification sequence, and n is greater than or equal to 2; the memory controller is configured to map the n physical word line identifiers into n virtual word line identifiers, the physical word line identifiers corresponding to the adjacent m virtual word line identifiers are mutually spaced, and m is greater than or equal to 2 and less than or equal to n; and generating verification data based on the data corresponding to the m adjacent virtual word line identifiers. The verification data is generated by the data corresponding to the plurality of adjacent virtual word line identifiers, that is, the verification data is generated by the data corresponding to the plurality of non-adjacent physical word line identifiers, so that the influence on the verification data caused by the mutual influence between the adjacent physical word lines is reduced, the success rate of data recovery is improved, and the data recovery efficiency is improved. And the reliability of data storage and reading is improved.

Description

Storage system, storage system operating method, and computer-readable storage medium Technical Field

[0001] The present application relates to the field of storage technology, and in particular to a storage system, an operating method of the storage system, and a computer-readable storage medium. Background Art

[0002] Memory cells in a three-dimensional (3D) memory are coupled to word lines, and data is written into the memory cells via a programming voltage applied by the word lines.

[0003] When writing data to a 3D memory, to avoid errors when subsequently reading the data, verification data can be generated based on the written data. This data is then verified against the verification data when reading from the memory. If the verification fails, the correct data can be recovered based on the verification data. Ensuring successful data recovery in the event of a verification failure is a current research hotspot.

[0004] Summary of the Invention

[0005] This application provides a storage system, a method for operating the storage system, and a computer-readable storage medium, which can improve programming efficiency. The technical solution is as follows:

[0006] In one aspect, a memory system is provided, characterized in that the memory system includes: one or more memories, and a memory controller coupled to the memories and configured to control the memories; the memories include a memory array, the memory array is coupled to n word lines, the n word lines are arranged in a physical word line identification order, where n ≥ 2;

[0007] The memory controller is configured to obtain a plurality of copies of data to be written into the storage array;

[0008] The memory controller is configured to map the n physical word line identifiers to n virtual word line identifiers, wherein the physical word line identifiers corresponding to the adjacent m virtual word line identifiers are spaced apart from each other, and 2≤m≤n;

[0009] The memory controller is configured to generate verification data based on the data corresponding to the m adjacent virtual word line identifiers, where the verification data is used to verify and recover the data corresponding to the m adjacent virtual word line identifiers.

[0010] In an optional embodiment, the memory controller is configured to obtain a pre-set mapping relationship table, wherein the mapping relationship table includes a mapping correspondence between physical word line identifiers and virtual word line identifiers; match the n physical word line identifiers with the mapping relationship table to obtain the n virtual word line identifiers corresponding to the n physical word line identifiers.

[0011] In an optional embodiment, the memory controller is configured to obtain the preset mapping relationship table from a static random access memory.

[0012] In an optional embodiment, a reference number of physical word line identifiers are distributed between the physical word line identifiers corresponding to the m adjacent virtual word line identifiers.

[0013] In an optional embodiment, the memory controller is configured to obtain a preset algorithm, which is used to map physical word line identifiers to virtual word line identifiers; substitute the n physical word line identifiers into the preset algorithm to obtain the n virtual word line identifiers corresponding to the n physical word line identifiers.

[0014] In an optional embodiment, the memory controller is configured to process the data corresponding to the m adjacent virtual word line identifiers through a first operator to obtain the verification data, wherein the verification data is used to verify and recover the failed read data through a second operator when there is a data read failure in the data corresponding to the m adjacent virtual word line identifiers, and the first operator and the second operator are operators with opposite operation logic.

[0015] In an optional embodiment, the memory controller is configured to send a first read instruction to the memory, wherein the first read instruction includes a first physical word line identifier corresponding to the first data to be read; and receive a data read result returned by the memory;

[0016] The memory controller is configured to, when the data reading result indicates that the reading of the first data corresponding to the first physical word line identifier fails, determine a first virtual word line identifier corresponding to the first physical word line identifier; and obtain target verification data corresponding to the first virtual word line identifier to recover the first data that failed to be read.

[0017] In an optional embodiment, the memory controller is configured to obtain the target verification data corresponding to the first virtual word line identifier, and obtain a second virtual word line identifier used in combination with the first virtual word line identifier to generate the target verification data; determine a second physical word line identifier corresponding to the second virtual word line identifier;

[0018] The memory controller is configured to send a second read instruction to the memory, wherein the second read instruction includes the second physical word line identifier, and the second read instruction is used to instruct the memory to read the data stored in the storage cell row coupled to the word line corresponding to the second physical word line identifier; receive the second data corresponding to the second physical word line identifier returned by the memory, and recover the first data that failed to be read based on the target verification data and the second data.

[0019] In an optional embodiment, the memory controller is configured to, when reading first data corresponding to a first physical word line identifier, determine a first virtual word line identifier corresponding to the first physical word line identifier, and obtain the target verification data corresponding to the first virtual word line identifier; obtain a second virtual word line identifier that is used in combination with the first virtual word line identifier to generate the target verification data, and determine a second physical word line identifier corresponding to the second virtual word line identifier;

[0020] Sending a read instruction to the memory, wherein the read instruction is used to instruct to read data stored in a memory cell row coupled to the word line corresponding to the first physical word line identifier and the second physical word line identifier;

[0021] The memory controller is configured to receive a data read result returned by the memory; and when the data read result indicates that the first data reading fails, call the target verification data and the second data corresponding to the second physical word line identifier to recover the first data that failed to read.

[0022] In another aspect, a method for operating a memory system is provided, wherein the memory system includes a memory having a memory array, the memory array being coupled to n word lines, the n word lines being arranged in a physical word line identification order, where n≥2;

[0023] The method comprises:

[0024] Acquiring multiple copies of data to be written into the storage array;

[0025] Verification data is written into the memory, where the verification data is generated based on data corresponding to physical word line identifiers spaced apart from each other, and the verification data is used to verify and recover the data.

[0026] In an optional embodiment, before writing the verification data into the memory, the method further includes:

[0027] Mapping the n physical word line identifiers to n virtual word line identifiers, wherein the physical word line identifiers corresponding to the adjacent m virtual word line identifiers are spaced apart from each other, and 2≤m≤n;

[0028] The verification data is generated based on the data corresponding to the m adjacent virtual word line identifiers, and the verification data is used to verify and recover the data corresponding to the m adjacent virtual word line identifiers.

[0029] In an optional embodiment, mapping the n physical word line identifiers to n virtual word line identifiers includes:

[0030] Acquire a preset mapping relationship table, wherein the mapping relationship table includes a mapping correspondence between physical word line identifiers and virtual word line identifiers;

[0031] The n physical word line identifiers are matched with the mapping relationship table to obtain the n virtual word line identifiers corresponding to the n physical word line identifiers.

[0032] In an optional embodiment, obtaining a preset mapping relationship table includes:

[0033] The preset mapping relationship table is obtained from the static random access memory.

[0034] In an optional embodiment, a reference number of physical word line identifiers are distributed between the physical word line identifiers corresponding to the m adjacent virtual word line identifiers.

[0035] In an optional embodiment, mapping the n physical word line identifiers to n virtual word line identifiers includes:

[0036] Obtaining a preset algorithm, wherein the preset algorithm is used to map a physical word line identifier to a virtual word line identifier;

[0037] The n physical word line identifiers are substituted into the preset algorithm to obtain the n virtual word line identifiers corresponding to the n physical word line identifiers.

[0038] In an optional embodiment, generating verification data based on data corresponding to the m adjacent virtual word line identifiers includes:

[0039] The data corresponding to the m adjacent virtual word line identifiers are processed by a first operator to obtain the verification data, wherein the verification data is used to verify and recover the failed read data by a second operator when there is a data read failure in the data corresponding to the m adjacent virtual word line identifiers, and the first operator and the second operator are operators with opposite operation logic.

[0040] In an optional embodiment, after writing the verification data into the memory, the method further includes:

[0041] Sending a first read instruction to the memory, where the first read instruction includes a first physical word line identifier corresponding to first data to be read;

[0042] receiving a data reading result returned by the memory;

[0043] When the data reading result indicates that the reading of the first data corresponding to the first physical word line identifier fails, determining a first virtual word line identifier corresponding to the first physical word line identifier;

[0044] Target verification data corresponding to the first virtual word line identifier is acquired to recover the first data that fails to be read.

[0045] In an optional embodiment, the acquiring target verification data corresponding to the first virtual word line identifier to recover the first data that failed to be read includes:

[0046] Acquire the target verification data corresponding to the first virtual word line identifier, and acquire a second virtual word line identifier used in conjunction with the first virtual word line identifier to generate the target verification data;

[0047] Determining a second physical word line identifier corresponding to the second virtual word line identifier;

[0048] Sending a second read instruction to the memory, where the second read instruction includes the second physical word line identifier, and the second read instruction is used to instruct the memory to read data stored in a memory cell row coupled to a word line corresponding to the second physical word line identifier;

[0049] Second data corresponding to the second physical word line identifier returned by the memory is received, and the first data that fails to be read is recovered based on the target verification data and the second data.

[0050] In an optional embodiment, after generating verification data based on the data corresponding to the m adjacent virtual word line identifiers, the method further includes:

[0051] Sending a first read instruction to the memory, where the first read instruction includes a first physical word line identifier corresponding to first data to be read;

[0052] Determine a first virtual word line identifier corresponding to the first physical word line identifier, and obtain the target verification data corresponding to the first virtual word line identifier;

[0053] Acquire a second virtual word line identifier that is used in combination with the first virtual word line identifier to generate the target verification data, and determine a second physical word line identifier corresponding to the second virtual word line identifier;

[0054] Sending a second read instruction to the memory, where the second read instruction includes the second physical word line identifier, and the second read instruction is used to instruct the memory to read data stored in a memory cell row coupled to a word line corresponding to the second physical word line identifier;

[0055] receiving a data reading result returned by the memory;

[0056] In a case where the data reading result indicates that the first data fails to be read, the target verification data and second data corresponding to the second physical word line identifier are called to recover the first data that fails to be read.

[0057] On the other hand, a computer-readable storage medium is provided, in which instructions are stored. When the instructions are executed on a memory controller, the operating method of the storage system as described in any of the above embodiments is implemented.

[0058] The technical solution provided by this application may have the following beneficial effects:

[0059] By setting a mapping relationship between physical word line identifiers and virtual word line identifiers, a virtual word line identifier corresponding to the physical word line identifier is generated, so that the physical word line identifiers corresponding to adjacent virtual word line identifiers are spaced, that is, non-adjacent, and verification data is generated using data corresponding to multiple adjacent virtual word line identifiers, that is, verification data is generated using data corresponding to multiple non-adjacent physical word line identifiers, which reduces the impact of mutual influence between adjacent physical word lines on the verification data, improves the success rate of data recovery, and improves the reliability of data storage and reading. BRIEF DESCRIPTION OF THE DRAWINGS

[0060] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0061] FIG1 is a schematic structural diagram of a storage system provided in an embodiment of the present application;

[0062] FIG2 is a schematic diagram of an integrated scenario of a storage system provided by an exemplary embodiment of the present application;

[0063] FIG3 is a schematic diagram of an integration scenario of a storage system provided by another exemplary embodiment of the present application;

[0064] FIG4 is a schematic diagram of a memory provided in an embodiment of the present application;

[0065] FIG5 is a cross-sectional schematic diagram of a memory array including memory strings provided in an embodiment of the present application;

[0066] FIG6 is a schematic diagram of a peripheral circuit provided in an embodiment of the present application;

[0067] FIG7 is a flowchart of an operating method of a storage system provided by an exemplary embodiment of the present application;

[0068] FIG8 is a schematic diagram of a mapping relationship table provided by an exemplary embodiment of the present application;

[0069] FIG9 is a schematic diagram of a verification data generation process provided by an exemplary embodiment of the present application;

[0070] FIG10 is a flowchart of an operating method of a storage system provided by another exemplary embodiment of the present application;

[0071] FIG11 is a schematic diagram of a data verification and recovery process provided by an exemplary embodiment of the present application;

[0072] FIG12 is a schematic diagram of the structure of a memory controller provided by an exemplary embodiment of the present application. DETAILED DESCRIPTION

[0073] The embodiments of the present application are described in further detail below with reference to the accompanying drawings.

[0074] The operating method of the storage system provided in the embodiment of the present application can be applied to a storage system that can include a 3D memory, such as a 3D NAND flash memory.

[0075] FIG1 is a schematic diagram of a memory system 10 provided in an embodiment of the present application. As shown in FIG1 , the memory system 10 includes: one or more memories 100 , and a memory controller 200 coupled to the memories 100 and configured to control the memories 100 .

[0076] The memory controller 200 can be configured to control operations performed by the memory 100, such as read, erase, and program operations. The memory controller 200 can also be configured to manage various functions related to data stored or to be stored in the memory 100, including but not limited to bad block management, garbage collection, conversion of logical addresses to physical addresses, wear leveling, etc. Optionally, the memory controller 200 can also be configured to process error correction codes (ECC) for data read from or written to the memory 100. The memory controller 200 can also perform any other suitable functions, such as formatting the memory 100.

[0077] The memory controller 200 may also communicate with an external device according to a specific communication protocol. For example, the memory controller 200 may communicate with the external device through at least one of various interface protocols. The interface protocol may be a Universal Serial Bus (USB) protocol, a Multi-Media Card (MMC) protocol, a Peripheral Component Interconnect (PCI) protocol, a PCI Express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a Serial ATA protocol, a Parallel ATA protocol, a Small Computer System Interface (SCSI) protocol, an Enhanced Small Drive Interface (ESDI) protocol, an Integrated Development Environment (IDE) protocol, a FireWire protocol, or the like.

[0078] In some embodiments, the memory controller 200 and one or more memories 100 can be integrated into various types of electronic devices. The electronic device can be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory therein. In this scenario, as shown in FIG1 , the storage system 10 further includes a host 300. The memory controller 200 is coupled to the host 300. The memory controller 200 can manage the data stored in the memory 100 and communicate with the host 300 to implement the functions of the aforementioned electronic device.

[0079] In other embodiments, the memory controller 200 and one or more memories 100 may be integrated into various types of memory devices.

[0080] As an example, as shown in FIG2 , the memory controller 200 and the single memory 100 may be integrated into a memory card 400. The memory card 400 may include a Personal Computer Memory Card International Association (PCMCIA, PC) card, a Compact Flash (CF) card, a Smart Media (SM) card, a Memory Stick, a Multi-Media Card (MMC), a RS-MMC, a micro-MMC, a Secure Digital (SD) card, a Universal Flash Storage (UFS), etc. As shown in FIG2 , the memory card 400 may further include a connector 410 for coupling the memory card 400 to a host.

[0081] As another example, as shown in FIG3 , the memory controller 200 and the plurality of memories 100 may be integrated into a solid-state drive (SSD) 500. The SSD 500 may further include a connector 510 for coupling the SSD 500 to a host. The storage capacity and / or operating speed of the SSD 500 may be greater than the storage capacity and / or operating speed of the memory card 400.

[0082] In addition, the memory 100 in FIG1 to FIG3 can be any memory involved in the embodiments of the present application. For example, it can be a 3D NAND (NAND gate) memory. The structure of the memory 100 is explained below.

[0083] FIG4 is a schematic diagram of a memory 100 provided in an embodiment of the present application. As shown in FIG4 , the memory 100 includes:

[0084] A memory array 110 , wherein the memory array 110 includes a plurality of memory cell rows;

[0085] a plurality of word lines 120 , wherein the plurality of word lines 120 are respectively coupled to the plurality of memory cell rows;

[0086] The peripheral circuit 130 is coupled to the plurality of word lines 120 and is configured to perform a verification operation or a programming operation on a selected memory cell row among the plurality of memory cell rows, the selected memory cell row being the memory cell row coupled to the selected word line, wherein, in order to perform the verification operation or the programming operation, the peripheral circuit 130 is configured to execute the memory operation method provided in the embodiment of the present application.

[0087] Memory array 110 may be a NAND flash memory array. As shown in FIG1 , a NAND flash memory array includes a plurality of memory strings 111 arranged in an array on a substrate, with each memory string 111 extending vertically above the substrate (not shown). In some embodiments, each memory string 111 includes a plurality of memory cells 112 coupled in series and stacked vertically.

[0088] As shown in FIG4 , each memory string 111 may further include a source select gate (SSG) 113 at the bottom and a drain select gate (DSG) 114 at the top. The source select gate is also known as a bottom select gate (BSG), or source select gate, and the drain select gate is also known as an upper select gate, top select gate (TSG), or drain select gate. The source select gate 113 and the drain select gate 114 may be configured to activate the selected memory string 111 during read and program operations.

[0089] In some embodiments, the drain select gate 114 of each memory string 111 is coupled to a corresponding bit line 115 , and data can be read from or written to the bit line 115 via an output bus (not shown).

[0090] In some embodiments, each memory string 111 is configured to apply a select voltage (e.g., higher than the threshold voltage of the transistor having the drain select gate 114) or a deselect voltage (e.g., 0V) to the corresponding drain select gate 114 via one or more DSG lines 116. And / or, in some embodiments, each memory string 111 is configured to be selected or deselected by applying a select voltage (e.g., higher than the threshold voltage of the transistor having the source select gate 113) or a deselect voltage (e.g., 0V) to the corresponding source select gate 113 via one or more SSG lines 117.

[0091] As shown in FIG4 , the memory strings 111 may be organized into a plurality of blocks 140. For any one of the plurality of blocks 140, the block 140 may have a source line (SL) 118, through which the sources of all the memory strings 111 in the block 140 are coupled. The source line is also referred to as a common source line or an array common source (ACS).

[0092] The source line 118 can be used for grounding, so that in certain subsequent operations, the source of each memory cell in the memory string in the block 140 can be grounded. Optionally, in some other operations, the source of each memory cell in the memory string in the block 140 can also be connected to a high voltage via the source line 118.

[0093] Each block 140 is a basic data unit for an erase operation, that is, all memory cells 112 on the same block 140 are erased simultaneously. To erase the memory cells 112 in a selected block, a source line coupled to the selected block may be biased with an erase voltage (Vers), such as a high positive voltage (20V or higher).

[0094] It will be appreciated that in alternative embodiments, the erase operation may be performed at the half-block level, at the quarter-block level, or at any suitable fractional level having any suitable number of blocks or blocks.

[0095] As shown in FIG. 4 , the same layer of memory cells 112 of adjacent memory strings 111 in the same block 140 may be coupled via word lines 120 , which are used to select which layer of memory cells 112 in the block 140 are affected by read and program operations.

[0096] In some embodiments, each word line 120 is coupled to a page to which memory cells 112 belong. A page is a basic unit of data for programming operations. The size of a page may be related to the number of memory strings 111 coupled by word lines 120 in a block 140. Each word line 120 may be coupled to the control gate (i.e., gate electrode) of each memory cell 112 in the corresponding page. It will be understood that

[0097] It should be noted that the memory cells in the same layer of a block 140 correspond to the same word line, but the memory cells in the same layer can be divided into one or more pages. In other words, one word line can be coupled to one or more pages. For example, for SLC, one word line is coupled to one page, and for MLC, one word line is coupled to two pages.

[0098] FIG5 is a schematic cross-sectional view of a memory array 110 including memory strings 111 according to an embodiment of the present application. As shown in FIG5 , the memory strings 111 may extend vertically above the substrate 101 and through the stacked layers 102. The substrate 101 may include silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material.

[0099] The stack 102 may include alternating gate conductive layers 103 and gate-to-gate dielectric layers 104. The number of pairs of gate conductive layers 103 and gate-to-gate dielectric layers 104 in the stack 102 may determine the number of memory cells 112 in the memory array 110.

[0100] The gate conductive layer 103 may include a conductive material, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate conductive layer 103 includes a metal layer, such as a tungsten layer. In other embodiments, each gate conductive layer 103 includes a doped polysilicon layer. In addition, each gate conductive layer 103 may include a control gate surrounding the memory cell 112 and may extend laterally at the top of the stacked layer 102 as a DSG line 116, extend laterally at the bottom of the stacked layer 102 as an SSG line 117, or extend laterally between the DSG line 116 and the SSG line 117 as a word line 120.

[0101] As shown in FIG5 , the memory string 111 includes a channel structure 105 extending vertically through the stacked layer 102. In some embodiments, the channel structure 105 includes a channel hole filled with (one or more) semiconductor materials (e.g., as a semiconductor channel) and (one or more) dielectric materials (e.g., as a memory film). The semiconductor channel includes silicon, such as polycrystalline silicon. The memory film is a composite dielectric layer including a tunneling layer, a memory layer (also called a "charge trapping / storage layer"), and a barrier layer.

[0102] In some embodiments, the channel structure 105 has a cylindrical shape (eg, a pillar shape), and the layers in the semiconductor channel and the memory film are arranged radially in this order from the center of the pillar toward the outer surface of the pillar.

[0103] It should be understood that, although not shown in FIG. 5 , the memory array 110 may further include other additional components, including but not limited to gate line gaps / source contacts, local contacts, interconnect layers, and the like.

[0104] 4 , peripheral circuitry 130 may be coupled to memory array 110 via bit lines 115, word lines 120, source lines 118, SSG lines 117, and DSG lines 116. Peripheral circuitry 130 may include any suitable analog, digital, and mixed-signal circuitry for facilitating operation of memory array 110 by applying and sensing voltage and / or current signals to and from memory cells 112 via bit lines 115, word lines 120, source lines 118, SSG lines 117, and DSG lines 116.

[0105] The peripheral circuits 130 may include various types of peripheral circuits formed using metal-oxide-semiconductor (MOS) technology. For example, FIG6 shows some exemplary peripheral circuits 130, which include a page buffer / sense amplifier 131, a column decoder / bit line (BL) driver 132, a row decoder / word line (WL) driver 133, a voltage generator 134, a control logic unit 135, a register 136, an interface 137, and a data bus 138. It should be understood that in some examples, additional peripheral circuits not shown in FIG6 may also be included.

[0106] The page buffer / sense amplifier 131 can be configured to read data from the memory array 110 and program (write) data to the memory array 110 based on control signals from the control logic unit 135. For example, the page buffer / sense amplifier 131 can store a page of program data (write data) to be programmed into one page 130 of the memory array 110. The page buffer / sense amplifier 131 can also perform verification operations to ensure that the data has been correctly programmed into the memory cell 112 coupled to the selected word line 120. The page buffer / sense amplifier 131 can also sense the low-power signal from the bit line 115, which represents the data bit stored in the memory cell 112, and amplify the small voltage swing to a recognizable logic level during a read operation.

[0107] The column decoder / bit line driver 132 may be configured to be controlled by the control logic unit 135 and select one or more memory strings 111 by applying a bit line voltage generated from the voltage generator 134 .

[0108] The row decoder / word line driver 133 can be configured to be controlled by the control logic unit 135 and select / deselect the block 140 of the memory array 110 and select / deselect the word line 120 of the block 140. The row decoder / word line driver 133 can also be configured to drive the word line 120 using the word line voltage (VWL) generated from the voltage generator 134. In some embodiments, the row decoder / word line driver 133 can also select / deselect and drive the SSG line 117 and the DSG line 116. As described in detail below, the row decoder / word line driver 133 is configured to perform an erase operation on the memory cell 112 coupled to the selected word line(s) 120.

[0109] The voltage generator 134 may be configured to be controlled by the control logic unit 135 and generate word line voltages (eg, read voltage, program voltage, pass voltage, local voltage, verification voltage, etc.), bit line voltages, and source line voltages to be supplied to the memory array 110 .

[0110] The control logic unit 135 may be coupled to each of the above-described peripheral circuits and configured to control operations of the respective circuits.

[0111] The register 136 may be coupled to the control logic unit 135 and may include a status register, a command register, and an address register for storing status information, a command operation code (OP code), and a command address for controlling the operation of each circuit in the peripheral circuit.

[0112] Interface (I / F) 137 may be coupled to control logic unit 135 and function as a control buffer to buffer control commands received from a host (not shown) and relay them to control logic unit 135, as well as buffer status information received from control logic unit 135 and relay it to the host. Interface 137 may also be coupled to column decoder / bit line driver 132 via data bus 138 and function as a data I / O interface and data buffer to buffer data and relay it to or from memory array 110.

[0113] The above description of the memory-related hardware embodiment has similar beneficial effects as the following method embodiment. For technical details not disclosed in the memory-related hardware embodiment, please refer to the description of the method embodiment of this application for understanding.

[0114] Taking the memory system shown in Figure 1 as an example, the memory system includes one or more memories, and a memory controller coupled to the memory and configured to control the memory; the memory includes a memory array, the memory array is coupled to n word lines, and the n word lines are arranged in a physical word line identification order, where n≥2.

[0115] In this embodiment, a memory controller is configured to obtain multiple copies of data to be written to a storage array, map n physical word line identifiers to n virtual word line identifiers, wherein the physical word line identifiers corresponding to m adjacent virtual word line identifiers are spaced apart from each other, and 2≤m≤n; and the memory controller is configured to generate verification data based on the data corresponding to the m adjacent virtual word line identifiers, and the verification data is used to verify and recover the data corresponding to the m adjacent virtual word line identifiers.

[0116] In some embodiments, the memory controller is configured to obtain a pre-set mapping relationship table, which includes a mapping correspondence between physical word line identifiers and virtual word line identifiers; match n physical word line identifiers with the mapping relationship table to obtain n virtual word line identifiers corresponding to the n physical word line identifiers.

[0117] In some embodiments, the memory controller is configured to obtain a preset mapping relationship table from a static random access memory.

[0118] In some embodiments, a reference number of physical word line identifiers are distributed between the physical word line identifiers corresponding to the adjacent m virtual word line identifiers.

[0119] In some embodiments, the memory controller is configured to obtain a preset algorithm for mapping physical word line identifiers to virtual word line identifiers; substitute n physical word line identifiers into the preset algorithm to obtain n virtual word line identifiers corresponding to the n physical word line identifiers.

[0120] In some embodiments, a memory controller is configured to process data corresponding to m adjacent virtual word line identifiers through a first operator to obtain verification data, wherein the verification data is used to verify and recover the failed read data through a second operator when there is a data read failure in the data corresponding to the m adjacent virtual word line identifiers, and the first operator and the second operator are operators with opposite operation logic.

[0121] In some embodiments, the memory controller is configured to send a first read instruction to the memory, wherein the first read instruction includes a first physical word line identifier corresponding to first data to be read; and receive a data read result returned by the memory;

[0122] The memory controller is configured to determine a first virtual word line identifier corresponding to the first physical word line identifier when a data read result indicates that the reading of the first data corresponding to the first physical word line identifier fails; and obtain target verification data corresponding to the first virtual word line identifier to recover the first data that failed to be read.

[0123] In some embodiments, the memory controller is configured to obtain target verification data corresponding to a first virtual word line identifier, and obtain a second virtual word line identifier used in combination with the first virtual word line identifier to generate the target verification data; determine a second physical word line identifier corresponding to the second virtual word line identifier;

[0124] A memory controller is configured to send a second read instruction to the memory, wherein the second read instruction includes a second physical word line identifier, and the second read instruction is used to instruct the memory to read data stored in a row of storage cells coupled to a word line corresponding to the second physical word line identifier; receive second data corresponding to the second physical word line identifier returned by the memory, and recover the first data that failed to be read based on target verification data and the second data.

[0125] In some embodiments, the memory controller is configured to, when reading first data corresponding to a first physical word line identifier, determine a first virtual word line identifier corresponding to the first physical word line identifier and obtain target verification data corresponding to the first virtual word line identifier; obtain a second virtual word line identifier that is used in conjunction with the first virtual word line identifier to generate the target verification data, and determine a second physical word line identifier corresponding to the second virtual word line identifier;

[0126] Sending a read instruction to the memory, where the read instruction is used to instruct to read data stored in a memory cell row coupled to word lines corresponding to the first physical word line identifier and the second physical word line identifier;

[0127] The memory controller is configured to receive a data read result returned by the memory; when the data read result indicates that the first data reading fails, call the target verification data and the second data corresponding to the second physical word line identifier to recover the first data that failed to be read.

[0128] FIG7 is a flow chart of an operating method of a storage system provided by an exemplary embodiment of the present application. Taking the method applied to a storage system as an example, as shown in FIG7 , the method includes:

[0129] Step 701: Acquire multiple copies of data to be written into a storage array.

[0130] The multiple copies of data are data to be written to a memory array of a memory. In some embodiments, the memory array includes n memory cell rows, each of which is coupled to n word lines, wherein the i-th memory cell row is coupled to the i-th word line, and i is a positive integer less than or equal to n. The multiple copies of data are data to be written to the n memory cell rows. The n word lines coupled to the n memory cell rows are arranged in a physical word line identifier order, that is, each of the n word lines corresponds to a physical word line identifier, which is used to uniquely indicate the word line in the word line arrangement order.

[0131] In some embodiments, a memory controller in a storage system receives multiple copies of data to be written to a storage array; or, the memory controller periodically and actively obtains multiple copies of data to be written to the storage array.

[0132] In some embodiments, after acquiring the multiple copies of data, the memory controller writes the multiple copies of data into the storage array based on the physical word line identifier.

[0133] Step 702 : writing verification data into the memory. The verification data is data generated based on data corresponding to physical word line identifiers spaced apart from each other. The verification data is used to verify and recover the data.

[0134] The memory controller first determines the arrangement of multiple copies of data written in the storage cell row, that is, the physical word line identifier corresponding to the storage cell row to which the data is written, such as: data a, data b, data c and data d, where data a is written to the storage cell row coupled to word line 1, data b is written to the storage cell row coupled to word line 2, data c is written to the storage cell row coupled to word line 3, and data d is written to the storage cell row coupled to word line 4.

[0135] The memory controller generates verification data based on the arrangement of multiple copies of data written in the storage cell row, and writes the verification data to the memory, wherein the verification data is generated based on the data corresponding to the spaced physical word line identifiers, that is, taking the above-mentioned data a, data b, data c and data d as an example, since word line 1 and word line 3 are separated by word line 2, and word line 2 and word line 4 are separated by word line 3, verification data is generated based on data a and data c, and verification data is generated based on data b and data d.

[0136] In some embodiments, when generating verification data based on data corresponding to spaced physical word line identifiers, n physical word line identifiers are first mapped to n virtual word line identifiers, where the physical word line identifiers corresponding to m adjacent virtual word line identifiers are spaced apart, 2≤m≤n. Verification data is generated based on the data corresponding to the m adjacent virtual word line identifiers, and the verification data is used to verify and recover the data corresponding to the m adjacent virtual word line identifiers. For illustration, m is 2 as an example, that is, verification data is generated based on data corresponding to two adjacent virtual word line identifiers, and there is a space between the physical word line identifiers corresponding to the two adjacent virtual word line identifiers.

[0137] Optionally, the m virtual word line identifiers include an adjacent first virtual word line identifier and a second virtual word line identifier, wherein the first virtual word line identifier is mapped to a first physical word line identifier, the second virtual word line identifier is mapped to a second physical word line identifier, and at least one physical word line identifier is distributed between the first physical word line identifier and the second physical word line identifier.

[0138] In some embodiments, there is one physical word line identifier distributed between the first physical word line identifier and the second physical word line identifier, that is, by spacing one physical word line, verification data is generated for data corresponding to the separated physical word lines; or, there are multiple physical word line identifiers distributed between the first physical word line identifier and the second physical word line identifier, such as a reference number of physical word line identifiers distributed between the physical word line identifiers corresponding to m adjacent virtual word line identifiers, that is, by spacing multiple physical word lines, verification data is generated for data corresponding to the separated physical word lines; or, the number of physical word line identifiers distributed between the first physical word line identifier and the second physical word line identifier is an indeterminate number determined based on an algorithm, that is, by spacing one or more physical word lines, verification data is generated for data corresponding to the separated physical word lines.

[0139] Illustratively, when mapping between the physical word line identifier and the virtual word line identifier, at least one of the following methods is included:

[0140] First, a preset mapping relationship table is obtained, which includes mapping relationships between physical word line identifiers and virtual word line identifiers; n physical word line identifiers are matched with the mapping relationship table to obtain n virtual word line identifiers corresponding to the n physical word line identifiers.

[0141] In some embodiments, the mapping relationship table is stored in a static random-access memory (SRAM), and the pre-set mapping relationship table is obtained from the SRAM; or, the mapping relationship table is stored in a 3D NAND memory, and the memory controller obtains the pre-set mapping relationship table from the 3D NAND memory.

[0142] In some embodiments, the mapping relationship table stores the correspondence between the physical word line identifier and the virtual word line identifier in the form of a key-value pair. Schematically, the physical word line identifier 1 is stored in the form of a key, and the virtual word line identifier 1 corresponding to the physical word line identifier 1 is stored in the form of a value; the physical word line identifier 2 is stored in the form of a key, and the virtual word line identifier 6 corresponding to the physical word line identifier 1 is stored in the form of a value. Figure 8 shows a schematic diagram of a mapping relationship table provided by an exemplary embodiment of the present application. As shown in Figure 8, the virtual word line identifiers 810 are identified as 1-5, which correspond to the physical word line identifiers 820 as 1 / 6 / 11 / 16 / 21, and the corresponding data 830 are Data1 / Data6 / Data11 / Data16 / Data21, respectively, and the generated verification data 840 is Parity1; the virtual word line identifiers 810 are identified as 6-10, which correspond to the physical word line identifiers 820 as 26 / 31 / 36 / 41 / 46, respectively, and the corresponding data 830 are Data26 / Data31 / Data36 / Data41 / Data46, respectively, and the generated verification data 840 is Parity2, and so on.

[0143] It is worth noting that the above mapping relationship table takes the example of 4 physical word line identifiers between the physical word line identifiers corresponding to two adjacent virtual word line identifiers for explanation, but the above number of intervals is only an illustrative example. In some embodiments, taking 5 word lines to generate a check data as an example, virtual word line identifiers 1-5 can also correspond to physical word line identifiers 1 / 3 / 5 / 7 / 9, virtual word line identifiers 6-10 correspond to physical word line identifiers 2 / 4 / 6 / 8 / 10, and so on. That is, the physical word line identifiers corresponding to two adjacent virtual word line identifiers are separated by 1 physical word line identifier. word line identifiers; alternatively, virtual word line identifiers 1-5 may also correspond to physical word line identifiers 1 / 4 / 7 / 10 / 13, virtual word line identifiers 6-10 may correspond to physical word line identifiers 2 / 5 / 8 / 11 / 14, and so on, that is, there are two physical word line identifiers between the physical word line identifiers corresponding to two adjacent virtual word line identifiers; alternatively, on the basis of ensuring a one-to-one correspondence between virtual word line identifiers and physical word line identifiers, there may be any number of physical word line identifiers between the physical word line identifiers corresponding to two adjacent virtual word line identifiers; the embodiment of the present application does not limit the number of intervals. In some embodiments, the number of intervals between the physical word line identifiers corresponding to different two groups of adjacent virtual word line identifiers may be different.

[0144] Second, a preset algorithm is obtained, which is used to map physical word line identifiers to virtual word line identifiers; n physical word line identifiers are substituted into the preset algorithm to obtain n virtual word line identifiers corresponding to the n physical word line identifiers.

[0145] In some embodiments, a pre-stored preset algorithm is retrieved from SRAM.

[0146] Optionally, the preset algorithm includes a parameter substitution bit for a physical word line identifier. After the physical word line identifier is substituted into the parameter substitution bit, the preset algorithm is used for processing to output a virtual word line identifier corresponding to the physical word line identifier.

[0147] For example, taking 50 physical word line identifiers, the physical word line identifiers are sequentially 1-50, and the preset algorithm is implemented as follows: when the physical word line identifier is an odd number, the virtual word line identifier is equal to the physical word line identifier; when the physical word line identifier is an even number, the virtual word line identifier is equal to 50 minus the value of the physical word line identifier.

[0148] It should be noted that the above method of mapping between physical word line identifiers and virtual word line identifiers is only an illustrative example and is not limited to this in the embodiments of the present application.

[0149] In some embodiments, when generating verification data, at least one of the following methods is included:

[0150] 1. Perform an XOR operation on the data corresponding to the m adjacent virtual word line identifiers to obtain verification data.

[0151] In some embodiments, the check data can be generated using a parity check. For example, for any piece of data, the total number of bits in the binary encoding of the data that are 1 is determined, and then check data is generated to record the parity of this total number. This facilitates subsequent verification of the read data based on the check data.

[0152] 2. The data corresponding to the m adjacent virtual word line identifiers are processed by the first operator to obtain verification data, wherein the verification data is used to verify and recover the failed read data by the second operator when there is a data read failure in the data corresponding to the m adjacent virtual word line identifiers. The first operator and the second operator are operators with opposite operation logic.

[0153] FIG9 is a schematic diagram of a verification data generation process provided by an exemplary embodiment of the present application. As shown in FIG9 , K data to be written into the memory are first obtained 900, wherein data 1 is written into physical word lines 1-5, data 2 is written into physical word lines 6-10, and so on, data K is written into physical word lines k-k+4. First, physical word line identifiers are mapped to virtual word line identifiers through mapping 910, wherein physical word line identifiers 1-5 are mapped to virtual word line identifiers 1 / 6 / 11 / 16 / 21, and physical word line identifiers 6-10 are mapped to virtual word line identifiers 2 / 7 / 12 / 17 / 22. After mapping the virtual word line identifiers to the physical word line identifiers, data of consecutive virtual word line identifiers is obtained 920, such as: data of virtual word line identifiers 1-5 is obtained and verification data 1 is obtained through integration 930, data of virtual word line identifiers 6-10 is obtained and verification data 2 is obtained through integration 930, and so on.

[0154] In some embodiments, a sequential write operation is performed on the memory through a logic analyzer to observe whether the NAND write address sent by the memory controller on the logic analyzer is a non-sequential WL number. If it is a non-sequential WL number, it proves that the operation method of the storage system provided by the embodiment of the present application is used.

[0155] To sum up, the method provided in the embodiment of the present application generates a virtual word line identifier corresponding to the physical word line identifier by setting a mapping relationship between the physical word line identifier and the virtual word line identifier, so that the physical word line identifiers corresponding to adjacent virtual word line identifiers are spaced, that is, not adjacent, and generates verification data using data corresponding to multiple adjacent virtual word line identifiers, that is, generates verification data using data corresponding to multiple non-adjacent physical word line identifiers, which reduces the impact of mutual influence between adjacent physical word lines on the verification data, improves the success rate of data recovery, and improves the reliability of data storage and reading.

[0156] The method provided in this embodiment pre-sets a mapping relationship table to intuitively correspond physical word line identifiers to virtual word line identifiers one by one, thereby mapping physical word line identifiers to virtual word line identifiers through the mapping relationship table, thereby improving the efficiency of determining virtual word line identifiers.

[0157] The method provided in this embodiment matches the physical word line identifier with the virtual word line identifier through a preset algorithm, thereby mapping the physical word line identifier to the virtual word line identifier through the preset algorithm, thereby improving the efficiency of determining the virtual word line identifier.

[0158] In an optional embodiment, after generating and storing the verification data, a process of reading the stored data is also included. FIG10 is a flowchart of a method for operating a storage system provided by another exemplary embodiment of the present application. Take the method as an example, in which the method is applied to the storage system shown in FIG1 and is executed after step 702 shown in FIG7. The method includes:

[0159] Step 1001: Send a first read instruction to a memory, where the first read instruction includes a first physical word line identifier corresponding to first data to be read.

[0160] Since data is still accessed through physical word line identifiers from the perspective of the memory, when reading data, a first read instruction with a first physical word line identifier is sent to the memory to read data from the storage cell row coupled to the word line corresponding to the first physical word line identifier.

[0161] In some embodiments, when the computer device where the storage system is located receives a data read operation, a first read instruction is sent to the memory through the memory controller to read the first data stored in the storage cell row coupled to the word line corresponding to the first physical word line identifier.

[0162] In some embodiments, the data reading process corresponding to the first read instruction includes at least one of the following situations:

[0163] The first method is to determine the virtual word line identifier and obtain verification data when data reading fails.

[0164] Step 1021: Receive the data reading result returned by the memory.

[0165] Wherein, if the first data can be read normally, the data read result includes the first data read from the memory cell row coupled to the word line corresponding to the first physical word line identifier. If the first data cannot be read normally, for example, if the memory cell row coupled to the word line corresponding to the first physical word line identifier is damaged, the first data cannot be correctly read, and the data read result includes an indicator indicating that the first data read failed.

[0166] That is, the data reading result includes: 1. the read data; 2. an indication mark of reading failure, or at least one of the above two contents.

[0167] In some embodiments, the first read instruction is used to read multiple first physical word lines, then the first data includes sub-data corresponding to multiple physical word lines respectively, and the data read result may also include an indication mark of failure to read some data. In some embodiments, the data read result includes the first physical word line mark corresponding to the data that failed to be read and other data that was successfully read.

[0168] Step 1031 : When the data reading result indicates that the reading of the first data corresponding to the first physical word line identifier fails, determine a first virtual word line identifier corresponding to the first physical word line identifier.

[0169] Optionally, when generating the verification data, the verification data is generated by mapping the physical word line identifier to the virtual word line identifier, and thus the first physical word line identifier is mapped using the same mapping method to determine the corresponding first virtual word line identifier. Illustratively, when generating the verification data, the physical word line identifier is mapped to the virtual word line identifier using a mapping relationship table, and in the event that the first data fails to be read, the first virtual word line identifier corresponding to the first physical word line identifier is determined using the mapping relationship table; when generating the verification data, the physical word line identifier is mapped to the virtual word line identifier using a preset algorithm, and in the event that the first data fails to be read, the first virtual word line identifier corresponding to the first physical word line identifier is determined using the preset algorithm.

[0170] Step 1041 : Obtain target verification data corresponding to the first virtual word line identifier to recover the first data that failed to be read.

[0171] In some embodiments, target verification data corresponding to the first virtual word line identifier is read from a memory, thereby verifying the first data.

[0172] In some embodiments, target verification data corresponding to a first virtual wordline identifier is obtained, and a second virtual wordline identifier that is used in conjunction with the first virtual wordline to generate the target verification data is obtained; optionally, during the verification data storage process, the verification data and the physical wordline identifiers and virtual wordline identifiers corresponding to the data used to generate the verification data are stored in correspondence, then the second virtual wordline identifier corresponding to the target verification data containing the first virtual wordline identifier is obtained, and the second physical wordline identifier corresponding to the second virtual wordline identifier is determined; optionally, when generating the verification data, the physical wordline identifier is mapped to the virtual wordline identifier through mapping, and the second virtual wordline identifier is mapped to the corresponding second physical wordline identifier through inverse mapping. In an exemplary embodiment, when generating the verification data, the physical wordline identifier is mapped to the virtual wordline identifier through a mapping relationship table, and the second virtual wordline identifier is still mapped to the second physical wordline identifier through the mapping relationship table; when generating the verification data, the physical wordline identifier is mapped to the virtual wordline identifier through a preset algorithm, and the second virtual wordline identifier is substituted into the second virtual wordline identifier based on the preset algorithm to determine the corresponding second physical wordline identifier.

[0173] A second read instruction is sent to the memory, wherein the second read instruction includes a second physical word line identifier, and the second read instruction is used to instruct the memory to read data stored in a storage cell row coupled to a word line corresponding to the second physical word line identifier; second data corresponding to the second physical word line identifier is received from the memory, and the first data that failed to be read is recovered based on the target verification data and the second data.

[0174] 11 is a schematic diagram of a data verification and recovery process provided by an exemplary embodiment of the present application. As shown in FIG11 , when memory controller 1101 sends a read instruction to memory 1102, instructing it to read data corresponding to physical word line identifiers 1-5, memory 1102 then reports back to memory controller 1101 that the data corresponding to physical word line identifier 5 has failed to be read. Memory controller 1101 then first determines virtual word line identifier 21 corresponding to physical word line identifier 5 through mapping 1110 and determines verification data n corresponding to virtual word line identifier 21 through verification data lookup 1120. It then obtains other virtual word line identifiers p that constitute verification data n through generation data lookup 1130 of verification data n and determines physical word line identifier q corresponding to virtual word line identifier p through mapping 1140. Memory controller 1101 then sends a read instruction to memory 1102, instructing it to read data corresponding to physical word line identifier q. After memory 1102 reports data q back to memory controller 1101, memory controller 1101 performs verification and recovery on the data corresponding to physical word line identifier 5.

[0175] The second method is to obtain target verification data and second data in advance, and perform verification using the target verification data and second data when reading of the first data fails.

[0176] Step 1022 : Determine a first virtual word line identifier corresponding to the first physical word line identifier, and obtain target verification data corresponding to the first virtual word line identifier.

[0177] In some embodiments, when generating verification data, the physical word line identifier is mapped to a virtual word line identifier through a mapping relationship table. In the event that the first data reading fails, the first virtual word line identifier corresponding to the first physical word line identifier is determined through the mapping relationship table. When generating verification data, the physical word line identifier is mapped to a virtual word line identifier through a preset algorithm. In the event that the first data reading fails, the first virtual word line identifier corresponding to the first physical word line identifier is determined through the preset algorithm.

[0178] Step 1032 : Acquire a second virtual word line identifier that is used in combination with the first virtual word line identifier to generate target verification data, and determine a second physical word line identifier corresponding to the second virtual word line identifier.

[0179] In some embodiments, target verification data corresponding to a first virtual word line identifier is obtained, and a second virtual word line identifier that is used in combination with the first virtual word line to generate the target verification data is obtained; optionally, in the process of storing the verification data, the verification data and the physical word line identifier and the virtual word line identifier corresponding to the data for generating the verification data are stored correspondingly, then the corresponding second virtual word line identifier in the target verification data containing the first virtual word line identifier is obtained, and the second physical word line identifier corresponding to the second virtual word line identifier is determined; optionally, when generating the verification data, the physical word line identifier is mapped to the virtual word line identifier by mapping, and then the second virtual word line identifier is mapped to the corresponding second physical word line identifier by inverse mapping.

[0180] Step 1042: Send a second read instruction to the memory, where the second read instruction includes a second physical word line identifier.

[0181] The second read instruction is used to instruct the memory to read data stored in a memory cell row coupled to a word line corresponding to a second physical word line identifier.

[0182] Step 1052: Receive the data reading result returned by the memory.

[0183] Optionally, the data reading result includes a result of reading the memory cell row coupled to the word line corresponding to the first physical word line identifier and a result of reading the memory cell row coupled to the word line corresponding to the second physical word line identifier.

[0184] In the embodiment of the present application, in the case where the first data fails to be read but the second data is read successfully, the first data is verified and recovered.

[0185] Step 1062 : When the data reading result indicates that the first data fails to be read, the target verification data and the second data corresponding to the second physical word line identifier are called to recover the first data that failed to be read.

[0186] To sum up, the method provided in the embodiment of the present application generates a virtual word line identifier corresponding to the physical word line identifier by setting a mapping relationship between the physical word line identifier and the virtual word line identifier, so that the physical word line identifiers corresponding to adjacent virtual word line identifiers are spaced, that is, not adjacent, and generates verification data using data corresponding to multiple adjacent virtual word line identifiers, that is, generates verification data using data corresponding to multiple non-adjacent physical word line identifiers, which reduces the impact of mutual influence between adjacent physical word lines on the verification data, improves the success rate of data recovery, and improves the reliability of data storage and reading.

[0187] The method provided in this embodiment verifies and recovers data by verifying data in the event of a data read failure. On the one hand, this avoids the problem that adjacent word lines affect each other and the verification data cannot verify and recover the data. On the other hand, it improves the security and accuracy of data storage.

[0188] Figure 12 is a schematic diagram of the structure of a memory controller provided by an exemplary embodiment of the present application. The storage system operation method provided by the embodiment of the present application is primarily implemented by the memory controller. As shown in Figure 12, the memory controller 1200 includes a memory interface 1210, a storage controller 1220, a configuration register 1230, and a bus interface 1240.

[0189] The memory interface 1210 is used to connect to the memory and convert the data exchange on the bus into data exchange that complies with the storage timing of the storage medium.

[0190] The memory controller 1220 is used to control the functions of the entire memory controller, control the memory interface to correctly complete the data exchange between the memory and the internal bus of the microcontroller unit (MCU), and is responsible for the management of interrupt signals.

[0191] The configuration register 1230 is used to configure the functions of the memory controller, such as the timing configuration of the memory interface.

[0192] The bus interface 1240 is used to connect to the internal bus of the MCU, and is generally used for 1. transmitting configuration information of the memory controller; 2. transmitting storage data that complies with the memory controller interface.

[0193] In some embodiments, the memory controller 1200 includes at least two interfaces, wherein the at least two interfaces include at least one interface for communicating with a memory and at least one front-end interface for communicating with a host.

[0194] An embodiment of the present application provides a control circuit, which includes a programmable logic circuit and / or program instructions. The control circuit can be used to implement the operating method of the storage system provided by the aforementioned embodiment of the present application.

[0195] An embodiment of the present application provides a computer-readable storage medium, which stores instructions. When the instructions are executed on a memory controller, the operation method of the storage system provided in the aforementioned embodiment of the present application is implemented.

[0196] In this application, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance. The term "at least one" refers to one or more, and the term "plurality" refers to two or more, unless otherwise clearly defined.

[0197] In this application, the term "and / or" simply describes an association between related objects, indicating that three possible relationships exist. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / " in this document generally indicates that the related objects are in an "or" relationship.

[0198] The above description is merely an exemplary embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A storage system, characterized in that: The memory system comprises: one or more memories, and a memory controller coupled to the memory and configured to control the memory; the memory comprises a memory array, the memory array is coupled to n word lines, the n word lines are arranged in a physical word line identification order, n≥2; The memory controller is configured to obtain a plurality of copies of data to be written into the storage array; The memory controller is configured to map the n physical word line identifiers to n virtual word line identifiers, wherein the physical word line identifiers corresponding to the adjacent m virtual word line identifiers are spaced apart from each other, 2≤m≤n; The memory controller is configured to generate verification data based on the data corresponding to the m adjacent virtual word line identifiers, and the verification data is used to verify and recover the data corresponding to the m adjacent virtual word line identifiers.

2. The system according to claim 1, characterized in that The memory controller is configured to obtain a preset mapping relationship table, wherein the mapping relationship table includes a mapping correspondence between physical word line identifiers and virtual word line identifiers; match the n physical word line identifiers with the mapping relationship table to obtain the n virtual word line identifiers corresponding to the n physical word line identifiers.

3. The system according to claim 2, characterized in that The memory controller is configured to obtain the preset mapping relationship table from a static random access memory.

4. The system according to claim 1, characterized in that A reference number of physical word line identifiers are distributed between the physical word line identifiers corresponding to the m adjacent virtual word line identifiers.

5. The system according to claim 1, characterized in that The memory controller is configured to obtain a preset algorithm, wherein the preset algorithm is used to map a physical word line identifier to a virtual word line identifier; Substituting the n physical word line identifiers into the preset algorithm, the n virtual word line identifiers corresponding to the n physical word line identifiers are obtained.

6. The system according to claim 1, characterized in that The memory controller is configured to process the data corresponding to the m adjacent virtual word line identifiers through a first operator to obtain the verification data, wherein the verification data is used to verify and recover the failed read data through a second operator when there is a data read failure in the data corresponding to the m adjacent virtual word line identifiers, and the first operator and the second operator are operators with opposite operation logic.

7. The system according to any one of claims 1 to 6, characterized in that: The memory controller is configured to send a first read instruction to the memory, wherein the first read instruction includes a first physical word line identifier corresponding to first data to be read; and receive a data read result returned by the memory; The memory controller is configured to determine a first virtual word line identifier corresponding to the first physical word line identifier when the data reading result indicates that the reading of the first data corresponding to the first physical word line identifier fails; Target verification data corresponding to the first virtual word line identifier is obtained to recover the first data that fails to be read.

8. The system according to claim 7, characterized in that The memory controller is configured to obtain the target verification data corresponding to the first virtual word line identifier, and obtain a second virtual word line identifier that is matched with the first virtual word line identifier to generate the target verification data; Determine a second physical word line identifier corresponding to the second virtual word line identifier; The memory controller is configured to send a second read instruction to the memory, wherein the second read instruction includes the second physical word line identifier, and the second read instruction is used to instruct the memory to read data stored in a storage cell row coupled to a word line corresponding to the second physical word line identifier; receive second data corresponding to the second physical word line identifier returned by the memory, and recover the first data that failed to be read based on the target verification data and the second data.

9. The system according to any one of claims 1 to 6, characterized in that: The memory controller is configured to determine a first virtual word line identifier corresponding to a first physical word line identifier when reading first data corresponding to the first physical word line identifier, and obtain the target verification data corresponding to the first virtual word line identifier; Acquire a second virtual word line identifier that is matched with the first virtual word line identifier to generate the target verification data, and determine a second physical word line identifier corresponding to the second virtual word line identifier; Sending a read instruction to the memory, wherein the read instruction is used to instruct to read data stored in a storage cell row coupled to a word line corresponding to the first physical word line identifier and the second physical word line identifier; The memory controller is configured to receive a data read result returned by the memory; when the data read result indicates that the first data reading fails, call the target verification data and the second data corresponding to the second physical word line identifier to recover the first data that failed to read.

10. A method for operating a storage system, characterized in that: The storage system includes a memory having a storage array, the storage array is coupled to n word lines, the n word lines are arranged in a physical word line identification order, n≥2; The method comprises: Acquire multiple copies of data to be written into the storage array; Verification data is written into the memory, where the verification data is generated based on data corresponding to physical word line identifiers spaced apart from each other, and the verification data is used to verify and recover the data.

11. The method according to claim 10, characterized in that Before writing the verification data into the memory, the method further comprises: Mapping the n physical word line identifiers to n virtual word line identifiers, wherein the physical word line identifiers corresponding to the adjacent m virtual word line identifiers are spaced apart from each other, and 2≤m≤n; The verification data is generated based on the data corresponding to the m adjacent virtual word line identifiers, and the verification data is used to verify and restore the data corresponding to the m adjacent virtual word line identifiers.

12. The method according to claim 11, characterized in that The mapping of the n physical word line identifiers to n virtual word line identifiers includes: Acquire a preset mapping relationship table, wherein the mapping relationship table includes a mapping correspondence relationship between physical word line identifiers and virtual word line identifiers; The n physical word line identifiers are matched with the mapping relationship table to obtain the n virtual word line identifiers corresponding to the n physical word line identifiers.

13. The method according to claim 12, characterized in that The obtaining of a preset mapping relationship table includes: The preset mapping relationship table is obtained from the static random access memory.

14. The method according to claim 11, characterized in that A reference number of physical word line identifiers are distributed between the physical word line identifiers corresponding to the m adjacent virtual word line identifiers.

15. The method according to claim 11, characterized in that The mapping of the n physical word line identifiers to n virtual word line identifiers includes: Obtaining a preset algorithm, wherein the preset algorithm is used to map a physical word line identifier to a virtual word line identifier; Substituting the n physical word line identifiers into the preset algorithm, the n virtual word line identifiers corresponding to the n physical word line identifiers are obtained.

16. The method according to claim 11, characterized in that The generating verification data based on the data corresponding to the m adjacent virtual word line identifiers includes: The data corresponding to the m adjacent virtual word line identifiers are processed by a first operator to obtain the verification data, wherein the verification data is used to verify and recover the failed read data by a second operator when there is a data read failure in the data corresponding to the m adjacent virtual word line identifiers, and the first operator and the second operator are operators with opposite operation logic.

17. The method according to any one of claims 11 to 16, characterized in that: After writing the verification data into the memory, the method further comprises: Sending a first read instruction to the memory, wherein the first read instruction includes a first physical word line identifier corresponding to first data to be read; Receiving a data reading result returned by the memory; When the data reading result indicates that the reading of the first data corresponding to the first physical word line identifier fails, determining a first virtual word line identifier corresponding to the first physical word line identifier; Target verification data corresponding to the first virtual word line identifier is obtained to recover the first data that fails to be read.

18. The method according to claim 17, characterized in that The acquiring target verification data corresponding to the first virtual word line identifier to recover the first data that failed to be read includes: Acquire the target verification data corresponding to the first virtual word line identifier, and acquire a second virtual word line identifier that is matched with the first virtual word line identifier to generate the target verification data; Determine a second physical word line identifier corresponding to the second virtual word line identifier; Sending a second read instruction to the memory, wherein the second read instruction includes the second physical word line identifier, and the second read instruction is used to instruct the memory to read data stored in a storage cell row coupled to a word line corresponding to the second physical word line identifier; Second data corresponding to the second physical word line identifier returned by the memory is received, and the first data that fails to be read is recovered based on the target verification data and the second data.

19. The method according to any one of claims 11 to 16, characterized in that: After the verification data is generated based on the data corresponding to the m adjacent virtual word line identifiers, the method further includes: Sending a first read instruction to the memory, wherein the first read instruction includes a first physical word line identifier corresponding to first data to be read; Determine a first virtual word line identifier corresponding to the first physical word line identifier, and obtain the target verification data corresponding to the first virtual word line identifier; Acquire a second virtual word line identifier that is matched with the first virtual word line identifier to generate the target verification data, and determine a second physical word line identifier corresponding to the second virtual word line identifier; Sending a second read instruction to the memory, wherein the second read instruction includes the second physical word line identifier, and the second read instruction is used to instruct the memory to read data stored in a storage cell row coupled to a word line corresponding to the second physical word line identifier; Receiving a data reading result returned by the memory; When the data reading result indicates that the first data fails to be read, the target verification data and second data corresponding to the second physical word line identifier are called to recover the first data that failed to be read.

20. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores instructions, and when the instructions are executed on the memory controller, the operating method of the storage system according to any one of claims 1 to 9 is implemented.

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