Display substrate and display device

Abstract

The invention provides a display substrate and a display device. The display substrate comprises a substrate body, a first transistor, a second transistor, a third transistor, a first shading layer and a second shading layer. According to the embodiment of the invention, the first transistor for detecting the ambient light intensity, the second transistor for detecting the backlight intensity and the third transistor for detecting the temperature are arranged, the first light shielding layer is used for shielding the lower parts of the first transistor and the third transistor, and the second light shielding layer is used for shielding the upper parts of the second transistor and the third transistor; therefore, the working environment parameters of the display panel can be effectively and accurately collected, and the compensation effect on the display effect is improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display substrate and a display device. Background Art

[0002] In order to improve the color display accuracy of mobile phones and other display devices in different environments, it is necessary to compensate the display effect of the display panel in a targeted manner. In the related art, the electrical characteristics of the semiconductor layer of the transistor are sensitive to brightness, and the brightness of the display panel is detected to compensate the display effect of the display panel. However, for the low-temperature polycrystalline silicon (LTPS) display panel with relatively excellent performance, due to the structural limitations of the top-gate LTPS transistor, its semiconductor layer is blocked, affecting the accuracy of brightness acquisition, and further affecting the compensation effect of the display device. Summary of the invention

[0003] The embodiments of the present invention provide a display substrate and a display device to solve the problem that the existing method has low accuracy in collecting brightness of a display panel and affects the compensation effect.

[0004] To solve the above problems, the present invention is achieved as follows:

[0005] In a first aspect, an embodiment of the present invention provides a display substrate, comprising:

[0006] A substrate, comprising a display area and a peripheral area surrounding the display area;

[0007] A first transistor, disposed in the peripheral area, for detecting the ambient light intensity of the display substrate;

[0008] A second transistor, disposed in the peripheral area, for detecting the backlight intensity of the display substrate;

[0009] A third transistor, disposed in the peripheral area, for detecting the temperature of the display substrate;

[0010] The display substrate further comprises a semiconductor layer, a gate metal layer formed on a side of the semiconductor layer away from the base substrate, and a source-drain metal layer formed on a side of the gate metal layer away from the base substrate;

[0011] A first light shielding layer is disposed between the semiconductor layer and the base substrate, wherein an orthographic projection of the first light shielding layer on the base substrate covers a first orthographic projection of the semiconductor layer of the first transistor on the base substrate and a third orthographic projection of the semiconductor layer of the third transistor on the base substrate;

[0012] A second light shielding layer is provided on a side of the semiconductor layer away from the base substrate, wherein the orthographic projection of the second light shielding layer on the base substrate covers the second orthographic projection and the third orthographic projection of the semiconductor layer of the second transistor on the base substrate;

[0013] The orthographic projection of the metal layer of the display substrate located on the side of the semiconductor layer away from the base substrate on the base substrate does not overlap with the first orthographic projection.

[0014] In some of the embodiments, the display substrate includes a light shielding layer formed between the semiconductor layer and the base substrate, and the first light shielding layer is the light shielding layer.

[0015] In some embodiments, the orthographic projection of the gate metal layer on the substrate does not overlap with the first orthographic projection;

[0016] The gate metal layer includes a gate signal line pattern for transmitting a data signal, and the gate signal line pattern is electrically connected to the light shielding layer so that the light shielding layer is multiplexed as the first transistor.

[0017] In some embodiments, each of the first transistors shares a same planar gate.

[0018] In some of the embodiments, the light blocking layer includes a plurality of light blocking layer patterns used as gates of the first transistors, the plurality of light blocking layer patterns are spaced apart from each other, and each of the light blocking layer patterns is used as a gate of one or more of the first transistors.

[0019] In some of the embodiments, the orthographic projection of the gate metal layer on the base substrate and the orthographic projection of the source-drain metal layer on the base substrate individually or jointly cover the space between the light shielding layer patterns.

[0020] In some of the embodiments, the gate metal layer and the source-drain metal layer are reused as the second light-shielding layer, and the orthographic projection of the gate metal layer on the substrate and the orthographic projection of the source-drain metal layer on the substrate individually cover or jointly cover the second orthographic projection and / or the third orthographic projection.

[0021] In some embodiments, the gate metal layer includes a gate signal line pattern for transmitting data signals, and the orthographic projection of the gate signal line pattern on the substrate and the orthographic projection of the source / drain metal layer on the substrate individually or jointly cover the second orthographic projection and / or the third orthographic projection.

[0022] In some embodiments, the gate metal layer includes a dummy gate pattern, and the orthographic projection of the dummy gate pattern on the substrate and the orthographic projection of the source / drain metal layer on the substrate individually or jointly cover the second orthographic projection and / or the third orthographic projection.

[0023] In some embodiments, the source-drain metal layer includes a dummy source-drain metal pattern and a source-drain signal line pattern, and the orthographic projection of the dummy source-drain metal pattern on the substrate covers the second orthographic projection and / or the third orthographic projection.

[0024] In some of the embodiments, the gate metal layer includes a transfer gate pattern, the orthographic projection of the transfer gate pattern on the substrate overlaps with the orthographic projection of the source-drain signal line pattern on the substrate, and the orthographic projection of the transfer gate pattern on the substrate overlaps with the second orthographic projection, the transfer gate pattern is electrically connected to the source-drain signal line pattern, and the transfer gate pattern is electrically connected to the semiconductor layer of the second transistor; and / or

[0025] The orthographic projection of the transfer gate pattern on the base substrate overlaps with the third orthographic projection, the transfer gate pattern is electrically connected to the source-drain signal line pattern, and the transfer gate pattern is electrically connected to the semiconductor layer of the third transistor.

[0026] In some embodiments, the display substrate also includes a touch metal layer, which is formed on a side of the source and drain metal layer away from the base substrate, and the touch metal layer is reused as the second light-shielding layer, and the orthographic projection of the touch metal layer on the base substrate covers the second orthographic projection and / or the third orthographic projection.

[0027] In some embodiments, a avoidance opening is provided on the light shielding layer, and the orthographic projection of the avoidance opening on the base substrate overlaps with the second orthographic projection.

[0028] In some embodiments, the light blocking layer includes a switching light blocking pattern, the switching light blocking pattern is electrically connected to the semiconductor layer of the second transistor, the switching light blocking pattern is electrically connected to a switching gate pattern, and the switching gate pattern is electrically connected to the source and drain metal layer.

[0029] In a second aspect, an embodiment of the present invention provides a display device, comprising the display substrate described in any one of the first aspects.

[0030] The embodiment of the present invention sets a first transistor for detecting ambient light intensity, a second transistor for detecting backlight intensity, and a third transistor for detecting temperature, and uses a first shading layer to block the bottom of the first transistor and the third transistor, and uses a second shading layer to block the top of the second transistor and the third transistor, so that the working environment parameters of the display panel can be effectively and accurately collected to improve the compensation effect on the display effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative labor.

[0032] Figure 1 is a schematic structural diagram of a display substrate in one embodiment of the present invention;

[0033] Figure 2 is a structural schematic diagram of a display substrate in another embodiment of the present invention;

[0034] Figure 3 yes Figure 2 The AA' cross-sectional view of the display substrate is shown;

[0035] Figure 4 is a structural schematic diagram of a display substrate in another embodiment of the present invention;

[0036] Figure 5 yes Figure 4 The BB' cross-sectional view of the display substrate is shown;

[0037] Figure 6 is a structural schematic diagram of a display substrate in another embodiment of the present invention;

[0038] Figure 7 yes Figure 6 The CC' cross-sectional view of the display substrate is shown;

[0039] Figure 8 is a structural schematic diagram of a display substrate in another embodiment of the present invention;

[0040] Fig. 9 yes Figure 8 The DD' cross-sectional view of the display substrate is shown;

[0041] Fig.10 is a structural schematic diagram of a display substrate in another embodiment of the present invention;

[0042] Fig.11 yes Fig.10The EE' cross-sectional view of the display substrate is shown;

[0043] Fig.12 is a structural schematic diagram of a display substrate in another embodiment of the present invention;

[0044] Fig.13 yes Fig.12 The sectional view of the substrate taken along the line F-F' is shown;

[0045] Fig.14 is a structural schematic diagram of a display substrate in another embodiment of the present invention;

[0046] Fig.15 yes Fig.14 The cross-sectional view of the display substrate taken along the line G-G' is shown;

[0047] Fig.16 is a structural schematic diagram of a display substrate in another embodiment of the present invention;

[0048] Fig.17 yes Fig.16 The H-H' cross-sectional view of the display substrate is shown;

[0049] Fig.18 is a structural schematic diagram of a display substrate in another embodiment of the present invention;

[0050] Fig.19 yes Fig.18 The display substrate is shown in a cross-sectional view taken along line II';

[0051] Fig. 20 is a structural schematic diagram of a display substrate in another embodiment of the present invention;

[0052] Fig.21 yes Fig. 20 The J-J' cross-sectional view of the display substrate is shown;

[0053] Fig. 22 is a structural schematic diagram of a display substrate in another embodiment of the present invention;

[0054] Fig.23 yes Fig. 22 The K-K' cross-sectional view of the display substrate is shown;

[0055] Fig.24 is a structural schematic diagram of a display substrate in another embodiment of the present invention;

[0056] Fig.25 yes Fig.24 The sectional view of the substrate shown is taken along the line LL'.

[0057] Fig.26 is a structural schematic diagram of a display substrate in another embodiment of the present invention;

[0058] Fig. 27 yes Fig.26 The sectional view of the substrate taken along the line M-M' is shown;

[0059] Fig.28 is a structural schematic diagram of a display substrate in another embodiment of the present invention;

[0060] Fig.29 yes Fig.28 The N-N' cross-sectional view of the display substrate is shown;

[0061] Fig.30 is a structural schematic diagram of a display substrate in another embodiment of the present invention;

[0062] Fig.31 yes Fig.30 The O-O' cross-sectional view of the display substrate is shown;

[0063] Fig.32 is a structural schematic diagram of a display substrate in another embodiment of the present invention;

[0064] Fig.33 yes Fig.32 The PP' cross-sectional view of the display substrate is shown;

[0065] Fig.34 is a structural schematic diagram of a display substrate in another embodiment of the present invention;

[0066] Fig.35 yes Fig.34 A further perspective view of an embodiment of the display substrate is shown;

[0067] Fig.36 yes Fig.34 A further perspective view of yet another embodiment of the display substrate is shown;

[0068] Fig.37 is a structural schematic diagram of a display substrate in another embodiment of the present invention;

[0069] Fig.38 yes Fig.37 A further perspective view of an embodiment of the display substrate is shown;

[0070] Fig.39 yes Fig.37 A further perspective view of yet another embodiment of the display substrate is shown;

[0071] Fig.40 It is the numerical curve of ambient light value at different temperature and illumination;

[0072] Fig.41 The backlight contrast value and G / W relationship curve in one embodiment of the present invention;

[0073] Fig.42 1 is a curve of brightness detection values ​​under different ambient brightnesses in one embodiment of the present invention. DETAILED DESCRIPTION

[0074] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0075] The terms "first", "second" etc. in the embodiments of the present invention are used to distinguish similar objects, and need not be used to describe a specific order or sequential order. In addition, the terms "include" and "have" and any variation thereof are intended to cover non-exclusive inclusions, for example, the process, method, system, product or equipment comprising a series of steps or units need not be limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or equipment. In addition, "and / or" is used in the present application to represent at least one of the connected objects, such as A and / or B and / or C, which represents 7 situations including single A, single B, single C, and A and B all exist, B and C all exist, A and C all exist, and A, B and C all exist.

[0076] An embodiment of the present invention provides a display substrate.

[0077] In some of the embodiments, the display substrate is taken as a 9-mask (9-time mask exposure and etching process) or 11-mask array substrate for exemplary description.

[0078] In an exemplary embodiment, the 9mask array substrate includes a substrate substrate 101 and a light shielding layer (Light Shield, abbreviated as LS, generally made of metal molybdenum Mo) 102, a buffer layer (Buffer, generally made of SiO2) 103, a semiconductor layer (Poly, low temperature polysilicon P-Si is used in LTPS panels) 104, a gate insulating layer (generally made of SiO2 / SiN x )105, gate metal layer (usually Mo) 106, interlayer dielectric layer (ILD, generally SiO2 / SiN x )107. Source & Drain metal layer (SD, Source & Drain, generally made of titanium aluminum titanium Ti / Al / Ti)108. Flat layer (PLN, generally made of acryl-based Acryl material)109. First insulating layer (PVX, generally made of SiN x)110 a first electrode layer (generally a surface electrode used as a common electrode, usually made of indium tin oxide ITO), an electrode insulating layer (generally made of SiNx) and a second electrode layer (generally a driving electrode), and a first liquid crystal alignment layer (PI) 111.

[0079] The array substrate can be assembled with the color filter substrate to form a liquid crystal cell, in which a liquid crystal layer 112 is disposed. The color filter substrate includes a second liquid crystal alignment layer (PI) 113, a G / W color resist 114, a black matrix (black resin material) 115 and a glass cover 116.

[0080] In some other embodiments, the display substrate can also be an 11mask array substrate. The main difference from the above-mentioned 9mask array substrate is that touch wiring is further added. Accordingly, it is necessary to add a touch wiring layer (generally using Ti / Al / Ti) and a touch wiring insulation layer (generally using SiNx) in sequence between the two steps of making PLN and the first electrode layer 110.

[0081] In this embodiment, the base substrate 101 includes a display area and a peripheral area surrounding the display area, wherein the display area includes sub-pixels. It should be noted that in this embodiment, any unmentioned parts about the structure and process of the display substrate itself can refer to the relevant technology and will not be repeated in this application.

[0082] like Figure 1 As shown, in this embodiment, a first transistor 11 for detecting the ambient light intensity of the display substrate, a second transistor 12 for detecting the backlight intensity of the display substrate, and a third transistor 13 for detecting the temperature of the display substrate are arranged in the peripheral area.

[0083] The display substrate also includes a first shading layer 21 and a second shading layer 22. The first shading layer 21 is arranged between the semiconductor layer 104 and the base substrate 101. The orthographic projection of the first shading layer 21 on the base substrate 101 covers the first orthographic projection of the semiconductor layer 104 of the first transistor 11 on the base substrate 101 and the third orthographic projection of the semiconductor layer 104 of the third transistor 13 on the base substrate 101.

[0084] The second light shielding layer 22 is disposed on a side of the semiconductor layer 104 away from the base substrate 101 , and the orthographic projection of the second light shielding layer 22 on the base substrate 101 covers the second orthographic projection and the third orthographic projection of the semiconductor layer 104 of the second transistor 12 on the base substrate 101 .

[0085] The orthographic projection of the metal layer of the display substrate located on the side of the semiconductor layer 104 away from the base substrate 101 on the base substrate 101 does not overlap with the first orthographic projection. It should be understood that the display substrate in this embodiment is an LTPS display substrate, and generally speaking, its gate is located above the semiconductor layer 104 of the transistor. In the technical solution of this embodiment, in order to avoid the structure above the first transistor 11 blocking the semiconductor layer 104 of the first transistor 11, the orthographic projection of the metal layer located above the semiconductor layer 104 on the base substrate 101 does not overlap with the first orthographic projection, so that the semiconductor layer 104 can fully receive external light.

[0086] It should be understood that the liquid crystal display device is backlit by a backlight source, and the backlight may have light leakage. In this embodiment, the first light-shielding layer 21 is used to block the bottom of the first transistor 11, thereby preventing the backlight from irradiating the semiconductor layer 104 of the first transistor 11, ensuring that the electrical performance of the first transistor 11 is only affected by light from external ambient light.

[0087] The electrical properties of the semiconductor layer 104 are sensitive to light. Thus, since the influence of backlight is shielded and the external ambient light is avoided from being blocked, the electrical properties of the first transistor 11 can be used to accurately detect the brightness of the external environment in this embodiment.

[0088] It should be noted that the various directional words in this embodiment, such as above and below, all refer to Figure 1 In the illustrated embodiment, the upper side and the lower side of a structure refer to the side of the structure away from the base substrate 101 , and the lower side of a structure refers to the area between the structure and the base substrate 101 .

[0089] In this embodiment, a second transistor 12 is further provided, and the second transistor 12 is shielded by a second shading layer 22 above. Thus, the electrical performance of the second transistor 12 is only affected by the light and the leaked backlight, thereby improving the backlight detection effect.

[0090] In the present embodiment, a third transistor 13 is further provided. Since the third transistor 13 is shielded by the first shading layer 21 at the bottom and by the second shading layer 22 at the top, the electrical performance of the third transistor 13 is not affected by the backlight and the ambient brightness, and its electrical performance is only affected by temperature changes. In this way, the operating temperature can be detected by detecting the electrical performance of the third transistor 13.

[0091] By combining the detection results of the first transistor 11, the second transistor 12 and the third transistor 13, it is possible to detect and calibrate the temperature, backlight and external ambient light, so as to compensate the display effect in a targeted manner according to the detection and calibration results, which helps to improve the compensation effect.

[0092] In some of the embodiments, the first light-shielding layer 21 is a light-shielding layer 102. By setting the light-shielding layer 102, the backlight can be effectively shielded. During implementation, the light-shielding layer 102 is formed in the area corresponding to the semiconductor layer 104 of the first transistor 11 and the third transistor 13 through a mask process, thereby achieving backlight shielding.

[0093] like Figure 2 and Figure 3 As shown, in some embodiments, the orthographic projection of the gate metal layer 106 on the substrate 101 does not overlap with the first orthographic projection.

[0094] The gate metal layer 106 includes a gate signal line pattern 1061 for transmitting a data signal. The gate signal line pattern 1061 is electrically connected to the light shielding layer 102 so that the light shielding layer 102 is multiplexed as a gate of the first transistor 11 .

[0095] It should be understood that in order to accurately detect external ambient light, it is necessary to avoid external light. If the gate of the first transistor 11 is set above the semiconductor layer 104 of the first transistor 11 like a traditional LTPS transistor, then its gate will block the external ambient light. Therefore, in this embodiment, the light blocking layer 102 is reused as the gate of the first transistor 11.

[0096] like Figure 2 and Figure 3 As shown, in this embodiment, the position of the gate signal line pattern 1061 corresponding to the first transistor 11 is adjusted so that its orthographic projection does not overlap with the orthographic projection of the semiconductor layer 104 of the first transistor 11 on the substrate, so as to avoid blocking external ambient light. At the same time, the gate signal line pattern 1061 is connected to the light shielding layer 102 corresponding to the first transistor 11 to transmit the gate signal.

[0097] The light blocking layer 102 corresponding to the first transistor 11 serves as the first light blocking layer 21 for blocking the semiconductor layer 104 below the first transistor 11, and its position is just opposite to the semiconductor layer 104 of the first transistor 11. Therefore, by using the light blocking layer 102 as the gate of the first transistor 11, it is possible to prevent the gate metal layer 106 from blocking the upper part of the semiconductor layer 104 of the first transistor 11 without affecting the normal function of the first transistor 11.

[0098] Similar to the setting method of the first transistor 11, since the bottom of the third transistor 13 also needs to be shielded by the light blocking layer 102, the setting method for the first transistor 11 in each embodiment of the present application is also applicable to the third transistor 13. Only the first transistor 11 will be further explained below and will not be repeated.

[0099] Of course, the gate of the third transistor 13 may be directly set in a manner similar to that of the conventional gate metal layer 106 , and does not have to be exactly the same as that of the first transistor 11 . This embodiment does not specifically limit or describe this.

[0100] Referring to the a-Si structure, the semiconductor layer 104 of the first transistor 11 in this embodiment may not be doped. off To prevent leakage current, N-doping and LDD (Lightly Drain Doping) doping can be performed. There is no gate metal layer 106 on the upper layer of the semiconductor layer 104, and a layer of N-Gate mask is also required to achieve N-doping and LDD doping.

[0101] The technical solution of this embodiment is based on the existing solution. After the gate insulation layer 105 is completed, a mask process is further added to open a via hole, and then a gate metal layer 106 is made to achieve electrical connection between the gate signal line pattern 1061 corresponding to the first transistor 11 and the light shielding layer 102 corresponding to the first transistor 11.

[0102] like Figure 4 and Figure 5 As shown, in some embodiments, each first transistor 11 shares the same planar gate.

[0103] That is to say, in this embodiment, the light shielding layer 102 serving as the gate of the first transistor 11 is a continuous, whole-piece large-area structure, so that its area is larger and the shielding effect for the backlight from below is better.

[0104] like Figures 6 to 11 As shown, in some embodiments, the light blocking layer 102 includes a plurality of light blocking layer patterns used as gates of the first transistor 11 , the plurality of light blocking layer patterns are spaced apart from each other, and each light blocking layer pattern is used as a gate of one or more first transistors 11 .

[0105] It should be understood that if the size of the light blocking layer pattern serving as the gate is too large, it may cause voltage instability. Therefore, in this embodiment, multiple light blocking layer patterns can be set, and each light blocking layer pattern serves as the gate of one or more first transistors 11. In this way, it can avoid voltage instability caused by the size of a single light blocking layer pattern being too large.

[0106] In some of the embodiments, the orthographic projection of the gate metal layer 106 on the base substrate 101 and the orthographic projection of the source-drain metal layer 108 on the base substrate 101 individually or jointly cover the space between the light shielding layer patterns.

[0107] like Figure 6 and Figure 7 As shown, during implementation, only the gate metal layer 106 can be used to shield the intervals between the light shielding layer patterns; Figure 8 and Fig. 9 As shown, the intervals between the light shielding layer patterns can also be shielded only by the source / drain metal layer 108; in addition, as Fig.10 and Fig.11 As shown, the gate metal layer 106 and the source-drain metal layer 108 can cooperate with each other to achieve shielding of the intervals between the light shielding layer patterns; Fig.12 and Fig.13 As shown, in some embodiments, the above solutions can also be used in combination, that is, the intervals between the light shielding layer patterns are shielded by the source-drain metal layer 108, and at the same time, the light shielding layer 102 is used as the gate of the first transistor 11.

[0108] By shielding the spaces between the light shielding layer patterns, it is possible to prevent the backlight from leaking out of the spaces and affecting the display effect.

[0109] In some of the embodiments, the gate metal layer 106 and the source-drain metal layer 108 are reused as the second light-shielding layer 22, and the orthographic projection of the gate metal layer 106 on the substrate 101 and the orthographic projection of the source-drain metal layer 108 on the substrate 101 individually or jointly cover the second orthographic projection and / or the third orthographic projection.

[0110] like Figures 14 to 17 As shown, in this embodiment, when manufacturing the gate metal layer 106 and the source-drain metal layer 108, the position of the pattern is appropriately adjusted so that the orthographic projections of the gate metal layer 106 and the source-drain metal layer 108 on the substrate 101 can cover the second orthographic projection and / or the third orthographic projection, that is, they can cover the semiconductor layer 104 of the second transistor 12 and the third transistor 13.

[0111] It should be understood that in the embodiment of the present application, the shielding method for the upper part of the second transistor 12 and the shielding method for the upper part of the third transistor 13 may be the same.

[0112] In addition, it should be noted that, for the third transistor 13, the corresponding light shielding layer 102 may not be used as the gate of the third transistor 13. In this case, it is necessary to disconnect it from the portion used as the gate of the third transistor 13 or the gate of the first transistor 11 to insulate them from each other. In this way, the gaps between different light shielding layer patterns can also be used. Figures 6 to 13 The solution of the embodiment shown is shielded to prevent backlight leakage from affecting the display effect.

[0113] like Fig.14 and Fig.15 As shown, in some embodiments, the gate metal layer 106 includes a gate signal line for transmitting a data signal, and the orthographic projection of the gate signal line on the substrate 101 and the orthographic projection of the source-drain metal layer 108 on the substrate 101 individually or jointly cover the second orthographic projection and / or the third orthographic projection.

[0114] It should be noted that when manufacturing the first transistor 11, an additional mask process is required to open a via for connecting the gate metal layer 106 and the light shielding layer 102. In this process, it does not matter whether the second transistor 12 and the third transistor 13 have vias in the areas corresponding to the source and drain metal layers 108, and it will not affect the product itself.

[0115] like Fig.16 and Fig.17 As shown, in some embodiments, the gate metal layer 106 includes a dummy gate pattern 1062, and the orthographic projection of the dummy gate pattern 1062 on the base substrate 101 and the orthographic projection of the source-drain metal layer 108 on the base substrate 101 individually or jointly cover the second orthographic projection and / or the third orthographic projection.

[0116] In this embodiment, the width of the virtual gate pattern 1062 needs to be greater than the spacing between the source and drain metal layers 108 to improve the shielding effect. During implementation, the layout position of the black matrix can be further adjusted to help further improve the shielding effect above the second transistor 12 and the third transistor 13.

[0117] It should be noted that, for the second transistor 12, under the premise of ensuring better detection effect, since it is necessary to detect backlight, the light blocking layer 102 at the second transistor 12 needs to be removed or opened to avoid blocking the bottom of the semiconductor layer 104 of the second transistor 12. Therefore, the light blocking layer 102 is difficult to be used as the gate of the second transistor 12. Accordingly, it is necessary to use the gate metal layer 106 to form the gate of the second transistor 12. In this way, at the second transistor 12, the gate metal layer 106 is difficult to be used as a dummy gate pattern 1062. Therefore, the gate metal layer 106 forms a dummy gate pattern 1062 to block the top of the semiconductor layer 104. This solution is more suitable for the third transistor 13.

[0118] like Figures 18 to 21As shown, in some embodiments, the display substrate further includes a touch metal layer 117, the touch metal layer 117 is formed on a side of the source / drain metal layer 108 away from the base substrate 101, the touch metal layer 117 is reused as a second light shielding layer 22, and the orthographic projection of the touch metal layer 117 on the base substrate 101 covers the second orthographic projection and / or the third orthographic projection.

[0119] like Fig.18 and Fig.19 As shown, the touch metal layer 117 as the second light shielding layer 22 is suitable for the solution of using the light shielding layer 102 as the gate, such as Fig. 20 and Fig.21 As shown, the touch metal layer 117 as the second light shielding layer 22 is also applicable to the conventional solution of forming a gate through the gate metal layer 106 .

[0120] like Fig. 22 and Fig.23 As shown, in some embodiments, the source-drain metal layer 108 includes a dummy source-drain metal pattern 1082 and a source-drain signal line pattern 1081, and the orthographic projection of the dummy source-drain metal pattern 1082 on the base substrate 101 covers the second orthographic projection and / or the third orthographic projection.

[0121] In this embodiment, the dummy source-drain metal pattern 1082 is used to block the second transistor 12 and / or the third transistor 13 .

[0122] Please continue reading Fig. 22 and Fig.23 In some embodiments, the gate metal layer 106 includes a transfer gate pattern 1063, the orthographic projection of the transfer gate pattern 1063 on the base substrate 101 overlaps with the orthographic projection of the source-drain signal line pattern 1081 on the base substrate 101, and the orthographic projection of the transfer gate pattern 1063 on the base substrate 101 overlaps with the second orthographic projection, the transfer gate pattern 1063 is electrically connected to the source-drain signal line pattern 1081, and the transfer gate pattern 1063 is electrically connected to the semiconductor layer 104 of the second transistor 12; and / or

[0123] The orthographic projection of the transfer gate pattern 1063 on the base substrate 101 overlaps with the third orthographic projection, the transfer gate pattern 1063 is electrically connected to the source-drain signal line pattern 1081 , and the transfer gate pattern 1063 is electrically connected to the semiconductor layer 104 of the third transistor 13 .

[0124] During implementation, by measuring the temperature / value curve of batch products and burning the value at a certain temperature, the current temperature can be directly calculated through the value of a certain temperature, and the temperature data can be directly output to realize the temperature sensor function.

[0125] In some of the embodiments, a avoidance opening is provided on the light shielding layer 102 , and the orthographic projection of the avoidance opening on the base substrate 101 overlaps with the second orthographic projection.

[0126] like Fig.24 and Fig.25 As shown, based on Fig.16 and Fig.17 The solution of the embodiment shown can directly start to open holes at corresponding positions when manufacturing the light shielding layer 102 to receive the backlight leakage from the bottom of the display substrate.

[0127] like Fig.26 and Fig. 27 As shown, based on Fig.18 and Fig.19 The solution of the embodiment shown can also be used to avoid opening holes at corresponding positions when manufacturing the light shielding layer 102 to receive backlight leakage from the bottom of the display substrate.

[0128] like Fig.26 and Fig. 27 As shown in the left part, when the light shielding layer 102 is used as a gate, openings can be opened on both sides of the region used as the gate, but this solution has relatively high requirements on the driving capability of the gate.

[0129] like Fig.26 and Fig. 27 As shown in the right part, the semiconductor layer 104 can be completely exposed, and the effect is relatively good.

[0130] like Fig.28 and Fig.29 As mentioned above, similar solutions can also be applied to Fig.23 and Fig.24 The solutions of the embodiments shown can achieve the same effect and will not be described in detail here.

[0131] In some of the embodiments, the light blocking layer 102 includes a switching light blocking pattern, which is electrically connected to the semiconductor layer 104 of the second transistor 12 , the switching light blocking pattern is electrically connected to the switching gate pattern 1063 , and the switching gate pattern 1063 is electrically connected to the source-drain metal layer 108 .

[0132] like Fig.30 and Fig.31As shown, in the technical solution of this embodiment, the two poles of the semiconductor layer 104 transition through the underlying light shielding layer 102, that is, in this embodiment, the size of the gate metal layer 106 is adjusted, and the top of the semiconductor layer 104 is mainly blocked by the gate signal line pattern 1061 and the source-drain metal layer 108, wherein the gate signal line pattern 1061 plays a major shielding role, and the source-drain metal layer 108 is electrically connected to the transfer gate pattern 1063 and the transfer light shielding pattern in turn, thereby further realizing electrical connection with the semiconductor layer 104.

[0133] like Fig.32 and Fig.33 As shown, Fig.30 and Fig.31 The main difference between the embodiments shown is that in this embodiment, a virtual source-drain metal pattern 1082 is used to mainly shield the semiconductor layer 104, wherein the electrical connection between the source-drain metal layer 108 and the semiconductor layer 104 is basically the same in the two embodiments.

[0134] like Figures 34 to 40 As shown, during implementation, by combining the above-mentioned different shielding methods, it is possible to set a first transistor 11 that is shielded at the bottom and used to detect the brightness of the external environment, a second transistor 12 that is shielded at the top and used to detect the backlight intensity, and a third transistor 13 that is shielded at both the top and the bottom and used to detect the temperature in the peripheral area of ​​the display substrate.

[0135] Please continue reading Figure 34 to Figure 39 During implementation, the different shielding methods provided above can be selected and combined as needed to shield the first transistor 11, the second transistor 12 and the third transistor 13. Furthermore, the arrangement of each transistor can also be adjusted as needed, for example, Fig.35 and Fig.38 In the embodiment shown, the transistors are arranged in the horizontal direction as shown in the figure. Fig.36 and Fig.39 The transistors in the circuit are arranged along the vertical direction as shown in the figure.

[0136] In some other embodiments, for the second transistor 12 and the third transistor 13 , it is also possible to consider using the ink layer on the cover glass for shielding. It should be noted that the black matrix 115 has a black matrix opening 1151 at the first transistor 11 .

[0137] Thus, in the technical solution of this embodiment, since each transistor is affected by temperature in the same way at the same temperature, a third transistor 13 for measuring temperature is provided to test its operation without being affected by ambient light and backlight. At this time, its electrical performance is mainly affected by temperature, and the temperature curve tends to be consistent under different ambient light intensities, so that real-time temperature calibration can be achieved without turning off the backlight module.

[0138] like Fig.40 As shown, Fig.40 are ambient light values ​​at different temperature illumination levels, wherein curve 1 is the temperature curve at 0 lux, curve 2 is the temperature curve at 500 lux before improvement, and curve 3 is the temperature curve at 500 lux after improvement by the technical solution of this embodiment. It can be seen from the figure that the temperature curve before calibration has a large deviation, while the temperature curve after calibration has a high degree of matching under different illumination levels.

[0139] like Fig.41 As shown, Fig.41 The horizontal axis is the medium backlight contrast value, and the vertical axis is the G / W (green light / white light) value, which can be understood as the ambient brightness. The upper curve is the change curve before improvement, and the lower curve is the change curve after improvement. It can be seen from the figure that the slope decreases significantly under high illumination, from about 0.25 to about 0.04, and the backlight brightness has less impact on the G / W of the photosensitive area.

[0140] By shielding the third transistor 13 from above and below, in the absence of backlight, the temperature control group tends to be a straight line when the ambient light changes, such as Fig.42 As shown, Fig.42 The horizontal axis is the ambient light illumination, and the vertical axis is the detection result of each transistor, wherein curve 1 is the value of W / G, which can be understood as the ambient brightness, curve 2 is the result before improvement, and curve 3 is the result after improvement of the solution of this embodiment. By comparing curve 2 and curve 3, it can be seen that the technical solution of this embodiment can effectively block the ambient light, and when the brightness increases, it can also avoid the ambient light from affecting the third transistor 13, which helps to improve the accuracy of temperature collection.

[0141] An embodiment of the present invention provides a display device, comprising any one of the above display substrates.

[0142] Since the technical solution of this embodiment includes all the technical solutions of the above-mentioned display substrate embodiment, it can at least achieve all the above-mentioned technical effects, which will not be described in detail here.

[0143] The above is a preferred implementation of the embodiment of the present disclosure. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles described in the present disclosure. These improvements and modifications should also be regarded as the scope of protection of the present disclosure.

Claims

1. A display substrate, comprising: A substrate, comprising a display area and a peripheral area surrounding the display area; A first transistor, disposed in the peripheral area, for detecting the ambient light intensity of the display substrate; A second transistor, disposed in the peripheral area, for detecting the backlight intensity of the display substrate; A third transistor, disposed in the peripheral area, for detecting the temperature of the display substrate; The display substrate further comprises a semiconductor layer, a gate metal layer formed on a side of the semiconductor layer away from the base substrate, and a source-drain metal layer formed on a side of the gate metal layer away from the base substrate; A first light shielding layer is disposed between the semiconductor layer and the base substrate, wherein an orthographic projection of the first light shielding layer on the base substrate covers a first orthographic projection of the semiconductor layer of the first transistor on the base substrate and a third orthographic projection of the semiconductor layer of the third transistor on the base substrate; A second light shielding layer is arranged on a side of the semiconductor layer away from the base substrate, wherein the orthographic projection of the second light shielding layer on the base substrate covers the second orthographic projection and the third orthographic projection of the semiconductor layer of the second transistor on the base substrate; The orthographic projection of the metal layer of the display substrate located on the side of the semiconductor layer away from the base substrate on the base substrate does not overlap with the first orthographic projection.

2. The display substrate according to claim 1, wherein: The display substrate includes a light shielding layer formed between the semiconductor layer and the base substrate, and the first light shielding layer is the light shielding layer.

3. The display substrate according to claim 2, wherein: The orthographic projection of the gate metal layer on the base substrate does not overlap with the first orthographic projection; The gate metal layer includes a gate signal line pattern for transmitting a data signal. The gate signal line pattern is electrically connected to the light shielding layer so that the light shielding layer is reused as a gate of the first transistor.

4. The display substrate according to claim 3, wherein: Each of the first transistors shares a same planar gate.

5. The display substrate according to claim 3, wherein: The light shielding layer includes a plurality of light shielding layer patterns used as gates of the first transistors. The plurality of light shielding layer patterns are arranged at intervals from each other, and each of the light shielding layer patterns is used as a gate of one or more of the first transistors.

6. The display substrate according to claim 5, wherein: The orthographic projection of the gate metal layer on the base substrate and the orthographic projection of the source-drain metal layer on the base substrate cover the space between the light shielding layer patterns individually or together.

7. The display substrate according to claim 1, wherein: The gate metal layer and the source-drain metal layer are reused as the second light-shielding layer, and the orthographic projection of the gate metal layer on the base substrate and the orthographic projection of the source-drain metal layer on the base substrate individually or jointly cover the second orthographic projection and / or the third orthographic projection.

8. The display substrate according to claim 7, wherein: The gate metal layer includes a gate signal line pattern for transmitting a data signal, and the orthographic projection of the gate signal line pattern on the base substrate and the orthographic projection of the source-drain metal layer on the base substrate individually or jointly cover the second orthographic projection and / or the third orthographic projection.

9. The display substrate according to claim 7, wherein: The gate metal layer includes a dummy gate pattern, and the orthographic projection of the dummy gate pattern on the base substrate and the orthographic projection of the source-drain metal layer on the base substrate individually or jointly cover the second orthographic projection and / or the third orthographic projection.

10. The display substrate according to claim 7, wherein: The source-drain metal layer includes a dummy source-drain metal pattern and a source-drain signal line pattern, and the orthographic projection of the dummy source-drain metal pattern on the base substrate covers the second orthographic projection and / or the third orthographic projection.

11. The display substrate according to claim 10, wherein: The gate metal layer includes a transfer gate pattern, the orthographic projection of the transfer gate pattern on the base substrate overlaps with the orthographic projection of the source-drain signal line pattern on the base substrate, and the orthographic projection of the transfer gate pattern on the base substrate overlaps with the second orthographic projection, the transfer gate pattern is electrically connected to the source-drain signal line pattern, and the transfer gate pattern is electrically connected to the semiconductor layer of the second transistor; and / or The orthographic projection of the transfer gate pattern on the base substrate overlaps with the third orthographic projection, the transfer gate pattern is electrically connected to the source-drain signal line pattern, and the transfer gate pattern is electrically connected to the semiconductor layer of the third transistor.

12. The display substrate according to claim 1, wherein: The display substrate also includes a touch metal layer, which is formed on a side of the source and drain metal layer away from the base substrate, and is reused as the second light-shielding layer. The orthographic projection of the touch metal layer on the base substrate covers the second orthographic projection and / or the third orthographic projection.

13. The display substrate according to claim 1, wherein: The light shielding layer is provided with an avoidance opening, and the orthographic projection of the avoidance opening on the base substrate overlaps with the second orthographic projection.

14. The display substrate according to claim 13, wherein: The light shielding layer includes a switching light shielding pattern, the switching light shielding pattern is electrically connected to the semiconductor layer of the second transistor, the switching light shielding pattern is electrically connected to a switching gate pattern, and the switching gate pattern is electrically connected to the source-drain metal layer.

15. A display device, characterized in that: A display substrate comprising any one of claims 1 to 14.

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