Display substrate and display device

Abstract

The invention provides a display substrate and a display device. The display substrate comprises a substrate body, a first transistor, a second transistor, a third transistor, a first shading layer and a second shading layer. According to the embodiment of the invention, the first transistor for detecting the ambient light intensity, the second transistor for detecting the backlight intensity and the third transistor for detecting the temperature are arranged, the first light shielding layer is used for shielding the lower parts of the first transistor and the third transistor, and the second light shielding layer is used for shielding the upper parts of the second transistor and the third transistor; therefore, the working environment parameters of the display panel can be effectively and accurately collected, and the compensation effect on the display effect is improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display substrate and a display device. Background Art

[0002] In order to improve the color display accuracy of mobile phones and other display devices in different environments, it is necessary to compensate the display effect of the display panel in a targeted manner. In the related art, the electrical characteristics of the semiconductor layer of the transistor are sensitive to brightness, and the brightness of the display panel is detected to compensate the display effect of the display panel. However, for the bottom-gate display substrate, due to the structural limitations of its transistors, it is difficult to take into account both the external brightness test and the backlight brightness test, which affects the compensation effect of the display device. Summary of the invention

[0003] The embodiments of the present invention provide a display substrate and a display device to solve the problem that the existing method has low accuracy in collecting brightness of a display panel and affects the compensation effect.

[0004] To solve the above problems, the present invention is achieved as follows:

[0005] In a first aspect, an embodiment of the present invention provides a display substrate, comprising:

[0006] A substrate, comprising a display area and a peripheral area surrounding the display area;

[0007] A first transistor, disposed in the peripheral area, for detecting the ambient light intensity of the display substrate;

[0008] A second transistor, disposed in the peripheral area, for detecting the backlight intensity of the display substrate;

[0009] A third transistor, disposed in the peripheral area, for detecting the temperature of the display substrate;

[0010] The display substrate further comprises a gate metal layer, a semiconductor layer formed on a side of the gate metal layer away from the base substrate, and a source-drain metal layer formed on a side of the semiconductor layer away from the base substrate;

[0011] A first light shielding layer is disposed between the semiconductor layer and the base substrate, wherein an orthographic projection of the first light shielding layer on the base substrate covers a first orthographic projection of the semiconductor layer of the first transistor on the base substrate and a third orthographic projection of the semiconductor layer of the third transistor on the base substrate;

[0012] A second light shielding layer is arranged on a side of the semiconductor layer away from the base substrate, wherein the orthographic projection of the second light shielding layer on the base substrate covers the second orthographic projection and the third orthographic projection of the semiconductor layer of the second transistor on the base substrate;

[0013] The orthographic projection of the metal layer of the display substrate located on the side of the semiconductor layer away from the base substrate on the base substrate does not overlap with the first orthographic projection.

[0014] In some embodiments, the gate metal layer is reused as the first light shielding layer.

[0015] In some embodiments, each of the first transistors shares a same continuous planar gate.

[0016] In some embodiments, the gate metal layer includes a plurality of gate metal patterns used to serve as gates of the first transistors, the plurality of gate metal patterns are spaced apart from each other, and each of the gate metal patterns is used to serve as a gate of one or more of the first transistors.

[0017] In some embodiments, an orthographic projection of the source-drain metal layer on the substrate overlaps a space between the gate metal patterns.

[0018] In some embodiments, the source-drain metal layer includes a target source-drain metal pattern whose orthographic projection overlaps with the interval between the gate metal pattern;

[0019] At least some of the adjacent two first transistors share the same target source-drain metal pattern.

[0020] In some of the embodiments, among the plurality of first transistors arranged in sequence, two adjacent ones alternately share the target source-drain metal pattern and the gate metal pattern in sequence.

[0021] In some embodiments, a second orthographic projection of the semiconductor layer of the second transistor on the substrate at least partially does not overlap with an orthographic projection of the gate metal layer on the substrate.

[0022] In some embodiments, the gate metal layer and the source / drain metal layer are reused as the second light shielding layer;

[0023] The gate metal layer includes a gate signal pattern and a transfer gate pattern, and the source-drain metal layer includes a source-drain signal pattern and a transfer source-drain metal pattern;

[0024] The gate signal pattern is electrically connected to the transfer source-drain metal pattern to transmit the gate signal of the second transistor;

[0025] The source-drain signal pattern is electrically connected to the transfer gate pattern, and the transfer gate pattern is electrically connected to the semiconductor layer of the second transistor to transmit the source-drain signal of the second transistor.

[0026] In some embodiments, the gate metal layer includes a gate signal pattern for transmitting a gate signal, the source-drain metal layer includes a source-drain signal pattern and a dummy source-drain metal pattern, and the orthographic projection of the dummy source-drain metal pattern on the substrate covers the second orthographic projection.

[0027] In some embodiments, the source-drain metal layer includes a source-drain signal pattern and a dummy source-drain metal pattern, and the orthographic projection of the dummy source-drain metal pattern on the substrate covers the second orthographic projection;

[0028] The display substrate further includes a first electrode layer located between the semiconductor layer and the source-drain metal layer, the first electrode layer includes a switching electrode pattern, the source-drain signal pattern is electrically connected to the switching electrode pattern, and the switching electrode pattern is electrically connected to the semiconductor layer of the second transistor.

[0029] In some embodiments, the gate metal layer includes a gate signal pattern for transmitting a gate signal, and the gate signal pattern for transmitting the gate signal does not overlap with the second orthographic projection;

[0030] The display substrate further includes a second gate layer, which is located on a side of the source-drain metal layer away from the base substrate, an orthographic projection of the second gate layer on the base substrate overlaps with the second orthographic projection, and the second gate layer is electrically connected to the gate signal pattern.

[0031] In a second aspect, an embodiment of the present invention provides a display device, comprising the display substrate described in any one of the first aspects.

[0032] The embodiment of the present invention sets a first transistor for detecting ambient light intensity, a second transistor for detecting backlight intensity, and a third transistor for detecting temperature, and uses a first shading layer to block the bottom of the first transistor and the third transistor, and uses a second shading layer to block the top of the second transistor and the third transistor, so that the working environment parameters of the display panel can be effectively and accurately collected to improve the compensation effect on the display effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative labor.

[0034] Figure 1 is a schematic structural diagram of a display substrate in one embodiment of the present invention;

[0035] Figure 2is a schematic structural diagram of a display substrate in another embodiment of the present invention;

[0036] Figure 3 In one embodiment Figure 2 The AA' cross-sectional view of the display substrate is shown;

[0037] Figure 4 In yet another embodiment Figure 2 The AA' cross-sectional view of the display substrate is shown;

[0038] Figure 5 is a schematic structural diagram of a display substrate in another embodiment of the present invention;

[0039] Figure 6 In one embodiment Figure 5 The BB' cross-sectional view of the display substrate is shown;

[0040] Figure 7 In another embodiment Figure 5 The BB' cross-sectional view of the display substrate is shown;

[0041] Figure 8 is a schematic structural diagram of a display substrate in another embodiment of the present invention;

[0042] Fig. 9 In one embodiment Figure 8 The CC' cross-sectional view of the display substrate is shown;

[0043] Fig.10 In another embodiment Figure 8 The CC' cross-sectional view of the display substrate is shown;

[0044] Fig.11 is a schematic structural diagram of a display substrate in another embodiment of the present invention;

[0045] Fig.12 yes Fig.11 The DD' cross-sectional view of the display substrate is shown;

[0046] Fig.13 is a schematic structural diagram of a display substrate in another embodiment of the present invention;

[0047] Fig.14 yes Fig.13 The EE' cross-sectional view of the display substrate is shown;

[0048] Fig.15 is a schematic structural diagram of a display substrate in another embodiment of the present invention;

[0049] Fig.16 yes Fig.15 The sectional view of the substrate taken along the line F-F' is shown;

[0050] Fig.17 is a schematic structural diagram of a display substrate in another embodiment of the present invention;

[0051] Fig.18 In one embodiment Fig.17 The cross-sectional view of the display substrate taken along the line G-G' is shown;

[0052] Fig.19 In another embodiment Fig.17 The cross-sectional view of the display substrate taken along the line G-G' is shown;

[0053] Fig. 20 is a schematic structural diagram of a display substrate in another embodiment of the present invention;

[0054] Fig.21 yes Fig. 20 The H-H' cross-sectional view of the display substrate is shown;

[0055] Fig. 22 is a schematic structural diagram of a display substrate in another embodiment of the present invention;

[0056] Fig.23 In one embodiment Fig. 22 The display substrate is shown in a cross-sectional view taken along the line II'.

[0057] Fig.24 Another embodiment Fig. 22 The display substrate is shown in a cross-sectional view taken along the line II'.

[0058] Fig.25 is a schematic structural diagram of a display substrate in another embodiment of the present invention;

[0059] Fig.26 In one embodiment Fig.25 The J-J' cross-sectional view of the display substrate is shown;

[0060] Fig. 27 In another embodiment Fig.25 The J-J' cross-sectional view of the display substrate is shown;

[0061] Fig.28 is a schematic structural diagram of a display substrate in another embodiment of the present invention;

[0062] Fig.29 yes Fig.28 The K-K' cross-sectional view of the display substrate is shown;

[0063] Fig.30 is a schematic structural diagram of a display substrate in another embodiment of the present invention;

[0064] Fig.31 yes Fig.30 The sectional view of the substrate shown is taken along the line L-L';

[0065] Fig.32 is a schematic structural diagram of a display substrate in another embodiment of the present invention;

[0066] Fig.33 is a schematic structural diagram of a display substrate in another embodiment of the present invention;

[0067] Fig.34 It is the numerical curve of ambient light value at different temperatures and illumination levels;

[0068] Fig.35 The backlight contrast value and G / W relationship curve in one embodiment of the present invention;

[0069] Fig.36 1 is a curve of brightness detection values ​​under different ambient brightnesses in one embodiment of the present invention. DETAILED DESCRIPTION

[0070] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0071] The terms "first", "second" etc. in the embodiments of the present invention are used to distinguish similar objects, and need not be used to describe a specific order or sequential order. In addition, the terms "include" and "have" and any variation thereof are intended to cover non-exclusive inclusions, for example, the process, method, system, product or equipment comprising a series of steps or units need not be limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or equipment. In addition, "and / or" is used in the present application to represent at least one of the connected objects, such as A and / or B and / or C, which represents 7 situations including single A, single B, single C, and A and B all exist, B and C all exist, A and C all exist, and A, B and C all exist.

[0072] An embodiment of the present invention provides a display substrate.

[0073] In some of the embodiments, the display substrate is taken as a 7-mask (9-time mask exposure and etching process) or 7-mask bottom gate array substrate for exemplary description.

[0074] In an exemplary embodiment, the 6mask array substrate includes a base substrate 101 and a gate metal layer (generally Mo) 102, a gate insulating layer (generally SiO2 / SiN x)103, semiconductor layer (Poly, low temperature polysilicon P-Si is used in LTPS panel) 104, first electrode layer (usually used as the surface electrode of the common electrode, usually indium tin oxide ITO), first insulating layer (PVX, generally SiN x )105, source and drain metal layer (SD, Source & Drain, generally made of titanium aluminum titanium Ti / Al / Ti) 106, second insulating layer (PVX, generally made of SiN x ), a second electrode layer (generally a driving electrode) and a first liquid crystal alignment layer (PI) 107. Based on the above-mentioned 6-mask array substrate, the 7-mask array substrate needs to further manufacture an insulating layer after manufacturing the source and drain metal layer 106.

[0075] The array substrate can be assembled with the color filter substrate to form a liquid crystal cell, in which a liquid crystal layer 108 is disposed. The color filter substrate includes a second liquid crystal alignment layer (PI) 109, a G / W color resist 110, a black matrix (black resin material) 111 and a glass cover 112.

[0076] In this embodiment, the base substrate 101 includes a display area and a peripheral area surrounding the display area, wherein the display area includes sub-pixels. It should be noted that in this embodiment, any unmentioned parts about the structure and process of the display substrate itself can refer to the relevant technology and will not be repeated in this application.

[0077] like Figure 1 As shown, in this embodiment, a first transistor 11 for detecting the ambient light intensity of the display substrate, a second transistor 12 for detecting the backlight intensity of the display substrate, and a third transistor 13 for detecting the temperature of the display substrate are arranged in the peripheral area.

[0078] The display substrate also includes a first shading layer 21 and a second shading layer 22. The first shading layer 21 is arranged between the semiconductor layer 104 and the base substrate 101. The orthographic projection of the first shading layer 21 on the base substrate 101 covers the first orthographic projection of the semiconductor layer 104 of the first transistor 11 on the base substrate 101 and the third orthographic projection of the semiconductor layer 104 of the third transistor 13 on the base substrate 101.

[0079] The second light shielding layer 22 is disposed on a side of the semiconductor layer 104 away from the base substrate 101 , and the orthographic projection of the second light shielding layer 22 on the base substrate 101 covers the second orthographic projection and the third orthographic projection of the semiconductor layer 104 of the second transistor 12 on the base substrate 101 .

[0080] The orthographic projection of the metal layer of the display substrate located on the side of the semiconductor layer 104 away from the base substrate 101 on the base substrate 101 does not overlap with the first orthographic projection.

[0081] It should be understood that the display substrate in this embodiment is a bottom-gate display substrate, that is, the gate metal layer 102 is located between the semiconductor layer 104 and the base substrate 101 .

[0082] In the technical solution of this embodiment, in order to avoid the structure above the first transistor 11 blocking the semiconductor layer 104 of the first transistor 11, the orthographic projection of the metal layer above the semiconductor layer 104 on the base substrate 101 does not overlap with the first orthographic projection, so that the semiconductor layer 104 can fully receive external light.

[0083] It should be understood that the liquid crystal display device is backlit by a backlight source, and the backlight may have light leakage. In this embodiment, the first light-shielding layer 21 is used to block the bottom of the first transistor 11, thereby preventing the backlight from irradiating the semiconductor layer 104 of the first transistor 11, ensuring that the electrical performance of the first transistor 11 is only affected by light from external ambient light.

[0084] The electrical properties of the semiconductor layer 104 are sensitive to light. Thus, since the influence of backlight is shielded and the external ambient light is avoided from being blocked, the electrical properties of the first transistor 11 can be used to accurately detect the brightness of the external environment in this embodiment.

[0085] It should be noted that the various directional words in this embodiment, such as above and below, all refer to Figure 1 In the illustrated embodiment, the upper side and the lower side of a structure refer to the side of the structure away from the base substrate 101 , and the lower side of a structure refers to the area between the structure and the base substrate 101 .

[0086] In this embodiment, a second transistor 12 is further provided, and the second transistor 12 is shielded by a second shading layer 22 above. Thus, the electrical performance of the second transistor 12 is only affected by the light and the leaked backlight, thereby improving the backlight detection effect.

[0087] In the present embodiment, a third transistor 13 is further provided. Since the third transistor 13 is shielded by the first shading layer 21 at the bottom and by the second shading layer 22 at the top, the electrical performance of the third transistor 13 is not affected by the backlight and the ambient brightness, and its electrical performance is only affected by temperature changes. In this way, the operating temperature can be detected by detecting the electrical performance of the third transistor 13.

[0088] By combining the detection results of the first transistor 11, the second transistor 12 and the third transistor 13, it is possible to detect and calibrate the temperature, backlight and external ambient light, so as to compensate the display effect in a targeted manner according to the detection and calibration results, which helps to improve the compensation effect.

[0089] like Figures 2 to 4 As shown, in one embodiment, the gate metal layer 102 is reused as the first light shielding layer 21 .

[0090] like Figures 2 to 4 As shown, in some embodiments, each first transistor 11 shares a same continuous planar gate.

[0091] That is to say, in this embodiment, the gate of the first transistor 11 is a continuous, whole-piece large-area structure, so that its area is larger and the shielding effect of the backlight from below is better.

[0092] like Figures 5 to 7 As shown, in some embodiments, the gate metal layer 102 includes a plurality of gate metal patterns used as gates of the first transistor 11 , the plurality of gate metal patterns are spaced apart from each other, and each gate metal pattern is used as a gate of one or more first transistors 11 .

[0093] It should be understood that if the size of the gate metal pattern is too large, it may cause voltage instability. Therefore, in this embodiment, multiple gate metal patterns can be set, and each gate metal pattern serves as the gate of one or more first transistors 11. In this way, it is possible to avoid voltage instability caused by the size of a single gate metal pattern being too large.

[0094] Please continue reading Figures 5 to 7 In some embodiments, the orthographic projection of the source / drain metal layer 106 on the substrate 101 overlaps with the space between the gate metal patterns.

[0095] In this embodiment, when the gate metal patterns are arranged at intervals, the intervals between the gate metal patterns are shielded by the source-drain metal layer 106 to prevent backlight leakage during image display and thus prevent the display effect from being affected.

[0096] like Figures 8 to 10 As shown, in some embodiments, the source-drain metal layer 106 includes a target source-drain metal pattern whose orthographic projection overlaps with the interval between the gate metal pattern; at least two adjacent first transistors 11 share the same target source-drain metal pattern.

[0097] In some of the embodiments, among the plurality of first transistors 11 arranged in sequence, two adjacent ones alternately share the target source-drain metal pattern and the gate metal pattern in sequence.

[0098] It can be understood that, in this embodiment, the gaps between adjacent gate metal patterns are shielded by the source-drain metal layer 106, and the gaps between the source-drain metal patterns of the source-drain metal layer 106 are shielded by the gate metal layer 102. In this way, the source-drain metal layer 106 and the gate metal layer 102 cooperate to achieve shielding of the gaps, which can avoid backlight leakage when displaying images and affect the display effect.

[0099] like Fig.11 and Fig.12 As shown, in some embodiments, a second orthographic projection of the semiconductor layer 104 of the second transistor 12 on the substrate 101 at least partially does not overlap with an orthographic projection of the gate metal layer 102 on the substrate 101 .

[0100] For the second transistor 12 used to detect the backlight brightness, it is necessary to shield the top thereof to avoid the influence of external ambient light. Further, in the area corresponding to the second transistor 12, by adjusting the shape of the gate metal layer 102, the bottom of the second transistor 12 is exposed to detect the backlight brightness.

[0101] Please continue reading Fig.11 and Fig.12 In one embodiment, the gate metal layer 102 and the source-drain metal layer 106 are reused as the second light shielding layer 22; the gate metal layer 102 includes a gate signal pattern 1021 and a switching gate pattern 1022, and the source-drain metal layer 106 includes a source-drain signal pattern 1061 and a switching source-drain metal pattern 1062;

[0102] The gate signal pattern 1021 and the switching source-drain metal pattern 1062 are electrically connected to transmit the gate signal of the second transistor 12; the source-drain signal pattern 1061 and the switching gate pattern 1022 are electrically connected, and the switching gate pattern 1022 is electrically connected to the semiconductor layer 104 of the second transistor 12 to transmit the source-drain signal of the second transistor 12.

[0103] In the technical solution of this embodiment, the position and size of the switching source-drain metal pattern 1062 in the source-drain metal layer 106 are first adjusted so that it can effectively cover the upper part of the semiconductor layer 104 of the second transistor 12 .

[0104] Furthermore, in this embodiment, the gate signal is transferred through the source-drain metal layer 106, and the source-drain electrode signal is transferred through the gate metal layer 102. In this way, the technical solution of this embodiment can cleverly use the source-drain metal layer 106 located above the semiconductor layer 104 of the second transistor 12 to play the role of the gate of the second transistor 12, so that the area occupied by the gate metal layer 102 can be released to avoid blocking the semiconductor layer 104 below the second transistor 12.

[0105] like Fig.13 and Fig.14 As shown, in some embodiments, the gate metal layer 102 includes a gate signal pattern 1021 for transmitting a gate signal, the source-drain metal layer 106 includes a source-drain signal pattern 1061 and a dummy source-drain metal pattern 1063, and the orthographic projection of the dummy source-drain metal pattern 1063 on the substrate 101 covers the second orthographic projection.

[0106] In the technical solution of this embodiment, the gate metal layer 102 is still used to form the gate of the second transistor 12. During implementation, openings are provided on both sides of the gate signal pattern 1021 so that the backlight can illuminate the semiconductor layer 104 of the second transistor 12. Furthermore, the portion of the source-drain metal layer 106 located above the semiconductor layer 104 of the second transistor 12 is used as a virtual source-drain metal pattern 1063 to block the light above the semiconductor layer 104 of the second transistor 12.

[0107] like Fig.15 and Fig.16 As shown, in some embodiments, the source-drain metal layer 106 includes a source-drain signal pattern 1061 and a dummy source-drain metal pattern 1063 , and the orthographic projection of the dummy source-drain metal pattern 1063 on the base substrate 101 covers the second orthographic projection.

[0108] The display substrate further includes a first electrode layer located between the semiconductor layer 104 and the source-drain metal layer 106 . The first electrode layer includes a switching electrode pattern 113 . The source-drain signal pattern 1061 is electrically connected to the switching electrode pattern 113 . The switching electrode pattern 113 is electrically connected to the semiconductor layer 104 of the second transistor 12 .

[0109] In this embodiment, the switching electrode pattern 113 is manufactured when the first electrode layer is manufactured, so that the source-drain signal is transmitted through the switching electrode pattern 113 .

[0110] like Figures 17 to 19 As shown, in some embodiments, the gate metal layer 102 includes a gate signal pattern 1021 for transmitting a gate signal, and the gate signal pattern 1021 does not overlap with the second orthographic projection.

[0111] The display substrate further includes a second gate layer 114 , which is located on a side of the source / drain metal layer 106 away from the base substrate 101 , an orthographic projection of the second gate layer 114 on the base substrate 101 overlaps with the second orthographic projection, and the second gate layer 114 is electrically connected to the gate signal pattern 1021 .

[0112] In the technical solution of this embodiment, a second gate layer 114 can be further fabricated on the side of the source / drain metal layer 106 away from the base substrate 101 as the gate of the second transistor 12 , and the second gate layer 114 is connected to the gate signal pattern 1021 to obtain a gate signal.

[0113] like Fig. 20 and Fig.21 As shown, for the third transistor 13 , it is necessary to shield the top and bottom thereof at the same time. Therefore, the above-mentioned solutions applied to the first transistor 11 and the second transistor 12 can be combined to shield the third transistor 13 .

[0114] Please continue reading Fig. 20 and Fig.21 In this embodiment, the entire gate metal layer 102 shields the bottom of the semiconductor layer 104 of the third transistor 13, and the dummy source and drain metal pattern 1063 shields the top of the semiconductor layer 104 of the third transistor 13.

[0115] like Fig. 22 Zhihe Fig.24 As shown, in some embodiments, the entire gate metal layer 102 is used to shield the semiconductor layer 104 below the third transistor 13 , and an additional shielding metal layer 115 is formed to shield the semiconductor layer 104 above the third transistor 13 .

[0116] like Fig.25 Zhihe Fig. 27 As shown, in some of the embodiments, the entire gate metal layer 102 is used to block the bottom of the semiconductor layer 104 of the third transistor 13, and a second gate layer 114 is made on the side of the source-drain metal layer 106 away from the substrate 101 as the gate of the third transistor 13, and the second gate layer 114 can also block the top of the semiconductor layer 104 of the third transistor 13.

[0117] like Fig.28 and Fig.29 As shown, in some of the embodiments, a virtual source-drain metal pattern 1063 is used to shield the upper part of the semiconductor layer 104 of the third transistor 13, and a separate light shielding layer 115 is made between the substrate 101 and the gate metal layer 102 to shield the lower part of the semiconductor layer 104 of the third transistor 13.

[0118] like Fig.30 and Fig.31 As shown, in some of the embodiments, the entire gate metal layer 102 is used to shield the bottom of the semiconductor layer 104 of the third transistor 13, and the virtual source and drain metal pattern 1063 is used to shield the top of the semiconductor layer 104 of the third transistor 13, while the source and drain signals are transmitted by setting the switching electrode pattern 113.

[0119] like Figure 32 to Figure 33As shown, during implementation, by combining the above-mentioned different shielding methods, it is possible to set a first transistor 11 that is shielded at the bottom and used to detect the brightness of the external environment, a second transistor 12 that is shielded at the top and used to detect the backlight intensity, and a third transistor 13 that is shielded at both the top and the bottom and used to detect the temperature in the peripheral area of ​​the display substrate.

[0120] In some other embodiments, it may also be considered to use an ink layer on the cover glass to shield the second transistor 12 and the third transistor 13 .

[0121] Thus, in the technical solution of this embodiment, since each transistor is affected by temperature in the same way at the same temperature, a third transistor 13 for measuring temperature is provided to test its operation without being affected by ambient light and backlight. At this time, its electrical performance is mainly affected by temperature, and the temperature curve tends to be consistent under different ambient light intensities, so that real-time temperature calibration can be achieved without turning off the backlight module.

[0122] like Fig.34 As shown, Fig.34 are ambient light values ​​at different temperature illumination levels, wherein curve 1 is the temperature curve at 0 lux, curve 2 is the temperature curve at 500 lux before improvement, and curve 3 is the temperature curve at 500 lux after improvement by the technical solution of this embodiment. It can be seen from the figure that the temperature curve before calibration has a large deviation, while the temperature curve after calibration has a high degree of matching under different illumination levels.

[0123] like Fig.35 As shown, Fig.35 The horizontal axis is the medium backlight contrast value, and the vertical axis is the G / W (green light / white light) value, which can be understood as the ambient brightness. The upper curve is the change curve before improvement, and the lower curve is the change curve after improvement. It can be seen from the figure that the slope decreases significantly under high illumination, from about 0.25 to about 0.04, and the backlight brightness has less impact on the G / W of the photosensitive area.

[0124] By shielding the third transistor 13 from above and below, in the absence of backlight, the temperature control group tends to be a straight line when the ambient light changes, such as Fig.36 As shown, Fig.36 The horizontal axis is the ambient light illumination, and the vertical axis is the detection result of each transistor, wherein curve 1 is the value of W / G, which can be understood as the ambient brightness, curve 2 is the result before improvement, and curve 3 is the result after improvement of the solution of this embodiment. By comparing curve 2 and curve 3, it can be seen that the technical solution of this embodiment can effectively block the ambient light, and when the brightness increases, it can also avoid the ambient light from affecting the third transistor 13, which helps to improve the accuracy of temperature collection.

[0125] An embodiment of the present invention provides a display device, comprising any one of the above display substrates.

[0126] Since the technical solution of this embodiment includes all the technical solutions of the above-mentioned display substrate embodiment, it can at least achieve all the above-mentioned technical effects, which will not be described in detail here.

[0127] The above is a preferred implementation of the embodiment of the present disclosure. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles described in the present disclosure. These improvements and modifications should also be regarded as the scope of protection of the present disclosure.

Claims

1. A display substrate, comprising: A substrate, comprising a display area and a peripheral area surrounding the display area; A first transistor, disposed in the peripheral area, for detecting the ambient light intensity of the display substrate; A second transistor, disposed in the peripheral area, for detecting the backlight intensity of the display substrate; A third transistor, disposed in the peripheral area, for detecting the temperature of the display substrate; The display substrate further comprises a gate metal layer, a semiconductor layer formed on a side of the gate metal layer away from the base substrate, and a source-drain metal layer formed on a side of the semiconductor layer away from the base substrate; A first light shielding layer is disposed between the semiconductor layer and the base substrate, wherein an orthographic projection of the first light shielding layer on the base substrate covers a first orthographic projection of the semiconductor layer of the first transistor on the base substrate and a third orthographic projection of the semiconductor layer of the third transistor on the base substrate; A second light shielding layer is arranged on a side of the semiconductor layer away from the base substrate, wherein the orthographic projection of the second light shielding layer on the base substrate covers the second orthographic projection and the third orthographic projection of the semiconductor layer of the second transistor on the base substrate; The orthographic projection of the metal layer of the display substrate located on the side of the semiconductor layer away from the base substrate on the base substrate does not overlap with the first orthographic projection.

2. The display substrate according to claim 1, wherein: The gate metal layer is reused as the first light shielding layer.

3. The display substrate according to claim 2, wherein: Each of the first transistors shares a same continuous planar gate.

4. The display substrate according to claim 3, wherein: The gate metal layer includes a plurality of gate metal patterns used as gates of the first transistors. The plurality of gate metal patterns are arranged at intervals from each other, and each of the gate metal patterns is used as a gate of one or more of the first transistors.

5. The display substrate according to claim 4, wherein: The orthographic projection of the source-drain metal layer on the base substrate overlaps the interval between the gate metal patterns.

6. The display substrate according to claim 4 or 5, characterized in that: The source-drain metal layer includes a target source-drain metal pattern whose orthographic projection overlaps with the interval between the gate metal pattern; At least some of the adjacent two first transistors share the same target source-drain metal pattern.

7. The display substrate according to claim 6, wherein: Among the plurality of first transistors arranged in sequence, two adjacent ones alternately share the target source-drain metal pattern and the gate metal pattern in sequence.

8. The display substrate according to claim 1, wherein: A second orthographic projection of the semiconductor layer of the second transistor on the substrate does not at least partially overlap with an orthographic projection of the gate metal layer on the substrate.

9. The display substrate according to claim 8, wherein: The gate metal layer and the source-drain metal layer are reused as the second light shielding layer; The gate metal layer includes a gate signal pattern and a transfer gate pattern, and the source-drain metal layer includes a source-drain signal pattern and a transfer source-drain metal pattern; The gate signal pattern is electrically connected to the transfer source-drain metal pattern to transmit the gate signal of the second transistor; The source-drain signal pattern is electrically connected to the transfer gate pattern, and the transfer gate pattern is electrically connected to the semiconductor layer of the second transistor to transmit the source-drain signal of the second transistor.

10. The display substrate according to claim 8, wherein: The gate metal layer includes a gate signal pattern for transmitting a gate signal, and the source-drain metal layer includes a source-drain signal pattern and a dummy source-drain metal pattern, and the orthographic projection of the dummy source-drain metal pattern on the base substrate covers the second orthographic projection.

11. The display substrate according to claim 8, wherein: The source-drain metal layer includes a source-drain signal pattern and a dummy source-drain metal pattern, and the orthographic projection of the dummy source-drain metal pattern on the base substrate covers the second orthographic projection; The display substrate further includes a first electrode layer located between the semiconductor layer and the source-drain metal layer, the first electrode layer includes a switching electrode pattern, the source-drain signal pattern is electrically connected to the switching electrode pattern, and the switching electrode pattern is electrically connected to the semiconductor layer of the second transistor.

12. The display substrate according to claim 8, wherein: The gate metal layer includes a gate signal pattern for transmitting a gate signal, and the gate signal pattern for transmitting the gate signal does not overlap with the second orthographic projection; The display substrate further includes a second gate layer, which is located on a side of the source-drain metal layer away from the base substrate, an orthographic projection of the second gate layer on the base substrate overlaps with the second orthographic projection, and the second gate layer is electrically connected to the gate signal pattern.

13. A display device, characterized in that: A display substrate comprising any one of claims 1 to 12.

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