Power supply circuit and electronic equipment
By setting up an operational amplifier between the current generation branch and the copy branch, the accurate replication of the reference reference current and the current adjustment unit are solved, and the problem of changes in the load circuit state affecting the target current is achieved, and the stability and accuracy of the target current are achieved.
Patent Information
- Application Number
- CN202411771154.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-03
- Publication Date
- 2025-03-11
AI Technical Summary
In the prior art, changes in the operating state of the load circuit will inversely affect the output voltage of the current mirror, resulting in a deviation in the target current.
By providing a first operational amplifier between the current generation branch and the current copy branch, the reference reference current is equal to the replication current, thereby ensuring accurate replication of the replication current, and adjusting the current through the second operational amplifier in the current adjustment unit to reduce the impact of the load circuit.
The stability and accuracy of the target current are achieved when the working state of the load circuit changes, reducing the impact of the load circuit on the output current.
Smart Images
Figure CN119597091A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of power supply, and in particular to a power supply circuit and electronic equipment. Background Art
[0002] In analog circuits, a constant current source is used to provide a stable reference current that is not affected by the outside world. The reference current is copied, doubled, or reduced by a current mirror to obtain the target current, and the target current is output to other circuit modules to provide the current required for normal operation of other circuit modules.
[0003] Since different circuit modules may require different currents, the current mirror can adjust the output target current so that the current meets the working requirements. In the prior art, when the current mirror provides the required current for different circuit modules, the change in the working state of the load circuit will reversely affect the output voltage of the current mirror, thereby causing the output target current to deviate. Summary of the invention
[0004] The present invention aims at providing a power supply circuit which can provide a stable target current which does not vary with the working state of the load circuit.
[0005] In a first aspect, the present invention provides a power supply circuit, comprising: a bias voltage generating unit, a reference current copying unit and a current adjusting unit, wherein: the bias voltage generating unit is suitable for generating and outputting a bias voltage; the reference current copying unit is coupled to the bias voltage generating unit, and is suitable for generating a reference reference current and outputting a copy current; the reference current copying unit comprises: a current generating branch, a current copying branch and a first operational amplifier, wherein: the current generating branch is suitable for generating the reference reference current; the current copying branch is suitable for copying the reference reference current to obtain the copy current; the first operational amplifier has a first input terminal coupled to the current generating branch, a second input terminal coupled to the current copying branch, and an output terminal coupled to the current adjusting unit; the current adjusting unit is suitable for adjusting the copy current to obtain a target current.
[0006] A first operational amplifier is provided between the current generating branch and the current copying branch. Through the first operational amplifier, the base reference current on the current generating branch is equal to the copy current on the current copying branch. Thus, the current copying branch can accurately copy the base reference current, and the copy current will not change with the state of the load circuit. Furthermore, the target current obtained by adjusting the copy current is less affected by the load circuit.
[0007] Optionally, the current generating branch includes a first MOS tube, a second MOS tube and a reference current source; the current replicating branch includes a third MOS tube, a fourth MOS tube and a tenth MOS tube; wherein: the first MOS tube, a first end thereof is coupled to the second end of the second MOS tube, a second end thereof is coupled to the first end of the reference current source, and a control end thereof inputs the bias voltage; the second MOS tube, a first end thereof is input with a power supply voltage, a second end thereof is coupled to the first input end of the first operational amplifier, and a control end thereof is coupled to the first end of the reference current source; the reference current source, a second end thereof is grounded, and the reference The first end of the reference current source is suitable for outputting the reference current; the first end of the third MOS tube inputs the power supply voltage, the second end of the third MOS tube is coupled to the second input end of the first operational amplifier, and the control end of the third MOS tube is coupled to the control end of the second MOS tube; the third MOS tube and the second MOS tube form a current mirror; the first end of the fourth MOS tube is coupled to the second end of the third MOS tube, the second end of the fourth MOS tube is coupled to the first end of the tenth MOS tube, and the control end of the fourth MOS tube is coupled to the output end of the first operational amplifier; the second end of the tenth MOS tube is coupled to the current adjustment unit, and the control end of the tenth MOS tube is grounded.
[0008] Optionally, the current adjustment unit comprises: a third current branch, a current adjustment branch and a second operational amplifier, wherein: the third current branch is suitable for replicating the reference current; the current adjustment branch comprises M sub-branches; and is suitable for selecting N sub-branches to be turned on from the M sub-branches based on the received first control signal, and the current on each turned-on sub-branch is associated with the copied current; the target current is the sum of the currents on all turned-on sub-branches; N is a positive integer and N≤M; and the second operational amplifier has a first input terminal coupled to the current adjustment branch, a second input terminal coupled to the third current branch, and an output terminal coupled to its second input terminal and the current replication branch.
[0009] Optionally, the third current branch includes a fifth MOS tube and a sixth MOS tube; in the current adjustment branch, any sub-branch includes a seventh MOS tube, an eighth MOS tube, and a first switch unit; wherein: the fifth MOS tube, a first end of which inputs a power supply voltage, a second end of which is coupled to the first end of the sixth MOS tube, and a control end of which is coupled to the control end of the third MOS tube; the sixth MOS tube, a second end of which is coupled to the second input end of the second operational amplifier, and a control end of which is coupled to the control end of the fourth MOS tube; the seventh MOS tube, a first end of which inputs the power supply voltage, a second end of which is coupled to the first end of the eighth MOS tube, and a control end of which is coupled to the control end of the fifth MOS tube; the eighth MOS tube, a second end of which is coupled to the first end of the first switch unit, and a control end of which is coupled to the control end of the sixth MOS tube; the first switch unit, a second end of which outputs the target current, and a control end of which inputs a first control signal; the first control signal is used to control N first switch units to be turned on, and the target current is the sum of the currents of the N sub-branches that are turned on.
[0010] By setting the second operational amplifier, the current on any sub-branch that is turned on in the current adjustment branch is equal to the copy current. When the number of sub-branches that are turned on in the current adjustment branch is N, the target current is N times the copy current. When the copy current is not affected by changes in the working state of the load circuit, the target current output by the current adjustment branch will not be affected by changes in the working state of the load circuit.
[0011] Optionally, the first switch unit includes a first PMOS tube; a first end of which is coupled to the second end of the eighth MOS tube of the corresponding sub-branch, a second end of which is coupled to the first input end of the second operational amplifier, and a control end of which inputs the first control signal.
[0012] Optionally, the current adjustment unit also includes: a second switch unit and a third switch unit, wherein: the second switch unit, a first end of which is coupled to the output end of the current adjustment branch, a second end of which is coupled to the first input end of the second operational amplifier, and a control end of which inputs a second control signal; the third switch unit, a first end of which is coupled to the second end of the sixth MOS tube, a second end of which is coupled to the first input end of the second operational amplifier, and a control end of which inputs a third control signal; the second control signal is inverted with the third control signal.
[0013] By setting the second switch unit and the third switch unit, in a scenario where there is no target current output, the target current can be stopped from being output, thereby reducing the power consumption of the power supply circuit.
[0014] Optionally, the second switch unit is a transmission gate or an NMOS tube; the third switch unit is a transmission gate or an NMOS tube.
[0015] Optionally, the second switch unit includes a second NMOS tube, and the third switch unit includes a third NMOS tube, wherein: the second NMOS tube has a drain coupled to the output end of the current adjustment branch, a source coupled to the first input end of the second operational amplifier, and a gate inputting the second control signal; the third NMOS tube has a drain coupled to the second end of the sixth MOS tube, a source coupled to the first input end of the second operational amplifier, and a gate inputting the third control signal.
[0016] Optionally, the second switch unit includes a first transmission gate, and the third switch unit includes a second transmission gate, wherein: the first transmission gate, whose first end is coupled to the output end of the current adjustment branch, and whose second end is coupled to the first input end of the second operational amplifier, whose positive control signal end inputs the second control signal, and whose negative control signal end inputs the third control signal; the second transmission gate, whose first end is coupled to the second end of the sixth MOS tube, and whose second end is coupled to the first input end of the second operational amplifier, whose positive control end inputs the third control signal, and whose negative control end inputs the second control signal.
[0017] Optionally, the third current branch further includes: a first resistor, a first end of which is coupled to the second end of the sixth MOS tube, and a second end of which is grounded.
[0018] By providing the first resistor in the third current branch, it is possible to prevent the sixth MOS tube from being short-circuited with the ground, thereby preventing the power supply circuit from being unable to operate normally.
[0019] Optionally, the bias voltage generating unit includes: a ninth MOS tube and a bias current source, wherein: the ninth MOS tube has a first end that inputs a power supply voltage, a second end that is coupled to the first end of the bias current source, and a control end that is coupled to the output end of the bias voltage generating unit; the bias current source has a first end that is coupled to the output end of the bias voltage generating unit, and a second end that is grounded.
[0020] In a second aspect, the present invention further provides an electronic device, comprising any one of the power supply circuits described above. BRIEF DESCRIPTION OF THE DRAWINGS
[0021] Figure 1 is a schematic structural diagram of a power supply circuit in an embodiment of the present invention;
[0022] Figure 2 It is a structural schematic diagram of another power supply circuit in an embodiment of the present invention. DETAILED DESCRIPTION
[0023] As described in the background art, when the working state of the load circuit changes, it will affect the target current output by the current mirror.
[0024] In an embodiment of the present invention, a first operational amplifier is provided between the current generating branch and the current copying branch. Through the first operational amplifier, the base reference current on the current generating branch is equal to the copy current on the current copying branch. Thus, the current copying branch can accurately copy the base reference current, and the copy current will not change with the working state of the load circuit. Furthermore, the target current obtained by adjusting the copy current is less affected by the change of the working state of the load circuit.
[0025] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.
[0026] Reference Figure 1 The present invention provides a power supply circuit, including: a bias voltage generating unit 101, a reference current copying unit 102 and a current adjusting unit 103.
[0027] In the embodiment of the present invention, the bias voltage generating unit 101 is adapted to generate a bias voltage and output the generated bias voltage to the reference current replicating unit 102 .
[0028] The reference current replication unit 102 may include: a current generating branch, a current replication branch and a first operational amplifier OP1, wherein: the current generating branch is suitable for generating a reference reference current; the current replication branch is suitable for replicating the reference reference current to obtain a replication current; the first input terminal of the first operational amplifier OP1 is coupled to the current generating branch, the second input terminal of the first operational amplifier OP1 is coupled to the current replication branch, and the output terminal of the first operational amplifier OP1 is coupled to the current adjustment unit 103.
[0029] The current adjustment unit 103 can adjust the copied current to obtain a target current.
[0030] The current adjustment unit 103 adjusts the copied current, which may refer to: copying the copied current, or amplifying the copied current by a certain multiple, or scaling the copied current by a certain multiple, etc.
[0031] The specific structure of the power supply circuit is described in detail below.
[0032] In the specific implementation, Figure 1 As shown, the bias voltage generating unit 101 may include a ninth MOS transistor M9 and a bias current source IBIAS, wherein:
[0033] A first end of the ninth MOS transistor M9 inputs the power supply voltage VDD, a second end of the ninth MOS transistor M9 is coupled to a first end of the bias current source IBIAS, and a control end of the ninth MOS transistor M9 is coupled to an output end of the bias voltage generating unit 101;
[0034] In a specific implementation, the bias current source IBIAS can be generated by a current generation module or copied by a current mirror circuit. The bias current source can provide a bias current for the reference current copy unit 102 .
[0035] A first terminal of the bias current source IBIAS is coupled to the output terminal of the bias voltage generating unit 101 , and a second terminal of the bias current source IBIAS is grounded.
[0036] In some embodiments, the ninth MOS transistor M9 may be a PMOS transistor, the first end of which is the source of the PMOS transistor, the second end of which is the drain of the PMOS transistor, and the control end of which is the gate of the PMOS transistor.
[0037] In the embodiment of the present invention, the reference current copy unit 102 may include: a first MOS transistor M1, a second MOS transistor M2, a third MOS transistor M3, a fourth MOS transistor M4, a tenth MOS transistor M10, a reference current source IREF, and a first operational amplifier OP1. The first MOS transistor M1, the second MOS transistor M2, and the reference current source constitute a current generation branch, and the third MOS transistor M3, the fourth MOS transistor M4, and the tenth MOS transistor M10 constitute a current copy branch.
[0038] In a specific implementation, the first end of the first MOS transistor M1 is coupled to the second end of the second MOS transistor M2, the second end of the first MOS transistor M1 is coupled to the first end of the reference current source IREF, and the control end of the first MOS transistor M1 inputs a bias voltage.
[0039] The first end of the second MOS transistor M2 is input with the power supply voltage VDD, the second end of the second MOS transistor M2 is coupled with the first input end of the first operational amplifier OP1, the control end of the second MOS transistor M2 is coupled with the control end of the third MOS transistor M3 and the first end of the reference current source IREF; the first input end of the first operational amplifier OP1 is the “+” input end, and the second input end of the first operational amplifier OP1 is the “-” input end.
[0040] The second end of the reference current source IREF is grounded, and the first end of the reference current source IREF outputs a reference current I REF .
[0041] The first end of the third MOS tube M3 is input with the power supply voltage VDD, the second end of the third MOS tube M3 is coupled with the second input end of the first operational amplifier OP1, and the control end of the third MOS tube M3 is coupled with the control end of the second MOS tube M2. Thus, the third MOS tube M3 and the second MOS tube M2 form a current mirror, so that the reference current generated by the current generation branch can be copied to obtain a copy current.
[0042] A first end of the fourth MOS tube M4 is coupled to the second end of the third MOS tube M3 , a second end of the fourth MOS tube M4 is coupled to the first end of the tenth MOS tube M10 , and a control end of the fourth MOS tube M4 is coupled to the output end of the first operational amplifier OP1 .
[0043] A first end of the tenth MOS tube M10 is coupled to the second end of the fourth MOS tube M4 , a second end of the tenth MOS tube M10 is coupled to the current adjustment unit 103 , and a control end of the tenth MOS tube M10 is directly grounded.
[0044] In a specific implementation, the reference current source IREF can be generated based on a bandgap reference current source, thereby ensuring that the output reference current I REF It does not change with temperature, further improving the accuracy of the final output target current.
[0045] In some embodiments, the first MOS transistor M1 , the second MOS transistor M2 , the third MOS transistor M3 , the fourth MOS transistor M4 and the tenth MOS transistor M10 may all be PMOS transistors.
[0046] In the embodiment of the present invention, for a PMOS tube, the first end of the PMOS tube is the source of the PMOS tube, the second end of the PMOS tube is the drain of the PMOS tube, and the control end of the PMOS tube is the gate of the PMOS tube. For example, when the first MOS tube M1 is a PMOS tube, the first end of the first MOS tube M1 is the source, the second end of the first MOS tube M1 is the drain, and the gate of the first MOS tube M1 is the control end.
[0047] In the embodiment of the present invention, the current adjustment unit 103 may include a third current branch, a current adjustment branch and a second operational amplifier OP2, wherein:
[0048] The third current branch may be adapted to replicate the replica current;
[0049] The current adjustment branch includes M sub-branches. Based on the first control signal TRIM, N sub-branches can be selected from the current adjustment branch to be turned on. The current on each turned-on sub-branch is associated with the replica current. The target current IOUT is the sum of the currents on all turned-on sub-branches. N is a positive integer and N≤M.
[0050] The first input terminal of the second operational amplifier OP2 may be coupled to the current adjustment branch, the second input terminal of the second operational amplifier OP2 may be coupled to the third current branch, and the output terminal of the second operational amplifier OP2 may be coupled to the second input terminal of the second operational amplifier OP2 and the output terminal of the first operational amplifier OP1. The first input terminal of the second operational amplifier OP2 may be a "+" input terminal, and the second input terminal of the second operational amplifier OP2 may be a "-" input terminal.
[0051] In a specific implementation, the third current branch may include a fifth MOS transistor M5 and a sixth MOS transistor M6, wherein:
[0052] A first end of the fifth MOS tube M5 inputs a power supply voltage VDD, a second end of the fifth MOS tube M5 is coupled to a first end of the sixth MOS tube M6, and a control end of the fifth MOS tube M5 inputs a copy current;
[0053] The second end of the sixth MOS transistor M6 is coupled to the second input end of the second operational amplifier OP2 through the switch unit, and the control end of the sixth MOS transistor M6 is coupled to the output end of the first operational amplifier OP1.
[0054] In a specific implementation, the current adjustment branch may include M sub-branches, each of which may include a seventh MOS transistor M7, an eighth MOS transistor M8, and a first switch unit SW1. For any sub-branch, wherein:
[0055] The first end of the seventh MOS tube M7 inputs the power supply voltage VDD, the second end of the seventh MOS tube M7 is coupled to the first end of the eighth MOS tube M8, and the control end of the seventh MOS tube M7 is coupled to the control end of the fifth MOS tube M5; thus, the seventh MOS tube M7 can form a current mirror with the fifth MOS tube M5;
[0056] The second end of the eighth MOS tube M8 is coupled to the first end of the first switch unit SW1, and the control end of the eighth MOS tube M8 is coupled to the control end of the sixth MOS tube M6;
[0057] The control terminal of the first switch unit SW1 inputs the first control signal TRIM, and the second terminal of the first switch unit SW1 outputs the target current; through the first control signal TRIM, N first switch units can be selected to be turned on, that is, N sub-branches can be selected to be turned on. In this scenario, the target current is the sum of the currents of the N turned-on sub-branches.
[0058] In some embodiments, the current on each conducting sub-branch may be equal to the replica current. Thus, the target current is N times the replica current. For example, two conducting sub-branches are selected through the first control signal, and then the target current is 2 times the replica current.
[0059] In some other embodiments, a seventh MOS transistor M7 having a different width-to-length ratio from the fifth MOS transistor M5 may also be selected, so as to obtain target currents with more different values.
[0060] The fifth MOS transistor M5 , the sixth MOS transistor M6 , the seventh MOS transistor M7 and the eighth MOS transistor M8 mentioned above can all be PMOS transistors.
[0061] In a specific implementation, the current adjustment unit 103 may further include a first resistor R, a first end of the first resistor R may be coupled to a second end of the sixth MOS transistor M6 , and a second end of the first resistor R is grounded. The first resistor R may be used to limit power consumption.
[0062] That is, the fifth MOS transistor M5, the sixth MOS transistor M6 and the first resistor R form a series path. By providing the first resistor R, the sixth MOS transistor M6 can be prevented from being short-circuited with the ground, thereby preventing the power circuit from being unable to work normally.
[0063] In some embodiments, the current adjustment unit 103 may further include a second switch unit SW2 and a third switch unit SW3, wherein:
[0064] A second switch unit SW2, a first end of which is coupled to the output end of the current adjustment branch, a second end of which is coupled to the first input end of the second operational amplifier OP2, and a control end of which inputs a second control signal;
[0065] The third switch unit SW3 has a first end coupled to the second end of the sixth MOS tube M6, a second end coupled to the second input end of the second operational amplifier OP2, and a control end inputting a third control signal; the second control signal is inverted with the third control signal.
[0066] In a specific implementation, the second switch unit SW2 and the third switch unit SW3 are not turned on at the same time. When the second switch unit SW2 is turned on, the third switch unit SW3 is turned off; when the second switch unit SW2 is turned off, the third switch unit SW3 is turned on.
[0067] In some embodiments, the second switch unit SW2 includes a first transmission gate, and the third switch unit SW3 includes a second transmission gate, wherein:
[0068] A first transmission gate, a first end of which is coupled to the output end of the current adjustment branch, a second end of which is coupled to the first input end of the second operational amplifier OP2, a positive phase control signal end of which is input with the second control signal S, and a negative phase control signal end of which is input with the third control signal;
[0069] The second transmission gate has a first end coupled to the second end of the sixth MOS transistor M6, a second end coupled to the first input end of the second operational amplifier OP2, a positive control end inputting the third control signal SN, and a negative control end inputting the second control signal S; the second control signal S is inverted with the third control signal SN.
[0070] In some other embodiments, the second switch unit SW2 includes a second NMOS transistor, and the third switch unit SW3 includes a third NMOS transistor. Figure 2 , a structural schematic diagram of another power supply circuit in an embodiment of the present invention is given.
[0071] and Figure 1 The difference is, Figure 2 In the embodiment, the second switch unit is the second NMOS transistor MN2, and the third switch unit is the third NMOS transistor MN3.
[0072] A second NMOS transistor MN2, a drain of which is coupled to the output end of the current adjustment branch, a source of which is coupled to the first input end of the second operational amplifier OP2, and a gate of which is input with the second control signal S;
[0073] The third NMOS transistor MN3 has a drain coupled to the second end of the sixth MOS transistor M6, a source coupled to the first input end of the second operational amplifier OP2, and a gate inputting the third control signal SN; the second control signal S is inverted with the third control signal SN.
[0074] In some embodiments, an inverter may be provided to invert the second control signal to obtain a third control signal.
[0075] The specific working process and working principle of the power supply circuit provided in the embodiment of the present invention are described below.
[0076] In the embodiment of the present invention, in any MOS tube among the first MOS tube M1 to the eighth MOS tube M8, the first end of the MOS tube is the source of the MOS tube, the second end of the MOS tube is the drain of the MOS tube, and the control end of the MOS tube is the gate of the MOS tube.
[0077] The bias voltage generating unit 101 generates and outputs a bias voltage, and the bias voltage is input to the gate of the first MOS transistor M1. By outputting a suitable bias voltage, the first MOS transistor M1 can be operated in a saturation region.
[0078] The second MOS transistor M2 and the third MOS transistor M3 in the reference current copy unit 102 form a current mirror. The current generation branch where the second MOS transistor M2 is located generates a reference current, and correspondingly, the current copy branch where the third MOS transistor M3 is located copies the reference current. Therefore, the current flowing through the third MOS transistor M3 is the copied reference current (hereinafter referred to as the copy current).
[0079] The drain of the second MOS tube M2 is coupled to the first input terminal of the first operational amplifier OP1, and the drain of the third MOS tube M3 is coupled to the second input terminal of the first operational amplifier OP1. When the first operational amplifier OP1 is working, the voltage at point A is equal to the voltage at point B, so that the gate-source voltage of the second MOS tube M2 is equal to the gate-source voltage of the third MOS tube M3, and the source-drain voltage of the second MOS tube M2 is equal to the source-drain voltage of the third MOS tube M3. As a result, the third MOS tube M3 can accurately copy the reference current.
[0080] The output end of the first operational amplifier OP1 can dynamically adjust the gate voltage of the fourth MOS transistor M4 according to the working state change of the load circuit, and can control the gate voltages of the sixth MOS transistor M6 and the eighth MOS transistor M8 in the current adjustment unit 103 to make them work in the saturation region.
[0081] When there is no load circuit, the current adjustment unit 103 can be in a dormant state. In this scenario, the second control signal S is at a low level, and the second switch unit SW2 is in a disconnected state; the third control signal SN is at a high level, and the third switch unit SW3 is in a conductive state. The voltage at the second end of the fourth MOS tube M4 is equal to the voltage at the second end of the sixth MOS tube M6, and the current on the current replication branch where the fourth MOS tube M4 is located is equal to the current on the branch where the sixth MOS tube M6 is located. The current on the sixth MOS tube M6 is output to the ground via the first resistor.
[0082] When there is a load circuit, the current adjustment unit 103 is in working state. In this scenario, the second control signal S is at a high level, and the second switch unit SW2 is in working state; the third control signal SN is at a low level, and the third switch unit SW3 is in a disconnected state. The current on the current copy branch where the fourth MOS tube M4 is located is equal to the current on a single sub-branch in the current adjustment branch. The target current is the sum of the sub-branch currents selected to be turned on by the first control signal.
[0083] Therefore, by setting the corresponding first control signal and selecting the total number N of sub-branches to be turned on, different target currents can be obtained.
[0084] When the load circuit changes, due to the existence of the second operational amplifier OP2, the voltages at point G and point E are equal, and the output of the first operational amplifier OP1 synchronously adjusts the control terminal voltages of the fourth MOS tube M4 and the eighth MOS tube M8, so the gate-source voltage of the fourth MOS tube M4 is equal to the gate-source voltage of the eighth MOS tube M8, and finally the gate-source voltages of the third MOS tube M3 and the seventh MOS tube M7 are equal, thereby ensuring the accuracy of current replication.
[0085] In a specific implementation, the load circuit is a load module (or referred to as a load unit, load module, load device, etc.) coupled to the current adjustment unit 103 , and the target current of the current adjustment unit 103 is the input current of the load circuit.
[0086] In the embodiment of the present invention, when the first switch unit SW1 is a first PMOS tube, the size of the tenth MOS tube is the same as that of the first PMOS tube, thereby ensuring that the drain-source voltage of the tenth MOS tube is equal to the drain-source voltage of the first PMOS tube.
[0087] In the embodiment of the present invention, the first operational amplifier OP1 may use a high-gain amplifier to reduce the offset between the first input terminal and the second input terminal of the first operational amplifier OP1, thereby ensuring that the drain-source voltages of the second MOS transistor M2 and the third MOS transistor M3 are precisely equal.
[0088] In the embodiment of the present invention, the second operational amplifier OP2 may use a buffer so that the voltage of the second input terminal and the output terminal of the second operational amplifier OP2 are precisely equal.
[0089] In the above embodiments of the present invention, for all NMOS transistors, their substrates can be connected to the ground terminal, and for all PMOS transistors, their substrates can be connected to the power supply voltage.
[0090] Specifically, the substrates of the second NMOS transistor MN2 and the third NMOS transistor MN3 may be connected to the ground. The first MOS transistor M1 to the tenth MOS transistor M10 may all be PMOS transistors, and their substrates may be connected to the power supply voltage.
[0091] The first operational amplifier may further include a power supply terminal and a ground terminal, and a power supply voltage may be input to the power supply terminal of the first operational amplifier. The second operational amplifier may further include a power supply terminal and a ground terminal, and a power supply voltage may be input to the power supply terminal of the second operational amplifier.
[0092] The present invention also provides an electronic device, comprising the power supply circuit provided by any one of the above embodiments.
[0093] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.
Claims
1. A power supply circuit, characterized in that: include: A bias voltage generating unit, a reference current replicating unit and a current adjusting unit, wherein: The bias voltage generating unit is adapted to generate and output a bias voltage; The reference current replication unit is coupled to the bias voltage generation unit, and is suitable for generating a reference reference current and outputting a replicated current; the reference current replication unit includes: a current generation branch, a current replication branch and a first operational amplifier, wherein: the current generation branch is suitable for generating the reference reference current; the current replication branch is suitable for replicating the reference reference current to obtain the replicated current; the first operational amplifier has a first input terminal coupled to the current generation branch, a second input terminal coupled to the current replication branch, and an output terminal coupled to the current adjustment unit; the current adjustment unit is suitable for adjusting the replicated current to obtain a target current.
2. The power supply circuit according to claim 1, characterized in that The current generation branch includes a first MOS transistor, a second MOS transistor and a reference current source; the current replication branch includes a third MOS transistor, a fourth MOS transistor and a tenth MOS transistor; wherein: The first MOS transistor has a first end coupled to the second end of the second MOS transistor, a second end coupled to the first end of the reference current source, and a control end inputting the bias voltage; The second MOS tube has a first end inputting a power supply voltage, a second end coupled to the first input end of the first operational amplifier, and a control end coupled to the first end of the reference current source; The reference current source has a second terminal connected to ground, and a first terminal connected to the reference current source is adapted to output the base reference current; The third MOS transistor has a first end inputting the power supply voltage, a second end coupled to the second input end of the first operational amplifier, and a control end coupled to the control end of the second MOS transistor; the third MOS transistor and the second MOS transistor form a current mirror; The fourth MOS transistor has a first end coupled to the second end of the third MOS transistor, a second end coupled to the first end of the tenth MOS transistor, and a control end coupled to the output end of the first operational amplifier; The second end of the tenth MOS tube is coupled to the current adjustment unit, and the control end of the tenth MOS tube is grounded.
3. The power supply circuit according to claim 2, characterized in that: The current adjustment unit includes: a third current branch, a current adjustment branch and a second operational amplifier, wherein: The third current branch is suitable for replicating the replica current; The current adjustment branch comprises M sub-branches; adapted to select N sub-branches from the M sub-branches to be turned on based on the received first control signal, the current on each turned-on sub-branch being associated with the replica current; the target current is the sum of the currents on all turned-on sub-branches; N is a positive integer and N≤M; The second operational amplifier has a first input terminal coupled to the current adjustment branch, a second input terminal coupled to the third current branch, and an output terminal coupled to its second input terminal and the current replication branch.
4. The power supply circuit according to claim 3, characterized in that: The third current branch includes a fifth MOS transistor and a sixth MOS transistor; any sub-branch includes a seventh MOS transistor, an eighth MOS transistor and a first switch unit; wherein: The fifth MOS tube has a first end inputting a power supply voltage, a second end coupled to the first end of the sixth MOS tube, and a control end coupled to the control end of the third MOS tube; The sixth MOS transistor has a second end coupled to the second input end of the second operational amplifier, and a control end coupled to the control end of the fourth MOS transistor; The seventh MOS tube has a first end inputting the power supply voltage, a second end coupled to the first end of the eighth MOS tube, and a control end coupled to the control end of the fifth MOS tube; The eighth MOS tube has a second end coupled to the first end of the first switch unit, and a control end coupled to the control end of the sixth MOS tube; The first switch unit has a second terminal that outputs the target current and a control terminal that inputs a first control signal; The first control signal is used to control the N first switch units to be turned on, and the target current is the sum of the currents of the N turned-on sub-branches.
5. The power supply circuit according to claim 4, characterized in that: The first switch unit includes a first PMOS tube; the first end of the first PMOS tube is coupled to the second end of the eighth MOS tube of the corresponding sub-branch; the second end of the first PMOS tube is coupled to the first input end of the second operational amplifier; and the control end of the first control signal is input.
6. The power supply circuit according to claim 4, characterized in that: The current adjustment unit further includes: a second switch unit and a third switch unit, wherein: The second switch unit has a first end coupled to the output end of the current adjustment branch, a second end coupled to the first input end of the second operational amplifier, and a control end inputting a second control signal; The third switch unit has a first end coupled to the second end of the sixth MOS tube, a second end coupled to the first input end of the second operational amplifier, and a control end inputting a third control signal; the second control signal is inverted with the third control signal.
7. The power supply circuit according to claim 6, characterized in that: The second switch unit is a transmission gate or an NMOS tube; the third switch unit is a transmission gate or an NMOS tube.
8. The power supply circuit according to any one of claims 4 to 7, characterized in that: The third current branch further includes: a first resistor, a first end of which is coupled to the second end of the sixth MOS tube, and a second end of which is grounded.
9. The power supply circuit according to claim 1, characterized in that: The bias voltage generating unit comprises: a ninth MOS tube and a bias current source, wherein: The ninth MOS transistor has a first end inputting a power supply voltage, a second end coupled to the first end of the bias current source, and a control end coupled to the output end of the bias voltage generating unit; The bias current source has a first end coupled to the output end of the bias voltage generating unit and a second end grounded.
10. An electronic device, characterized in that: The invention comprises a power supply circuit as claimed in any one of claims 1 to 9.