Fractional order circuit with editable order

Abstract

The invention discloses an order-editable fractional order circuit. The order-editable fractional order circuit comprises a signal processing circuit module, a bias current output circuit module and a current sampling circuit module, the signal processing circuit module is used for receiving an external input signal; the bias current output circuit module is used for outputting a bias current signal; the current sampling circuit module is used for converting the bias current signal into a voltage signal; the bias current output circuit module is also used for adjusting the voltage signal based on the core MCU to obtain a PWM voltage signal; the bias current output circuit module is also used for converting the PWM voltage signal into an adjusted bias current signal and adjusting a bias current value input into the signal processing circuit module so as to adjust the order of the fractional order circuit to be a target order; and the signal processing circuit module is used for processing an external input signal to obtain an output signal, so that the core MCU controls and outputs a PWM voltage signal, and the order of the fractional order circuit is editable.

Description

Technical Field

[0001] The present application relates to the technical field of signal processing, and in particular to an order-editable fractional-order circuit. Background Art

[0002] In the field of signal processing, frequency response curves are usually used to analyze signal quality. The various circuits used in the analysis process are generally classified as integer-order circuits. However, most studies have shown that fractional-order circuits can better reflect circuit characteristics than integer-order circuits. If fractional-order circuits are used in the analysis process, the required signals can be processed more accurately.

[0003] However, fractional-order circuits with independent structures do not exist in reality, and fractional-order circuits are generally approximated by circuit combinations.

[0004] When changing the order of the fractional order, the current fractional order circuit needs to change the overall circuit structure, and the order change is relatively complicated. Therefore, there is an urgent need for a fractional order circuit that can quickly adjust the order of the fractional order and reduce the complexity of the process of changing the order of the fractional order. Summary of the invention

[0005] The present application provides a fractional-order circuit with editable order, which can quickly adjust the fractional order of the fractional-order circuit and reduce the complexity of the process of changing the fractional order.

[0006] In a first aspect, the present application provides a programmable fractional-order circuit, comprising:

[0007] A signal processing circuit module, a bias current output circuit module and a current sampling circuit module; the signal processing circuit module includes N groups of programmable operational amplifier circuits, N is a positive integer, and the N groups of programmable operational amplifier circuits are connected in sequence; the bias current output circuit module includes a core MCU;

[0008] The current sampling circuit module is respectively connected to the core MCU of the bias current output circuit module and the output loop of the bias current output circuit module; the bias current output circuit module is connected to the signal processing circuit module;

[0009] The signal processing circuit module is used to receive an external input signal;

[0010] The bias current output circuit module is used to output a bias current signal;

[0011] The current sampling circuit module is used to collect the bias current signal and convert the bias current signal into a voltage signal;

[0012] The bias current output circuit module is further used to adjust the voltage signal based on the core MCU to obtain a pulse width modulation PWM voltage signal, and the PWM voltage signal is used to obtain an adjusted bias current signal;

[0013] The bias current output circuit module is further used to convert the PWM voltage signal into the adjusted bias current signal, and adjust the bias current value input to the N groups of programmable operational amplifier circuits according to the adjusted bias current signal, so as to adjust the order of the fractional-order circuit to the target order;

[0014] The signal processing circuit module is used to process the external input signal according to the N groups of programmable operational amplifiers after adjusting the input bias current value to obtain an output signal, and the output signal is a signal that satisfies the fractional order property.

[0015] Optionally, the core MCU includes an ADC sampling unit and a control algorithm unit;

[0016] The ADC sampling unit is used to sample the voltage signal to obtain a digital signal;

[0017] The control algorithm unit is used to calculate and obtain the PWM voltage signal according to the control algorithm and the digital signal.

[0018] Optionally, the bias current output circuit module 2 includes a voltage-current V / I converter; the core MCU is connected to the voltage-current V / I converter;

[0019] The V / I converter is used to receive the PWM voltage signal output by the current source and the core MCU, and output the adjusted bias current signal. The current source is obtained by performing resistance voltage division on a DC negative voltage power supply using a voltage dividing resistor.

[0020] Optionally, the V / I converter includes a V / I conversion chip, a voltage-dividing resistor and a current-inducing resistor, a modulation current input port and a voltage input port;

[0021] The modulation current input port is used to receive the current source;

[0022] The voltage input port is used to receive the PWM voltage signal;

[0023] The voltage-dividing resistor is used to divide the PWM voltage signal and input the divided PWM voltage signal into the V / I conversion chip;

[0024] The V / I conversion chip is used to receive the divided PWM voltage signal and convert the divided PWM voltage signal into a current signal;

[0025] The current induction resistor is used to adjust the current signal to obtain the adjusted bias current signal.

[0026] Optionally, the current sampling circuit module includes a current-voltage I / V converter; the I / V converter is connected to the core MCU;

[0027] The current sampling circuit module is specifically used to: call the I / V converter to convert the bias current signal into the voltage signal, and input the voltage signal into the core MCU.

[0028] Optionally, the I / V converter includes an I / V conversion chip, an external sampling resistor and a voltage output port;

[0029] The I / V conversion chip is used to convert the bias current signal into the voltage signal;

[0030] The external sampling resistor is used to control the voltage value of the voltage signal during the process of converting the bias current signal into the voltage signal.

[0031] Optionally, the target order is greater than or equal to 0.1 and the target order is less than or equal to 0.9, or the target order is greater than or equal to -0.9 and the target order is less than or equal to -0.1.

[0032] Optionally, the signal processing circuit module includes a first programmable operational amplifier circuit;

[0033] The first programmable operational amplifier circuit is used to receive the adjusted first bias current signal;

[0034] The first programmable operational amplifier circuit is further used to receive the external input signal, process the external input signal according to the adjusted first bias current signal, and obtain the output signal; the adjusted first bias current signal corresponds to the first programmable operational amplifier circuit;

[0035] The first programmable operational amplifier circuit is also used to output the output signal.

[0036] Optionally, the signal processing circuit module further includes: a second programmable operational amplifier circuit; an output port of the second programmable operational amplifier circuit is connected to an input port of the first programmable operational amplifier circuit;

[0037] The second programmable operational amplifier circuit is used to receive the external input signal, receive the adjusted second bias current signal, process the external input signal according to the first output sub-signal and the adjusted second bias current signal to obtain a second output sub-signal, and input the second output sub-signal into the first programmable operational amplifier circuit; the adjusted second bias current signal corresponds to the second programmable operational amplifier circuit;

[0038] The first programmable operational amplifier circuit is specifically used to: receive the second output sub-signal, and process the external input signal according to the second output sub-signal and the adjusted first bias current signal to obtain the output signal.

[0039] Optionally, the signal processing circuit module further includes: a third programmable operational amplifier circuit; an output port of the third programmable operational amplifier circuit is connected to an input port of the second programmable operational amplifier circuit;

[0040] The third programmable operational amplifier circuit is used to receive the external input signal, receive the adjusted third bias current signal, process the external input signal according to the adjusted third bias current signal, obtain a first output sub-signal, and input the first output sub-signal into the second programmable operational amplifier circuit; the adjusted third bias current signal corresponds to the third programmable operational amplifier circuit;

[0041] The second programmable operational amplifier circuit is specifically used to: receive the first output sub-signal, process the external input signal according to the first output sub-signal and the adjusted second bias current signal, and obtain the second output sub-signal.

[0042] It can be seen that this application has the following beneficial effects:

[0043] The present application provides an order-editable fractional-order circuit, comprising a signal processing circuit module, a bias current output circuit module and a current sampling circuit module; the signal processing circuit module comprises N groups of programmable operational amplifier circuits, N is a positive integer, and the N groups of programmable operational amplifier circuits are connected in sequence; the bias current output circuit module comprises a core MCU; the current sampling circuit module is respectively connected to the core MCU of the bias current output circuit module and the output loop of the bias current output circuit module; the bias current output circuit module is connected to the signal processing circuit module; the signal processing circuit module is used to receive an external input signal; the bias current output circuit module is used to output a bias current signal; the current sampling circuit module is used to collect bias current. The bias current output circuit module is further used to adjust the voltage signal based on the core MCU to obtain a PWM voltage signal, and the PWM voltage signal is used to obtain the adjusted bias current signal; the bias current output circuit module is further used to convert the PWM voltage signal into an adjusted bias current signal, and adjust the bias current value of the input N groups of programmable operational amplifier circuits according to the adjusted bias current signal to adjust the order of the fractional-order circuit to the target order; the signal processing circuit module is used to process the external input signal according to the N groups of programmable operational amplifiers after adjusting the input bias current value to obtain an output signal, and the output signal is a signal that satisfies the fractional-order property. In this way, the programmable order fractional-order circuit in the embodiment of the present application is divided into three parts, a signal processing circuit module, a bias current output circuit module and a current sampling circuit module. The current sampling circuit module collects the bias current signal and outputs the voltage signal. The bias current output circuit module uses the core MCU to adjust the voltage signal to obtain a PWM voltage signal, obtains the adjusted bias current according to the PWM voltage signal, and adjusts the bias current value of the input N groups of programmable operational amplifier circuits according to the adjusted bias current signal to adjust the order of the fractional-order circuit to the target order. In this way, the external input signal is processed by the signal processing circuit module that adjusts the bias current after the input to obtain the final output signal, so that the output signal is a signal that satisfies the fractional-order property. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present application. For ordinary technicians in this field, other drawings can also be obtained based on these drawings.

[0045] Figure 1 A schematic diagram of the overall structure of an order-editable fractional-order circuit provided in an embodiment of the present application;

[0046] Figure 2A schematic diagram of the specific structure of an order-editable fractional-order circuit provided in an embodiment of the present application;

[0047] Figure 3 A schematic diagram of the structure of the current sampling circuit module 3 provided in an embodiment of the present application;

[0048] Figure 4 A schematic diagram of structure 1 in the signal processing circuit module 1 provided in an embodiment of the present application;

[0049] Figure 5 A schematic diagram of structure 2 in the signal processing circuit module 1 provided in an embodiment of the present application;

[0050] Figure 6 A schematic diagram of the circuit structure of a V / I converter 20 provided in an embodiment of the present application;

[0051] Figure 7 A schematic diagram of the structure of the core MCU 21 provided in the embodiment of the present application;

[0052] Figure 8 A schematic diagram of the circuit structure of an I / V converter provided in an embodiment of the present application;

[0053] Fig. 9 A schematic diagram of the specific structure of a programmable operational amplifier device provided in an embodiment of the present application;

[0054] Fig.10 A schematic diagram of the specific structure of the V / I converter 20 provided in an embodiment of the present application;

[0055] Fig.11 The frequency response curve of the fractional-order circuit provided in the embodiment of the present application when the order is 0.5;

[0056] Fig.12 This is a frequency response curve of the fractional-order circuit provided in an embodiment of the present application when the order is -0.5. DETAILED DESCRIPTION

[0057] The multiple involved in the embodiments of the present application means greater than or equal to two. It should be noted that in the description of the embodiments of the present application, the words "first", "second", etc. are only used for the purpose of distinguishing the description, and cannot be understood as indicating or implying relative importance, nor can they be understood as indicating or implying an order.

[0058] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the embodiments of the present application are further described in detail below in conjunction with the accompanying drawings and specific implementation methods. It is understood that the specific embodiments described herein are only used to explain the present application and are not intended to limit the present application. In addition, it should be noted that, for ease of description, only the parts related to the present application are shown in the accompanying drawings, not all structures.

[0059] The applicant has found that in the prior art, when changing the fractional order of the current fractional-order circuit, it is necessary to change the overall circuit structure. The order change is relatively complex, and the method of changing the circuit combination from low segment to high segment is not clear enough, making the overall change very difficult.

[0060] The applicant noticed that the fractional-order circuit can be realized by an operational amplifier circuit. When selecting such an operational amplifier circuit, attention is paid to operational amplifier circuits with programmable characteristics. A circuit structure suitable for programmable operational amplifier parameters can be designed to achieve the adjustment of the order of the fractional-order circuit without changing the circuit structure, thus solving the problem of the difficulty in adjusting the order of the fractional-order circuit in the prior art. At the same time, the operational amplifier circuit combination is a splicing type, which can be simply combined from a low-segment combination to a high-segment combination, thereby improving the problem of poor approximation accuracy under a low number of segments.

[0061] Based on this, an embodiment of the present application provides an order-editable fractional-order circuit, including a signal processing circuit module, a bias current output circuit module and a current sampling circuit module; the signal processing circuit module includes N groups of programmable operational amplifier circuits, N is a positive integer, and the N groups of programmable operational amplifier circuits are connected in sequence; the bias current output circuit module includes a core MCU; the current sampling circuit module is respectively connected to the core MCU of the bias current output circuit module and the output loop of the bias current output circuit module; the bias current output circuit module is connected to the signal processing circuit module; the signal processing circuit module is used to receive an external input signal; the bias current output circuit module is used to output a bias current signal; the current sampling circuit module is used to sample The bias current signal is collected and converted into a voltage signal; the bias current output circuit module is also used to adjust the voltage signal based on the core MCU to obtain a PWM voltage signal, and the PWM voltage signal is used to obtain the adjusted bias current signal; the bias current output circuit module is also used to convert the PWM voltage signal into an adjusted bias current signal, and adjust the bias current value of the input N groups of programmable operational amplifier circuits according to the adjusted bias current signal to adjust the order of the fractional order circuit to the target order; the signal processing circuit module is used to process the external input signal according to the N groups of programmable operational amplifiers after adjusting the input bias current value to obtain an output signal, and the output signal is a signal that meets the fractional order property.

[0062] Thus, the programmable fractional-order circuit in the embodiment of the present application is divided into three parts, a signal processing circuit module, a bias current output circuit module and a current sampling circuit module. The current sampling circuit module collects the bias current signal and outputs the voltage signal. The bias current output circuit module uses the core MCU to adjust the voltage signal to obtain a PWM voltage signal, obtains the adjusted bias current according to the PWM voltage signal, and adjusts the bias current value of the input N groups of programmable operational amplifier circuits according to the adjusted bias current signal, so as to adjust the order of the fractional-order circuit to the target order. In this way, the external input signal is processed by the signal processing circuit module after the bias current is adjusted to obtain the final output signal, so that the output signal is a signal that satisfies the fractional-order property. In addition, because the signal processing circuit module includes N groups of programmable operational amplifier circuits, by controlling the number of N, different numbers of programmable operational amplifier circuits can be spliced, without complex improvements to the circuit, and can be simply combined from a low segment to a high segment, or from a high segment to a low segment, because the approximate accuracy of the fractional-order circuit is approximately proportional to the number of segments, then by changing from a low segment combination to a high segment combination, the problem of poor approximate accuracy under a low segment number is improved to a certain extent.

[0063] To facilitate understanding of the specific implementation of the fractional-order circuit with order editing provided in the embodiment of the present application, an explanation will be given below with reference to the accompanying drawings.

[0064] See also Figure 1 , is a schematic diagram of the overall structure of a programmable fractional-order circuit provided in an embodiment of the present application and Figure 2 A specific structural diagram of an order-editable fractional-order circuit is provided; in an embodiment of the present application, the order-programmable fractional-order circuit includes a signal processing circuit module 1, a bias current output circuit module 2 and a current sampling circuit module 3; the signal processing circuit module 1 includes N groups of programmable operational amplifier circuits, where N is a positive integer; the bias current output circuit 2 includes a core MCU21;

[0065] The current sampling circuit module 3 is respectively connected to the core MCU 21 of the bias current output circuit module 2 and the output loop of the bias current output circuit module 2; the bias current output circuit module 2 is connected to the signal processing circuit module 1;

[0066] The signal processing circuit module 1 is used to receive an external input signal;

[0067] A bias current output circuit module 2, used for outputting a bias current signal;

[0068] The current sampling circuit module 3 is used to collect the bias current signal and convert the bias current signal into a voltage signal;

[0069] The bias current output circuit module 2 is also used to adjust the voltage signal based on the core MCU 21 to obtain a pulse width modulation PWM voltage signal, and the PWM voltage signal is used to obtain an adjusted bias current signal;

[0070] The bias current output circuit module 2 is also used to convert the PWM voltage signal into an adjusted bias current signal, and adjust the bias current value input to the N groups of programmable operational amplifier circuits according to the adjusted bias current signal to adjust the order of the fractional-order circuit to the target order;

[0071] The signal processing circuit module 1 is used to process the external input signal according to the N groups of programmable operational amplifiers after adjusting the input bias current value to obtain the output signal, and the output signal is a signal satisfying the fractional order property.

[0072] In the embodiment of the present application, the programmable fractional-order circuit is divided into three parts, a signal processing circuit module 1, a bias current output circuit module 2 and a current sampling circuit module 3. The current sampling circuit module 3 collects and controls the bias current signal. The bias current output circuit module is used to adjust the bias current and output the adjusted bias current to the signal processing circuit module 1. In this way, the external input signal is processed by the signal processing circuit module 1 that inputs the adjusted bias current to obtain the final output signal, which is a signal that satisfies the fractional-order property.

[0073] It should be noted that in the embodiment of the present application, the signal processing circuit module 1 includes N groups of programmable operational amplifier circuits, where N is a positive integer. The applicant has found through experimental tests that when N=3, the order of the fractional-order circuit can be edited and good approximation accuracy can be guaranteed. Therefore, in order to facilitate the understanding of the technical solution provided by the present application, the following description is based on N=3, that is, the signal processing circuit module 1 includes 3 groups of programmable operational amplifier circuits.

[0074] Then, in a possible implementation, the signal processing circuit module 1 includes a first programmable operational amplifier circuit 10, a second programmable operational amplifier circuit 11 and a third programmable operational amplifier circuit 12, and the external input signal is simultaneously connected to the three groups of programmable operational amplifier circuits. It should be noted that the second programmable operational amplifier circuit 11 and the third programmable operational amplifier circuit 12 are exactly the same. For the convenience of the following description, the first programmable operational amplifier circuit 10 is uniformly divided into structure one, and the second programmable operational amplifier circuit 11 and the third programmable operational amplifier circuit 12 are uniformly divided into structure two.

[0075] In a possible implementation, the current sampling circuit module 3 includes a current-voltage I / V converter 31; the I / V converter 31 is connected to the core MCU 21;

[0076] The current sampling circuit module 3 is specifically used to call the I / V converter 31 to convert the bias current signal into a voltage signal, and input the voltage signal into the core MCU 21 .

[0077] See Figure 3 , Figure 3 It is a specific structural diagram of the current sampling circuit module 3. The bias current signal is connected to the I / V converter 31 to obtain the converted voltage signal, and the voltage signal is connected to the core MCU 21. The current sampling circuit module 3 and the bias current output circuit module 2 are interconnected.

[0078] See also Figure 4 , Figure 4 is a schematic diagram of structure 1 (first editable operational amplifier circuit 10) in the signal processing circuit module 1, see Figure 5 , Figure 5 It is a schematic diagram of structure 2 (the second editable operational amplifier circuit 11 or the third editable operational amplifier circuit 12 ) in the signal processing circuit module 1 .

[0079] First of all, Figure 4 The signal port identification is explained, Vi represents the input port of a group of programmable operational amplifier circuits, and the input port Vi includes a positive signal input port Vi+ and a negative signal input port Vi-; Iset represents the bias current input port, wherein the identification Iset is only used as a schematic symbol of the bias current circuit, and Vo represents the output port of a group of programmable operational amplifier circuits.

[0080] It should be noted that different programmable operational amplifier devices need to be configured with different bias current values ​​according to fractional-order circuit parameters, and each bias current needs to be configured separately and independently of each other.

[0081] It should be noted that Figure 4 Ports with the same symbolic name in the table are connected, such as Figure 4 The two places with the same symbol Vi- are connected to each other, and the two places with the same symbol Vi+ are connected to each other, that is, the positive signal input port Vi+ of the programmable operational amplifier device 101 is connected to the positive signal input port Vi+ of the programmable operational amplifier device 103, and the negative signal input port Vi- of the programmable operational amplifier device 101 is connected to the negative signal input port Vi- of the programmable operational amplifier device 103. The programmable operational amplifier device 104 is used as an output port to output a signal, and the output port output signal is connected to the negative signal port of the programmable operational amplifier device 100 and the common output of the programmable operational amplifier device 102 and the programmable operational amplifier device 103.

[0082] It should be noted that the first editable operational amplifier circuit 10 includes 5 programmable operational amplifier devices and 1 non-polar capacitor element 105, the 5 programmable operational amplifier devices are programmable operational amplifier device 100, programmable operational amplifier device 101, programmable operational amplifier device 102, programmable operational amplifier device 103, and programmable operational amplifier device 104, each programmable operational amplifier device is configured with a configuration current signal Iset, wherein the programmable operational amplifier device 101 and the programmable operational amplifier device 103 are external input ports of the signal processing circuit module 1, and can be connected to differential signals; the first end of the capacitor Cu is respectively connected to the output port of the programmable operational amplifier device 100 and the output port of the programmable operational amplifier device 101, and are jointly connected to the positive signal port of the programmable operational amplifier device 102, the second end of the capacitor Cu is connected to the ground plane, the negative signal port of the programmable operational amplifier device 102 is connected to the ground plane, the output port of the programmable operational amplifier device 102 and the output port of the programmable operational amplifier device 103 are jointly connected to the negative signal port of the programmable operational amplifier device 104, and the positive signal port of the programmable operational amplifier device 104 is connected to the ground plane.

[0083] Similarly, yes Figure 5 The signal port identification is explained, the programmable operational amplifier device 107 and the programmable operational amplifier device 110 are external signal input ports. It should be noted that the same symbol name Vi- and Vi+ indicate that the ports are connected together, and Vo is the output port of the overall signal. Figure 4 The output port Vo is included, and Figure 5 The ports with the Vo symbol are connected to each other.

[0084] It should be noted that Figure 4 The symbol name of the positive signal port of the programmable operational amplifier device 100 in the structure diagram is Vu, which is Figure 5 contains a port with the same symbol name Vu, which means that the two ports are connected together. In other words, Figure 5 The Vu port in the configuration shown is connected to Figure 4 At the Vu port in the structure shown, the two Vy ports are connected to each other, and the common output port of the programmable operational amplifier device 109 and the programmable operational amplifier device 110 and the capacitor element 111 is connected to the positive signal input port of the programmable operational amplifier device 106 .

[0085] Figure 5 The identifier Iset in Figure 4 Similarly, Iset represents the bias current input port. Different programmable operational amplifier devices need to be configured with different bias current values ​​according to the fractional-order circuit parameters. Each bias current needs to be configured separately and independently of each other.

[0086] It should be noted that (Structure 2) the second editable operational amplifier circuit 11 includes two programmable operational amplifier devices and one non-polar capacitor element 108 , and the two programmable operational amplifier devices are programmable operational amplifier device 106 and programmable operational amplifier device 107 .

[0087] It should be noted that (Structure 2) the third editable operational amplifier circuit 12 includes two programmable operational amplifier devices and one non-polar capacitor element 111 , and the two programmable operational amplifier devices are programmable operational amplifier device 109 and programmable operational amplifier device 110 .

[0088] Figure 5 The two places with the same sign Vi- are connected to each other, and the two places with the same sign Vi+ are connected to each other. That is to say, the positive signal input port Vi+ of the programmable operational amplifier device 107 is connected to the positive signal input port Vi+ of the programmable operational amplifier device 110, and the negative signal input port Vi- of the programmable operational amplifier device 107 is connected to the negative signal input port Vi- of the programmable operational amplifier device 110.

[0089] The first end of the capacitor Cy is connected to the output port of the programmable operational amplifier device 106 and the output port of the programmable operational amplifier device 107, which serve together as the output port Vu of the second editable operational amplifier circuit 11, and the second end of the capacitor Cy is connected to the ground plane.

[0090] The first end of the capacitor Ct is connected to the output port of the programmable operational amplifier device 109 and the output port of the programmable operational amplifier device 110, which serve as the output port Vy of the third editable operational amplifier circuit 12, and the second end of the capacitor Ct is connected to the ground plane.

[0091] like Figure 5 As shown, port Vu is connected to Figure 4 When the same symbol is at the same position in the structure, the number of stages of the fractional-order circuit can be increased from 1 to 2, and the port Vy is connected to Figure 5 When the same symbol is at the structure, the number of stages of the fractional-order circuit is increased to 3, and circuits with higher stages can be connected to the Vt port. Where Vy, Vu, and Vt have the same port names, it means that the ports are connected together. The names are just for ease of understanding, and the same port names are electrically connected.

[0092] It should be noted that when the fractional-order circuit only contains Figure 4 When the structure shown in the figure is 1, the number of circuit segments is 1. For each additional structure 2, the number of circuit segments increases by one. Adding a structure 2 is done by splicing, that is, ports with the same name are connected together as shown in the port names Vy and Vu. If the number of circuit segments reaches the required requirement, only the last connected structure 2 circuit needs to be adjusted, and the positive signal port of the upper part of the programmable operational amplifier device is connected to the ground plane, such as Figure 5The positive signal port Vt of the programmable operational amplifier device 109 in the circuit is connected to the ground plane, so that the number of stages of the fractional-order circuit is 3. Figure 5 In the third editable operational amplifier circuit 12, the positive signal port Vy is connected to the ground plane, and the number of segments of the fractional-order circuit is 2.

[0093] That is to say, in the embodiment of the present application, if the number of circuit segments is 3, all three editable operational amplifier circuits need to exist, and Vt is grounded; if the number of circuit segments is 2, the third editable operational amplifier circuit 12 is removed and Vy is grounded; if the number of circuit segments is 1, the second editable operational amplifier circuit 11 and the third editable operational amplifier circuit 12 are removed, and Vu is grounded.

[0094] That is to say, if the number of circuit segments is 1, then, in one possible implementation, the signal processing circuit module includes a first programmable operational amplifier circuit 10; the first programmable operational amplifier circuit 10 is used to receive the adjusted first bias current signal; the first programmable operational amplifier circuit is also used to receive an external input signal, and processes the external input signal according to the adjusted first bias current signal to obtain an output signal; the adjusted first bias current signal corresponds to the first programmable operational amplifier circuit; the first programmable operational amplifier circuit is also used to output the output signal.

[0095] If the number of circuit segments is 2, then, in a possible implementation, the signal processing circuit module further includes: a second programmable operational amplifier circuit 11; an output port of the second programmable operational amplifier circuit 11 is connected to an input port of the first programmable operational amplifier circuit 10;

[0096] The second programmable operational amplifier circuit 11 is used to receive an external input signal, receive an adjusted second bias current signal, process the external input signal according to the first output sub-signal and the adjusted second bias current signal, obtain a second output sub-signal, and input the second output sub-signal into the first programmable operational amplifier circuit 10; the adjusted second bias current signal corresponds to the second programmable operational amplifier circuit 11;

[0097] The first programmable operational amplifier circuit 10 is specifically used to receive the second output sub-signal, and process the external input signal according to the second output sub-signal and the adjusted first bias current signal to obtain an output signal.

[0098] If the number of circuit segments is 3, then, in a possible implementation, the signal processing circuit module further includes: a third programmable operational amplifier circuit 12; the output port of the third programmable operational amplifier circuit is connected to the input port of the second programmable operational amplifier circuit 11;

[0099] The third programmable operational amplifier circuit 12 is used to receive an external input signal, receive an adjusted third bias current signal, process the external input signal according to the adjusted third bias current signal, obtain a first output sub-signal, and input the first output sub-signal into the second programmable operational amplifier circuit; the adjusted third bias current signal corresponds to the third programmable operational amplifier circuit 12;

[0100] The second programmable operational amplifier circuit 11 is specifically used to receive the first output sub-signal, and process the external input signal according to the first output sub-signal and the adjusted second bias current signal to obtain the second output sub-signal.

[0101] It should be noted that in the signal processing circuit module 1 provided in the embodiment of the present application, a complex circuit structure is not required, and the number of segments of the fractional-order circuit can be increased by a simple splicing method, thereby improving the approximation accuracy.

[0102] In a possible implementation, the bias current output circuit module 2 may include a voltage-current V / I converter 20; the core MCU 21 is connected to the voltage-current V / I converter 20;

[0103] The V / I converter 20 is used to receive the PWM voltage signal output by the current source and the core MCU, and output an adjusted bias current signal. The current source is obtained by performing resistor voltage division on a DC negative voltage power supply using a voltage dividing resistor.

[0104] See Figure 6 , is a schematic diagram of the circuit structure of the V / I converter 20 in the embodiment of the present application. The structure is constructed by a V / I conversion chip, and the programmable operational amplifier device 200 and the programmable operational amplifier device 205 are conversion chips. The resistor element 201 and the resistor element 206 are current induction resistors. The resistor element 202, the resistor element 203, the resistor element 207, and the resistor element 208 are voltage divider resistors.

[0105] It should be noted that the resistance value of resistor R0 can be 10Ω (Europe). The voltage divider resistor is used to divide the voltage and input the PMW voltage signal into the conversion chip.

[0106] for Figure 6 The voltage dividing resistor R1 and the voltage dividing resistor R2 are described, the voltage dividing resistor R1 includes a resistor element 203 and a resistor element 208, and the voltage dividing resistor R2 includes a resistor element 202 and a resistor element 207; the PWM voltage signal value is a unidirectional output signal.

[0107] The PWM voltage signal value is connected to the first end of the resistor element 203, the second end of the resistor element 203 is connected to the first end of the resistor element 202, and the second end of the resistor element 202 is connected to the ground plane. The second end of the resistor element 203 (i.e., the second end of the resistor element 203 and the first end of the resistor element 202 are connected) is connected to the positive signal input port of the conversion chip 200, and the negative signal input port of the conversion chip 200 is connected to the ground plane. The output port of the conversion chip 200 is connected to the first end of the resistor element 201, and the second end of the resistor element 201 is used as the bias current output port Iset.

[0108] The PWM voltage signal value is connected to the first end of the resistor element 208, the second end of the resistor element 208 is connected to the first end of the resistor element 207, the second end of the resistor element 207 is connected to the ground plane, the second end of the resistor element 208 (i.e., the connection between the second end of the resistor element 208 and the first end of the resistor element 207) is connected to the positive signal input port of the conversion chip 205, and the negative signal input port of the conversion chip 205 is connected to the ground plane. The output port of the conversion chip 205 is connected to the first end of the resistor element 206, and the second end of the resistor element 206 is used as the bias current output port Iset.

[0109] It should be noted that, according to the voltage value range of the PWM voltage signal, voltage dividing resistors R1 and R2 with different resistance values ​​are used for voltage dividing processing. Figure 6 The two conversion circuit structures are the same, and the resistance values ​​of the voltage-dividing resistors R1, R2 and the current-inducing resistor R0 can be adjusted according to different PWM voltage signals.

[0110] It should be noted that Figure 6 This is a schematic diagram of the structure of the V / I conversion circuit in the embodiment of the present application. In the programmable fractional-order circuit in the embodiment of the present application, the number of V / I conversion circuits needs to correspond to the number of I / V converters, that is, 8 circuits. The reason for 8 circuits is that the programmable operational amplifier device 102 has a fixed bias current value and does not need to use a V / I conversion circuit. The total number of programmable operational amplifier devices is 9, so it is 8 circuits. In order to improve the simplicity of the embodiment of the present application, Figure 6 The number of V / I conversion circuits is 2 for exemplary purposes only, but the number of I / V converters needs to be the same as the number of PWM channels, that is, 8.

[0111] Taking the PWM voltage signal value with a maximum output of 3.3V as an example, the voltage is divided. The resistance value of the voltage divider resistor R1 is 13.3KΩ (kilo-ohm), the resistance value of the voltage divider resistor R2 is 200Ω, and the resistance value of the current induction resistor R0 is 10Ω.

[0112] The negative signal input port of the V / I conversion chip in the V / I converter 20 is connected to the ground plane, and the positive signal port is used as the input. The maximum input voltage supported by this V / I conversion chip is 200mV. In addition, the output port of the V / I conversion chip is connected to the programmable operational amplifier device in the programmable operational amplifier circuit.

[0113] It should be noted that in the embodiment of the present application, the current source I0 is connected to the modulation current port of the conversion chip 200 and the conversion chip 205, wherein the larger the input value of the current source is, the larger the current value obtained by the V / I conversion under the same PWM voltage value is. Fig.10 In the specific structural diagram of the V / I converter 200, the current source circuit is described here. The current source circuit is obtained by dividing the negative voltage power supply, and includes a voltage dividing resistor and a DC negative voltage source.

[0114] Below Figure 6 The bias current output port Iset in the figure is explained. The conversion chip converts the PWM voltage value into a current value, and after passing through the load resistor R0, the output is the bias current Iset. The Iset current value is determined by the PWM voltage value and the current source I0. The larger the PWM voltage value, the larger the Iset value, and the larger the current source I0 value, the larger the Iset value.

[0115] It should be noted that Figure 6 The bias current output port Iset in is connected to Figure 5 The current in is input to the Iset port as the bias current of the programmable operational amplifier device.

[0116] The programmable characteristics in the embodiment of the present application are explained. The PWM voltage signal controls the conversion current value of the V / I conversion circuit. The current is used as the bias current input of the programmable operational amplifier device in the programmable operational amplifier circuit in the signal processing circuit module 1. By changing the bias current value, the overall circuit properties can be changed to meet the characteristics of the fractional-order circuit. At the same time, the PWM voltage signal voltage is programmed and regulated by the core MCU21. Therefore, the overall circuit is programmed and controlled by the core MCU21, and the programmable characteristics of the fractional-order circuit can be realized without completely changing the circuit structure.

[0117] In a possible implementation, the core MCU includes an ADC sampling unit 211 and a control algorithm unit 214;

[0118] ADC sampling unit 211, used to sample the voltage signal to obtain a digital signal;

[0119] The control algorithm unit 214 is used to calculate and obtain the PWM voltage signal 212 according to the control algorithm and the digital signal. The control algorithm unit 214 receives control from the MCU core 210 .

[0120] See Figure 7 , Figure 7 It is a structural diagram of the core MCU21, including the MCU core 210, the ADC sampling unit 211, the control algorithm unit 214, the PWM voltage signal 212, and the core power supply 3.3V power supply 213. The ADC sampling unit 211 is used to sample the voltage signal to obtain a digital signal; after the MCU processes the ADC sampling data, the control algorithm unit 214 obtains the PWM voltage signal, the PWM voltage signal is connected to the V / I conversion circuit, and the output bias current is used for the programmable operational amplifier device. The MCU core 210 is used to control the overall circuit to realize the programmable order of the fractional-order circuit. Among them, the core MCU21 includes 8-channel PWM, among which structure one uses 4-channel PWM, and structure two uses 4-channel PWM. The sampling accuracy of the ADC sampling unit can be selected as 16 bits.

[0121] In a possible implementation, the I / V converter 31 includes an I / V conversion chip, an external sampling resistor, and a voltage output port;

[0122] The I / V conversion chip is used to convert the bias current signal into a voltage signal;

[0123] The external sampling resistor is used to control the voltage value of the voltage signal during the process of converting the bias current signal into the voltage signal.

[0124] See Figure 8 , Figure 8 It is a schematic diagram of the circuit structure of an I / V converter, including an I / V converter 311, a power supply 310 of the converter, an external sampling resistor element 312, a sampling current positive input port 313, a sampling current reverse input port 314, and a converted voltage output port 315. The I / V converter 311 selects a current-to-voltage chip, which converts the bias current signal to obtain a voltage signal.

[0125] The ports in the I / V conversion circuit can be reserved for better access to the bias current output loop. The ports include a sampling current positive input port 313, a reverse input port 314, and a converted voltage output port 315. The I / V conversion chip is powered by a positive 12V power supply.

[0126] The direction when the sampling current flows into the port is the positive direction. Figure 8 The sampling current positive input port IN+ is connected to the bias current output port, and the sampling current reverse input port IN- is connected to the port that needs to provide bias current. The converted voltage output port is connected to the ADC port of the MCU, and the maximum voltage value after conversion is 3000mV.

[0127] The sampling resistor R0 in the I / V conversion circuit is explained. The resistance specification selects the sampling resistor type. The larger the value of the resistor R0, the larger the voltage output value after conversion, and the lower the accuracy of the current sampling circuit module. According to the maximum voltage output value of 3000mV, the resistor R0 can select a high-precision sampling resistor below 100 ohms.

[0128] See also Fig. 9 , is a schematic diagram of the specific structure of a programmable operational amplifier device in an embodiment of the present application, the programmable operational amplifier device includes a programmable operational amplifier 100a, an internal current matching resistor 100b, a positive power supply 100c and a negative power supply 100d. The programmable operational amplifier device is powered by a dual power supply, and the positive and negative power supplies are +12V and -12V. -IN represents the negative signal input port of the programmable operational amplifier device, +IN represents the positive signal input port of the programmable operational amplifier device, Iset represents the bias current input port, and Iout represents the signal output port of the programmable operational amplifier device.

[0129] The Iout signal output port is connected to the matching resistor R0, and the resistance of the matching resistor R0 is 10 ohms. It is used to limit the voltage value of the output signal to avoid the situation where the programmable operational amplifier device is damaged due to a large voltage when connected to the input port of other programmable operational amplifier devices.

[0130] Fig. 9 The programmable operational amplifier device 100 is taken as an example. It should be noted that in Figure 4 and Figure 5 The specific structure of the programmable operational amplifier device shown in the figure can be found in Fig. 9 The specific structural diagram of the programmable operational amplifier device shown in the figure includes a programmable operational amplifier device 100, a programmable operational amplifier device 101, a programmable operational amplifier device 102, a programmable operational amplifier device 103, a programmable operational amplifier device 104, a programmable operational amplifier device 106, a programmable operational amplifier device 107, a programmable operational amplifier device 109 and a programmable operational amplifier device 110. Figure 4 and Figure 5 Connect according to the specific structural schematic diagram shown.

[0131] In a possible implementation, the V / I converter 20 includes a V / I conversion chip, a voltage-dividing resistor and a current-inducing resistor, a modulation current input port, and a voltage input port;

[0132] A modulation current input port for receiving a current source;

[0133] Voltage input port, used to receive PWM voltage signal;

[0134] The voltage-dividing resistor is used to divide the PWM voltage signal and input the divided PWM voltage signal into the V / I conversion chip;

[0135] A V / I conversion chip is used to receive the divided PWM voltage signal and convert the divided PWM voltage signal into a current signal;

[0136] The current induction resistor is used to adjust the current signal to obtain an adjusted bias current signal.

[0137] See Fig.10 , is a schematic diagram of the specific structure of the V / I converter in the embodiment of the present application, including a V / I conversion chip 200a, a positive power supply 200b and a negative power supply 200c, a negative voltage power supply 200d in the current source circuit, and a voltage dividing resistor 200e, a voltage dividing resistor 200f and a voltage dividing resistor 200g of the negative voltage power supply.

[0138] It should be noted that the V / I conversion chip uses dual power supplies, the positive power supply is +12V, the negative power supply is -12V, -IN represents the negative signal input port of the V / I conversion chip, +IN represents the positive signal input port of the conversion chip, I0 represents the input port of the modulation current source, and Iout represents the signal output port of the V / I conversion chip. The output port Iout of the V / I conversion chip is connected to the bias current Iset port of the programmable operational amplifier device. The current source I0 is obtained by dividing the negative voltage power supply. Fig.10 The resistors R1, R2 and R3 are voltage divider resistors, and the negative voltage power supply is -12 V. The first end of the resistor element 200e is connected to the negative voltage power supply, and the second end is connected to the common connection point of the element 200f and the element 200g. The other end of the resistor element 200f is connected to the ground plane, and the other end of the resistor element 200g is used as the output of the current source and connected to the I0 port.

[0139] for Fig.10 The specific structure of the V / I converter is shown in FIG. 200. Figure 6 The specific structures are Fig.10 As shown, the invention comprises a programmable operational amplifier device 200, a programmable operational amplifier device 205 and a V / I conversion circuit with the same structure, each V / I converter is Figure 6 Make the connections as shown.

[0140] It should be noted that Figure 2 The structure shown builds a programmable-order fractional-order circuit. The number of segments of the implemented fractional-order circuit is 3. The overall circuit requires 9 programmable operational amplifiers, 8 V / I conversion circuits, and 8 I / V conversion circuits. One of the programmable operational amplifiers uses a current source to provide bias current, and the other programmable operational amplifiers use the bias current output by the conversion circuit.

[0141] It should be noted that the signal processing circuit module is as follows Figure 4 and Figure 5The structure shown includes structure 1 and structure 2, and the V / I conversion circuit is as follows Figure 6 As shown in the structure, the output Iset bias current is connected to the Iset port of the programmable operational amplifier, and the I / V conversion circuit is as follows Figure 8 In the structure shown, the current sampling port is connected to the output loop of the bias current, the converted voltage output port is connected to the ADC port of the core MCU, the PWM voltage signal is adjusted by the control algorithm, the PWM voltage signal is connected to the V / I conversion chip, and the bias current value adjusted by the output algorithm is output. The change of the bias current value changes the circuit characteristics of the programmable operational amplifier, so the overall circuit is adjusted to meet the fractional-order circuit characteristics under the specified order. In this process, the circuit structure can remain completely unchanged and the order is programmable.

[0142] According to the derivation of fractional-order circuit theory, under the circuit scheme provided in the embodiment of the present application, the designed bias current value meets the parameter standard of the programmable operational amplifier, and the transfer function of the output signal and the input signal of the entire circuit meets the theoretical characteristics of the fractional-order circuit.

[0143] First, the fractional order is related to the frequency response characteristics of the circuit. From the perspective of the circuit transfer function, the circuit provided by the present application satisfies the following signal transmission formula (1), where g 109 It represents the transconductance parameter of the programmable operational amplifier device 109. The same is true for other programmable operational amplifier devices. n is a constant. The transconductance value of the programmable operational amplifier device under this circuit scheme = 10×bias current value. The bias current value is linearly related to the transconductance value.

[0144]

[0145] According to the characteristics of the operational amplifier, the transfer function of the circuit satisfies the following conditions, where the subscript numbers correspond to the schematic diagram Figure 4 , Figure 5 The programmable operational amplifier devices and capacitor element numbers in the structure diagram are Cu, Cy, and Ct, respectively, and n is a constant.

[0146]

[0147] The above formulas (2)-(4) are the transfer functions of the proposed circuit and the conditions that the circuit needs to meet. According to the theoretical transfer function characteristics of the fractional-order circuit, combined with the circuit structure and formula provided in the embodiment of the present application, the following fractional-order circuit implementation formula (5) can be obtained, where H(s) is the theoretical transfer function, S represents the complex frequency domain, S is obtained after Laplace transform in the time domain, and A 1 , A 2 , A 3 is a theoretical constant. When the fractional order is changed, A 1 , A 2 , A 3The values ​​of are different.

[0148]

[0149] g 109 =A 3 g 110 , g 101 =A 2 g 110 , g 107 =A 1 g 110 ; g 100 =g 107 , g 106 =g 101 , g 104 =g 110 , g 103 =g 109 .

[0150] In order to solve the problem that the order of the fractional-order circuit is difficult to adjust, the embodiment of the present application can adjust the order of the fractional-order circuit without changing the circuit structure; select a programmable operational amplifier to build a fractional-order circuit, design different bias current values ​​according to the values ​​of A1, A2, and A3 under different orders, and change the bias current value so that the circuit meets the fractional-order circuit characteristics under the specified order; use a V / I converter to convert the PWM voltage signal into a current signal, and the PWM voltage signal is adjusted by the core MCU, so the fractional order can be programmed and controlled by the core MCU.

[0151] In summary, the embodiment of the present application, under the provided circuit scheme, is derived according to the fractional-order circuit theory, and the designed bias current value meets the parameter standard of the programmable operational amplifier, and the transfer function of the output signal and the input signal of the entire circuit meets the theoretical characteristics of the fractional-order circuit.

[0152] It should be noted that the programmable order fractional-order circuit solution provided by the present invention is explained under the frequency response, the phase value = order × 90, the slope of the amplitude curve is the fractional order, the target order is greater than or equal to 0.1 and the target order is less than or equal to 0.9, or, the target order is greater than or equal to -0.9 and the target order is less than or equal to -0.1. That is to say, the order range is [-0.9, -0.1], [+0.1, +0.9].

[0153] Thus, the embodiment of the present application provides a programmable order fractional-order circuit, in which the number of combined segments of the circuit can be increased by splicing in the signal processing circuit module 1, and the higher the number of segments, the higher the approximate accuracy of the fractional-order circuit. That is to say, the fractional-order circuit provided in the embodiment of the present application can change the order of the fractional-order circuit by programming and regulating the MCU without changing the circuit structure at all;

[0154] Among them, the result of the fractional-order circuit under frequency response is as follows Fig.11 and Fig.12 shown. Fig.11 This is the frequency response curve of the fractional-order circuit when the order is 0.5, where the left ordinate represents the amplitude, the right ordinate represents the phase, and the phase value is 45, which satisfies the properties of the fractional-order circuit within a frequency range. Fig.12 This is the frequency response curve of the fractional-order circuit when the order is -0.5, and the phase value is -45, which satisfies the properties of the fractional-order circuit within a certain frequency range. The phase value has a small range of floating error. Fig.11 , Fig.12 The frequency response results of the three-stage fractional-order circuit are shown in the figure. The frequency range that satisfies the properties of the fractional-order circuit is 10 2 to 10 4 The slope of the amplitude curve in this frequency range is the order. By increasing the number of sections in the fractional-order circuit, this frequency range will become wider.

[0155] Combination Fig.11 as well as Fig.12 , which verifies the feasibility and accuracy of the circuit of the embodiment of the present application. The frequency response of the circuit can be adjusted according to the formulas and conditions provided in the embodiment of the present application to achieve fractional-order circuit properties of different orders.

[0156] In summary, an embodiment of the present application provides a fractional-order circuit with programmable order. An external signal is input into a signal processing circuit module, and the output signal obtained satisfies the properties of a fractional-order circuit. The signal processing circuit module includes a programmable operational amplifier device. The bias current output loop is connected to an I / V conversion circuit. The converted voltage port is connected to a core MCU. The core MCU controls the PWM voltage signal to access the V / I conversion circuit to obtain a bias current that is provided to N groups of programmable operational amplifier circuits. By changing the bias current value input to the N groups of programmable operational amplifier circuits, the circuit satisfies the fractional-order circuit characteristics of a specified order.

[0157] Compared with the complex circuits in the prior art, the circuit solution provided in the embodiment of the present application can change the order of the fractional-order circuit through the overall control of the core MCU without completely changing the circuit structure, thereby realizing the programmable order feature of the overall circuit.

[0158] In addition, the order-editable fractional-order circuit solution provided in the embodiment of the present application can increase the number of combined segments of the circuit by splicing. The higher the number of segments, the higher the approximation accuracy of the fractional-order circuit, that is, the larger the frequency range that satisfies the fractional-order properties.

[0159] In addition, the embodiments of the present application also provide a series of derivation formulas and conditions for fractional-order circuits. It can be seen that when the circuit parameters meet the conditions, a frequency response curve that satisfies the characteristics of the fractional-order circuit can be obtained. The results show that the circuit satisfies the fractional-order properties within a frequency range, the phase value has a small range of floating errors, and the slope of the amplitude curve within this frequency range is order. The overall circuit can better meet the characteristics of the fractional-order circuit.

[0160] Through the description of the above implementation methods, it can be known that those skilled in the art can clearly understand that all or part of the steps in the above-mentioned embodiment method can be implemented by means of software plus a general hardware platform. Based on such an understanding, the technical solution of the present application can be embodied in the form of a software product, which can be stored in a storage medium, such as a read-only memory (ROM) / RAM, a magnetic disk, an optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, a server, or a network communication device such as a router) to execute the methods described in each embodiment of the present application or some parts of the embodiments.

[0161] Each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment. The device embodiment described above is only schematic, in which the modules described as separate components may or may not be physically separated, and the components displayed as modules may or may not be physical modules, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules can be selected according to actual needs to achieve the goals of the scheme of this embodiment. Ordinary technicians in this field can understand and implement it without paying creative work.

[0162] The above is only a preferred embodiment of the present application and is not intended to limit the protection scope of the present application. It should be noted that, for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the present application, and these improvements and modifications should also be regarded as the protection scope of the present application.

Claims

1. A fractional-order circuit with programmable order, characterized in that: include: A signal processing circuit module, a bias current output circuit module and a current sampling circuit module; The signal processing circuit module includes N groups of programmable operational amplifier circuits, N is a positive integer, and the N groups of programmable operational amplifier circuits are connected in sequence; the bias current output circuit module includes a core MCU; The current sampling circuit module is respectively connected to the core MCU of the bias current output circuit module and the output loop of the bias current output circuit module; the bias current output circuit module is connected to the signal processing circuit module; The signal processing circuit module is used to receive an external input signal; The bias current output circuit module is used to output a bias current signal; The current sampling circuit module is used to collect the bias current signal and convert the bias current signal into a voltage signal; The bias current output circuit module is further used to adjust the voltage signal based on the core MCU to obtain a pulse width modulation PWM voltage signal, and the PWM voltage signal is used to obtain an adjusted bias current signal; The bias current output circuit module is further used to convert the PWM voltage signal into the adjusted bias current signal, and adjust the bias current value input to the N groups of programmable operational amplifier circuits according to the adjusted bias current signal, so as to adjust the order of the fractional-order circuit to the target order; The signal processing circuit module is used to process the external input signal according to the N groups of programmable operational amplifiers after adjusting the input bias current value to obtain an output signal, and the output signal is a signal that satisfies the fractional order property.

2. The circuit according to claim 1, characterized in that The core MCU includes an ADC sampling unit and a control algorithm unit; The ADC sampling unit is used to sample the voltage signal to obtain a digital signal; The control algorithm unit is used to calculate and obtain the PWM voltage signal according to the control algorithm and the digital signal.

3. The circuit according to claim 1, characterized in that The bias current output circuit module includes a voltage-to-current V / I converter; The core MCU is connected to the voltage-current V / I converter; The V / I converter is used to receive the PWM voltage signal output by the current source and the core MCU, and output the adjusted bias current signal. The current source is obtained by performing resistance voltage division on a DC negative voltage power supply using a voltage dividing resistor.

4. The circuit according to claim 3, characterized in that The V / I converter includes a V / I conversion chip, a voltage dividing resistor and a current induction resistor, a modulation current input port and a voltage input port; The modulation current input port is used to receive the current source; The voltage input port is used to receive the PWM voltage signal; The voltage-dividing resistor is used to divide the PWM voltage signal and input the divided PWM voltage signal into the V / I conversion chip; The V / I conversion chip is used to receive the divided PWM voltage signal and convert the divided PWM voltage signal into a current signal; The current induction resistor is used to adjust the current signal to obtain the adjusted bias current signal.

5. The circuit according to claim 1, characterized in that The current sampling circuit module includes a current-voltage I / V converter; the I / V converter is connected to the core MCU; The current sampling circuit module is specifically used to: call the I / V converter to convert the bias current signal into the voltage signal, and input the voltage signal into the core MCU.

6. The circuit according to claim 5, characterized in that The I / V converter includes an I / V conversion chip, an external sampling resistor and a voltage output port; The I / V conversion chip is used to convert the bias current signal into the voltage signal; The external sampling resistor is used to control the voltage value of the voltage signal during the process of converting the bias current signal into the voltage signal.

7. The circuit according to claim 1, characterized in that: The target order is greater than or equal to 0.1 and the target order is less than or equal to 0.9, or the target order is greater than or equal to -0.9 and the target order is less than or equal to -0.

1.

8. The circuit according to claim 1, characterized in that The signal processing circuit module includes a first programmable operational amplifier circuit; The first programmable operational amplifier circuit is used to receive the adjusted first bias current signal; The first programmable operational amplifier circuit is further used to receive the external input signal, process the external input signal according to the adjusted first bias current signal, and obtain the output signal; the adjusted first bias current signal corresponds to the first programmable operational amplifier circuit; The first programmable operational amplifier circuit is also used to output the output signal.

9. The circuit according to claim 8, characterized in that The signal processing circuit module further includes: a second programmable operational amplifier circuit; an output port of the second programmable operational amplifier circuit is connected to an input port of the first programmable operational amplifier circuit; The second programmable operational amplifier circuit is used to receive the external input signal, receive the adjusted second bias current signal, process the external input signal according to the first output sub-signal and the adjusted second bias current signal to obtain a second output sub-signal, and input the second output sub-signal into the first programmable operational amplifier circuit; the adjusted second bias current signal corresponds to the second programmable operational amplifier circuit; The first programmable operational amplifier circuit is specifically used to: receive the second output sub-signal, and process the external input signal according to the second output sub-signal and the adjusted first bias current signal to obtain the output signal.

10. The circuit according to claim 9, characterized in that The signal processing circuit module further includes: a third programmable operational amplifier circuit; the output port of the third programmable operational amplifier circuit is connected to the input port of the second programmable operational amplifier circuit; The third programmable operational amplifier circuit is used to receive the external input signal, receive the adjusted third bias current signal, process the external input signal according to the adjusted third bias current signal, obtain a first output sub-signal, and input the first output sub-signal into the second programmable operational amplifier circuit; the adjusted third bias current signal corresponds to the third programmable operational amplifier circuit; The second programmable operational amplifier circuit is specifically used to: receive the first output sub-signal, process the external input signal according to the first output sub-signal and the adjusted second bias current signal, and obtain the second output sub-signal.

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