An order-editable fractional circuit

Abstract

This application discloses an order-editable fractional-order circuit, including a signal processing circuit module, a bias current output circuit module, and a current sampling circuit module. The signal processing circuit module is used to receive external input signals. The bias current output circuit module is used to output bias current signals. The current sampling circuit module is used to convert the bias current signals into voltage signals. The bias current output circuit module is also used to adjust the voltage signals based on the core MCU to obtain PWM voltage signals. The bias current output circuit module is also used to convert the PWM voltage signals into adjusted bias current signals and adjust the bias current value of the input signal processing circuit module to adjust the order of the fractional-order circuit as the target order. The signal processing circuit module is used to process external input signals to obtain output signals. In this way, the core MCU controls and outputs the PWM voltage signals, realizing the order-editable fractional-order circuit.

Description

Technical Field

[0001] This application relates to the field of signal processing technology, and in particular to a fractional-order circuit with editable order. Background Technology

[0002] In the field of signal processing, frequency response curves are usually used to analyze signal quality. The various circuits used in the analysis process are generally classified as integer-order circuits. However, most studies have shown that fractional-order circuits can better reflect circuit characteristics than integer-order circuits. If fractional-order circuits are used in the analysis process, the required signal can be processed more accurately.

[0003] However, fractional-order circuits with independent structures do not exist in reality; fractional-order circuits are generally approximated by circuit combinations.

[0004] Current fractional-order circuits require changes to the overall circuit structure to alter the fractional order, making the order change quite complex. Therefore, there is an urgent need for a fractional-order circuit that can quickly adjust the fractional order, reducing the complexity of this process. Summary of the Invention

[0005] This application provides an order-editable fractional-order circuit, which can quickly adjust the fractional-order of the circuit and reduce the complexity of changing the fractional-order.

[0006] In a first aspect, this application provides an order-programmable fractional-order circuit, comprising:

[0007] The circuit includes a signal processing circuit module, a bias current output circuit module, and a current sampling circuit module; the signal processing circuit module includes N sets of programmable operational amplifier circuits, where N is a positive integer, and the N sets of programmable operational amplifier circuits are connected in sequence; the bias current output circuit module includes a core MCU;

[0008] The current sampling circuit module is connected to the core MCU of the bias current output circuit module and the output circuit of the bias current output circuit module, respectively; the bias current output circuit module is connected to the signal processing circuit module.

[0009] The signal processing circuit module is used to receive external input signals;

[0010] The bias current output circuit module is used to output a bias current signal;

[0011] The current sampling circuit module is used to acquire the bias current signal and convert the bias current signal into a voltage signal;

[0012] The bias current output circuit module is also used to adjust the voltage signal based on the core MCU to obtain a pulse width modulation (PWM) voltage signal, and the PWM voltage signal is used to obtain the adjusted bias current signal.

[0013] The bias current output circuit module is also used to convert the PWM voltage signal into the adjusted bias current signal, and adjust the bias current value of the N groups of programmable operational amplifier circuits according to the adjusted bias current signal, so as to adjust the order of the fractional-order circuit as the target order.

[0014] The signal processing circuit module is used to process the external input signal according to the N groups of programmable operational amplifiers after adjusting the input bias current value, and obtain an output signal, wherein the output signal is a signal that satisfies the fractional order property.

[0015] Optionally, the core MCU includes an ADC sampling unit and a control algorithm unit;

[0016] The ADC sampling unit is used to sample the voltage signal to obtain a digital signal;

[0017] The control algorithm unit is used to calculate the PWM voltage signal based on the control algorithm and the digital signal.

[0018] Optionally, the bias current output circuit module 2 includes a voltage-to-current (V / I) converter; the core MCU is connected to the voltage-to-current (V / I) converter.

[0019] The V / I converter is used to receive the current source and the PWM voltage signal output by the core MCU, and output the adjusted bias current signal. The current source is obtained by using a voltage divider resistor to divide the DC negative voltage power supply.

[0020] Optionally, the V / I converter includes a V / I conversion chip, voltage divider resistors and current-induced resistors, a modulated current input port and a voltage input port;

[0021] The modulated current input port is used to receive the current source;

[0022] The voltage input port is used to receive the PWM voltage signal;

[0023] The voltage divider resistor is used to divide the PWM voltage signal and input the divided PWM voltage signal into the V / I conversion chip;

[0024] The V / I conversion chip is used to receive the divided PWM voltage signal and convert the divided PWM voltage signal into a current signal.

[0025] The current-induced resistor is used to adjust the current signal to obtain the adjusted bias current signal.

[0026] Optionally, the current sampling circuit module includes a current-to-voltage (I / V) converter; the I / V converter is connected to the core MCU.

[0027] The current sampling circuit module is specifically used to: call the I / V converter to convert the bias current signal into the voltage signal, and input the voltage signal into the core MCU.

[0028] Optionally, the I / V converter includes an I / V conversion chip, an external sampling resistor, and a voltage output port;

[0029] The I / V conversion chip is used to convert the bias current signal into the voltage signal;

[0030] The external sampling resistor is used to measure the voltage value of the voltage signal during the process of controlling the conversion of the bias current signal into the voltage signal.

[0031] Optionally, the target order is greater than or equal to 0.1 and less than or equal to 0.9, or the target order is greater than or equal to -0.9 and less than or equal to -0.1.

[0032] Optionally, the signal processing circuit module includes a first programmable operational amplifier circuit;

[0033] The first programmable operational amplifier circuit is used to receive the adjusted first bias current signal;

[0034] The first programmable operational amplifier circuit is further configured to receive the external input signal, process the external input signal according to the adjusted first bias current signal, and obtain the output signal; the adjusted first bias current signal corresponds to the first programmable operational amplifier circuit.

[0035] The first programmable operational amplifier circuit is also used to output the output signal.

[0036] Optionally, the signal processing circuit module further includes: a second programmable operational amplifier circuit; the output port of the second programmable operational amplifier circuit is connected to the input port of the first programmable operational amplifier circuit;

[0037] The second programmable operational amplifier circuit is used to receive the external input signal, receive the adjusted second bias current signal, process the external input signal according to the first output sub-signal and the adjusted second bias current signal to obtain the second output sub-signal, and input the second output sub-signal into the first programmable operational amplifier circuit; the adjusted second bias current signal corresponds to the second programmable operational amplifier circuit.

[0038] The first programmable operational amplifier circuit is specifically used to: receive the second output sub-signal, process the external input signal according to the second output sub-signal and the adjusted first bias current signal, and obtain the output signal.

[0039] Optionally, the signal processing circuit module further includes: a third programmable operational amplifier circuit; the output port of the third programmable operational amplifier circuit is connected to the input port of the second programmable operational amplifier circuit;

[0040] The third programmable operational amplifier circuit is used to receive the external input signal, receive the adjusted third bias current signal, process the external input signal according to the adjusted third bias current signal to obtain a first output sub-signal, and input the first output sub-signal into the second programmable operational amplifier circuit; the adjusted third bias current signal corresponds to the third programmable operational amplifier circuit.

[0041] The second programmable operational amplifier circuit is specifically used to: receive the first output sub-signal, process the external input signal according to the first output sub-signal and the adjusted second bias current signal, and obtain the second output sub-signal.

[0042] Therefore, this application has the following beneficial effects:

[0043] This application provides an order-editable fractional-order circuit, including a signal processing circuit module, a bias current output circuit module, and a current sampling circuit module. The signal processing circuit module includes N programmable operational amplifier circuits, where N is a positive integer, connected sequentially. The bias current output circuit module includes a core MCU. The current sampling circuit module is connected to both the core MCU of the bias current output circuit module and its output circuit. The bias current output circuit module is connected to the signal processing circuit module. The signal processing circuit module receives external input signals. The bias current output circuit module outputs a bias current signal. The current sampling circuit module acquires the bias current signal. The current signal is converted into a voltage signal. The bias current output circuit module is also used to adjust the voltage signal based on the core MCU to obtain a PWM voltage signal, which is used to obtain the adjusted bias current signal. The bias current output circuit module is also used to convert the PWM voltage signal into an adjusted bias current signal, and adjust the bias current value of the input N programmable operational amplifier circuits according to the adjusted bias current signal, with the order of the fractional-order circuit as the target order. The signal processing circuit module is used to process the external input signal based on the adjusted input bias current value of the N programmable operational amplifiers to obtain an output signal, which is a signal that satisfies the fractional-order property. Thus, in this embodiment, the order-programmable fractional-order circuit is divided into three parts: a signal processing circuit module, a bias current output circuit module, and a current sampling circuit module. The current sampling circuit module acquires the bias current signal and outputs a voltage signal. The bias current output circuit module uses the core MCU to adjust the voltage signal to obtain a PWM voltage signal. Based on the PWM voltage signal, the adjusted bias current is obtained. Based on the adjusted bias current signal, the bias current values ​​of the N sets of programmable operational amplifier circuits are adjusted to adjust the order of the fractional-order circuit as the target order. In this way, the external input signal is processed by the signal processing circuit module after adjusting the input bias current to obtain the final output signal, so that the output signal satisfies the fractional-order property. Attached Figure Description

[0044] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments recorded in this application. For those skilled in the art, other drawings can be obtained based on these drawings.

[0045] Figure 1 A schematic diagram of the overall structure of a fractional-order circuit with editable order provided in an embodiment of this application;

[0046] Figure 2A schematic diagram of the specific structure of a fractional-order circuit with editable order provided in an embodiment of this application;

[0047] Figure 3 This is a schematic diagram of the structure of the current sampling circuit module 3 provided in the embodiments of this application;

[0048] Figure 4 This is a schematic diagram of structure one in the signal processing circuit module 1 provided in the embodiments of this application;

[0049] Figure 5 This is a schematic diagram of structure two in signal processing circuit module 1 provided in an embodiment of this application;

[0050] Figure 6 A schematic diagram of the circuit structure of the V / I converter 20 provided in the embodiments of this application;

[0051] Figure 7 This is a schematic diagram of the core MCU21 provided in the embodiments of this application;

[0052] Figure 8 A schematic diagram of the circuit structure of an I / V converter provided in an embodiment of this application;

[0053] Figure 9 This is a schematic diagram of the specific structure of the programmable operational amplifier device provided in the embodiments of this application;

[0054] Figure 10 This is a schematic diagram of the specific structure of the V / I converter 20 provided in the embodiments of this application;

[0055] Figure 11 The frequency response curve of the fractional-order circuit with an order of 0.5 provided in the embodiments of this application;

[0056] Figure 12 The frequency response curve of the fractional-order circuit provided in this application embodiment when the order is -0.5. Detailed Implementation

[0057] The "multiple" mentioned in the embodiments of this application refers to two or more. It should be noted that in the description of the embodiments of this application, terms such as "first" and "second" are used only for the purpose of distinguishing descriptions and should not be construed as indicating or implying relative importance, nor should they be construed as indicating or implying order.

[0058] To make the above-mentioned objectives, features, and advantages of this application more apparent and understandable, the embodiments of this application will be further described in detail below with reference to the accompanying drawings and specific implementation methods. It should be understood that the specific embodiments described herein are merely for explaining this application and are not intended to limit it. Furthermore, it should be noted that, for ease of description, only the parts relevant to this application are shown in the accompanying drawings, not the entire structure.

[0059] The applicant's research found that in the existing technology, the current fractional-order circuits require changes to the overall circuit structure when changing the fractional order, the order change is relatively complex, and the method of changing the circuit combination from the lower to the higher segment is not clear enough, making the overall change very difficult.

[0060] The applicant noted that the fractional-order circuit can be implemented by an operational amplifier circuit. When selecting such an operational amplifier circuit, attention is paid to operational amplifier circuits with programmable characteristics. A circuit structure suitable for programmable operational amplifier parameters can be designed to achieve the adjustment of the order of the fractional-order circuit without changing the circuit structure. This solves the problem that the order of the fractional-order circuit is not easy to adjust in the prior art. At the same time, the operational amplifier circuit is combined in a splicing type, which can easily go from low-segment combination to high-segment combination, thereby improving the problem of poor approximate accuracy at low segment numbers.

[0061] Based on this, this application provides an order-editable fractional-order circuit, including a signal processing circuit module, a bias current output circuit module, and a current sampling circuit module. The signal processing circuit module includes N programmable operational amplifier circuits, where N is a positive integer, and these N circuits are connected sequentially. The bias current output circuit module includes a core MCU. The current sampling circuit module is connected to both the core MCU of the bias current output circuit module and the output circuit of the bias current output circuit module. The bias current output circuit module is connected to the signal processing circuit module. The signal processing circuit module receives external input signals. The bias current output circuit module outputs a bias current signal. The current sampling circuit module samples the current. The circuit consists of several modules: a bias current signal and a bias current output circuit. The bias current output circuit module is used to adjust the voltage signal based on the core MCU to obtain a PWM voltage signal, which is then used to acquire the adjusted bias current signal. The bias current output circuit module is also used to convert the PWM voltage signal into an adjusted bias current signal, and adjust the bias current value of the N programmable operational amplifier circuits based on the adjusted bias current signal, with the target order being the order of the fractional-order circuit. The signal processing circuit module is used to process the external input signal based on the adjusted input bias current value of the N programmable operational amplifiers to obtain an output signal that satisfies the fractional-order property.

[0062] Thus, in this embodiment, the order-programmable fractional-order circuit is divided into three parts: a signal processing circuit module, a bias current output circuit module, and a current sampling circuit module. The current sampling circuit module acquires the bias current signal and outputs a voltage signal. The bias current output circuit module uses the core MCU to adjust the voltage signal to obtain a PWM voltage signal. Based on the PWM voltage signal, it obtains the adjusted bias current and adjusts the bias current values ​​of the N sets of programmable operational amplifier circuits according to the adjusted bias current signal, with the order of the fractional-order circuit as the target order. In this way, the external input signal is processed by the signal processing circuit module after adjusting the input bias current to obtain the final output signal, making the output signal a signal that satisfies the fractional-order property. In addition, because the signal processing circuit module includes N sets of programmable operational amplifier circuits, by controlling the number of N, different numbers of programmable operational amplifier circuits can be spliced ​​together without complex circuit modifications. It is easy to go from low-segment combinations to high-segment combinations, or from high-segment combinations to low-segment combinations. Since the approximate accuracy of the fractional-order circuit is approximately proportional to the number of segments, changing from low-segment combinations to high-segment combinations improves the problem of poor approximate accuracy at low segment numbers to a certain extent.

[0063] To facilitate understanding of the specific implementation of the fractional-order circuit for order editing provided in the embodiments of this application, the following description will be provided in conjunction with the accompanying drawings.

[0064] Please see Figure 1 This is a schematic diagram of the overall structure of a fractional-order programmable circuit provided in an embodiment of this application. Figure 2 A schematic diagram of the specific structure of a fractional-order circuit with programmable order is provided. In this embodiment, the fractional-order circuit with programmable order includes a signal processing circuit module 1, a bias current output circuit module 2, and a current sampling circuit module 3. The signal processing circuit module 1 includes N sets of programmable operational amplifier circuits, where N is a positive integer. The bias current output circuit 2 includes a core MCU 21.

[0065] The current sampling circuit module 3 is connected to the core MCU21 of the bias current output circuit module 2 and the output circuit of the bias current output circuit module 2, respectively; the bias current output circuit module 2 is connected to the signal processing circuit module 1;

[0066] Signal processing circuit module 1 is used to receive external input signals;

[0067] Bias current output circuit module 2 is used to output bias current signal;

[0068] The current sampling circuit module 3 is used to acquire the bias current signal and convert the bias current signal into a voltage signal;

[0069] The bias current output circuit module 2 is also used to adjust the voltage signal based on the core MCU 21 to obtain a pulse width modulation (PWM) voltage signal, which is used to obtain the adjusted bias current signal.

[0070] The bias current output circuit module 2 is also used to convert the PWM voltage signal into an adjusted bias current signal, and adjust the bias current value of the input N programmable operational amplifier circuits according to the adjusted bias current signal, with the order of the fractional-order circuit as the target order.

[0071] Signal processing circuit module 1 is used to process external input signals based on N programmable operational amplifiers after adjusting the input bias current value, and obtain output signals. The output signals are signals that satisfy the fractional order property.

[0072] In this embodiment, the order-programmable fractional-order circuit is divided into three parts: signal processing circuit module 1, bias current output circuit module 2, and current sampling circuit module 3. The current sampling circuit module 3 acquires the bias current signal and controls it. The bias current output circuit module is used to adjust the bias current and output the adjusted bias current to the signal processing circuit module 1. In this way, the external input signal is processed by the signal processing circuit module 1 with the input adjusted bias current to obtain the final output signal, which is a signal that satisfies the fractional-order property.

[0073] It should be noted that the signal processing circuit module 1 in this application embodiment includes N sets of programmable operational amplifier circuits, where N is a positive integer. The applicant found through experimental testing that when N=3, the order of the fractional-order circuit can be edited and good approximation accuracy can be guaranteed. Therefore, in order to facilitate understanding of the technical solution provided in this application, the following description uses N=3, that is, the signal processing circuit module 1 includes 3 sets of programmable operational amplifier circuits.

[0074] In one possible implementation, the signal processing circuit module 1 includes a first programmable operational amplifier circuit 10, a second programmable operational amplifier circuit 11, and a third programmable operational amplifier circuit 12, with external input signals simultaneously connected to all three programmable operational amplifier circuits. It should be noted that the second programmable operational amplifier circuit 11 and the third programmable operational amplifier circuit 12 are identical. For ease of description below, the first programmable operational amplifier circuit 10 will be uniformly classified as Structure 1, and the second programmable operational amplifier circuit 11 and the third programmable operational amplifier circuit 12 will be classified as Structure 2.

[0075] In one possible implementation, the current sampling circuit module 3 includes a current-to-voltage I / V converter 31; the I / V converter 31 is connected to the core MCU 21.

[0076] The current sampling circuit module 3 is specifically used to: call the I / V converter 31 to convert the bias current signal into a voltage signal, and input the voltage signal into the core MCU 21.

[0077] See details Figure 3 , Figure 3 This is a schematic diagram of the specific structure of the current sampling circuit module 3. The bias current signal is connected to the I / V converter 31 to obtain the converted voltage signal. The voltage signal is connected to the core MCU 21. The current sampling circuit module 3 and the bias current output circuit module 2 are interconnected.

[0078] See Figure 4 , Figure 4 This is a schematic diagram of structure one (first programmable operational amplifier circuit 10) in signal processing circuit module 1. See [link / reference] Figure 5 , Figure 5 This is a schematic diagram of structure two (second programmable operational amplifier circuit 11 or third programmable operational amplifier circuit 12) in signal processing circuit module 1.

[0079] First of all, Figure 4 The signal port identifiers are explained below. Vi represents a set of input ports of a programmable operational amplifier circuit. Input port Vi includes positive signal input port Vi+ and negative signal input port Vi-. Iset represents the bias current input port. The identifier Iset is only used as a schematic symbol for the bias current circuit. Vo represents a set of output ports of a programmable operational amplifier circuit.

[0080] It should be noted that different programmable operational amplifier devices require different bias current values ​​to be configured according to the fractional-order circuit parameters. Each bias current needs to be configured individually and independently.

[0081] It should be noted that, Figure 4 Ports with the same symbol name in the code indicate that they are connected, such as... Figure 4 The two identical symbols Vi- are interconnected, and the two identical symbols Vi+ are interconnected. That is, the positive signal input port Vi+ of programmable operational amplifier 101 is connected to the positive signal input port Vi+ of programmable operational amplifier 103, and the negative signal input port Vi- of programmable operational amplifier 101 is connected to the negative signal input port Vi- of programmable operational amplifier 103. Programmable operational amplifier 104 serves as the output port, and this output port is connected to the negative signal port of programmable operational amplifier 100 and the common output of programmable operational amplifiers 102 and 103.

[0082] It should be noted that the first programmable operational amplifier circuit 10 includes five programmable operational amplifier devices and one non-polarized capacitor element 105. The five programmable operational amplifier devices are programmable operational amplifier device 100, programmable operational amplifier device 101, programmable operational amplifier device 102, programmable operational amplifier device 103, and programmable operational amplifier device 104. Each programmable operational amplifier device is configured with a configuration current signal Iset. Among them, programmable operational amplifier device 101 and programmable operational amplifier device 103 are external input ports of signal processing circuit module 1 and can be connected to differential signals. The first end of capacitor Cu is connected to the output port of programmable operational amplifier device 100 and the output port of programmable operational amplifier device 101, respectively, and is connected to the positive signal port of programmable operational amplifier device 102. The second end of capacitor Cu is connected to the ground plane. The negative signal port of programmable operational amplifier device 102 is connected to the ground plane. The output port of programmable operational amplifier device 102 and the output port of programmable operational amplifier device 103 are connected to the negative signal port of programmable operational amplifier device 104. The positive signal port of programmable operational amplifier device 104 is connected to the ground plane.

[0083] Similarly, for Figure 5 The signal port identifiers are explained below. Programmable operational amplifier devices 107 and 110 are external signal input ports. It should be noted that the same symbols Vi- and Vi+ indicate that the ports are connected together, and Vo is the output port for the entire signal. Figure 4 Includes output port Vo, and Figure 5 The ports with the Vo symbol are interconnected.

[0084] It should be noted that, Figure 4 The positive signal port of the programmable operational amplifier device 100 in the block diagram shown is symbolically named Vu. Figure 5 It includes a port with the same symbolic name Vu, indicating that the two ports are connected together. That is to say, Figure 5 The Vu port in the structure shown is connected to Figure 4 At the Vu port in the structure shown, the two Vy ports are interconnected. The common output port of programmable operational amplifier 109 and programmable operational amplifier 110 and capacitor element 111 is connected to the positive signal input port of programmable operational amplifier 106.

[0085] Figure 5 The identifier Iset and Figure 4 Similarly, Iset represents the bias current input port. Different programmable operational amplifier devices need to be configured with different bias current values ​​according to the fractional-order circuit parameters. Each bias current needs to be configured separately and is independent of each other.

[0086] It should be noted that (Structure 2) the second programmable operational amplifier circuit 11 includes two programmable operational amplifier devices and one non-polarized capacitor element 108. The two programmable operational amplifier devices are programmable operational amplifier device 106 and programmable operational amplifier device 107.

[0087] It should be noted that (Structure 2) the third programmable operational amplifier circuit 12 includes two programmable operational amplifier devices and one non-polarized capacitor element 111. The two programmable operational amplifier devices are programmable operational amplifier device 109 and programmable operational amplifier device 110.

[0088] Figure 5 The two identical symbols Vi- are connected to each other, and the two identical symbols Vi+ are connected to each other. That is to say, the positive signal input port Vi+ of the programmable operational amplifier 107 is connected to the positive signal input port Vi+ of the programmable operational amplifier 110, and the negative signal input port Vi- of the programmable operational amplifier 107 is connected to the negative signal input port Vi- of the programmable operational amplifier 110.

[0089] The first end of capacitor Cy is connected to both the output port of programmable operational amplifier device 106 and the output port of programmable operational amplifier device 107, and together they serve as the output port Vu of the second programmable operational amplifier circuit 11. The second end of capacitor Cy is connected to the ground plane.

[0090] The first end of capacitor Ct is connected to both the output port of programmable operational amplifier device 109 and the output port of programmable operational amplifier device 110, together serving as the output port Vy of the third programmable operational amplifier circuit 12. The second end of capacitor Ct is connected to the ground plane.

[0091] like Figure 5 As shown, port Vu is connected to Figure 4 When the same symbol is used in the structure, the number of segments in a fractional-order circuit can be increased from 1 to 2, and port Vy is connected to Figure 5 When the same symbol appears in the structure, the number of segments in a fractional-order circuit increases to 3. Circuits with higher segment numbers can be connected to the Vt port. Where Vy, Vu, and Vt have the same port name, it indicates that the ports are connected together. The names are only for ease of understanding; ports with the same name are electrically connected.

[0092] It should be noted that when a fractional-order circuit only contains Figure 4 In the structure shown, the number of circuit segments is 1. Each additional structure two increases the segment count by one. Adding a structure two involves splicing ports together, as indicated by the port names Vy and Vu. If the required number of circuit segments is reached, only the last added structure two circuit needs adjustment. Connect the positive signal port of the upper programmable operational amplifier to the ground plane. Figure 5The positive signal port Vt of the programmable operational amplifier 109 is connected to the ground plane, making the number of segments in the fractional-order circuit three. If we remove... Figure 5 If the third programmable operational amplifier circuit 12 in the circuit is connected to the ground plane with the positive signal port Vy, then the number of segments in the fractional-order circuit is 2.

[0093] In other words, in this embodiment of the application, if the number of circuit segments is 3, all three editable operational amplifier circuits need to exist, and Vt is grounded; if the number of circuit segments is 2, the third editable operational amplifier circuit 12 is removed, and Vy is grounded; if the number of circuit segments is 1, the second editable operational amplifier circuit 11 and the third editable operational amplifier circuit 12 are removed, and Vu is grounded.

[0094] In other words, if the number of circuit segments is 1, then in one possible implementation, the signal processing circuit module includes a first programmable operational amplifier circuit 10; the first programmable operational amplifier circuit 10 is used to receive an adjusted first bias current signal; the first programmable operational amplifier circuit is also used to receive an external input signal, process the external input signal according to the adjusted first bias current signal, and obtain an output signal; the adjusted first bias current signal corresponds to the first programmable operational amplifier circuit; the first programmable operational amplifier circuit is also used to output an output signal.

[0095] If the number of circuit segments is 2, then in one possible implementation, the signal processing circuit module further includes: a second programmable operational amplifier circuit 11; the output port of the second programmable operational amplifier circuit 11 is connected to the input port of the first programmable operational amplifier circuit 10;

[0096] The second programmable operational amplifier circuit 11 is used to receive external input signals, receive the adjusted second bias current signal, process the external input signals according to the first output sub-signal and the adjusted second bias current signal to obtain the second output sub-signal, and input the second output sub-signal into the first programmable operational amplifier circuit 10; the adjusted second bias current signal corresponds to the second programmable operational amplifier circuit 11.

[0097] The first programmable operational amplifier circuit 10 is specifically used to: receive the second output sub-signal, process the external input signal according to the second output sub-signal and the adjusted first bias current signal, and obtain the output signal.

[0098] If the number of circuit segments is 3, then in one possible implementation, the signal processing circuit module further includes: a third programmable operational amplifier circuit 12; the output port of the third programmable operational amplifier circuit is connected to the input port of the second programmable operational amplifier circuit 11.

[0099] The third programmable operational amplifier circuit 12 is used to receive external input signals, receive the adjusted third bias current signal, process the external input signals according to the adjusted third bias current signal, obtain the first output sub-signal, and input the first output sub-signal into the second programmable operational amplifier circuit; the adjusted third bias current signal corresponds to the third programmable operational amplifier circuit 12.

[0100] The second programmable operational amplifier circuit 11 is specifically used to: receive the first output sub-signal, process the external input signal according to the first output sub-signal and the adjusted second bias current signal, and obtain the second output sub-signal.

[0101] It should be noted that in the signal processing circuit module 1 provided in the embodiments of this application, there is no need for a complex circuit structure. The number of segments of the fractional-order circuit can be increased by simple splicing, thereby improving the approximation accuracy.

[0102] In one possible implementation, the bias current output circuit module 2 may include a voltage-to-current (V / I) converter 20; the core MCU 21 is connected to the voltage-to-current (V / I) converter 20.

[0103] The V / I converter 20 is used to receive the PWM voltage signal output from the current source and the core MCU, and output the adjusted bias current signal. The current source is obtained by resistive voltage division of the DC negative voltage power supply using voltage divider resistors.

[0104] See details Figure 6 This is a schematic diagram of the circuit structure of the V / I converter 20 in this embodiment of the application. The structure is built using V / I conversion chips, specifically programmable operational amplifiers 200 and 205. Resistors 201 and 206 are current-induced resistors. Resistors 202, 203, 207, and 208 are voltage divider resistors.

[0105] It should be noted that the resistance of resistor R0 can be 10Ω (ohms). The function of the voltage divider resistor is to divide the PWM voltage signal before inputting it into the conversion chip.

[0106] for Figure 6 The voltage divider resistors R1 and R2 are described below. Voltage divider resistor R1 includes resistor element 203 and resistor element 208, and voltage divider resistor R2 includes resistor element 202 and resistor element 207. The PWM voltage signal value is a unidirectional output signal.

[0107] In this circuit, the PWM voltage signal is connected to the first terminal of resistor 203, the second terminal of resistor 203 is connected to the first terminal of resistor 202, and the second terminal of resistor 202 is connected to ground. The second terminal of resistor 203 (i.e., the point where the second terminal of resistor 203 connects to the first terminal of resistor 202) is connected to the positive signal input port of converter chip 200, and the negative signal input port of converter chip 200 is connected to ground. The output port of converter chip 200 is connected to the first terminal of resistor 201, and the second terminal of resistor 201 is used as the bias current output port Iset.

[0108] In this circuit, the PWM voltage signal is connected to the first terminal of resistor 208. The second terminal of resistor 208 is connected to the first terminal of resistor 207. The second terminal of resistor 207 is connected to ground. The second terminal of resistor 208 (i.e., the connection point between the second terminal of resistor 208 and the first terminal of resistor 207) is connected to the positive signal input port of converter chip 205. The negative signal input port of converter chip 205 is connected to ground. The output port of converter chip 205 is connected to the first terminal of resistor 206, and the second terminal of resistor 206 is used as the bias current output port Iset.

[0109] It should be noted that, depending on the voltage range of the PWM voltage signal, voltage divider resistors R1 and R2 with different resistance values ​​are used for voltage division. Figure 6 The two conversion circuits in the circuit have the same structure, and the resistance values ​​of the voltage divider resistor R1, voltage divider resistor R2 and current induction resistor R0 can be adjusted according to different PWM voltage signals.

[0110] It should be noted that, Figure 6 This is a schematic diagram of the V / I conversion circuit in an embodiment of this application. In the programmable fractional-order circuit of this embodiment, the number of V / I conversion circuits needs to correspond to the number of I / V converters, that is, 8 channels in total. The 8 channels are because the programmable operational amplifier device 102 has a fixed bias current value and does not require a V / I conversion circuit. There are a total of 9 programmable operational amplifier devices, hence 8 channels. To improve the simplicity of this embodiment, Figure 6 The example given is for illustrative purposes only, showing 2 V / I conversion circuits. The number of I / V converters should be the same as the number of PWM channels, which is 8.

[0111] The following example uses a PWM voltage signal with a maximum output of 3.3V. The voltage divider resistor R1 has a resistance of 13.3KΩ, the voltage divider resistor R2 has a resistance of 200Ω, and the current-induced resistor R0 has a resistance of 10Ω.

[0112] The negative signal input port of the V / I conversion chip in V / I converter 20 is connected to the ground plane, and the positive signal port is used as the input. This V / I conversion chip supports a maximum input voltage of 200mV. In addition, the output port of the V / I conversion chip is connected to the programmable operational amplifier device in the programmable operational amplifier circuit.

[0113] It should be noted that in this embodiment, the current source I0 is connected to the modulation current port of the conversion chip 200 and the conversion chip 205. The larger the input value of the current source, the larger the current value obtained from the V / I conversion under the same PWM voltage value. Figure 10 The schematic diagram of the V / I converter 200 illustrates the current source circuit, which is obtained by voltage division of a negative voltage power supply and includes a voltage divider resistor and a DC negative voltage source.

[0114] The following is about Figure 6 The bias current output port Iset is explained below. The conversion chip converts the PWM voltage value into a current value, which is then passed through the load resistor R0 and output as the bias current Iset. The value of the Iset current is determined by both the PWM voltage value and the current source I0. The larger the PWM voltage value, the larger the value of Iset; the larger the value of the current source I0, the larger the value of Iset.

[0115] It should be noted that, Figure 6 The bias current output port Iset is connected to Figure 5 The current input to the Iset port is used as the bias current for the programmable operational amplifier.

[0116] The programmable characteristics in the embodiments of this application are explained. The PWM voltage signal controls the conversion current value of the V / I conversion circuit. The current serves as the bias current input of the programmable operational amplifier device in the programmable operational amplifier circuit of the signal processing circuit module 1. By changing the bias current value, the overall circuit properties can be changed to meet the characteristics of a fractional-order circuit. At the same time, the PWM voltage signal is programmed and regulated by the core MCU21. Therefore, the overall circuit is programmed and controlled by the core MCU21, and the programmable characteristics of a fractional-order circuit can be realized without changing the circuit structure.

[0117] In one possible implementation, the core MCU includes an ADC sampling unit 211 and a control algorithm unit 214;

[0118] The ADC sampling unit 211 is used to sample the voltage signal to obtain a digital signal;

[0119] The control algorithm unit 214 is used to calculate and obtain the PWM voltage signal 212 according to the control algorithm and the digital signal. The control algorithm unit 214 receives the control of the MCU core 210.

[0120] See details Figure 7 , Figure 7 This is a schematic diagram of the core MCU21, including the MCU core 210, ADC sampling unit 211, control algorithm unit 214, PWM voltage signal 212, and core power supply 3.3V power supply 213. The ADC sampling unit 211 samples the voltage signal to obtain a digital signal. After the MCU processes the ADC sampling data, the control algorithm unit 214 obtains the PWM voltage signal. The PWM voltage signal is connected to the V / I conversion circuit, and the output bias current is used for the programmable operational amplifier. The MCU core 210 is used to control the overall circuit, realizing programmable order of the fractional-order circuit. The core MCU21 includes 8 PWM channels; structure one uses 4 PWM channels, and structure two uses 4 PWM channels. The sampling accuracy of the ADC sampling unit can be selected as 16 bits.

[0121] In one possible implementation, the I / V converter 31 includes an I / V conversion chip, an external sampling resistor, and a voltage output port;

[0122] The I / V conversion chip is used to convert the bias current signal into a voltage signal;

[0123] The external sampling resistor is used to measure the voltage value of the voltage signal during the process of converting the control bias current signal into a voltage signal.

[0124] See details Figure 8 , Figure 8 This is a schematic diagram of the circuit structure of an I / V converter, including an I / V converter 311, a power supply 310 for the converter, an external sampling resistor element 312, a sampling current positive input port 313, a sampling current inverting input port 314, and a converted voltage output port 315. The I / V converter 311 selects a current-to-voltage chip, which converts the bias current signal to obtain a voltage signal.

[0125] Ports in the I / V conversion circuit can be reserved for better connection to the bias current output loop. The ports include a sampling current positive input port 313, an inverting input port 314, and a converted voltage output port 315. The I / V conversion chip is powered by a positive 12V power supply.

[0126] Taking the direction of the sampling current flowing into the port as positive, Figure 8 The sampling current positive input port IN+ is connected to the bias current output port, and the sampling current reverse input port IN- is connected to the port that needs to provide bias current. The converted voltage output port is connected to the MCU's ADC port, and the maximum converted voltage value is 3000mV.

[0127] The sampling resistor R0 in the I / V conversion circuit is explained. The resistor specification should be selected as a sampling resistor. The larger the value of resistor R0, the larger the converted voltage output value. At the same time, the lower the accuracy of the current sampling circuit module. Based on the maximum voltage output value of 3000mV, resistor R0 can be selected as a high-precision sampling resistor of less than 100 ohms.

[0128] See Figure 9 This diagram illustrates the specific structure of a programmable operational amplifier (op-amp) device according to an embodiment of this application. The programmable op-amp device includes a programmable op-amp 100a, an internal current matching resistor 100b, a positive power supply 100c, and a negative power supply 100d. The programmable op-amp device uses dual power supplies, with positive and negative power supplies of +12V and -12V respectively. -IN represents the negative signal input port of the programmable op-amp device, +IN represents the positive signal input port of the programmable op-amp device, Iset represents the bias current input port, and Iout represents the signal output port of the programmable op-amp device.

[0129] The Iout signal output port is connected to a matching resistor R0 with a resistance of 10 ohms. This resistor limits the voltage value of the output signal to prevent damage to the programmable operational amplifier device caused by excessive voltage when connected to the input port of other programmable operational amplifier devices.

[0130] Figure 9 Taking the programmable operational amplifier device 100 as an example, it should be noted that... Figure 4 and Figure 5 The specific structure of the programmable operational amplifier devices shown can be found in [reference needed]. Figure 9 The schematic diagram of the specific structure of the programmable operational amplifier devices shown includes programmable operational amplifier devices 100, 101, 102, 103, 104, 106, 107, 109, and 110. Each of these programmable operational amplifier devices is... Figure 4 and Figure 5 Connect the components shown in the detailed structural diagram.

[0131] In one possible implementation, the V / I converter 20 includes a V / I conversion chip, voltage divider resistors and current-induced resistors, a modulated current input port and a voltage input port;

[0132] The modulation current input port is used to receive a current source;

[0133] Voltage input port, used to receive PWM voltage signals;

[0134] The voltage divider resistor is used to divide the PWM voltage signal and input the divided PWM voltage signal into the V / I conversion chip.

[0135] The V / I conversion chip is used to convert the received voltage-divided PWM voltage signal into a current signal.

[0136] A current-induced resistor is used to adjust the current signal to obtain an adjusted bias current signal.

[0137] See details Figure 10 The diagram below illustrates the specific structure of the V / I converter in this embodiment, including a V / I conversion chip 200a, a positive power supply 200b and a negative power supply 200c, a negative voltage power supply 200d in the current source circuit, and voltage divider resistors 200e, 200f and 200g of the negative voltage power supply.

[0138] It should be noted that the V / I converter chip uses a dual power supply: a positive power supply of +12V and a negative power supply of -12V. -IN represents the negative signal input port of the V / I converter chip, +IN represents the positive signal input port, I0 represents the input port of the modulation current source, and Iout represents the signal output port of the V / I converter chip. The output port Iout of the V / I converter chip is connected to the bias current Iset port of the programmable operational amplifier. The current source I0 is obtained by voltage division through the negative power supply. Figure 10 Resistors R1, R2, and R3 are voltage divider resistors, and the negative voltage power supply is -12V. The first end of resistor 200e is connected to the negative voltage power supply, and the second end is connected to the common connection point of components 200f and 200g. The other end of resistor 200f is connected to the ground plane, and the other end of resistor 200g serves as the output of the current source and is connected to port I0.

[0139] for Figure 10 A schematic diagram of the specific structure of the V / I converter, numbered 200 overall. Figure 6 In the middle, the specific structure is all Figure 10 As shown, it includes programmable operational amplifier device 200, programmable operational amplifier device 205, and V / I conversion circuits of the same structure, each V / I converter using... Figure 6 Connect as shown.

[0140] It should be noted that, with Figure 2 The structure shown builds a fractional-order circuit with programmable order. The implemented fractional-order circuit has 3 segments. The overall circuit requires 9 programmable operational amplifiers, 8 V / I conversion circuits, and 8 I / V conversion circuits. One programmable operational amplifier uses a current source to provide bias current, while the other programmable operational amplifiers use the bias current output from the conversion circuits.

[0141] It should be noted that the signal processing circuit module, such as Figure 4 and Figure 5The structures shown include Structure 1 and Structure 2, and the V / I conversion circuit is as follows: Figure 6 The structure shown has the output Iset bias current connected to the Iset port of the programmable op-amp, and the I / V conversion circuit is as follows. Figure 8 The structure shown has a current sampling port connected to the output loop of the bias current, and a converted voltage output port connected to the ADC port of the core MCU. The PWM voltage signal is adjusted by the control algorithm and connected to the V / I conversion chip. The output bias current value adjusted by the algorithm is output. The change in the bias current value changes the circuit characteristics of the programmable op-amp, thus adjusting the overall circuit to meet the fractional-order circuit characteristics under a specified order. During this process, the circuit structure can remain completely unchanged, and the order is programmable.

[0142] Based on the fractional-order circuit theory, the following derivation shows that, under the circuit scheme provided in the embodiments of this application, the designed bias current value conforms to the parameter standard of the programmable operational amplifier, and the overall output signal and input signal transfer function of the circuit satisfy the characteristics of the fractional-order circuit theory.

[0143] First, the fractional order is related to the frequency response characteristics of the circuit. From the perspective of the circuit transfer function, the circuit provided in this application satisfies the following signal transmission formula (1), where g 109 This represents the transconductance parameter of the programmable operational amplifier device 109. The same applies to other programmable operational amplifier devices. n is a constant. In this circuit scheme, the transconductance value of the programmable operational amplifier device is 10 × the bias current value. The bias current value is linearly related to the transconductance value.

[0144]

[0145] Based on the operational amplifier characteristics, the transfer function of the circuit satisfies the following conditions, where the subscript numbers correspond to the schematic diagram. Figure 4 , Figure 5 The programmable operational amplifier and capacitor components are numbered, Cu, Cy, and Ct correspond to the capacitance values ​​in the structure diagram, and n is a constant.

[0146]

[0147] Formulas (2)-(4) above are the transfer functions of the proposed circuit and the conditions that the circuit needs to satisfy; based on the theoretical transfer function characteristics of the fractional-order circuit, combined with the circuit structure and formula provided in the embodiment of this application, the following fractional-order circuit implementation formula (5) can be obtained, where H(s) is the theoretical transfer function, S represents the complex frequency domain, S is obtained after the Laplace transform in the time domain, and A1, A2, A3 are theoretical constants. When the fractional order is changed, the values ​​of A1, A2, A3 are different.

[0148]

[0149] g109 =A3g 110 g 101 =A2g 110 g 107 =A1g 110 g 100 =g 107 g 106 =g 101 g 104 =g 110 g 103 =g 109 .

[0150] To address the difficulty in adjusting the order of fractional-order circuits, this application embodiment allows for adjustment of the order of the fractional-order circuit without altering its circuit structure. A programmable operational amplifier is selected to build the fractional-order circuit. Different bias current values ​​are designed based on the A1, A2, and A3 values ​​for different orders. Changing the bias current values ​​allows the circuit to meet the characteristics of a fractional-order circuit at a specified order. A V / I converter is used to convert the PWM voltage signal into a current signal. The PWM voltage signal is adjusted by the core MCU, thus the fractional-order order can be programmed and controlled by the core MCU.

[0151] In summary, under the circuit scheme provided in this application embodiment, the designed bias current value conforms to the parameter standard of the programmable operational amplifier based on the derivation of fractional-order circuit theory, and the overall output signal and input signal transfer function of the circuit satisfy the characteristics of fractional-order circuit theory.

[0152] It should be noted that the fractional-order circuit scheme with programmable order provided by the present invention, under the frequency response, the phase value = order × 90, the slope of the amplitude curve is the fractional order, the target order is greater than or equal to 0.1 and less than or equal to 0.9, or the target order is greater than or equal to -0.9 and less than or equal to -0.1. That is to say, the order range is [-0.9, -0.1], [+0.1, +0.9].

[0153] Thus, the fractional-order circuit with programmable order provided in this application embodiment can increase the number of circuit segments in the signal processing circuit module 1 by splicing. The higher the number of segments, the higher the approximate accuracy of the fractional-order circuit. In other words, the fractional-order circuit provided in this application embodiment can change the order of the fractional-order circuit by programming and controlling it through the MCU without changing the circuit structure.

[0154] The results of the fractional-order circuit in terms of frequency response are as follows: Figure 11 and Figure 12 As shown. Figure 11This is the frequency response curve of a fractional-order circuit with an order of 0.5. The left vertical axis represents the amplitude, and the right vertical axis represents the phase. The phase value is 45°, which satisfies the properties of a fractional-order circuit within a certain frequency range. Figure 12 This is the frequency response curve of a fractional-order circuit with an order of -0.5 and a phase value of -45°. It satisfies the properties of a fractional-order circuit over a certain frequency range. The phase value exhibits a small range of fluctuation error. Figure 11 , Figure 12 The image shows the frequency response of a three-segment fractional-order circuit. The frequency range that satisfies the properties of a fractional-order circuit is 10. 2 Up to 10 4 The slope of the amplitude curve within this frequency range is the order. Increasing the number of segments in a fractional-order circuit will widen this frequency range.

[0155] Combination Figure 11 as well as Figure 12 This verifies the feasibility and accuracy of the circuit in the embodiments of this application. The frequency response of the circuit can be adjusted according to the formulas and conditions provided in the embodiments of this application to achieve the properties of fractional-order circuits of different orders.

[0156] In summary, this application provides a fractional-order circuit with programmable order. An external signal is input to the signal processing circuit module, and the resulting output signal satisfies the properties of a fractional-order circuit. The signal processing circuit module includes a programmable operational amplifier device. The bias current output loop is connected to an I / V conversion circuit, and the converted voltage port is connected to the core MCU. The core MCU controls the PWM voltage signal to be input to the V / I conversion circuit, and the resulting bias current is provided to N sets of programmable operational amplifier circuits. By changing the bias current value input to the N sets of programmable operational amplifier circuits, the circuit satisfies the characteristics of a fractional-order circuit of a specified order.

[0157] Compared to the complex circuits in the prior art, the circuit solution provided in this application embodiment can change the order of the fractional-order circuit through the overall control of the core MCU without changing the circuit structure, thus realizing the order programmability of the overall circuit.

[0158] Furthermore, the order-editable fractional circuit scheme provided in this application embodiment can increase the number of circuit segments by splicing. The higher the number of segments, the higher the approximate accuracy of the fractional circuit, that is, the larger the frequency range that satisfies the fractional property.

[0159] Furthermore, the embodiments of this application also provide a series of derivation formulas and conditions for fractional-order circuits. It can be seen that, under the conditions, the circuit parameters can obtain a frequency response curve that satisfies the characteristics of a fractional-order circuit. The results show that the circuit satisfies the fractional-order property within a certain frequency range, the phase value has a small range of fluctuation error, the slope of the amplitude curve in this frequency range is the order, and the overall circuit can better satisfy the characteristics of a fractional-order circuit.

[0160] As can be seen from the above description of the embodiments, those skilled in the art can clearly understand that all or part of the steps in the methods of the above embodiments can be implemented by means of software plus a general-purpose hardware platform. Based on this understanding, the technical solution of this application can be embodied in the form of a software product. This computer software product can be stored in a storage medium, such as a read-only memory (ROM) / RAM, magnetic disk, optical disk, etc., including several instructions to cause a computer device (which may be a personal computer, a server, or a network communication device such as a router) to execute the methods described in various embodiments or some parts of the embodiments of this application.

[0161] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on its differences from other embodiments. In particular, the device embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions in the method embodiments. The device embodiments described above are merely illustrative. Modules described as separate components may or may not be physically separate. Components shown as modules may or may not be physical modules; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the objectives of this embodiment according to actual needs. Those skilled in the art can understand and implement this without creative effort.

[0162] The above description is merely a preferred embodiment of this application and is not intended to limit the scope of protection of this application. It should be noted that those skilled in the art can make various improvements and modifications without departing from this application, and these improvements and modifications should also be considered within the scope of protection of this application.

Claims

1. A fractional-order circuit with programmable order, characterized in that, include: Signal processing circuit module, bias current output circuit module, and current sampling circuit module; The signal processing circuit module includes N sets of programmable operational amplifier circuits, where N is a positive integer, and the N sets of programmable operational amplifier circuits are connected in sequence; the bias current output circuit module includes a core MCU. The current sampling circuit module is connected to the core MCU of the bias current output circuit module and the output circuit of the bias current output circuit module, respectively; the bias current output circuit module is connected to the signal processing circuit module. The signal processing circuit module is used to receive external input signals; The bias current output circuit module is used to output a bias current signal; The current sampling circuit module is used to acquire the bias current signal and convert the bias current signal into a voltage signal; The bias current output circuit module is also used to adjust the voltage signal based on the core MCU to obtain a pulse width modulation (PWM) voltage signal, and the PWM voltage signal is used to obtain the adjusted bias current signal. The bias current output circuit module is also used to convert the PWM voltage signal into the adjusted bias current signal, and adjust the bias current value of the N groups of programmable operational amplifier circuits according to the adjusted bias current signal, so as to adjust the order of the fractional-order circuit as the target order. The signal processing circuit module is used to process the external input signal according to the N groups of programmable operational amplifiers after adjusting the input bias current value, and obtain an output signal, wherein the output signal is a signal that satisfies the fractional order property. The bias current output circuit module includes a voltage-to-current (V / I) converter; the core MCU is connected to the voltage-to-current (V / I) converter. The V / I converter is used to receive the current source and the PWM voltage signal output by the core MCU, and output the adjusted bias current signal. The current source is obtained by using a voltage divider resistor to divide the DC negative voltage power supply. The V / I converter includes a V / I conversion chip, voltage divider resistors and current-induced resistors, a modulated current input port and a voltage input port; The modulated current input port is used to receive the current source; The voltage input port is used to receive the PWM voltage signal; The voltage divider resistor is used to divide the PWM voltage signal and input the divided PWM voltage signal into the V / I conversion chip; The V / I conversion chip is used to receive the divided PWM voltage signal and convert the divided PWM voltage signal into a current signal. The current-induced resistor is used to adjust the current signal to obtain the adjusted bias current signal.

2. The circuit according to claim 1, characterized in that, The core MCU includes an ADC sampling unit and a control algorithm unit; The ADC sampling unit is used to sample the voltage signal to obtain a digital signal; The control algorithm unit is used to calculate the PWM voltage signal based on the control algorithm and the digital signal.

3. The circuit according to claim 1, characterized in that, The current sampling circuit module includes a current-to-voltage (I / V) converter; the I / V converter is connected to the core MCU. The current sampling circuit module is specifically used to: call the I / V converter to convert the bias current signal into the voltage signal, and input the voltage signal into the core MCU.

4. The circuit according to claim 3, characterized in that, The I / V converter includes an I / V conversion chip, an external sampling resistor, and a voltage output port; The I / V conversion chip is used to convert the bias current signal into the voltage signal; The external sampling resistor is used to measure the voltage value of the voltage signal during the process of controlling the conversion of the bias current signal into the voltage signal.

5. The circuit according to claim 1, characterized in that, The target order is greater than or equal to 0.1 and less than or equal to 0.9, or the target order is greater than or equal to -0.9 and less than or equal to -0.

1.

6. The circuit according to claim 1, characterized in that, The signal processing circuit module includes a first programmable operational amplifier circuit; The first programmable operational amplifier circuit is used to receive the adjusted first bias current signal; The first programmable operational amplifier circuit is further configured to receive the external input signal, process the external input signal according to the adjusted first bias current signal, and obtain the output signal; the adjusted first bias current signal corresponds to the first programmable operational amplifier circuit. The first programmable operational amplifier circuit is also used to output the output signal.

7. The circuit according to claim 6, characterized in that, The signal processing circuit module further includes: a second programmable operational amplifier circuit; the output port of the second programmable operational amplifier circuit is connected to the input port of the first programmable operational amplifier circuit; The signal processing circuit module further includes: a third programmable operational amplifier circuit; the output port of the third programmable operational amplifier circuit is connected to the input port of the second programmable operational amplifier circuit; The third programmable operational amplifier circuit is used to receive the external input signal, receive the adjusted third bias current signal, process the external input signal according to the adjusted third bias current signal to obtain a first output sub-signal, and input the first output sub-signal into the second programmable operational amplifier circuit; the adjusted third bias current signal corresponds to the third programmable operational amplifier circuit. The second programmable operational amplifier circuit is configured to receive the external input signal, receive the adjusted second bias current signal, receive the first output sub-signal, process the external input signal according to the first output sub-signal and the adjusted second bias current signal to obtain the second output sub-signal, and input the second output sub-signal into the first programmable operational amplifier circuit; the adjusted second bias current signal corresponds to the second programmable operational amplifier circuit. The first programmable operational amplifier circuit is specifically used to: receive the second output sub-signal, process the external input signal according to the second output sub-signal and the adjusted first bias current signal, and obtain the output signal.

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