Amplifier circuit for carrier aggregation

Abstract

This disclosure relates to amplifier circuitry for carrier aggregation. An electronic device may include a wireless circuit having a baseband processor, transceiver circuitry, a front-end module, and an antenna. The front-end module may include amplifier circuitry, such as a low-noise amplifier for amplifying received radio frequency signals. The amplifier circuitry is capable of operating in both non-carrier aggregation and carrier aggregation modes. The amplifier circuitry may include an input transformer coupled to multiple amplifier stages, such as a common-gate amplifier stage, a common-source common-gate amplifier stage, and a common-source amplifier stage. The common-gate amplifier stage may include a switch for selectively activating a set of cross-coupled capacitors to help maintain input impedance matching in both the non-carrier aggregation and carrier aggregation modes. The common-source amplifier stage may include an additional switch for activating and deactivating the common-source amplifier stage to help maintain gain in both the non-carrier aggregation and carrier aggregation modes.

Description

[0001] This application is a divisional application of the invention patent application with application number 202111101353.7, application date September 18, 2021, and invention title "Amplifier Circuit for Carrier Aggregation".

[0002] Cross-reference to related applications

[0003] This application claims priority to U.S. Patent Application No. 17 / 028,598, filed on September 22, 2020, the entire contents of which are incorporated herein by reference. Technical Field

[0004] This disclosure relates in general to electronic devices, and more specifically to electronic devices having wireless communication circuitry. Background Technology

[0005] Electronic devices often possess wireless communication capabilities. This invention discloses an electronic device with wireless communication capabilities, which includes a wireless communication circuit having one or more antennas. The wireless receiver circuit in this wireless communication circuit uses the antennas to receive radio frequency signals.

[0006] The signal received by the antenna is fed through an RF front-end module, which typically includes a low-noise amplifier for amplifying the received RF signal. Designing a satisfactory low-noise amplifier circuit for electronic devices can be challenging. Summary of the Invention

[0007] The electronic device may include a wireless communication circuit configured to receive radio frequency (RF) signals from one or more base stations. The wireless communication circuit may include an antenna; transceiver circuitry configured to receive the RF signals from the antenna and generate corresponding baseband signals; and a baseband processor configured to receive the baseband signals from the transceiver circuitry. The wireless communication circuitry may also include an amplifier circuitry interposed on an RF transmission line path between the antenna and the transceiver circuitry. The amplifier circuitry may include a low-noise amplifier circuitry configured to amplify the RF signals received from the antenna.

[0008] The electronic device may optionally support carrier aggregation to combine component carriers from multiple base stations. The amplifier circuit is capable of operating in a non-carrier aggregation mode, during which it receives a signal from a single carrier (from one base station), and is also capable of operating in a carrier aggregation mode, during which it receives signals from multiple component carriers (from at least two different base stations).

[0009] One aspect of this disclosure provides an amplifier circuit capable of operating in both carrier aggregation and non-carrier aggregation modes. The amplifier circuit may include an input port configured to receive radio frequency signals from an antenna; a transformer circuit coupled to the input port; a first amplifier coupled to the transformer circuit; and a second amplifier coupled to the transformer circuit. The first and second amplifiers may each include a common-gate amplifier stage having an input coupled to the transformer circuit and an output; a common-source common-gate amplifier stage having an input coupled to the output of the common-source common-gate amplifier stage and an output; a common-source amplifier stage coupled to the common-source common-gate amplifier stage and coupled to a common-source bias voltage configured to activate and deactivate the common-source amplifier stage in both the non-carrier aggregation and carrier aggregation modes; and an output port coupled to the output of the common-source common-gate amplifier stage.

[0010] The transformer circuit may include: a primary coil having a first terminal coupled to the input port and a second terminal coupled to a ground wire; a first adjustable capacitor coupled in series between the input port and the first terminal; and a second adjustable capacitor having a first terminal coupled to the input port and a second terminal coupled to the ground wire. The transformer circuit may also include a first stage coil coupled to the input of the common-gate amplifier stage in the first amplifier; a third adjustable capacitor coupled in parallel with the first stage coil and configured to control the input impedance of the first amplifier in both the non-carrier aggregation mode and the carrier aggregation mode; a second stage coil coupled to the input of the common-gate amplifier stage in the second amplifier; and a fourth adjustable capacitor coupled in parallel with the second stage coil and configured to control the input impedance of the second amplifier in both the non-carrier aggregation mode and the carrier aggregation mode.

[0011] One aspect of this disclosure provides a method of operating an amplifier circuit. The method may include receiving a radio frequency (RF) signal from an antenna via an input port; coupling the RF signal from the input port to a first amplifier and a second amplifier via a transformer circuit; receiving the RF signal from the transformer circuit via a common-gate amplifier stage in each of the first and second amplifiers and outputting a corresponding first amplified signal; receiving the first amplified signal via a common-source common-gate amplifier stage in each of the first and second amplifiers and outputting a corresponding second amplified signal; further amplifying the second amplified signal via a common-source amplifier stage in each of the first and second amplifiers to output a corresponding carrier-aggregated output signal; and adjusting a common-source bias voltage in the common-source amplifier stage of each of the first and second amplifiers in a carrier-aggregation mode and a non-carrier-aggregation mode. The method may further include tuning the input impedance of the first amplifier via a first input capacitor coupled to the first amplifier in the carrier-aggregation mode and the non-carrier-aggregation mode, and tuning the input impedance of the second amplifier via a second input capacitor coupled to the second amplifier in the carrier-aggregation mode and the non-carrier-aggregation mode.

[0012] One aspect of this disclosure provides an electronic device capable of operating in both carrier aggregation and non-carrier aggregation modes. The electronic device may include an antenna configured to receive a radio frequency (RF) signal; a transceiver configured to generate a baseband signal based on the RF signal; a baseband processor configured to receive the baseband signal; and an amplifier circuit configured to receive the RF signal from the antenna and output a corresponding amplified signal to the transceiver. The amplifier circuit may include an input port; a transformer circuit coupled to the input port; a common-gate amplifier stage having an input coupled to the transformer circuit and an output; a common-source common-gate amplifier stage having an input coupled to the output and an output; a common-source amplifier stage coupled to the common-source common-gate amplifier stage and coupled to a common-source bias voltage configured to control the common-source amplifier stage in both the non-carrier aggregation mode and the carrier aggregation mode; and an output port coupled to the output of the common-source common-gate amplifier stage. The transformer circuit may include a primary coil having a first terminal coupled to the input port and a second terminal coupled to ground. The transformer circuit may include a secondary coil coupled to the input of the common-gate amplifier stage. The amplifier circuit may include an adjustable capacitor coupled in parallel with the secondary coil. The adjustable capacitor can be configured to tune the input impedance of the common-gate amplifier stage in both the non-carrier aggregation mode and the carrier aggregation mode. Attached Figure Description

[0013] Figure 1 This is a schematic diagram of an exemplary electronic device according to some implementation schemes, having a wireless communication circuit configured to communicate wirelessly with multiple external devices.

[0014] Figure 2 This is a schematic diagram of an exemplary wireless communication circuit with a front-end module coupled between an antenna and a transceiver circuit, according to some implementation schemes.

[0015] Figure 3 This is a schematic diagram of an exemplary amplifier circuit coupled to a mixer circuit according to some implementation schemes.

[0016] Figure 4 This is a state diagram illustrating how an exemplary low-noise amplifier can operate in both non-carrier aggregation and carrier aggregation modes according to some implementation schemes.

[0017] Figure 5A This is a circuit diagram of an exemplary low-noise amplifier circuit with a signal split at the input of a common-gate amplifier, according to some implementation schemes.

[0018] Figure 5B This illustrates operation in non-carrier aggregation mode according to some implementation schemes. Figure 5A The circuit diagram of the low-noise amplifier circuit.

[0019] Figure 5C This illustrates operation in carrier aggregation mode according to some implementation schemes. Figure 5A The circuit diagram of the low-noise amplifier circuit.

[0020] Figure 6A This is a circuit diagram of an exemplary low-noise amplifier circuit with a signal split at the output of a common-gate amplifier, according to some implementation schemes.

[0021] Figure 6B This illustrates operation in non-carrier aggregation mode according to some implementation schemes. Figure 6A The circuit diagram of the low-noise amplifier circuit.

[0022] Figure 6C This illustrates, according to some embodiments, operation in carrier aggregation mode by activating cross-coupled capacitors at the common gate level. Figure 6A The circuit diagram of the low-noise amplifier circuit.

[0023] Figure 6D This illustrates, according to some implementation schemes, operation in carrier aggregation mode by increasing the current. Figure 6A The circuit diagram of the low-noise amplifier circuit.

[0024] Figure 7AThis is a circuit diagram of an exemplary low-noise amplifier circuit with an amplifier having a separate tunable transformer circuit, according to some implementation schemes.

[0025] Figure 7B This illustrates operation in non-carrier aggregation mode according to some implementation schemes. Figure 7A The circuit diagram of the low-noise amplifier circuit.

[0026] Figure 7C This illustrates operation in carrier aggregation mode according to some implementation schemes. Figure 7A The circuit diagram of the low-noise amplifier circuit. Detailed Implementation

[0027] Electronic devices, such as Figure 1 The electronic device 10 may include wireless circuitry. This wireless circuitry may include amplifiers, such as low-noise amplifiers, capable of operating in non-carrier aggregation mode to support communication with a single base station at one frequency, or capable of operating in carrier aggregation mode to support communication with at least two different base stations at multiple frequencies. The low-noise amplifier (sometimes referred to as amplifier circuitry) may include an input port configured to receive radio frequency signals from an antenna, an input transformer, a first amplifier, and a second amplifier. The first and second amplifiers may have a common-gate amplifier stage and a common-source cascode stage. The common-gate amplifier stage may have cross-coupled capacitors that are activated and deactivated to tune the input impedance of the first and second amplifiers. The common-source cascode stage may also be coupled to a common-source stage activated in carrier aggregation mode to help eliminate noise and other undesirable nonlinearities generated by the common-source cascode stage. The input transformer may optionally be tuned via an adjustable input capacitor. This configuration and operation maintains the input impedance and gain of the low-noise amplifier when switching between non-carrier aggregation mode and carrier aggregation mode.

[0028] Figure 1The electronic device 10 may be: a computing device, such as a laptop computer, desktop computer, computer monitor containing an embedded computer, tablet computer, cellular phone, media player, or other handheld or portable electronic device; a smaller device, such as a wristwatch, a wristband, a headset or handset, a device embedded in glasses; or other equipment worn on a user's head; or other wearable or micro-devices, televisions, computer monitors without an embedded computer, gaming devices, navigation devices, embedded systems (such as systems in which electronic equipment with a display is installed in a kiosk or vehicle), voice-controlled speakers connected to the wireless Internet, home entertainment devices, remote control devices, game controllers, peripheral user input devices, wireless base stations or access points, equipment that enables the functions of two or more of these devices; or other electronic equipment.

[0029] like Figure 1 As illustrated in the schematic diagram, device 10 may include components located on or within an electronic device housing, such as housing 12. Housing 12 (sometimes referred to as a shell) may be formed of plastic, glass, ceramic, fiber composite material, metal (e.g., stainless steel, aluminum, metal alloys, etc.), other suitable materials, or combinations thereof. In some cases, part or all of housing 12 may be formed of dielectric or other low-conductivity materials (e.g., glass, ceramic, plastic, sapphire, etc.). In other cases, housing 12, or at least some of the structures constituting housing 12, may be formed of metallic elements.

[0030] Device 10 may include control circuitry 14. Control circuitry 14 may include storage devices, such as storage circuitry 16. Storage circuitry 16 may include hard disk drive storage devices, non-volatile memory (e.g., flash memory configured to form a solid-state drive or other electrically programmable read-only memory), volatile memory (e.g., static random access memory or dynamic random access memory), etc. Storage circuitry 16 may include storage devices and / or removable storage media integrated within device 10.

[0031] Control circuitry 14 may include processing circuitry, such as processing circuitry 18. Processing circuitry 18 may be used to control the operation of device 10. Processing circuitry 18 may include one or more microprocessors, microcontrollers, digital signal processors, host processors, baseband processor integrated circuits, application-specific integrated circuits, central processing units (CPUs), etc. Control circuitry 14 may be configured to perform operations in device 10 using hardware (e.g., dedicated hardware or circuitry), firmware, and / or software. Software code for performing operations in device 10 may be stored on storage circuitry 16 (e.g., storage circuitry 16 may include a non-transitory (tangible) computer-readable storage medium storing software code). This software code may sometimes be referred to as program instructions, software, data, commands, or code. The software code stored on storage circuitry 16 may be executed by processing circuitry 18.

[0032] Control circuitry 14 can be used to run software on device 10, such as satellite navigation applications, internet browsing applications, Voice over Internet Protocol (VoIP) telephone calling applications, email applications, media playback applications, operating system functions, etc. To support interaction with external equipment, control circuitry 14 can be used to implement communication protocols. Communication protocols that can be implemented using control circuitry 14 include: Internet Protocol, Wireless Local Area Network (WLAN) protocols (e.g., IEEE 802.11 protocol—sometimes referred to as...). Protocols for other short-range wireless communication links, such as This protocol may be any of the following: wireless personal area network (WPAN) protocols, IEEE 802.11ad protocols (e.g., ultra-wideband protocols), cellular phone protocols (e.g., 3G protocols, 4G (LTE) protocols, 5G New Radio (NR) protocols, etc.), MIMO protocols, antenna diversity protocols, satellite navigation system protocols (e.g., Global Positioning System (GPS) protocols, Global Navigation Satellite System (GLONASS) protocols, etc.), antenna-based spatial ranging protocols (e.g., radio detection and ranging (RADAR) protocols for signals transmitted at millimeter and centimeter wave frequencies or other desired distance detection protocols), or any other desired communication protocol. Each communication protocol may be associated with a corresponding radio access technology (RAT), which specifies the physical connection method used to implement the protocol.

[0033] Device 10 may include input-output circuitry 20. Input-output circuitry 20 may include input-output device 22. Input-output device 22 may be used to allow data to be supplied to device 10 and to allow data to be supplied from device 10 to external devices. Input-output device 22 may include user interface devices, data port devices, and other input-output components. For example, input-output device 22 may include touch sensors, displays, light-emitting components such as displays without touch sensor capability, buttons (mechanical, capacitive, optical, etc.), scroll wheels, touchpads, keypads, keyboards, microphones, cameras, buttons, speakers, status indicators, audio jacks and other audio port components, digital data port devices, motion sensors (accelerometers, gyroscopes, and / or compasses that detect motion), capacitive sensors, proximity sensors, magnetic sensors, force sensors (e.g., force sensors coupled to a display to detect pressure applied to the display), etc. In some configurations, keyboards, headphones, displays, pointing devices such as touchpads, mice, electronic pens (e.g., styluses), joysticks, and other input-output devices may be coupled to device 10 using wired or wireless connections (e.g., some of the input-output devices 22 may be peripherals of the main processing unit or other parts of device 10 coupled via wired or wireless links).

[0034] Input-output circuitry 24 may include wireless communication circuitry for wirelessly transmitting radio frequency signals, such as wireless communication circuitry 34 (sometimes referred to herein as wireless circuitry 24). Although control circuitry 14 is shown separately from wireless communication circuitry 24 for clarity, wireless communication circuitry 24 may include processing circuitry and / or storage circuitry, the processing circuitry forming part of processing circuitry 18 and the storage circuitry forming part of storage circuitry 16 of control circuitry 14 (e.g., portions of control circuitry 14 may be implemented on wireless communication circuitry 24). For example, control circuitry 14 (e.g., processing circuitry 18) may include baseband processor circuitry or other control components forming part of wireless communication circuitry 24.

[0035] The wireless communication circuit 24 may include a radio frequency (RF) transceiver circuit formed by one or more integrated circuits, a power amplifier circuit configured to amplify uplink RF signals (e.g., RF signals transmitted by device 10 to an external device), a low-noise amplifier configured to amplify downlink RF signals (e.g., RF signals received by device 10 from an external device), passive RF components, one or more antennas, transmission lines, and other circuitry for processing the RF wireless signals. Light (e.g., infrared communication) may also be used to transmit the wireless signals.

[0036] Wireless circuit 24 may include radio frequency transceiver circuitry for transmitting and / or receiving radio frequency signals in various radio frequency communication bands. For example, the radio frequency transceiver circuitry may handle wireless local area network (WLAN) communication bands such as 2.4 GHz and 5 GHz. (IEEE 802.11) bands, Wireless Personal Area Network (WPAN) communication bands such as 2.4 GHz Communication frequency bands, cellular telephone communication frequency bands such as the cellular low frequency band (LB) (e.g., 600MHz to 960MHz), the cellular low intermediate frequency band (LMB) (e.g., 1400MHz to 1550MHz), the cellular intermediate frequency band (MB) (e.g., 1700MHz to 2200MHz), the cellular high frequency band (HB) (e.g., 2300MHz to 2700MHz), the cellular ultra-high frequency band (UHB) (e.g., 3300MHz to 5000MHz), or other cellular communication frequency bands between approximately 600MHz and approximately 5000MHz (e.g., 3G bands, 4G bands). This includes LTE bands, 5G NR frequency range 1 (FR1) bands below 10 GHz, 5G NR frequency range 2 (FR2) bands with millimeter and centimeter wavelengths between 20 GHz and 60 GHz, etc., near field communication (NFC) bands (e.g., 13.56 MHz), satellite navigation bands (e.g., the 1575 MHz L1 Global Positioning System (GPS) band, the 1176 MHz L5 GPS band, the GLONASS band, the BeiDou Navigation Satellite System (BDS) band, etc.), ultra-wideband (UWB) communication bands supported by the IEEE 802.15.4 protocol and / or other UWB communication protocols (e.g., a first UWB communication band of 6.5 GHz and / or a second UWB communication band of 8.0 GHz), and / or any other desired communication bands. The communication bands processed by such RF transceiver circuits are sometimes referred to herein as frequency bands or simply "bands," and may span corresponding frequency ranges. Generally speaking, the radio frequency transceiver circuit in wireless circuit 24 can cover (process) any desired frequency band.

[0037] Device 10 can communicate with external devices such as accessories, computing equipment, and wireless networks via wired and wireless communication paths. For example, device 10 can communicate with wireless network equipment such as one or more cellular phone base stations 6 via a corresponding wireless link 8. Figure 1In the example, one or more antennas in the wireless communication circuit 24 can communicate with the first base station 6-1 via the first communication link 8-1, and with the second base station 6-N via the second communication link 8-N, or can communicate with both base station 6-1 and base station 6-N simultaneously via both communication links 8-1 and 8-N. In one embodiment, in a scheme sometimes referred to as carrier aggregation, the wireless communication circuit 24 can simultaneously transmit information with the first base station 6-1 in a first communication band associated with link 8-1 and with the second base station 6-N in a second communication band associated with link 8-N.

[0038] When operating using a carrier aggregation scheme, the first base station 6 that establishes a corresponding wireless link 8 with device 10 may sometimes be referred to herein as the primary component carrier (PCC) or the primary base station. The radio frequency signal transmitted between the primary base station and device 10 may sometimes be referred to herein as the primary component carrier signal, primary signal, primary component signal, primary carrier signal, or PCC signal, and the wireless link 8 between the primary base station and device 10 may sometimes be referred to herein as the primary connection or primary wireless link. Once a connection is established between device 10 and the primary base station, device 10 can establish other wireless connections with another base station 6 without interrupting its connection with the primary base station, and can communicate with two base stations simultaneously (e.g., using different frequency bands in the carrier aggregation scheme). Other base stations that establish connections with device 10 after device 10 has established a wireless connection with the primary base station may sometimes be referred to herein as secondary component carriers (SCC) or secondary base stations. The radio frequency signal transmitted between the secondary base station and device 10 may sometimes be referred to herein as the secondary component carrier signal, secondary signal, secondary component signal, secondary carrier signal, or SCC signal, and the wireless link 8 between the secondary base station and device 10 may sometimes be referred to herein as the secondary connection or secondary wireless link. If needed, device 10 can establish connections with the primary base station and one or more secondary base stations in the downlink and uplink communication bands.

[0039] Using carrier aggregation to combine data from multiple component carriers can significantly increase data throughput. For example, wireless communication circuitry 24 can be configured to aggregate data streams from at least two component carriers, up to five component carriers, two to five component carriers, more than five component carriers, up to 16 component carriers, 5 to 16 component carriers, more than 16 component carriers, up to 32 component carriers, 16 to 32 component carriers, more than 32 component carriers, up to 64 component carriers, 32 to 64 component carriers, more than 64 component carriers, 64 to 100 component carriers, more than 100 component carriers, hundreds of component carriers, less than 100 component carriers, less than 64 component carriers, less than 32 component carriers, or other suitable number of component carriers. The combined bandwidth from multiple component carriers aggregated in this way can be as high as 100 MHz or higher, 200 MHz or higher, 300 MHz or higher, 400 MHz or higher, 500 MHz or higher, 500 MHz to 1 GHz, or even greater than 1 GHz.

[0040] The various component carriers being aggregated may or may not belong to the same frequency band. The aggregation of multiple component carriers within the same frequency band is sometimes referred to as intra-band carrier aggregation. Specifically, if multiple component carriers within the same frequency band are located in consecutive frequency blocks without any frequency gaps separating them, this type of intra-band aggregation can also be called intra-band consecutive carrier aggregation. If multiple component carriers within the same frequency band are located in discontinuous frequency blocks separated by one or more frequency gaps, this type of intra-band aggregation can also be called intra-band discontinuous carrier aggregation. In other cases, multiple component carriers from different frequency bands can be aggregated together. This type of carrier aggregation can be called inter-band carrier aggregation.

[0041] Generally, carrier aggregation can combine component carriers from 3G bands, 4G LTE bands, 5G NR bands, or other cellular communication bands, WLAN communication bands, WPAN communication bands, NFC bands, GPS bands, GLONASS bands, UWB communication bands, combinations of these bands, or other desired communication bands. For example, multiple consecutive or non-consecutive component carriers from one or more 4G LTE bands can be aggregated together to perform 4G LTE carrier aggregation. Similarly, multiple consecutive or non-consecutive component carriers from one or more 5G NR bands can be aggregated together to perform 5G NR carrier aggregation. Furthermore, one or more component carriers from a 4G LTE band can be aggregated with one or more component carriers from a 5G NR band to perform dual connectivity carrier aggregation. Finally, multiple component carriers from two or more 4G LTE bands can be aggregated with multiple component carriers from two or more 5G NR bands. For example, component carriers from one or more 4G LTE bands can be aggregated with another type of cellular technology band (e.g., one or more GSM bands, one or more EDGE bands, one or more 3G bands, one or more 5G NR bands, etc.). Similarly, component carriers from one or more 5G NR bands can be aggregated with another type of cellular technology band (e.g., one or more GSM bands, one or more EDGE bands, one or more 3G bands, one or more LTE bands, etc.). These examples are merely illustrative. In general, any number of consecutive or discontinuous component carriers from one or more bands associated with any suitable wireless communication protocol can be aggregated to help improve the data throughput of wireless communication circuit 24.

[0042] Figure 2 This is a schematic diagram showing exemplary components within wireless circuit 24. For example... Figure 2 As shown, wireless circuitry 24 may include a baseband processor such as baseband processor 26, radio frequency (RF) transceiver circuitry such as RF transceiver 28, RF front-end circuitry such as RF front-end module (FEM) 40, and antenna 42. Baseband processor 26 may be coupled to transceiver 28 via baseband path 34. Transceiver 28 may be coupled to antenna 42 via RF transmission line path 36. RF front-end module 40 may be inserted into RF transmission line path 36 between transceiver 28 and antenna 42.

[0043] exist Figure 2In the example, for clarity, wireless circuit 24 is shown as including only a single baseband processor 26, only a single transceiver 28, only a single front-end module 40, and only a single antenna 42. Generally, wireless circuit 24 may include any desired number of baseband processors 26, any desired number of transceivers 36, any desired number of front-end modules 40, and any desired number of antennas 42. Each baseband processor 26 may be coupled to one or more transceivers 28 via a corresponding baseband path 34. Each transceiver 28 may include transmitter circuitry 30 configured to output uplink signals to antenna 42, may include receiver circuitry 32 configured to receive downlink signals from antenna 42, and may be coupled to one or more antennas 42 via a corresponding RF transmission line path 36. Each RF transmission line path 36 may have a corresponding front-end module 40 inserted thereon. If desired, two or more front-end modules 40 may be inserted on the same RF transmission line path 36. If desired, one or more RF transmission line paths 36 in wireless circuit 24 may be implemented without any front-end modules inserted thereon.

[0044] The RF transmission line path 36 may be coupled to an antenna feed section on the antenna 42. The antenna feed section may, for example, include a positive antenna feed terminal and a ground antenna feed terminal. The RF transmission line path 36 may have a positive transmission line signal path coupled to the positive antenna feed terminal on the antenna 42. The RF transmission line path 36 may also have a ground transmission line signal path coupled to the ground antenna feed terminal on the antenna 42. This example is merely illustrative, and in general, the antenna 42 may be fed using any desired antenna feeding scheme. If desired, the antenna 42 may have multiple antenna feed sections coupled to one or more RF transmission line paths 36.

[0045] RF transmission line path 36 may include routing device 10 ( Figure 1The transmission lines within the device 10 are for transmitting radio frequency (RF) antenna signals. The transmission lines in device 10 may include coaxial cables, microstrip transmission lines, stripline transmission lines, edge-coupled microstrip transmission lines, edge-coupled stripline transmission lines, and combinations thereof. Transmission lines in device 10, such as the RF transmission line path 36, may be integrated into rigid and / or flexible printed circuit boards. In one embodiment, the RF transmission line path, such as RF transmission line path 36, may also include transmission line conductors integrated within a multilayer laminate structure (e.g., layers of conductive materials (such as copper) and dielectric materials (such as resin) laminated together without the intervention of an adhesive). If desired, the multilayer laminate structure may be folded or bent in multiple dimensions (e.g., two-dimensional or three-dimensional) and may retain its bent or folded shape after bending (e.g., the multilayer laminate structure may be folded into a specific three-dimensional structural shape for wiring around other device components and may be sufficiently rigid to retain its shape after folding without the need for reinforcements or other structures to hold it in place). All the multiple layers of a laminated structure can be laminated together in batches without adhesive (e.g., in a single pressing process) (e.g., in contrast to performing multiple pressing processes to laminate multiple layers together with adhesive).

[0046] During wireless transmission, baseband processor 26 provides baseband signals to transceiver 28 via baseband path 34. Transceiver 28 may also include circuitry for converting the baseband signals received from baseband processor 26 into corresponding radio frequency (RF) signals. For example, transceiver circuitry 28 may include mixer circuitry for up-converting (or modulating) the baseband signals to RF before transmission via antenna 42. Transceiver circuitry 28 may also include digital-to-analog converter (DAC) circuitry and / or analog-to-digital converter (ADC) circuitry for converting signals between the digital and analog domains. Transceiver 28 may transmit RF signals via transmitter 30, RF transmission line path 42, and front-end module 40 through antenna 36. Antenna 42 transmits RF signals to external wireless equipment by radiating the RF signals into free space.

[0047] During wireless reception, antenna 42 can receive radio frequency (RF) signals from external wireless equipment. The received RF signals can be transmitted to transceiver 28 via RF transmission line path 36 and front-end module 40. Transceiver 28 may include circuitry for converting the received RF signals into corresponding baseband signals. For example, transceiver 28 may include mixer circuitry for down-converting (or demodulating) the received RF signals to baseband frequencies before transmitting the received signals via baseband path 34 to baseband processor 26.

[0048] Front-end module (FEM) 40 may include radio frequency front-end circuitry that operates on radio frequency signals transmitted (transmitted and / or received) through radio frequency transmission line path 36. For example, FEM 40 may include front-end module (FEM) components such as radio frequency filter circuitry 44 (e.g., low-pass filter, high-pass filter, notch filter, band-pass filter, multiplexing circuitry, duplexer circuitry, antenna common circuitry, tripplexer circuitry, etc.), switching circuitry 46 (e.g., one or more radio frequency switches), radio frequency amplifier circuitry 48 (e.g., one or more power amplifier circuitry 50 and / or one or more low-noise amplifier circuitry 52), impedance matching circuitry (e.g., circuitry that helps match the impedance of antenna 42 with the impedance of radio frequency transmission line 36), antenna tuning circuitry (e.g., a network of capacitors, resistors, inductors, and / or switches that adjust the frequency response of antenna 42), radio frequency coupler circuitry, charge pump circuitry, power management circuitry, digital control and interface circuitry, and / or any other desired circuitry that operates on radio frequency signals transmitted and / or received by antenna 42. Each of the front-end module components can be mounted on a common (shared) substrate, such as a rigid printed circuit board substrate or a flexible printed circuit board substrate. If needed, the various front-end module components can also be integrated into a single integrated circuit chip.

[0049] Filter circuit 44, switching circuit 46, amplifier circuit 48, and other circuits may be inserted within the RF transmission line path 36, may be integrated into the FEM 40, and / or may be integrated into the antenna 42 (e.g., to support antenna tuning, to support operation in a desired frequency band, etc.). These components (sometimes referred to herein as antenna tuning components) may be adjusted (e.g., using control circuit 14) to adjust the frequency response and wireless performance of the antenna 42 over time.

[0050] Transceiver 28 may be separate from front-end module 40. For example, transceiver 28 may be formed on another substrate such as the main logic board of device 10, a rigid printed circuit board, or a flexible printed circuit that is not part of front-end module 40. Although for clarity, in Figure 1In the example, control circuitry 14 is shown separate from wireless circuitry 24, but wireless circuitry 24 may include processing circuitry and / or storage circuitry, the processing circuitry forming part of processing circuitry 18, and the storage circuitry forming part of storage circuitry 16 of control circuitry 14 (e.g., portions of control circuitry 14 may be implemented on wireless circuitry 24). As an example, portions of baseband processor 26 and / or transceiver 28 (e.g., a host processor on transceiver 28) may form part of control circuitry 14. Control circuitry 14 (e.g., portions of control circuitry 14 formed on baseband processor 26, portions of control circuitry 14 formed on transceiver 28, and / or portions of control circuitry 14 separate from wireless circuitry 24) may provide control signals (e.g., via one or more control paths in device 10) to control the operation of front-end module 40.

[0051] Transceiver circuitry 28 may include processing WLAN communication bands (e.g., (IEEE 802.11) or other WLAN communication bands) such as the 2.4 GHz WLAN band (e.g., 2400 MHz to 2480 MHz), the 5 GHz WLAN band (e.g., 5180 MHz to 5825 MHz), 6E band (e.g., 5925MHz to 7125MHz) and / or others Wireless LAN transceiver circuitry covering a frequency band (e.g., 1875MHz to 5160MHz); handling 2.4GHz. Wireless personal area network transceiver circuits for frequency bands or other WPAN communication bands; cellular phone transceiver circuits for processing cellular phone frequency bands (e.g., bands from about 600 MHz to about 5 GHz, 3G bands, 4G LTE bands, 5G NR frequency range 1 (FR1) band below 10 GHz, 5G NR frequency range 2 (FR2) band between 20 GHz and 60 GHz, etc.); near field communication (NFC) transceiver circuits for processing near field communication bands (e.g., 13.56 MHz); satellite navigation receiver circuits for processing satellite navigation bands (e.g., GPS band from 1565 MHz to 1610 MHz, GLONASS band, BeiDou Navigation Satellite System (BDS) band, etc.); ultra-wideband (UWB) transceiver circuits for processing communications using the IEEE 802.15.4 protocol and / or other ultra-wideband communication protocols; and / or any other desired radio frequency transceiver circuits for covering any other desired communication bands of interest.

[0052] Wireless circuit 24 may include one or more antennas, such as antenna 42. Antenna 42 can be formed using any desired antenna structure. For example, antenna 42 may be an antenna with a resonant element, formed from a loop antenna structure, patch antenna structure, inverted F-shaped antenna structure, slot antenna structure, planar inverted F-shaped antenna structure, helical antenna structure, monopole antenna, dipole, a combination of these designs, etc. Two or more antennas 42 may be arranged in one or more phased antenna arrays (e.g., for transmitting radio frequency signals at millimeter-wave frequencies). Parasitic elements may be included in antenna 42 to adjust antenna performance. Antenna 42 may be provided with a conductive cavity that supports the antenna resonant element of antenna 42 (e.g., antenna 42 may be a cavity-backed antenna, such as a cavity-backed slot antenna).

[0053] As described above, the front-end module 40 may include one or more low-noise amplifier (LNA) circuits 52 in the receive (downlink) path. The low-noise amplifier 52 (sometimes referred to as a low-noise amplifier circuit or amplifier circuit) may be configured to amplify the received radio frequency signal without significantly reducing the signal-to-noise ratio (SNR) of the amplified signal. For example, the low-noise amplifier 52 may be used to provide a voltage gain of 2dB, 3dB, 4dB, 5dB, 6dB, 3dB to 4dB, 2dB to 5dB, 5dB to 10dB, or other suitable amounts of voltage gain.

[0054] Figure 3 This is a schematic diagram of an exemplary low-noise amplifier circuit 52 coupled to transceiver 28. (See diagram for example.) Figure 3As shown, amplifier circuit 52 has an input port RFIN configured to receive radio frequency signals from an antenna, an input transformer (such as input transformer circuit 60), a first amplifier 62, and a second amplifier 64. Transformer circuit 60 can feed signals in parallel to both the first amplifier 62 and the second amplifier 64. The first amplifier 62 has a first carrier aggregation output port CA1, while the second amplifier 64 has a second carrier aggregation output port CA2. Transceiver 28 may include mixer circuitry, such as a first mixer 66 and a second mixer 68, among other wireless transceiver components. The first mixer 66 can receive a signal from the first carrier aggregation output port CA1 of the first amplifier 62 and a local oscillator signal LO. The second mixer 68 can receive a signal from the second carrier aggregation output port CA2 of the second amplifier 64 and another local oscillator signal. The local oscillator signals received by mixers 66 and 68 can be the same or different (e.g., the local oscillator signals can have the same frequency but a phase shift). Mixer 66 can then output a corresponding first baseband output signal BB1 associated with a component carrier. Similarly, mixer 68 can output a corresponding second baseband output signal BB2 associated with another component carrier. Baseband signals BB1 and BB2 can then be provided to baseband processor 26 (see [link to relevant documentation]). Figure 2 ).

[0055] In device 10 supporting carrier aggregation of multiple component carriers, device 10 may include one or more low-noise amplifiers 52 capable of operating in both non-carrier aggregation (NCA) and carrier aggregation (CA) modes. Ideally, the gain and input matching characteristics associated with the low-noise amplifier should be identical in both NCA and CA operating modes. However, if not carefully designed, the gain and input impedance of the low-noise amplifier circuitry may become mismatched when switching from NCA mode to CA mode, and vice versa.

[0056] Figure 4 This is a state diagram illustrating how the low-noise amplifier circuit 52 can switch between non-carrier aggregation mode 70 and carrier aggregation mode 72. When amplifier circuit 52 operates in non-carrier aggregation mode 70, only one of the two amplifiers 62 and 64 is activated. For example, only the first amplifier 62 is activated, while the second amplifier 64 is deactivated or idle. Alternatively, only the second amplifier 64 is turned on (enabled), while the first amplifier 62 is turned off (deactivated). In either case, the activated amplifier may include a cross-coupled common-source amplifier stage that is deactivated during non-carrier aggregation mode 70.

[0057] When amplifier circuit 52 operates in carrier aggregation mode 72, both amplifiers 62 and 64 are activated. In mode 72, the first amplifier 62 outputs a signal at the first carrier aggregation output port CA1, while the second amplifier 64 simultaneously outputs a signal at the second carrier aggregation output port CA2. Unlike mode 70, amplifiers 62 and 64 may each include a cross-coupled common-source amplifier stage that is activated (switched to enabled) during carrier aggregation mode 72. Switching the cross-coupled common-source amplifier stage to enabled helps recover any gain that might otherwise be reduced when splitting the current from the input transformer between the two amplifiers, while also providing the benefit of noise cancellation and other higher-order nonlinear terms associated with other stages in amplifier circuit 52. The first and second amplifiers may include switching circuitry configured to control (i.e., activate and deactivate) at least a portion of the low-noise amplifier circuit 52 when switching between modes 70 and 72. Details of such switching circuitry may depend on the specific implementation of amplifier circuit 52, which will be described in more detail below in conjunction with Figures 5 through 7.

[0058] Figure 5A This is a circuit diagram illustrating a suitable embodiment of a low-noise amplifier circuit 52, which is operable to provide input matching and equal gain in both non-carrier aggregation mode and carrier aggregation mode. Figure 5A As shown, amplifier circuit 52 includes an input port RFIN, an input transformer circuit 60, a first amplifier 62, and a second amplifier 64. The input port RFIN can be configured to receive radio frequency signals from an antenna. (As shown in the diagram...) Figure 2 The circuitry, including one or more circuits such as filter circuits, switching circuits, antenna tuning circuits, and / or other control circuits, may optionally be coupled along the RF transmission line path 36 between the antenna and the amplifier input port RFIN.

[0059] Transformer circuit 60 may include a primary winding such as primary winding 60p and a secondary winding such as secondary winding 60s. Primary winding 60p and secondary winding 60s may sometimes be referred to as primary coil and secondary coil, respectively. Primary winding 60p may be a single-ended coil having a first terminal coupled to the input port RFIN and a second terminal coupled to a ground line (e.g., a ground power supply line providing a ground signal thereon). Secondary winding 60s may be configured to support differential signaling. Specifically, secondary coil 60s has a first (1) terminal coupled to both amplifiers 62 and 64 and a second (2) terminal also coupled to both amplifiers 62 and 64. Secondary coil 60s may have a center tap coupled to the ground line.

[0060] The first amplifier 62 may include transistors M1 to M6 forming portions of different amplifier stages within the first amplifier. Figure 5A In the example, transistors M1 through M6 are N-channel metal-oxide-semiconductor (NMOS) transistors. This is merely illustrative. If desired, at least some of transistors M1 through M6 can be implemented as P-channel metal-oxide-semiconductor (PMOS) transistors. Alternatively, all transistors M1 through M6 can be PMOS transistors. In general, any suitable type of semiconductor switching component can be used. Configurations in which transistors M1 through M6 are implemented as NMOS transistors are sometimes described as examples herein.

[0061] Transistor M1 has a source (input) terminal coupled to a first terminal of the secondary coil 60s; a gate (control) terminal; and a drain (output) terminal. The terms "source" and "drain" terminals used to refer to current-carrying terminals in a transistor are used interchangeably and are sometimes referred to as "source-drain" terminals. Therefore, the source terminal of transistor M1 can be referred to as the first source-drain terminal, and the drain terminal of transistor M1 can be referred to as the second source-drain terminal (or vice versa). Transistor M2 has a source (input) terminal coupled to a second terminal of the secondary coil 60s; a gate terminal; and a drain (output) terminal.

[0062] The gate terminal of transistor M1 can be selectively coupled to the source terminal of transistor M2 via capacitor C1 by turning the first switch 100 on and off. Similarly, the gate terminal of transistor M2 can be selectively coupled to the source terminal of transistor M1 via capacitor C2 by turning the second switch 100 on and off. Therefore, when switch 100 is activated, transistors M1 and M2 are allegedly cross-coupled via capacitors C1 and C2 (e.g., the control terminal of M1 is cross-coupled to the input terminal of M2 via C1, and the control terminal of M2 is cross-coupled to the input terminal of M1 via C2).

[0063] The gate terminal of transistor M1 can also be coupled to a common-gate voltage line, which provides a common-gate voltage Vcg via a first bias resistor Rb and a first switch 102. When transistor M1 is turned on and connected to the cross-coupled capacitors C1 and C2 (i.e., when switch 100 is on), the first switch 102 is off and the gate of transistor M1 is biased by the resistor Rb connected to the voltage Vcg. When transistor M1 is turned on and disconnected from the cross-coupled capacitors C1 and C2 (i.e., when switch 100 is off), the first switch 102 is on and the gate of transistor M1 is directly connected to the DC voltage Vcg. When transistor M1 is off, the voltage Vcg is set to 0V. The voltage Vcg can have some intermediate voltage level between the ground voltage level and the positive supply voltage level Vdd that powers the amplifier circuit 52. If desired, the common-gate voltage Vcg can also be equal to the positive supply voltage Vdd.

[0064] Similarly, the gate terminal of transistor M2 can also be coupled to the common-gate voltage line via a second bias resistor Rb and a second switch 102. When transistor M2 is turned on and connected to the cross-coupled capacitors C1 and C2 (i.e., when switch 100 is on), the second switch 102 is off, and the gate of transistor M2 is biased via the second resistor Rb connected to the voltage Vcg. When transistor M2 is turned on and disconnected from the cross-coupled capacitors C1 and C2 (i.e., when switch 100 is off), the second switch 102 is on, and the gate of transistor M2 is directly connected to the DC voltage Vcg. When transistor M2 is off, the voltage Vcg is set to 0V. Therefore, transistors M1 and M2 operating in this manner, along with the cross-coupled capacitors C1 and C2 and the associated switches 100 and 102, can sometimes be collectively referred to as a common-gate amplifier stage. A common-gate amplifier stage can be defined as an amplifier stage with an amplifying transistor whose gate terminal is coupled to a common (fixed) voltage source (e.g., Vcg). Therefore, switches 100 and 102, as well as the DC voltage level of Vcg, can be used to control the common-gate amplifier stage in the first amplifier 62.

[0065] Transistor M3 has a source (input) terminal coupled to the output terminal of transistor M1; a gate (control) terminal; and a drain (output) terminal. Similarly, transistor M4 has a source (input) terminal coupled to the output terminal of transistor M2; a gate (control) terminal; and a drain (output) terminal. The drain terminals of transistors M3 and M4 can be used as a first carrier aggregation output port CA1. A first output coil L1 can be coupled across the first carrier aggregation output port CA1. The output coil L1 can have a center tap coupled to a positive power supply line, on which a positive power supply voltage Vdd is provided.

[0066] The gate terminals of transistors M3 and M4 can be coupled to a common-source cascode bias voltage line, on which a common-source cascode bias voltage Vcascode is provided. The voltage Vcascode can have an intermediate voltage level between the ground voltage level and the positive supply voltage level Vdd that powers amplifier circuit 52. If desired, the voltage Vcascode can also be equal to the positive supply voltage Vdd. Transistors M3 and M4, coupled in series to the output of the common-source amplifier stage in this way, are sometimes collectively referred to as a common-source cascode amplifier stage or a common-source cascode amplifier stage. A common-source cascode amplifier stage can be defined as an amplifier stage with an amplifying transistor coupled to the output of a preceding amplifier stage (such as a common-gate amplifier stage) and having its gate terminal coupled to a common (fixed) voltage source (e.g., Vcascode). The common-source cascode amplifier stage with M3 and M4 can be used to increase the output impedance of amplifier 62, improve the isolation between amplifiers 62 and 64, and can optionally be used to provide different gain steps (e.g., by selectively adjusting the drive strength of transistors M3 and M4).

[0067] Transistors M5 and M6 are selectively cross-coupled with cascode transistors M3 and M4. Transistor M5 has a gate terminal coupled to the input terminal of transistor M3 via capacitor C3 and also coupled to the common-source voltage line via resistor R1, on which a common-source bias voltage Vcs is provided. Transistor M5 also has a source terminal coupled to ground and a drain terminal selectively coupled to the output terminal of transistor M4. Similarly, transistor M6 has a gate terminal coupled to the input terminal of transistor M4 via capacitor C4 and also coupled to the common-source voltage line via resistor R2 to receive the common-source voltage Vcs. Transistor M6 also has a source terminal coupled to ground and a drain terminal selectively coupled to the output terminal of transistor M3.

[0068] Transistors M5 and M6 are cross-coupled with a common-source, cascode amplifier stage. Therefore, transistors M5 and M6 operating in this manner, along with capacitors C3 and C5 and resistors R1 and R2, can sometimes be collectively referred to as a common-source amplifier stage. A common-source amplifier stage can be defined as an amplifier stage with amplifying transistors whose source terminals are coupled to a common (fixed) voltage source (e.g., ground). Transistors M5 and M6 can be turned off (disabling the common-source stage) by setting voltage Vcs to 0V, or turned on (activating the common-source stage) by setting voltage Vcs to an appropriate voltage level greater than 0V.

[0069] The structure of the second amplifier 64 may be similar to that of the first amplifier 62. The second amplifier 64 may include transistors M7 to M12 forming portions of different amplifier stages within the second amplifier. Figure 5AIn the example, transistors M7 through M12 are N-channel transistors. This is merely illustrative. If desired, at least some of transistors M7 through M12 can be implemented as P-channel transistors. Alternatively, all transistors M7 through M12 can be PMOS transistors. In general, any suitable type of semiconductor switching component can be used. Configurations in which transistors M7 through M12 are implemented as NMOS transistors are sometimes described as examples herein.

[0070] Transistor M7 has a source (input) terminal coupled to a first terminal of the secondary coil 60s; a gate (control) terminal; and a drain (output) terminal. Transistor M8 has a source (input) terminal coupled to a second terminal of the secondary coil 60s; a gate terminal; and a drain (output) terminal. The gate terminal of transistor M7 can be selectively coupled to the source terminal of transistor M8 via capacitor C5 by turning the first switch 110 on and off. Similarly, the gate terminal of transistor M8 can be selectively coupled to the source terminal of transistor M7 via capacitor C6 by turning the second switch 110 on and off. Therefore, when switch 110 is activated, transistors M7 and M8 are allegedly cross-coupled via capacitors C5 and C6 (e.g., the control terminal of M7 is cross-coupled to the input terminal of M8 via C5, and the control terminal of M8 is cross-coupled to the input terminal of M7 via C6).

[0071] The gate terminal of transistor M7 can also be coupled to the common-gate voltage line via a third resistor Rb and a first switch 112. Similarly, the gate terminal of transistor M8 can also be coupled to the common-gate voltage line via a fourth resistor Rb and a second switch 112. When transistors M7 and M8 are turned on and connected to the cross-coupled capacitors C5 and C6 (i.e., when switch 110 is on), switch 112 is off and the gates of transistors M7 and M8 are biased through resistor Rb connected to voltage Vcg. When transistors M7 and M8 are turned on and disconnected from the cross-coupled capacitors C5 and C6 (i.e., when switch 110 is off), switch 112 is on and the gates of transistors M7 to M8 are directly connected to the DC voltage Vcg. When transistors M7 to M8 are off, voltage Vcg is set to 0V. Therefore, transistors M7 and M8 operating in this manner, along with the cross-coupled capacitors C5 and C6 and the associated switches 110 and 112, can sometimes be collectively referred to as a common-gate amplifier stage. Therefore, switches 110 and 112, as well as the DC voltage level of Vcg, can be used to control the common-gate amplifier stage in the second amplifier 64.

[0072] Transistor M9 has a source (input) terminal coupled to the output terminal of transistor M7; a gate (control) terminal; and a drain (output) terminal. Similarly, transistor M10 has a source (input) terminal coupled to the output terminal of transistor M8; a gate (control) terminal; and a drain (output) terminal. The drain terminals of transistors M9 and M10 can be used as a second carrier aggregation output port CA2. A second output coil L2 can be coupled across the second carrier aggregation output port CA2. The output coil L2 can have a center tap coupled to the positive power supply line.

[0073] The gate terminals of transistors M9 and M10 can be coupled to the cascode bias voltage line. Transistors M9 and M10 coupled in series to the output of the cascode amplifier stage in this manner are sometimes collectively referred to as the cascode amplifier stage. The cascode amplifier stage with M9 and M10 can be used to increase the output impedance of amplifier 64, improve the isolation between amplifiers 64 and 62, and can optionally be used to provide different gain steps (e.g., by selectively adjusting the drive strength of transistors M9 and M10).

[0074] Transistors M11 and M12 are selectively cross-coupled with cascode transistors M9 and M10. Transistor M11 has a gate terminal coupled to the input terminal of transistor M9 via capacitor C7 and also coupled to the common-source voltage line via resistor R3. Transistor M11 also has a source terminal coupled to ground and a drain terminal selectively coupled to the output terminal of transistor M10. Similarly, transistor M12 has a gate terminal coupled to the input terminal of transistor M10 via capacitor C8 and also coupled to the common-source voltage line via resistor R4 to receive the common-source voltage Vcs. Transistor M12 also has a source terminal coupled to ground and a drain terminal selectively coupled to the output terminal of transistor M9.

[0075] Transistors M11 and M12 are cross-coupled to the common-source amplifier stage. Therefore, transistors M11 and M12 operating in this manner, along with capacitors C7 and C8 and resistors R3 and R4, can sometimes be collectively referred to as the common-source amplifier stage. Transistors M11 and M12 can be turned off (disabling the common-source amplifier stage) by setting the voltage Vcs to 0V, or turned on (activating the common-source amplifier stage) by setting the voltage Vcs to an appropriate voltage level greater than 0V.

[0076] Figure 5AThe switches 100, 102, 110, and 112 shown can be any type of semiconductor switch. For example, at least some of these switches can be implemented as metal-oxide-semiconductor field-effect transistors (e.g., NMOS or PMOS devices). Alternatively, at least some of these switches can be implemented as transmission gates (e.g., parallel-coupled N-channel and P-channel transistors). Alternatively, at least some of these switches can be implemented as bipolar junction transistors. Alternatively, at least some of these switches can be implemented as microelectromechanical systems (MEMS) switches. In general, any type of semiconductor switching device can be used.

[0077] Figure 5B This demonstrates operation in non-carrier aggregation mode. Figure 5A The circuit diagram of the low-noise amplifier circuit 52 is shown. Figure 5B As shown, the second amplifier 64 is disabled or idle in non-carrier aggregation mode. When the second amplifier 64 is disabled, current from the secondary coil 60s is fed to the first amplifier 62. In non-carrier aggregation mode, switch 100 is activated (turned on) to enable the cross-coupled capacitor connection. Switch 102 is turned off, causing the gate terminals of transistors M1 and M2 to be biased using resistor Rb. Switching the cross-coupled capacitors C1 and C2 to enable increases in the transconductance of transistors M1 and M2, and setting the real part of the input impedance of the common-gate amplifier stage (i.e., observing the impedance of the source terminals of transistors M1 and M2) to be equal to the reciprocal of the transconductance. In non-carrier aggregation mode, the common-source amplifier stage in the first amplifier 62 is turned off (e.g., by setting Vcs to 0V).

[0078] Figure 5C This is a circuit diagram showing amplifier circuit 52 operating in carrier aggregation mode. (See diagram for example.) Figure 5C As shown, both the first amplifier 62 and the second amplifier 64 are activated in carrier aggregation mode. When both amplifiers 62 and 64 are enabled, the current from the secondary transformer coil 60s is split between the first amplifier 62 and the second amplifier 64. Without other changes, splitting the current between the two amplifiers will reduce the gain of each amplifier. To help recover any potential gain that may have been lost due to current splitting, the common-source amplifier stage in the first amplifier 62 and the common-source amplifier stage in the second amplifier 64 are activated by setting Vcs to an appropriate voltage value.

[0079] Operating in this manner, the common-source amplifier stage helps increase the gain of each amplifier in carrier aggregation mode. Cross-coupling the common-source amplifier stage with the cascode amplifier stage also eliminates noise and higher-order nonlinear terms, such as the third-order nonlinearity (IM3) and / or other harmonic terms that may be generated by the cascode amplifier stage. The gain of the common-source amplifier stage should be matched to the gain of the cascode amplifier stage to ensure optimal cancellation of noise and harmonic distortion components.

[0080] When both amplifiers 62 and 64 are activated, the total input impedance, as seen from the two terminals of the secondary coil 60s, will differ from the total input impedance when only the first amplifier 62 is activated. For example, the first terminal of coil 60s will now supply current to the source terminals of both transistors M1 and M7, while the second terminal of coil 60s will supply current to the source terminals of both transistors M2 and M8. To compensate for this load variation, the cross-coupled capacitors in each of the common-gate stages are disabled by deactivating switches 100 and 110 in carrier aggregation mode. Switch 102 will be turned on to bias the gate terminals of transistors M1 and M2 to the common-gate bias voltage Vcg. Similarly, switch 112 will be turned on to bias the gate terminals of transistors M7 and M8 to voltage Vcg.

[0081] By disabling the cross-coupled capacitors and activating the common-gate bias, from the perspective of the secondary coil 60s, the total input impedance will again be equal to the reciprocal of the transconductance of transistors M1, M2, M7, and M8. The common-gate transistors M1, M2, M7, and M8 should be identical in size so that the input impedance can be maintained and matched when switching between non-carrier aggregation mode and carrier aggregation mode. Therefore, by activating the cross-coupled common-source stage and disabling the cross-coupled capacitors in the common-gate stage, the gain and input impedance of amplifier circuit 52 can be matched across both modes 70 and 72.

[0082] like Figure 5A The embodiment shown, in which the input signal is split at the input of the common-gate amplifier stage, is merely illustrative (e.g., the secondary coil 60s has terminals coupled to the two common-gate amplifier stages in amplifiers 62 and 64). Figure 6A Another embodiment is shown, in which the input signal is split at the output of a shared common-gate amplifier stage 150. The shared common-gate amplifier stage 150 may include transistors M1 and M2.

[0083] Transistor M1 has a source (input) terminal coupled to a first terminal of the secondary coil 60s; a gate (control) terminal; and a drain (output) terminal. Transistor M2 has a source (input) terminal coupled to a second terminal of the secondary coil 60s; a gate terminal; and a drain (output) terminal. The gate terminal of transistor M1 can be selectively coupled to the source terminal of transistor M2 via capacitor C1 by turning the first switch 100 on and off. Similarly, the gate terminal of transistor M2 can be selectively coupled to the source terminal of transistor M1 via capacitor C2 by turning the second switch 100 on and off. Therefore, when switch 100 is activated, transistors M1 and M2 are allegedly cross-coupled via capacitors C1 and C2 (e.g., the control terminal of M1 is cross-coupled to the input terminal of M2 via C1, and the control terminal of M2 is cross-coupled to the input terminal of M1 via C2).

[0084] The gate terminal of transistor M1 can also be coupled to a common-gate voltage line, which provides a common-gate voltage Vcg via a first bias resistor Rb and a first switch 102. When transistor M1 is turned on and connected to the cross-coupled capacitors C1 and C2 (i.e., when switch 100 is on), the first switch 102 is off and the gate of transistor M1 is biased by the resistor Rb connected to the voltage Vcg. When transistor M1 is turned on and disconnected from the cross-coupled capacitors C1 and C2 (i.e., when switch 100 is off), the first switch 102 is on and the gate of transistor M1 is directly connected to the DC voltage Vcg. When transistor M1 is off, the voltage Vcg is set to 0V. The voltage Vcg can have some intermediate voltage level between the ground voltage level and the positive supply voltage level Vdd that powers the amplifier circuit 52. If desired, the common-gate voltage Vcg can also be equal to the positive supply voltage Vdd.

[0085] Similarly, the gate terminal of transistor M2 can also be coupled to the common-gate voltage line via a second bias resistor Rb and a second switch 102. When transistor M2 is turned on and connected to the cross-coupled capacitors C1 and C2 (i.e., when switch 100 is on), the second switch 102 is off, and the gate of transistor M2 is biased via the second resistor Rb connected to voltage Vcg. When transistor M2 is turned on and disconnected from the cross-coupled capacitors C1 and C2 (i.e., when switch 100 is off), the second switch 102 is on, and the gate of transistor M2 is directly connected to the DC voltage Vcg. When transistor M2 is off, voltage Vcg is set to 0V. Therefore, transistors M1 and M2 operating in this manner, along with the cross-coupled capacitors C1 and C2 and the associated switches 100 and 102, can sometimes be collectively referred to as a common-gate amplifier stage. Thus, switches 100 and 102 and the DC voltage level of Vcg can be used to control the shared common-gate amplifier stage.

[0086] Then, the output (drain) terminal of transistor M1 can be coupled to the first amplifier 62 and the second amplifier 64. Similarly, the output (drain) terminal of transistor M2 can then be coupled to the first amplifier 62 and the second amplifier 64. The first amplifier 62 may include a first cascode amplifier stage (which includes transistors M3 and M4) and a first cross-coupled cascode amplifier stage (which includes components M5, M6, C3, C4, R1, and R2), the details of which are similar to those already combined. Figure 5A The details described are omitted for clarity. The second amplifier 62 may include a second common-source common-gate amplifier stage (which includes transistors M9 and M10) and a second cross-coupled common-source amplifier stage (which includes components M11, M12, C7, C8, R3, and R4), the details of which are similar to those already combined. Figure 5A The details of the description are omitted for clarity. Although the shared common-gate amplifier stage 150 is shown as a separate sub-circuit from amplifiers 62 and 64, amplifier stage 150 can sometimes be considered as part of the first amplifier 62 and the second amplifier 64.

[0087] Figure 6B This demonstrates operation in non-carrier aggregation mode. Figure 6A The circuit diagram of the low-noise amplifier circuit 52 is shown. Figure 6B As shown, the second amplifier 64 is disabled or idle in non-carrier aggregation mode. When the second amplifier 64 is disabled, current from the output of the shared common-gate amplifier stage 150 is fed to the first amplifier 62. In non-carrier aggregation mode, switch 100 is activated (turned on) to enable cross-coupled capacitor connections. Switching the cross-coupled capacitors C1 and C2 to enable increases in the transconductance of transistors M1 and M2, and setting the real part of the input impedance of the shared common-gate amplifier stage (i.e., the impedance of the source terminals of transistors M1 and M2) to be equal to the reciprocal of the transconductance. In non-carrier aggregation mode, the common-source amplifier stage in the first amplifier 62 is disabled (e.g., by setting Vcs to 0V).

[0088] Figure 6C This is a circuit diagram showing amplifier circuit 52 operating in carrier aggregation mode. (See diagram for example.) Figure 6CAs shown, both the first amplifier 62 and the second amplifier 64 are activated in carrier aggregation mode. When both amplifiers 62 and 64 are enabled, the current from the shared common-gate amplifier stage 150 is split between the first amplifier 62 and the second amplifier 64. Without other changes, splitting the current between the two amplifiers would reduce the gain of each amplifier. To help recover any potential gain that might have been lost due to signal splitting, the common-source amplifier stage in the first amplifier 62 and the common-source amplifier stage in the second amplifier 64 are activated by setting Vcs to an appropriate voltage level.

[0089] Operating in this manner, the common-source amplifier stage helps increase the gain of each amplifier in carrier aggregation mode. Cross-coupling the common-source amplifier stage with the cascode amplifier stage also eliminates noise and higher-order nonlinear terms, such as the third-order nonlinearity (IM3) and / or other harmonic terms that may be generated by the cascode amplifier stage. The gain of the common-source amplifier stage should be matched to the gain of the cascode amplifier stage to ensure optimal cancellation of noise and harmonic distortion components.

[0090] Because the common-gate amplifier stage 150 is shared between the first amplifier 62 and the second amplifier 64, the switch 100 can remain active in carrier aggregation mode and still maintain input impedance matching. Therefore, when switching between non-carrier aggregation mode and carrier aggregation mode (e.g., turning on switch 100 in both mode 70 and mode 72), the input impedance remains the same from the perspective of the secondary coil 60s without changing the switching configuration of the shared common-gate amplifier stage 150.

[0091] Figure 6C The example is merely illustrative, in which the cross-coupled capacitors in the shared common-gate amplifier stage remain unchanged when switching between non-carrier aggregation mode and carrier aggregation mode. Figure 6D Another implementation is shown, in which the cross-coupled capacitors in the shared common-gate amplifier stage 150 are deactivated in carrier aggregation mode. Figure 6D As shown, both the first amplifier 62 and the second amplifier 64 are activated in carrier aggregation mode. When both amplifiers 62 and 64 are enabled, the current from the shared common-gate amplifier stage 150 is split between the first amplifier 62 and the second amplifier 64. Without other changes, splitting the current between the two amplifiers would reduce the gain of each amplifier. To help recover any potential gain that might have been lost due to signal splitting, the common-source amplifier stage in the first amplifier 62 and the common-source amplifier stage in the second amplifier 64 are activated by setting Vcs to an appropriate voltage level.

[0092] Operating in this manner, the common-source amplifier stage helps increase the gain of each amplifier in carrier aggregation mode. Cross-coupling the common-source amplifier stage with the cascode amplifier stage also eliminates noise and higher-order nonlinear terms, such as the third-order nonlinearity (IM3) and / or other harmonic terms that may be generated by the cascode amplifier stage. The gain of the common-source amplifier stage should be matched to the gain of the cascode amplifier stage to ensure optimal cancellation of noise and harmonic distortion components.

[0093] exist Figure 6D In the example, switch 100 is turned off to disable the cross-coupled capacitors C1 and C2, and switch 102 is turned on to bias the gate terminals of transistors M1 and M2 to the common-gate bias voltage Vcg. Disabling the cross-coupled capacitors C1 and C2 in the shared common-gate amplifier stage 150 reduces the transconductance of transistors M1 and M2, which alters the input impedance of the common-gate amplifier stage 150. To compensate for this reduction in transconductance, the current flowing through transistors M1 and M2 can be increased by raising the common-gate bias voltage Vcg. Increasing the voltage Vcg in carrier aggregation mode helps increase the transconductance of transistors M1 and M2 and improves the linearity of amplifier circuit 52. Therefore, even with the cross-coupled capacitors disabled, increasing the common-gate voltage Vcg to increase the transconductance of transistors M1 and M2 helps maintain input impedance matching in carrier aggregation mode.

[0094] exist Figure 5A and Figure 6A In the implementation scheme, the secondary coil 60s is coupled to both the first amplifier 62 and the second amplifier 64, which are merely exemplary. Figure 7A Another embodiment of amplifier circuit 52 is shown, wherein amplifiers 62 and 64 each have their own independent secondary transformer coils. The primary coil 60p has a first terminal coupled to the input port RFIN via series capacitors Cseries and a second terminal coupled to ground. A parallel capacitor Cshunt is also coupled to the input port RFIN. Capacitors Cseries and Cshunt can sometimes be considered part of the input transformer circuit. Capacitors Cseries and Cshunt can be adjustable capacitors. Generally, adjustable capacitors can be implemented as capacitor arrays (capacitor banks), a portion of which can be activated according to a desired capacitance value. Variable capacitors are sometimes referred to as varactor tubes or varactor diodes, voltage-tuned capacitors, digitally tuned capacitors, mechanically controlled variable capacitors, combinations of these capacitors, or other types of adjustable capacitor components.

[0095] The first amplifier 62 has a first secondary coil 60s-1 inductively coupled to the primary coil 60p (see, for example, the first coupling path K1). The secondary coil 60s-1 has a first terminal coupled to the input (source) terminal of transistor M1, a second terminal coupled to the input (source) terminal of transistor M2, and a center tap coupled to ground. The first amplifier input capacitor Cin1 may be coupled across the secondary coil 60s-1 (in parallel with it). The capacitor Cin1 may also be an adjustable capacitor component with different capacitance values ​​in non-carrier aggregation mode and carrier aggregation mode. Therefore, the capacitor Cin1 may sometimes also be referred to as an adjustable input parallel capacitor.

[0096] The common-gate amplifier stage of the first amplifier 62 may have capacitors C1 and C2 that are always cross-coupled to transistors M1 and M2. The tuning capability of capacitor Cin1 eliminates the need for additional switches such as Figure 5A The requirements for switches 100 and 102 are specified. The gate terminals of M1 and M2 can be biased to voltage Vcg using corresponding bias resistors Rb. However, if desired, switches 100 and 102 can also be included as part of a common-gate amplifier stage to provide flexibility. The first amplifier 62 may also include a first common-source common-gate amplifier stage (which includes transistors M3 and M4) and a first cross-coupled common-source amplifier stage (which includes components M5, M6, C3, C4, R1, and R2), the details of which are similar to those already combined. Figure 5A The details described are omitted for clarity. If necessary, the first output capacitor Cout1 may also be coupled across the first carrier aggregation output port CA1. The capacitance of Cout1 may be the same in both non-carrier aggregation and carrier aggregation modes. The capacitor Cout11 may also be an adjustable capacitor controlled for frequency response tuning and / or channel selection purposes.

[0097] The second amplifier 64 has another secondary coil 60s-2 inductively coupled to the primary coil 60p (see, for example, the second coupling path K2). The secondary coil 60s-2 has a first terminal coupled to the input (source) terminal of transistor M7, a second terminal coupled to the input (source) terminal of transistor M8, and a center tap coupled to ground. The second amplifier input capacitor Cin2 can be coupled across the secondary coil 60s-2 (in parallel with it). Capacitor Cin2 can also be an adjustable capacitor component with different capacitance values ​​in non-carrier aggregation mode and carrier aggregation mode. Therefore, capacitor Cin2 is sometimes also referred to as an adjustable input parallel capacitor.

[0098] The common-gate amplifier stage of the second amplifier 64 may have capacitors C5 and C6 that are always cross-coupled to transistors M7 and M8. The tuning capability of capacitor Cin2 eliminates the need for additional switches such as Figure 5AThe requirements for switches 110 and 112 are specified. The gate terminals of M7 and M8 can be biased to voltage Vcg using corresponding bias resistors Rb. However, if desired, switches 110 and 112 can also be included as part of the common-gate amplifier stage in the second amplifier 64 to provide flexibility. The second amplifier 64 may also include a second common-source common-gate amplifier stage (which includes transistors M9 and M10) and a second cross-coupled common-source amplifier stage (which includes components M11, M12, C7, C8, R3, and R4), the details of which are similar to those already combined. Figure 5A The details described are omitted for clarity. If needed, the second output capacitor Cout2 can also be coupled across the second carrier aggregation output port CA2. The capacitance of Cout2 can be the same in both non-carrier aggregation and carrier aggregation modes. Capacitor Cout12 can also be an adjustable capacitor controlled for frequency response tuning and / or channel selection purposes.

[0099] Figure 7B This demonstrates operation in non-carrier aggregation mode. Figure 7A The circuit diagram of the low-noise amplifier circuit 52 is shown. Figure 7B As shown, the second amplifier 64 is disabled or idle in non-carrier aggregation mode. The current flowing through the primary coil 60p will generate an electromagnetic flux in the transformer, which will cause a corresponding current to flow through the secondary coil 60s-1. In non-carrier aggregation mode, capacitor Cin1 will be adjusted to the first capacitance value to provide the necessary input impedance matching at the input of the first amplifier 62. In non-carrier aggregation mode, the common-source amplifier stage in the first amplifier 62 is disconnected (e.g., by setting Vcs to 0V).

[0100] Figure 7C This is a circuit diagram showing amplifier circuit 52 operating in carrier aggregation mode. (See diagram for example.) Figure 7C As shown, both the first amplifier 62 and the second amplifier 64 are activated in carrier aggregation mode. When both amplifiers 62 and 64 are enabled, the current flowing through the primary coil 60p will generate an electromagnetic flux in the transformer, which will cause corresponding currents to flow through the secondary coil 60s-1 and corresponding currents to flow through the secondary coil 60s-2. In carrier aggregation mode, capacitor Cin1 will be adjusted to a second capacitance value to provide the necessary input impedance matching at the input of the first amplifier 62. Similarly, capacitor Cin2 can be adjusted to a second capacitance value to provide the necessary input impedance matching at the input of the second amplifier 64. Therefore, adjusting capacitors Cin1 and Cin2 helps maintain input impedance matching of amplifier circuit 52 when switching between non-carrier aggregation mode and carrier aggregation mode.

[0101] During carrier aggregation mode, the common-source amplifier stage in the first amplifier 62 and the common-source amplifier stage in the second amplifier 64 are activated by setting Vcs to an appropriate voltage value. Cross-coupling the common-source amplifier stages with the common-source cascode amplifier stages helps to eliminate noise and higher-order nonlinear terms, such as the third-order nonlinearity (IM3) and / or other harmonic terms that may be generated by the common-source cascode amplifier stages. The gain of the common-source amplifier stage should be matched with the gain of the common-source cascode amplifier stage to ensure optimal cancellation of noise and harmonic distortion components.

[0102] The above combination Figure 1 The methods and operations described up to Figure 7 can be performed by components of device 10 using software, firmware, and / or hardware (e.g., dedicated circuitry or hardware). The software code for performing these operations can be stored on a non-transitory computer-readable storage medium (e.g., a tangible computer-readable storage medium) stored on one or more components of device 10 (e.g., ...). Figure 1 The storage circuit 16 and / or wireless communication circuit 24). This software code may sometimes be referred to as software, data, instructions, program instructions, or code. Non-transitory computer-readable storage media may include drives, non-volatile memory such as non-volatile random access memory (NVRAM), removable flash drives or other removable media, other types of random access memory, etc. The software stored on the non-transitory computer-readable storage medium may be processed by processing circuitry on one or more components of device 10 (e.g., processing circuitry in wireless communication circuitry 24, etc.). Figure 1 The processing circuitry (e.g., 18) executes the operation. This processing circuitry may include a microprocessor, application processor, digital signal processor, central processing unit (CPU), application-specific integrated circuit (ASIC) with processing circuitry, or other processing circuitry.

[0103] According to one embodiment, an amplifier circuit is provided that is operable in carrier aggregation mode and non-carrier aggregation mode, comprising: an input port configured to receive radio frequency signals from an antenna; a transformer circuit coupled to the input port; a first amplifier coupled to the transformer circuit; and a second amplifier coupled to the transformer circuit. The first amplifier and the second amplifier each include a common-gate amplifier stage having an input coupled to the transformer circuit and an output; a common-source amplifier stage coupled to the output of the common-gate amplifier stage and coupled to a common-source bias voltage configured to activate and deactivate the common-source amplifier stage in both the carrier aggregation mode and the non-carrier aggregation mode; and an output port coupled to the output of the common-gate amplifier stage.

[0104] According to another embodiment, the transformer circuit includes a primary coil having a first terminal coupled to the input port and a second terminal coupled to a ground wire; a first adjustable capacitor coupled in series between the input port and the first terminal; and a second adjustable capacitor having a first terminal coupled to the input port and a second terminal coupled to the ground wire.

[0105] According to another embodiment, the transformer circuit includes a first stage coil coupled to the input of the common-gate amplifier stage in the first amplifier; a third adjustable capacitor coupled in parallel with the first stage coil and configured to control the input impedance of the first amplifier in both the non-carrier aggregation mode and the carrier aggregation mode; a second stage coil coupled to the input of the common-gate amplifier stage in the second amplifier; and a fourth adjustable capacitor coupled in parallel with the second stage coil and configured to control the input impedance of the second amplifier in both the non-carrier aggregation mode and the carrier aggregation mode.

[0106] According to another embodiment, the common-gate amplifier stage in each of the first amplifier and the second amplifier includes: a first transistor having a source terminal coupled to the input terminal of the common-gate amplifier stage, a drain terminal coupled to the output terminal of the common-gate amplifier stage, and a gate terminal; a second transistor having a source terminal coupled to the input terminal of the common-gate amplifier stage, a drain terminal coupled to the output terminal of the common-gate amplifier stage, and a gate terminal; a first capacitor having a first terminal coupled to the gate terminal of the first transistor and a second terminal coupled to the source terminal of the second transistor; and a second capacitor having a first terminal coupled to the gate terminal of the second transistor and a second terminal coupled to the source terminal of the first transistor.

[0107] According to another embodiment, each of the first amplifier and the second amplifier includes a cascode amplifier stage having an input terminal coupled to the output terminal of the cascode amplifier stage; an output terminal coupled to the output port; a first transistor having a source terminal coupled to the input terminal of the cascode amplifier stage, a drain terminal coupled to the output terminal of the cascode amplifier stage, and a gate terminal coupled to a cascode bias line; and a second transistor having a source terminal coupled to the input terminal of the cascode amplifier stage, a drain terminal coupled to the output terminal of the cascode amplifier stage, and a gate terminal coupled to the cascode bias line.

[0108] According to another embodiment, the common-source amplifier stage in each of the first amplifier and the second amplifier includes: a third transistor having a source terminal coupled to a ground line, a gate terminal coupled to the source terminal of the first transistor, and a drain terminal coupled to the drain terminal of the second transistor; and a fourth transistor having a source terminal coupled to a ground line, a gate terminal coupled to the source terminal of the second transistor, and a drain terminal coupled to the drain terminal of the first transistor.

[0109] According to another embodiment, the first amplifier and the second amplifier each include an output coil having a first terminal coupled to the output port, a second terminal coupled to the output port, and a center tap coupled to the positive power supply line.

[0110] According to another embodiment, the first amplifier and the second amplifier each include an adjustable output capacitor having a first terminal coupled to the first terminal of the output coil and a second terminal coupled to the second terminal of the output coil.

[0111] According to another embodiment, the transformer circuit includes a primary coil having a first terminal coupled to the input port and a second terminal coupled to a ground wire; and a secondary coil having a first terminal coupled to the first amplifier and the second amplifier and a second terminal coupled to the first amplifier and the second amplifier.

[0112] According to another embodiment, the common-gate amplifier stage in each of the first amplifier and the second amplifier includes: a first transistor having a source terminal coupled to the input terminal of the common-gate amplifier stage, a drain terminal coupled to the output terminal of the common-gate amplifier stage, and a gate terminal; a second transistor having a source terminal coupled to the input terminal of the common-gate amplifier stage, a drain terminal coupled to the output terminal of the common-gate amplifier stage, and a gate terminal; a first capacitor having a first terminal coupled to the gate terminal of the first transistor and a second terminal coupled to the source terminal of the second transistor; and a second capacitor having a first terminal coupled to the gate terminal of the second transistor and a second terminal coupled to the source terminal of the first transistor.

[0113] According to another embodiment, the common-gate amplifier stage in each of the first amplifier and the second amplifier includes: a first set of switches configured to activate and deactivate the first capacitor and the second capacitor in the non-carrier aggregation mode and the carrier aggregation mode; and a second set of switches configured to couple the gate terminal of the first transistor and the gate terminal of the second transistor to a common-gate bias line.

[0114] According to another embodiment, the amplifier circuit includes a single common-gate amplifier stage shared between a first amplifier and a second amplifier. The shared common-gate amplifier stage includes: a first transistor having a source terminal coupled to a first terminal of the secondary coil, a drain terminal coupled to the first amplifier and the second amplifier, and a gate terminal; a second transistor having a source terminal coupled to a second terminal of the secondary coil, a drain terminal coupled to the first amplifier and the second amplifier, and a gate terminal; a first capacitor having a first terminal coupled to the gate terminal of the first transistor and a second terminal coupled to the source terminal of the second transistor; a second capacitor having a first terminal coupled to the gate terminal of the second transistor and a second terminal coupled to the source terminal of the first transistor; a first set of switches configured to activate and deactivate the first capacitor and the second capacitor in both a non-carrier aggregation mode and a carrier aggregation mode; and a second set of switches configured to couple the gate terminal of the first transistor and the gate terminal of the second transistor to a common-gate bias line.

[0115] According to one embodiment, a method of operating an amplifier circuit is provided, the method comprising: receiving a radio frequency (RF) signal from an antenna via an input port; coupling the RF signal from the input port to a first amplifier via a transformer circuit; coupling the RF signal from the input port to a second amplifier via the transformer circuit; receiving the RF signal from the transformer circuit via a common-gate amplifier stage in each of the first and second amplifiers and outputting a corresponding amplified signal; receiving the amplified signal via a common-source amplifier stage in each of the first and second amplifiers and outputting a corresponding carrier aggregation output signal; and adjusting a common-source bias voltage in the common-source amplifier stage of each of the first and second amplifiers in a carrier aggregation mode and a non-carrier aggregation mode.

[0116] According to another embodiment, the method includes tuning the input impedance of the first amplifier in the carrier aggregation mode and the non-carrier aggregation mode by means of a first input capacitor coupled to the first amplifier, and tuning the input impedance of the second amplifier in the carrier aggregation mode and the non-carrier aggregation mode by means of a second input capacitor coupled to the second amplifier.

[0117] According to another embodiment, the method includes activating and deactivating a set of cross-coupled capacitors in the common-gate amplifier stage via a first set of switches in both the non-carrier aggregation mode and the carrier aggregation mode.

[0118] According to another embodiment, the method includes coupling the common-gate amplifier stage to a common-gate bias voltage in the carrier aggregation mode and the non-carrier aggregation mode via a second set of switches, and decoupling the common-gate amplifier stage from the common-gate bias voltage.

[0119] According to one embodiment, an electronic device capable of operating in carrier aggregation mode and non-carrier aggregation mode is provided. The electronic device includes: an antenna configured to receive a radio frequency (RF) signal; a transceiver configured to generate a baseband signal based on the RF signal; a baseband processor configured to receive the baseband signal; and an amplifier circuit configured to receive the RF signal from the antenna and output a corresponding amplified signal to the transceiver. The amplifier circuit has an input port; a transformer circuit coupled to the input port; a common-gate amplifier stage having an input coupled to the transformer circuit and an output; a common-source amplifier stage coupled to the output of the common-gate amplifier stage and coupled to a common-source bias voltage configured to control the common-source amplifier stage in both the non-carrier aggregation mode and the carrier aggregation mode; and an output port coupled to the output of the common-gate amplifier stage.

[0120] According to another embodiment, the amplifier circuit includes an additional common-gate amplifier stage having an input coupled to the transformer circuit and an output; and an additional common-source amplifier stage coupled to the output of the additional common-gate amplifier stage and coupled to the common-source bias voltage.

[0121] According to another embodiment, the transformer circuit includes: a primary coil having a first terminal coupled to the input port and a second terminal coupled to ground; a secondary coil coupled to the input of the common-gate amplifier stage; and an amplifier circuit including an adjustable capacitor coupled in parallel with the secondary coil and configured to tune the input impedance of the common-gate amplifier stage in both the non-carrier aggregation mode and the carrier aggregation mode.

[0122] According to another embodiment, the amplifier circuit includes a common-source cascode amplifier stage having an input terminal coupled to the output terminal of the common-source cascode amplifier stage and an output terminal coupled to the output terminal, and the common-source cascode amplifier stage includes: a first transistor having a source terminal coupled to the transformer circuit, a drain terminal coupled to the input terminal of the common-source cascode amplifier stage, and a gate terminal; a second transistor having a source terminal coupled to the transformer circuit, a drain terminal coupled to the input terminal of the common-source cascode amplifier stage, and a gate terminal; and a first capacitor. The capacitor has a first terminal coupled to the gate terminal of the first transistor and a second terminal coupled to the source terminal of the second transistor; a second capacitor has a first terminal coupled to the gate terminal of the second transistor and a second terminal coupled to the source terminal of the first transistor; a first set of switches configured to activate and deactivate the first capacitor and the second capacitor in the non-carrier aggregation mode and the carrier aggregation mode; and a second set of switches configured to couple the gate terminal of the first transistor and the gate terminal of the second transistor to a common gate bias line.

[0123] The foregoing is merely illustrative and various modifications can be made to the described implementation scheme. The aforementioned implementation scheme can be implemented independently or in any combination.

Claims

1. An amplifier circuit, the amplifier circuit comprising: an input port configured to receive a radio frequency signal from an antenna; a transformer circuit coupled to the input port; a first amplifier coupled to the transformer circuit; and a second amplifier coupled to the transformer circuit, the first and second amplifiers each comprising: a first amplifier stage having an input coupled to the transformer circuit and having an output, a second amplifier stage coupled to the output of the first amplifier stage and to a bias voltage, the bias voltage configured to activate and deactivate the second amplifier stage, and an output port coupled to the output of the first amplifier stage. the first amplifier stage comprises a common-gate amplifier stage.

2. The amplifier circuit of claim 1, wherein, the second amplifier stage comprises a common-source amplifier stage.

3. The amplifier circuit of claim 2, wherein, the second amplifier stage comprises a common-source amplifier stage.

4. The amplifier circuit of claim 1, wherein, the bias voltage is configured to activate and deactivate the second amplifier stage in a carrier aggregation mode and a non-carrier aggregation mode.

5. The amplifier circuit of claim 1, wherein, the transformer circuit comprises:

6. The amplifier circuit of claim 1, wherein, a primary coil having a first terminal coupled to the input port and a second terminal coupled to a ground line; a first adjustable capacitor coupled in series between the input port and the first terminal; and a second adjustable capacitor having a first terminal coupled to the input port and a second terminal coupled to the ground line. the transformer circuit comprises:

7. The amplifier circuit of claim 6, wherein, a first secondary coil coupled to the input of a first amplifier stage in the first amplifier; a third adjustable capacitor coupled in parallel with the first secondary coil and configured to control an input impedance of the first amplifier; a second secondary coil coupled to the input of a first amplifier stage in the second amplifier; and a fourth adjustable capacitor coupled in parallel with the second secondary coil and configured to control an input impedance of the second amplifier. the first amplifier stage in each of the first and second amplifiers comprises:

8. The amplifier circuit of claim 1, wherein, a first transistor having a source terminal coupled to the input of the first amplifier stage, a drain terminal coupled to the output of the first amplifier stage, and a gate terminal; a second transistor having a source terminal coupled to the input of the first amplifier stage, a drain terminal coupled to the output of the first amplifier stage, and a gate terminal; a first capacitor having a first terminal coupled to the gate terminal of the first transistor and having a second terminal coupled to the source terminal of the second transistor; and a second capacitor having a first terminal coupled to the gate terminal of the second transistor and having a second terminal coupled to the source terminal of the first transistor. ​ 9. The amplifier circuit of claim 1, wherein, Each of the first and second amplifiers includes a third amplifier stage, the third amplifier stage being a cascode amplifier stage, the cascode amplifier stage having: an input coupled with an output of the first amplifier stage; an output coupled to the output port; a first transistor having a source terminal coupled with an input of the cascode amplifier stage, a drain terminal coupled with an output of the cascode amplifier stage, and a gate terminal coupled to a cascode bias line; and a second transistor having a source terminal coupled with the input of the cascode amplifier stage, a drain terminal coupled with the output of the cascode amplifier stage, and a gate terminal coupled to the cascode bias line.

10. The amplifier circuit of claim 1, wherein, The second amplifier stage in each of the first and second amplifiers includes: a first transistor having a source terminal coupled to a ground line, a gate terminal coupled with an output of the first amplifier stage, and a drain terminal coupled with the output; and a second transistor having a source terminal coupled to the ground line, a gate terminal coupled with the output of the first amplifier stage, and a drain terminal coupled with the output.

11. The amplifier circuit of claim 1, wherein, Each of the first and second amplifiers includes: an output coil having a first terminal coupled to the output port, a second terminal coupled to the output port, and a center tap coupled to a positive power line.

12. The amplifier circuit of claim 11, wherein, Each of the first and second amplifiers includes: an adjustable output capacitor having a first terminal coupled with the first terminal of the output coil and a second terminal coupled with the second terminal of the output coil.

13. A method of operating an amplifier circuit, comprising: receiving a radio frequency signal from an antenna through an input port; coupling the radio frequency signal from the input port to a first amplifier through a transformer circuit; coupling the radio frequency signal from the input port to a second amplifier through the transformer circuit; receiving the radio frequency signal from the transformer circuit through a first amplifier stage in each of the first and second amplifiers and outputting a corresponding amplified signal; receiving the amplified signal through a second amplifier stage in each of the first and second amplifiers and outputting a corresponding output signal; and adjusting a bias voltage in the second amplifier stage in each of the first and second amplifiers.

14. The method of claim 13, wherein, The first amplifier stage includes a cascode amplifier stage.

15. The method of claim 14, wherein, The second amplifier stage includes a common source amplifier stage.

16. The method of claim 13, wherein, The second amplifier stage includes a common source amplifier stage.

17. The method of claim 13, wherein, Adjusting the bias voltage includes adjusting the bias voltage in the second amplifier stage in each of the first and second amplifiers in a carrier aggregation mode and a non-carrier aggregation mode.

18. An electronic device capable of operating in a first mode and a second mode, comprising: an antenna configured to receive a radio frequency signal; a transceiver configured to generate a baseband signal based on the radio frequency signal; a baseband processor configured to receive the baseband signal; and an amplifier circuit configured to receive the radio frequency signal from the antenna and output a corresponding amplified signal to the transceiver, the amplifier circuit having: an input port, a transformer circuit coupled to the input port, a first amplifier stage having an input coupled to the transformer circuit and having an output, a second amplifier stage coupled with the output of the first amplifier stage and coupled to a bias voltage, the bias voltage configured to control the second amplifier stage in the first mode and the second mode, and an output port coupled with the output of the first amplifier stage.

19. The electronic device of claim 18, wherein, The first amplifier stage includes a common gate amplifier stage, and wherein the second amplifier stage includes a common source amplifier stage.

20. The electronic device of claim 18, wherein, The first mode includes a carrier aggregation mode, and wherein the second mode includes a non-carrier aggregation mode.

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