A multi-discrete current source low noise JFET differential shunt amplifier

Abstract

The present application relates to the field of geophysical exploration equipment, and relates to a multi-discrete current source low-noise JFET differential parallel amplifier, which comprises a JFET primary amplifier circuit and an IOA secondary amplifier circuit; the JFET primary amplifier circuit comprises a common-source amplifier circuit composed of two groups of JFET pairs in parallel, the drain of each group of JFET pairs is connected to the positive pole of a lithium battery, the source of the JFET pair is connected to the negative pole of the lithium battery through an NPN-type BJT, the gate of the JFET pair is connected to the output signal of one side of a differential coil, and the drain of the JFET pair serves as an output; the IOA secondary amplifier circuit adopts a subtractor structure and is connected to the two outputs of the JFET primary amplifier circuit through two input ends. Discrete current sources are used to supply power to two pairs of parallel JFETs, the parameter difference between JFET pairs is reduced, parallel method is used to reduce the background noise of JFET devices, and the advantages of low-noise amplification of JFET devices are exerted.

Description

Technical Field

[0001] This invention relates to the field of geophysical exploration equipment, and more specifically, to a low-noise JFET differential parallel amplifier with multiple discrete current sources. Background Technology

[0002] The Transient Electronmagnetic Method (TEM) is a geophysical exploration method based on the law of electromagnetic induction. Due to its sensitivity to low-resistivity bodies, it has become the preferred method for geological structural exploration, mineral exploration, and other geological problems. Miniaturizing and lightweighting TEM systems facilitates deployment in urban areas. Compared to traditional TEM systems, the reduced size of urban TEM systems limits the emitted magnetic moment, resulting in weak secondary field responses from deep geological bodies. Furthermore, urban noise interference leads to low signal-to-noise ratios in the secondary field signals acquired by the instrument, affecting subsequent interpretation of deep data. Therefore, urban TEM systems require low-noise preamplifiers for amplification, providing high-quality data for subsequent processing and interpretation.

[0003] The paper "Low-Noise Optimization Design of Conditioning Circuit for Aircraft ZTEM Magnetic Sensor" published in the Journal of Instrumentation by Wang Yanzhang, Shi Jiaqing, Shi Hongyu, et al., discloses a low-noise signal conditioning circuit built using low-noise parallel JFET devices. This circuit exhibits good coil adaptability and excellent noise characteristics within the TEM signal frequency band, with the lowest noise level being only [insert value here]. The use of JFET differential parallel technology offers a new approach to low-noise optimization design of preamplifiers. Parallel design effectively reduces input voltage noise, and theoretically, it also makes it possible to design amplifier circuits approaching noise limits. However, in reality, due to limitations in semiconductor epitaxy, diffusion, oxidation, and photolithography processes, the parameters of JFET devices of the same model vary significantly. When multiple JFET devices are differentially paralleled, they are difficult to match, leading to problems such as uneven current distribution and failing to achieve ideal amplification. To mitigate this problem of unreliable operation caused by parameter differences, JFET manufacturers have implemented paired-transistor designs, containing a pair of JFET transistors with essentially identical parameters within a single device. This design ensures the design of JFET-based differential amplifier circuits, but it still cannot fundamentally solve the problem for differential parallel designs. Moreover, measurements of JFET devices of the same model reveal that the parameter differences between most single or paired JFET devices are substantial. Therefore, new technologies are urgently needed to eliminate the problem of large parameter differences between JFET devices of the same model that prevent differential parallel amplification. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a low-noise JFET differential parallel amplifier with multiple discrete current sources, which uses discrete current sources to power two pairs of parallel JFETs, reduces the parameter differences between JFET pairs, and uses the parallel method to reduce the noise floor of JFET devices and give full play to the advantages of low-noise amplification of JFET devices.

[0005] This invention is implemented as follows:

[0006] A low-noise JFET differential parallel amplifier with multiple discrete current sources includes a JFET first-stage amplifier circuit and an IOA second-stage amplifier circuit.

[0007] The JFET primary amplifier circuit includes a common-source amplifier circuit composed of two sets of JFET pairs connected in parallel. The drain of each JFET pair is connected to the positive terminal of the lithium battery, and the source of the JFET pair is connected to the negative terminal of the lithium battery through an NPN type BJT. The gates of the JFET pairs are connected to one side of the differential coil to output the signal, and the drain of the JFET pair serves as the output.

[0008] The IOA secondary amplifier circuit adopts a subtractor structure, and its two input terminals are connected to the two outputs of the JFET primary amplifier circuit.

[0009] Furthermore, the JFET pair includes two JFET devices. The drain of the JFET devices is connected to the positive terminal of the lithium battery through a first resistor. The source of the two JFET devices is connected to the collector of the NPN type BJT through a second resistor. The emitter of the NPN type BJT is connected to the negative terminal of the lithium battery through a third resistor. The second resistor, the NPN type BJT, and the third resistor constitute a constant current source.

[0010] Furthermore, the constant current source is connected in parallel with a first capacitor.

[0011] Furthermore, the IOA secondary amplifier circuit includes a low-noise IOA. Both input terminals of the low-noise IOA are connected to one side of the signal output of the JFET primary amplifier circuit through a fourth resistor and a second capacitor in series. A fifth resistor is connected between the inverting input terminal and the output terminal of the low-noise IOA. The non-inverting input terminal of the low-noise IOA is grounded through a sixth resistor.

[0012] The JFET first-stage amplifier circuit uses two low-noise JFET pairs and a current source composed of a pair of NPN BJTs to set the JFET's quiescent operating point. This ensures the JFET remains stable at its minimum noise operating point, maximizing its noise performance and preventing quiescent operating point shifts and amplification differences caused by uneven current distribution between the two arms in a long-tailed differential structure due to differences in device parameters. The high input impedance of the JFET facilitates impedance matching of the front-end coil, and the differential structure allows for the use of a front-end differential coil to suppress coil noise. Furthermore, the JFET first-stage amplifier circuit can also function as a JFET parameter detection circuit, screening out JFETs with high parameter consistency at the desired quiescent operating point for JFET pairing.

[0013] The IOA two-stage amplifier circuit uses a subtractor structure and is equipped with a CBB capacitor to eliminate the DC bias at the output of the first-stage amplifier circuit, thereby improving signal gain.

[0014] Compared with the prior art, the beneficial effects of this invention are as follows:

[0015] This invention proposes a low-noise JFET differential parallel amplifier with multiple discrete current sources, designed to achieve a low-noise amplifier circuit with a noise floor approaching the noise limit. Differential design reduces sensor common-mode noise, and parallel design effectively reduces the amplifier's equivalent input voltage noise. The newly designed amplifier achieves an equivalent input noise level of [missing information]. @1kHz.

[0016] To address the problem of unreliable operation caused by the large parameter dispersion of current JFET devices (single or paired transistors) of the same model, resulting in static operating point offset, this invention proposes a multi-discrete current source design scheme. Firstly, by modulating the parameters of the independent current source circuits, the core parameter I of the JFET is controlled. D V GS V DS First, each JFET is kept at the minimum noise quiescent operating point. Second, by connecting capacitors C1 and C2 in parallel on both sides of the constant current source, the AC loop of the JFET common-source amplifier circuit is changed, which overcomes the limitation of the constant current source internal resistance on the source resistance of the JFET circuit, improves the amplification factor of the common-source amplifier circuit, and ensures that each JFET works in a reliable amplification state, thus solving the problem of unreliable operation due to inconsistent JFET parameters. Attached Figure Description

[0017] Figure 1 A circuit block diagram of the low-noise amplifier of the present invention is shown;

[0018] Figure 2 The circuit structure diagram of the low-noise amplifier of the present invention is shown;

[0019] Figure 3An AC equivalent model of the first-stage amplifier circuit of the low-noise amplifier of the present invention is shown;

[0020] Figure 4 The system function of the low-noise amplifier of the present invention is shown;

[0021] Figure 5 The equivalent input noise curve of the low-noise amplifier of the present invention is shown;

[0022] Figure 6 The measured equivalent input noise of the discrete current source low-noise JFET differential parallel amplifier of the present invention is shown. Detailed Implementation

[0023] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0024] This invention provides a low-noise JFET differential amplifier circuit with multiple discrete current sources, the circuit block diagram and circuit structure diagram are as follows: Figure 1 and Figure 2 As shown.

[0025] A low-noise JFET differential parallel amplifier with multiple discrete current sources includes a JFET first-stage amplifier circuit and an IOA second-stage amplifier circuit;

[0026] The JFET primary amplifier circuit includes a common-source amplifier circuit composed of two sets of JFET pairs connected in parallel. The drain of each JFET pair is connected to the positive terminal of the lithium battery, and the source of the JFET pair is connected to the negative terminal of the lithium battery through an NPN type BJT. The gates of the JFET pairs are connected to one side of the differential coil to output the signal, and the drain of the JFET pair serves as the output.

[0027] The IOA second-stage amplifier circuit uses a subtractor structure, with its two input terminals connected to the two outputs of the JFET first-stage amplifier circuit.

[0028] According to Fris's formula as shown in equation (1)

[0029]

[0030] Where F is the total noise factor of the circuit, F1 is the noise factor of the first-stage amplifier circuit, K1 is the amplification factor of the first-stage amplifier circuit, and F2 is the noise factor of the second-stage amplifier circuit. From equation (1), it can be seen that for a cascaded amplifier circuit, the noise floor of the first-stage amplifier circuit determines the overall noise level of the amplifier circuit. Compared with the low-noise IOA amplifier circuit, the low-noise JFET amplifier circuit has a lower noise floor. Since the JFET only forms a conductive channel between the drain and source when it is working, and only a voltage is applied between the gate and drain and between the gate and source to control the conductive channel between the drain and source, there is almost no conducting current between the gate and drain and between the gate and source. Therefore, the JFET has the characteristics of "low voltage noise and negligible current noise", and its large source impedance can be adapted to various differential coils. Therefore, the multi-current-source low-noise JFET differential amplifier circuit of the present invention includes a JFET amplifier circuit and an IOA amplifier circuit, and the JFET amplifier circuit with a lower noise level and a larger source impedance is used as the first-stage amplifier circuit, and the IOA amplifier circuit is used for the second-stage amplification.

[0031] To further reduce the noise floor of the JFET and improve the noise performance of the differential amplifier circuit, a parallel connection method is required. The voltage noise and current noise after parallel connection are shown in equations (2) and (3).

[0032]

[0033]

[0034] Where e n For the voltage noise of each device, i n The current noise for each device, M is the number of parallel connections, e ntot Let i be the equivalent voltage noise after M devices are connected in parallel. ntot This is the equivalent current noise after M devices are connected in parallel. After the devices are connected in parallel, their voltage noise will follow N... 1 / 2 Reduce, current noise according to N 1 / 2 Increase. Due to the operating principle of JFET devices, during amplification, there is only a conduction current between the drain and source. The conduction channel width is controlled only by a voltage applied between the gate and source, and between the gate and drain. The conduction current between the gate and the source and drain is below pA. Therefore, the current noise of JFETs can be ignored. Considering only the device voltage noise, using a parallel connection method for JFET amplifier circuits can reduce their inherent noise floor.

[0035] The JFET primary amplifier circuit includes JFET devices J1, J2, J3, and J4. JFET devices J1 and J2 are integrated in the same JFET pair, while JFET devices J3 and J4 are integrated in another JFET pair. Other components include NPN BJTs T1 and T2, resistors R1, R2, R3, R4, R5, and R6, and capacitors C1 and C2. Differential amplification is achieved by connecting two common-source amplifier circuits in parallel. One common-source amplifier circuit consists of resistor R1, JFET devices J1 and J2, resistor R3, NPN BJT T1, resistor R5, and capacitor C1. The other common-source amplifier circuit consists of resistor R2, JFET devices J3 and J4, resistor R4, NPN BJT T2, resistor R6, and capacitor C2. The two circuits are symmetrical.

[0036] One end of resistor R1 is connected to the positive terminal of the lithium battery, and the other end is connected to the drain of JFET devices J1 and J2. The gates of JFET devices J1 and J2 are connected together to one side of the differential coil to output the signal. The source is connected to one end of resistor R3, and the drain serves as the signal output terminal of the first-stage amplifier circuit of the JFET. Resistors R3, NPN type BJT T1, and resistor R5 constitute a constant current source. One end of resistor R3 is connected to the collector of NPN type BJT T1, and one end of resistor R5 is connected to the negative terminal of the lithium battery. The base of NPN type BJT T1 is grounded. Capacitor C1 is connected in parallel with the constant current source, one end of which is connected to resistor R3, the source of JFET devices J1 and JFET devices J2, and the other end of which is connected to resistor R5 and the negative terminal of the lithium battery.

[0037] The JFET common-source amplifier circuit on the other side is connected in the same way:

[0038] Resistor R2 is connected at one end to the positive terminal of the lithium battery and at the other end to the drain of JFET devices J4 and J3. The gates of JFET devices J4 and J3 are connected together to one side of the differential coil to output the signal. Their sources are connected to one end of resistor R2, and their drains serve as the signal output terminal of the first-stage amplifier circuit of the JFET. Resistor R4, NPN BJT T2, and resistor R6 form a constant current source. One end of resistor R4 is connected to the collector of NPN BJT T2, and one end of resistor R6 is connected to the negative terminal of the lithium battery. The base of NPN BJT T2 is grounded. Capacitor C2 is connected in parallel with the constant current source, with one end connected to resistor R4, the source of JFET devices J4 and J3, and the other end connected to resistor R6 and the negative terminal of the lithium battery.

[0039] In a JFET primary amplifier circuit, two low-noise JFET pairs, along with a pair of NPN BJTs forming a current source, achieve the quiescent operating point setting of the JFETs, solving the problem of V in a JFET common-source amplifier circuit.DS V GS I D The problems include the interdependence of three parameters and the discrepancy between the theoretical and actual static operating points of the circuit. Among these, I... D The calculation formula is shown in equation (4):

[0040]

[0041] Where V PN VBJT is the forward conduction voltage of the PN junction, and V- is the negative terminal voltage of the power supply. VBJT is set in conjunction with a resistor. DS With V GS This ensures the JFET operates stably at its minimum noise quiescent operating point. Adjusting I... D V DS V GS To achieve the required quiescent operating point, ensuring the JFET remains stable at its minimum noise operating point and maximizing its noise performance, this design resolves the quiescent operating point offset issue in long-tailed differential circuits caused by the inherent parameter dispersion of JFETs due to device defects. Furthermore, the JFET first-stage amplifier circuit has a simple structure and easy parameter settings, making it suitable for JFET pairing.

[0042] Although the JFET first-stage amplifier circuit adopts the form of a common-source amplifier circuit, making its quiescent operating point setting the same as that of the long-tailed differential structure, the long-tailed differential structure avoids the influence of the tail resistance or current source on the amplification factor in the AC path. Its amplification factor is determined only by the JFET transconductance and the resistance between the power supply and drain. In contrast, the common-source amplifier circuit cannot avoid the limitation of the source-power supply resistance on the amplification factor in the AC loop, especially when using a constant current source to stabilize the current I. D This leads to the connection of the constant current source's internal resistance, further limiting the amplification factor of the common-source amplifier circuit. Therefore, using... Figure 3 The method shown involves connecting the stable CBB capacitors C1 and C2 in parallel between the source of the JFET and the negative terminal of the battery, thereby changing the AC loop and small-signal model of the JFET common-source amplifier circuit. The amplification factor is shown in equation (5).

[0043] H1(w)=-g m R1 = -g m R2 (5)

[0044] Where g m By using the JFET transconductance and connecting a CBB capacitor in parallel, the limitation of the constant current source internal resistance on the circuit amplification factor is eliminated. Its amplification factor is consistent with that of the traditional long-tail differential structure, achieving low-noise amplification of the signal received by the differential coil and maintaining the overall noise of the amplifier at an extremely low level.

[0045] The IOA secondary amplifier circuit adopts a subtraction circuit structure, including low-noise IOA A1, capacitor C3, capacitor C4, resistor R7, resistor R8, resistor R9, and resistor R. 10 One end of capacitor C3 is connected to the signal output of one stage of the JFET amplifier circuit, and the other end is connected to resistor R7. The other end of resistor R7 is connected to the inverting input terminal of low-noise IOA A1 and resistor R9, and the other end of resistor R9 is connected to the signal output terminal of low-noise IOA A1 as the output terminal of the second stage amplifier. One end of capacitor C4 is connected to the signal output of one stage of the JFET amplifier circuit, and the other end is connected to resistor R8. The other end of resistor R8 is connected to the non-inverting input terminal of low-noise IOA A1 and resistor R... 10 Connected, resistor R 10 The other side is grounded. The power supply pins of the low-noise IOA A1 are connected to the positive and negative terminals of the lithium battery, respectively. The subtractor structure of the second-stage circuit, together with the capacitor, forms a low-pass filter. This further amplifies the differential coil induced signal amplified by the low-noise amplification of the previous stage circuit, eliminates residual common-mode noise in the circuit, and improves the signal-to-noise ratio.

[0046] At this point, the system function of the multi-discrete current-source low-noise JFET differential parallel amplifier is as shown in equation (6):

[0047]

[0048] System transfer function such as Figure 4 As shown.

[0049] Example

[0050] Step 1: After connecting the circuit according to the specific implementation method, firstly, pair the JFET transistors using the first-stage amplifier circuit and select parameter V. DS V GS I D JFET pairs with similar parameters.

[0051] Step 2: According to the JFET parameter table, adjust resistors R5 and R6 in the constant current source circuit to adjust I... D Set to 5mA. With resistor R1 and resistor R2 set to V... DS V GS size.

[0052] Step 3: Connect the JFET pairs from the same batch into the circuit sequentially and record their V values. DS V GS Table 1 shows the parameter statistics of the low-noise JFET pair IF3602 in the same batch. The integrated JFETs in the JFET pair have been selected and matched, and their parameter differences are small. However, the parameter differences between devices are large. If you want to pursue a lower circuit noise floor, you need to screen and match devices based on the test results.

[0053] Table 1

[0054] Serial Number Internal JFET <![CDATA[I D ]]> <![CDATA[V DS ]]> <![CDATA[V GS ]]> 1 A 5mA 7.39V -1.017V B 5mA 7.31V -1.014V 2 A 5mA 7.44V -0.655V B 5mA 7.48V -0.649V 3 A 5mA 7.39V -0.983V B 5mA 7.34V -0.957V 4 A 5mA 7.42V -1.000V B 5mA 7.36V -0.995V 5 A 5mA 7.38V -0.929V B 5mA 7.34V -0.926V

[0055] Step 4: Adjust the parameters of R1 and R2 according to the selected two JFET pairs, so that their VF is equal to the VF of the JFET pairs. DS V GS The parameters are almost identical.

[0056] Step 5: After adjusting the quiescent operating point as in Step 4, apply input signals with an amplitude of 20mV, a frequency of 1kHz, and a phase difference of 180° to the amplifier's Sig+ and Sig- respectively. Observe the output signal amplitude and calculate the actual amplification factor. Due to the transconductance g... m Since the static operating point is related to the device's internal parameters and cannot be guaranteed to be completely consistent, and the resistors R1 and R2 differ when the static operating point is adjusted in the actual circuit, the measured amplification factor can verify the amplification capability and correct the system transfer function for subsequent equivalent input noise conversion.

[0057] Step 6: After completing the test of the first-stage amplifier circuit in Step 5, connect the second-stage amplifier circuit (IOA) and test the output signal.

[0058] Step 7: Short-circuit the input terminals of the low-noise JFET differential parallel amplifier with multiple discrete current sources. Measure the output noise using a dynamic signal analyzer, or collect the output data using a data acquisition card. The output noise can also be obtained by calculating the output power spectral density. Combined with the tested and corrected system transfer function, the equivalent input noise can be obtained. Figure 5 The equivalent input noise curve obtained from LTspice software simulation. Figure 6 The measured equivalent input noise of a low-noise JFET differential parallel amplifier with multiple discrete current sources.

[0059] Through simulation and actual measurement, the noise level of this invention is maintained at the nV level, with an equivalent input noise at 1kHz. This study demonstrates that the parallel method can significantly reduce the circuit's inherent noise. The multi-discrete current source power supply scheme can correct for the impact of device discreteness on the circuit results, making the simulation results consistent with the measured results. This is compared to the noise levels of the imported LT1028 integrated operational amplifier. The noise level of this invention is significantly reduced.

[0060] In summary, the multi-discrete current-source low-noise JFET differential amplifier circuit of this invention features high gain, low noise, and high stability. This invention can be directly applied to urban TEM receiving systems to achieve low-noise amplification of urban TEM signals, and can also be used in other TEM receiving systems. The circuit structure is simple, with low dependence on JFET device parameters and paired instruments, and possesses good economic and military prospects.

[0061] The above description of the present invention is not restrictive. If those skilled in the art are inspired by it and make other structural modifications and embodiments of the present invention without departing from the protection of the claims of the present invention, they shall all fall within the protection scope of the present invention.

Claims

1. A multiple discrete current source low noise JFET differential shunt amplifier characterized by, The JFET first-stage amplification circuit and the IOA second-stage amplification circuit are included; The JFET first-stage amplification circuit includes two groups of JFET pairs connected in parallel to form a common-source amplification circuit, the drain of each group of JFET pairs is connected to the positive pole of a lithium battery, the source of the JFET pairs is connected to the negative pole of the lithium battery through an NPN-type BJT, the gate of the JFET pairs is connected to the output signal of one side of a differential coil, and the drain of the JFET pairs is used as an output; The IOA second-stage amplification circuit adopts a subtracter structure, and two outputs of the JFET first-stage amplification circuit are connected to two input ends of the IOA second-stage amplification circuit; The JFET pair includes two JFET devices, the drain of the JFET devices is connected to the positive pole of the lithium battery through a first resistor, the source of the two JFET devices is connected to the collector of an NPN-type BJT through a second resistor, the emitter of the NPN-type BJT is connected to the negative pole of the lithium battery through a third resistor, and the second resistor, the NPN-type BJT and the third resistor form a constant current source; The constant current source is connected in parallel with a first capacitor.

2. The multiple discrete current source low noise JFET differential shunt amplifier of claim 1, wherein, The IOA second-stage amplification circuit includes a low-noise IOA, two input ends of the low-noise IOA are connected to the signal output of one side of the JFET first-stage amplification circuit through a fourth resistor and a second capacitor connected in series, a fifth resistor is connected between the reverse input end and the output end of the low-noise IOA, and the same input end of the low-noise IOA is connected to the ground through a sixth resistor.

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