Data access control method, memory controller of memory device, memory device and electronic device

Abstract

The invention relates to a method for controlling data access of a memory device by means of prediction information, a memory controller of the memory device, the memory device and an electronic device. The method includes: receiving a plurality of host commands from a host device to perform data access including data reading to a non-volatile memory according to the plurality of host commands; and performing a read parameter learning procedure to generate predicted data that predicts a read voltage parameter offset for adjustment of the read voltage parameter for maintaining correctness of the data read, e.g., for example, the read voltage parameter offset. Scanning the optimal value and adding the latest information containing the optimal value into one data set of one or more data sets in at least one read voltage control database; performing local linear regression according to the data set to update a read voltage prediction function corresponding to the read voltage prediction model; and generating or updating prediction data according to the read voltage prediction function.

Description

Technical Field

[0001] The present invention relates to memory control, and more particularly to a method and a related device for controlling data access of a memory device by using prediction information. Background Art

[0002] A memory device may include flash memory for storing data, and access management for the flash memory is quite complex. For example, the memory device may be a memory card, a solid state drive (SSD), or an embedded storage device (e.g., an embedded storage device that complies with the universal flash storage (UFS) specification). When manufacturers try to implement certain features of memory devices according to existing specifications, certain problems may occur. In particular, in response to host requests, the memory device may spend too much time performing certain internal operations of the memory device, which leads to overall performance degradation. Prior art attempts to solve this problem, however, may introduce more problems (e.g., certain side effects), and therefore, an innovative method and related architecture are needed to solve these problems without introducing side effects or in a manner that is less likely to introduce side effects. Summary of the invention

[0003] Therefore, one of the objectives of the present invention is to provide a method and a related device for controlling data access of a memory device by using prediction information to solve the above-mentioned problem.

[0004] At least one embodiment of the present invention provides a method for controlling data access of a memory device by using prediction information, wherein the method can be applied to a memory controller of the memory device, the memory device can include the memory controller and a non-volatile memory, and the non-volatile memory can include at least one non-volatile memory element (e.g., one or more non-volatile memory elements). The method can include: receiving a plurality of host commands from a host device for performing data access to the non-volatile memory according to the plurality of host commands, wherein the data access includes data reading; and performing a read parameter learning procedure to generate prediction data of a predicted read voltage parameter offset for adjusting a read voltage parameter, so as to maintain the accuracy of data reading. For example, a read parameter learning procedure may include: scanning an optimal value for adjustment of a read voltage parameter, and adding the latest information containing the optimal value to a data set among one or more data sets in at least one read voltage control database; performing local linear regression based on the data set to update a read voltage prediction function corresponding to a read voltage prediction model so as to fit a local curve of the predicted read voltage parameter offset to a corresponding local trend of the data set; and generating or updating prediction data of the predicted read voltage parameter offset based on the read voltage prediction function.

[0005] In addition to the above method, the present invention also provides a memory controller of a memory device, wherein the memory device includes a memory controller and a non-volatile memory, and the non-volatile memory may include at least one non-volatile memory element (e.g., one or more non-volatile memory elements). In addition, the memory controller includes a processing circuit and a transmission interface circuit, wherein the processing circuit is used to control the memory controller according to a plurality of host commands from a host device to allow the host device to access the non-volatile memory through the memory controller, and the transmission interface circuit is used to communicate with the host device. In addition, the memory controller receives a plurality of host commands from the host device through the transmission interface circuit of the memory controller for data access to the non-volatile memory according to the plurality of host commands, wherein the data access includes data reading; and the memory controller performs a read parameter learning procedure to generate a prediction data of a predicted read voltage parameter offset for adjusting a read voltage parameter, so as to maintain the correctness of data reading. For example, a read parameter learning procedure may include: scanning an optimal value for adjustment of a read voltage parameter, and adding the latest information containing the optimal value to a data set among one or more data sets in at least one read voltage control database; performing local linear regression based on the data set to update a read voltage prediction function corresponding to a read voltage prediction model so as to fit a local curve of the predicted read voltage parameter offset to a corresponding local trend of the data set; and generating or updating prediction data of the predicted read voltage parameter offset based on the read voltage prediction function.

[0006] In addition to the above method, the present invention also provides a memory device including the above memory controller, wherein the memory device includes: a non-volatile memory for storing information; and a memory controller coupled to the non-volatile memory and used to control the operation of the memory device.

[0007] In addition to the above method, the present invention also provides an electronic device including the above memory device, wherein the electronic device further includes a host device coupled to the memory device. The host device may include: at least one processor for controlling the operation of the host device; and a power supply circuit coupled to the at least one processor and used to provide power to the at least one processor and the memory device. In addition, the memory device provides storage space for the host device.

[0008] The method and related apparatus of the present invention can ensure that the memory device can operate properly under different circumstances, and in particular, can prevent the memory device from spending too much time on certain internal operations of the memory device (such as read retry operations) in response to host requests. In addition, the method and related apparatus of the present invention can solve the problems encountered in the prior art without introducing side effects or in a manner that is unlikely to introduce side effects. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a schematic diagram of an electronic device according to an embodiment of the present invention.

[0010] Figure 2 FIG. 4 is a schematic diagram of a control scheme for reading voltage codes according to an embodiment of the present invention.

[0011] Figure 3 FIG. 4 is a schematic diagram of a programming status monitoring control scheme according to an embodiment of the present invention.

[0012] Figure 4 FIG. 4 is a schematic diagram of a read voltage scan control scheme according to an embodiment of the present invention.

[0013] Figure 5 FIG. 4 is a schematic diagram of a read voltage learning control scheme of a method for controlling data access of a memory device by using prediction information according to an embodiment of the present invention.

[0014] Figure 6 According to an embodiment of the present invention Figure 5 A schematic diagram showing some implementation details of the read voltage learning control scheme shown.

[0015] Figure 7 FIG. 4 is a schematic diagram of a first database update control scheme of the method according to an embodiment of the present invention.

[0016] Figure 8 FIG. 4 is a schematic diagram of a second database update control scheme of the method according to an embodiment of the present invention.

[0017] Fig. 9 FIG. 4 is a schematic diagram of a local linear regression control scheme of the method according to an embodiment of the present invention.

[0018] Fig.10 According to an embodiment of the present invention, Fig. 9 Some examples of predetermined weight functions for the local linear regression control scheme are shown.

[0019] Fig.11 FIG. 4 is a schematic diagram of a workflow of the method according to an embodiment of the present invention.

[0020]

Explanation of symbols

[0021] 10: Electronic devices

[0022] 50: Host device

[0023] 52: Processor

[0024] 54: Power supply circuit

[0025] 58,118: Transmission interface circuit

[0026] 100: memory device

[0027] 110: memory controller

[0028] 112: Microprocessor

[0029] 112C: Program code

[0030] 112M: Read-only memory

[0031] 114: Control logic circuit

[0032] 115: Data access control engine circuit

[0033] 1151: Randomization circuit

[0034] 1152: Error correction code circuit

[0035] 116: Random Access Memory

[0036] 116D,120D: Read voltage control database

[0037] 116T: Temporary logical to physical address mapping table

[0038] 120: Non-volatile memory

[0039] 120T: Global logical to physical address mapping table

[0040] 122-1~122-N E :Non-volatile memory devices

[0041] 120C: Multiple memory cells

[0042] Vc: read voltage code

[0043] {Vc1(y),Vc2(y),Vc3(y)}: read voltage code offset

[0044] Vth: Read voltage

[0045] {Vth1(y),Vth2(y),Vth3(y)}: read voltage offset

[0046] PS(1)~PS(16),PS(Y): Programming status

[0047] Bit0: Bit zero count

[0048] ΔBit0: Bit zero count change

[0049] Bit0_ref(y): reference bit zero count

[0050] Vth_Opt(y), Vth_Opt(y1), Vth_Opt(y2), Vth_Opt(y3): Optimal read voltage

[0051] Vc_Opt(y),Vc_Opt(y1),Vc_Opt(y2),Vc_Opt(y3): Best reading voltage code

[0052] 110S: Scanning module

[0053] Vc_new(y): at least one new read voltage code offset

[0054] Vc_predict(y): predicts read voltage code offset

[0055] Vth_new(y): at least one new read voltage offset

[0056] Vth_predict(y): predicted read voltage offset

[0057] {V1(y),V2(y),V3(y)}: read voltage parameter offset

[0058] S11~S18: Steps DETAILED DESCRIPTION

[0059] Figure 11 is a schematic diagram of an electronic device 10 according to an embodiment of the present invention, wherein the electronic device 10 may include a host device 50 and a memory device 100. The host device 50 may include at least one processor (e.g., one or more processors; which may be collectively referred to as a processor 52), a power supply circuit 54, and a transmission interface circuit 58, wherein the processor 52 and the transmission interface circuit 58 may be coupled to each other through a bus, and may be coupled to the power supply circuit 54 to obtain power. The processor 52 may be used to control the operation of the host device 50, and the power supply circuit 54 may be used to provide power to the processor 52, the transmission interface circuit 58, and the memory device 100, and output one or more driving voltages to the memory device 100. The memory device 100 may be used to provide storage space for the host device 50, and may obtain one or more driving voltages from the host device 50 as a power supply for the memory device 100. Examples of the host device 50 may include, but are not limited to: a multi-function mobile phone, a tablet computer, a wearable device, and a personal computer, such as a desktop computer and a notebook computer. Examples of the memory device 100 may include, but are not limited to, portable memory devices (e.g., memory cards conforming to SD / MMC, CF, MS or XD specifications, solid state drives (SSDs), and different types of embedded memory devices (e.g., embedded memory devices conforming to universal flash storage (UFS) specifications or embedded multi media card (eMMC) specifications). According to the present embodiment, the memory device 100 may include a controller, such as a memory controller 110, and may further include a non-volatile memory 120 (for simplicity, the non-volatile memory 120 is not shown in FIG. 1 ). Figure 1 The non-volatile memory 120 may include at least one non-volatile memory element (e.g., one or more non-volatile memory elements), such as a plurality of non-volatile memory elements 122-1, 122-2, ..., and 122-N. E (For brevity, Figure 1 NV memory element), where “NV E " may represent a positive integer greater than 1. For example, the non-volatile memory 120 may be a flash memory, and the plurality of non-volatile memory elements 122-1, 122-2, ..., and 122-N may be E It may be a plurality of flash memory wafers or a plurality of flash memory dies, but the present invention is not limited thereto.

[0060] like Figure 1As shown, the memory controller 110 may include a processing circuit (e.g., a microprocessor 112), a storage unit (e.g., a read-only memory (ROM) 112M; for the sake of simplicity, it is labeled as "ROM"), a control logic circuit 114, a data access control (DAC) engine circuit 115, a random access memory 116 (random access memory, RAM; for the sake of simplicity, it is labeled as "RAM", for example, it can be implemented by a static random access memory (SRAM)) and a transmission interface circuit 118, wherein at least a portion (e.g., a portion or all) of the above components may be coupled to each other via a bus. The random access memory 116 may be used to provide an internal storage space for the memory controller 110 (e.g., temporarily storing information), but the present invention is not limited thereto. In addition, the ROM 112M of this embodiment is used to store the program code 112C, and the microprocessor 112 is used to execute the program code 112C to control the access of the non-volatile memory 120. It should be noted that the program code 112C can also be stored in the RAM 116 or any type of memory. In addition, the control logic circuit 114 may be used to control the non-volatile memory 120, and the data access control engine circuit 115 may be used to perform data access control for the memory controller 110, and in particular, may include a randomization circuit 1151 and an error correction code (ECC) circuit 1152, wherein the randomization circuit 1151 may perform a randomization operation on write data (e.g., data to be written into the non-volatile memory 120 during a write / programming operation on the non-volatile memory 120 in response to a write command from the host device 50) and perform a de-randomization operation on read data (e.g., data read from the non-volatile memory 120 during a read operation on the non-volatile memory 120 in response to a read command from the host device 50), and the error correction code circuit 1152 may perform an error correction code encoding on the write data and an error correction code decoding on the read data to protect the data and / or perform error correction, but the present invention is not limited thereto. According to some embodiments, at least a portion (e.g., a portion or all) of the data access control engine circuit 115, such as the randomization circuit 1151 and the error correction code circuit 1152, may be integrated into the control logic circuit 114. For write data, the error correction code circuit 1152 may perform error correction code encoding on the data to be written into the non-volatile memory 120 to generate encoded data, and the randomization circuit 1151 may perform a randomization operation on the encoded data to generate randomized data for programming into the non-volatile memory 120.For reading data, the randomization circuit 1151 can perform a de-randomization operation on a readout version of the randomized data stored in the non-volatile memory 120 to generate a readout version of the encoded data, and the error correction code circuit 1152 can be used to perform error correction code decoding on the readout version of the encoded data to correct any errors therein, so as to transmit an error-free version of the encoded data back to the host device 50.

[0061] The transmission interface circuit 118 may comply with one or more communication specifications among different communication specifications (e.g., Serial Advanced Technology Attachment (SATA) specification, Universal Serial Bus (USB) specification, Peripheral Component Interconnect Express (PCIe) specification, embedded multimedia card specification, or universal flash storage specification), and may enable the memory device 100 to communicate with the host device 50 (e.g., transmission interface circuit 58) according to the one or more communication specifications. Similarly, the transmission interface circuit 58 may comply with the one or more communication specifications, and may enable the host device 50 to communicate with the memory device 100 (e.g., transmission interface circuit 118) according to the one or more communication specifications.

[0062] In the present embodiment, the host device 50 can indirectly access the non-volatile memory 120 in the memory device 100 by transmitting a plurality of host commands and corresponding logical addresses to the memory controller 110. The memory controller 110 receives the plurality of host commands and corresponding logical addresses, and converts the plurality of host commands into a plurality of memory operation commands (which may be referred to as operation commands), and then uses the plurality of operation commands to control the non-volatile memory 120 to read or write / program the memory cells or data pages of the corresponding physical addresses in the non-volatile memory 120, etc., wherein the physical addresses may be related to the logical addresses. For example, the memory controller 110 may generate or update at least one logical-to-physical (L2P) address mapping table to manage the relationship between the physical addresses and the logical addresses, wherein the non-volatile memory 120 may store a global logical-to-physical address mapping table 120T for the memory controller 110 to control the memory device 100 to access the data in the non-volatile memory 120, but the present invention is not limited thereto. In addition, the memory controller 110 may generate or update at least one read voltage control database, such as a read voltage control database 120D, and the non-volatile memory 120 may store the read voltage control database 120D. The memory controller 110 may generate or update the read voltage control information (e.g., at least one data set related to the read voltage of the non-volatile memory 120) in the read voltage control database 120D for performing read voltage control.

[0063] For better understanding, the global logical-to-physical address mapping table 120T and the read voltage control database 120D may be located in a predetermined local area (e.g., a system local area) within the non-volatile memory 122-1 element, but the present invention is not limited thereto. For example, the global logical-to-physical address mapping table 120T may be divided into a plurality of local logical-to-physical address mapping tables, and the plurality of local logical-to-physical address mapping tables may be stored in the non-volatile memory elements 122-1, 122-2, and 122-N. E In particular, the non-volatile memory elements 122-1, 122-2, and 122-N may be stored in the non-volatile memory elements 122-1, 122-2, and 122-N, respectively. EWhen necessary, the memory controller 110 may load at least a portion (e.g., a portion or all) of the global logical-to-physical address mapping table 120T into the random access memory 116 or other memory. For example, the memory controller 110 may load a local logical-to-physical address mapping table among the multiple local logical-to-physical address mapping tables into the random access memory 116 as a temporary logical-to-physical address mapping table 116T, so as to access data in the non-volatile memory 120 according to the local logical-to-physical address mapping table stored as the temporary logical-to-physical address mapping table 116T, but the present invention is not limited thereto. In addition, the memory controller 110 may load the read voltage control database 120D into the random access memory 116 or other memory. For example, the memory controller 110 may load the read voltage control database 120D into the random access memory 116 as a temporary read voltage control database 116D, so as to perform read voltage control according to the temporary read voltage control database 116D. The memory controller 110 may generate or update read voltage control information (eg, at least one data set related to the read voltage of the non-volatile memory 120 ) in the temporary read voltage control database 116D, and update the read voltage control database 120D according to the latest read voltage control information in the temporary read voltage control database 116D.

[0064] In addition, the at least one non-volatile memory element (eg, one or more non-volatile memory elements, such as {122-1, 122-2, . . . , 122-N E}) may include a plurality of blocks, wherein the minimum unit for the memory controller 110 to perform a data erase operation on the non-volatile memory 120 is a block, and the minimum unit for the memory controller 110 to perform a data write operation on the non-volatile memory 120 is a page, but the present invention is not limited thereto. For example, the non-volatile memory elements 122-1, 122-2, ... and 122-N E Any non-volatile memory element 122-n (symbol "n" may represent a non-volatile memory element in the range [1, N E ] may include multiple blocks, and a block within the multiple blocks may include and record a specific number of pages, wherein the memory controller 110 may access a page of a block within the multiple blocks according to a block address and a page address.

[0065] According to some embodiments, for the non-volatile memory 120 (or the non-volatile memory elements 122-1, 122-2, ... and 122-N therein), E), a read voltage drift may occur, so the memory controller 110 may try to obtain an optimal read voltage Vth_Opt to perform a read operation on the non-volatile memory 120 to correctly read data, wherein the read voltage may be referred to as a threshold voltage according to some viewpoints, and therefore for a better understanding, the read voltage may be represented by the symbol “Vth”, but the present invention is not limited thereto.

[0066] Figure 2 Schematic diagram of a read voltage code control scheme according to an embodiment of the present invention. A plurality of memory cells 120C of a memory cell group in the non-volatile memory 120 may include a group of memory cells from among the plurality of memory cells in any of the above-mentioned non-volatile memory elements 122-n. Assuming that "Y" may represent a positive integer and "y" may be an integer in the interval [1, Y], any memory cell among the plurality of memory cells 120C may be in a programming state PS(y) selected from a plurality of candidate programming states {PS(1), ..., PS(Y)} (e.g., Y = 16). Figure 2 As shown, when necessary, the memory controller 110 may transmit a read voltage code Vc to the non-volatile memory 120 to configure a read voltage Vth corresponding to the read voltage code Vc. For example, the read voltage Vth may be positively correlated with the read voltage code Vc and / or may have a linear relationship with the read voltage code Vc, and the read voltage code Vc may be regarded as a representative of the read voltage Vth, but the present invention is not limited thereto. In addition, the memory controller 110 may dynamically adjust the read voltage code Vc to dynamically adjust the read voltage Vth to accurately determine the respective programming states {PS(y)} of the plurality of memory cells 120C, and thus may correctly determine the bit information corresponding to the programming state {PS(y)}. For example, in the case of Y=16, any candidate programming state PS among the candidate programming states {PS(1), ..., PS(16)} can be associated with a corresponding bit sequence among the bit sequence {0000, 0001, ..., 1111} according to a gray code, and any of the candidate programming states PS can represent the corresponding bit sequence, but the present invention is not limited thereto. According to some embodiments, the relationship between the bit sequence {0000, 0001, ..., 1111} and the candidate programming states {PS(1), ..., PS(16)} can vary.

[0067] For better understanding, the plurality of memory cells 120C may be configured as quad-level cells (QLCs), the candidate programming state count Y may be equal to 16, and thus the candidate programming states {PS(1), . . . , PS(Y)} may be formulated as Figure 2 The candidate programming states {PS(1), ..., PS(16)} are shown, but the present invention is not limited thereto. The plurality of memory cells 120C may be configured as any of a plurality of memory cell types. For example, the plurality of memory cells 120C may be configured as single-level cells (SLCs) for storing 1 bit per cell in the non-volatile memory element 122-n, where Y=2 1 =2; the plurality of memory cells 120C may be configured as multi-level cells (MLCs), such as double-level cells (DLCs) for storing 2 bits per cell in the non-volatile memory element 122-n, where Y=2 2 =4; the plurality of memory cells 120C may be configured as triple-level cells (TLCs) for storing 3 bits per cell in the non-volatile memory element 122-n, where Y=2 3 =8; the plurality of memory cells 120C may be configured as four-level cells for storing 4 bits per cell in the non-volatile memory element 122-n, where Y=2 4 =16; the plurality of memory cells 120C may be configured as penta-level cells (PLCs) for storing 5 bits per cell in the non-volatile memory element 122-n, where Y=2 5 =32; and the rest can be deduced by analogy.

[0068] Figure 3Schematic diagram of a program state monitoring control scheme according to an embodiment of the present invention. The memory controller 110 may increase or decrease the read voltage code Vc to correspondingly increase or decrease the read voltage Vth, and read the plurality of memory cells 120C according to the read voltage Vth to monitor the bit-zero count Bit0 of the original data bits equal to 0 among the respective original data bits of the plurality of memory cells 120C. For example, the bit-zero count Bit0 may represent the number of memory cells that output the original data having bit 0 among the plurality of memory cells 120C when the memory controller 110 controls the non-volatile memory 120 to read the plurality of memory cells 120C according to the read voltage Vth. The memory controller 110 may monitor the bit-zero count Bit0 to obtain a plurality of monitoring values ​​indicating a plurality of relationships between the bit-zero count Bit0 and the read voltage code Vc (or the read voltage Vth), and / or obtain a curve of the bit-zero count Bit0 relative to the read voltage code Vc (or the read voltage Vth). In addition, the memory controller 110 may determine the variation of the bit zero count Bit0 relative to the read voltage code Vc (or the read voltage Vth), and in particular, calculate the difference between any two adjacent monitoring values ​​of the bit zero count Bit0 along the Vc axis (or the Vth axis) as the variation of the bit zero count Bit0 at a corresponding point on the Vc axis (or the Vth axis) to obtain a plurality of difference values ​​indicating a plurality of relationships between the bit zero count variation ΔBit0 and the read voltage code Vc (or the read voltage Vth), and / or obtain a curve of the bit zero count variation ΔBit0 relative to the read voltage code Vc (or the read voltage Vth). Therefore, the curve of the bit zero count variation ΔBit0 relative to the read voltage code Vc (or the read voltage Vth) may have a plurality of partial curves corresponding to a plurality of candidate programming states {PS(1), . . . , PS(Y)}, respectively.

[0069] According to some embodiments, when the plurality of memory cells 120C are read according to the read voltage Vth, the memory controller 110 may obtain original data (e.g., an original bit such as “1” or “0” read according to the read voltage Vth) of a memory cell among the plurality of memory cells 120C from the non-volatile memory 120. For example, the memory cells in the non-volatile memory 120 may be implemented by floating-gate metal-oxide-semiconductor field-effect transistors (MOSFETs), and whether a current at a control gate voltage of a memory cell can easily flow through a channel (e.g., an n-channel) of the memory cell depends on the amount of charges (e.g., electrons) stored in the memory cell, wherein the original data (e.g., “0”) may indicate that the read voltage Vth and the control gate voltage are high enough to allow the current to flow through the channel, and the original data (e.g., “1”) may indicate that the read voltage Vth and the control gate voltage are insufficient to allow the current to flow through the channel, but the present invention is not limited thereto. According to some embodiments, the architecture of the memory cells in the non-volatile memory 120 may vary.

[0070] Figure 4 Schematic diagram of a read voltage scan control scheme according to an embodiment of the present invention, wherein the horizontal axis may represent a read voltage code Vc corresponding to a read voltage Vth, and the vertical axis may represent a bit zero count change ΔBit0 corresponding to a bit zero count Bit0. For example, a memory cell group may include at least a portion (e.g., a portion of the memory cells or all of the memory cells) of a plurality of memory cells of any of the above-mentioned non-volatile memory elements 122-n, and the respective programming states {PS(y)} of the memory cells in the memory cell group may vary and have a certain distribution relative to the read voltage code Vc (or the read voltage Vth). For a memory cell group, Figure 4 The curve shown may indicate a portion of multiple relationships between the bit zero count variation ΔBit0 and the read voltage code Vc (or the read voltage Vth), but the present invention is not limited thereto. According to some embodiments, the range of the read voltage code Vc, the range of the bit zero count variation ΔBit0 and / or Figure 4 The curve shown may vary. According to some embodiments, the memory cell group may include non-volatile memory elements 122-1, 122-2, ... and 122-N. E of memory cells.

[0071] For example, assuming that V_a≥V_min and V_b≤V_max, the memory controller 110 may select a predetermined read voltage range [V_a, V_b] (e.g., a range between read voltages V_a and V_b) from an adjustable read voltage range [V_min, V_max] (e.g., a range between a minimum read voltage V_min and a maximum read voltage V_max), and use a fixed step size V_step to scan the predetermined read voltage range [V_a, V_b]. In particular, the memory cells in the memory cell group are read according to the read voltages {V_a, (V_a+V_step), (V_a+(2*V_step)), ..., V_b} to obtain relevant information. The memory controller 110 may determine at least a local minimum value (e.g., a value between the zero bit count variation ΔBit0) of the zero bit count variation ΔBit0 according to the relationship between the zero bit count variation ΔBit0 and the read voltage code Vc. Figure 4 , PS(Y)} for distinguishing any two adjacent candidate programming states {PS} among a plurality of candidate programming states {PS(1), ..., PS(Y)} for the memory cell group. When the read voltage code Vc is used as a representative of the read voltage Vth, the memory controller 110 may select a predetermined read voltage code range [Vc_a, Vc_b] (e.g., a range between read voltage codes Vc_a and Vc_b corresponding to the read voltages V_a and V_b, respectively) from an adjustable read voltage code range [Vc_min, Vc_max] (e.g., a range between a minimum read voltage code Vc_min and a maximum read voltage code Vc_max corresponding to the minimum read voltage V_min and the maximum read voltage V_max, respectively), and scan the predetermined read voltage code range [Vc_a, Vc_b] using a fixed step size Vc_step (e.g., Vc_step=1) corresponding to the fixed step size V_step. Taking multiple memory cells 120C as four-level cells as an example, the memory controller 110 can perform a similar scanning operation to determine 15 values ​​on the Vc axis (or Vth axis) corresponding to 15 local minimum values ​​of the bit zero count change ΔBit0 as 15 optimal read voltage codes {Vc_Opt} (or 15 optimal read voltages {Vth_Opt}) for distinguishing candidate programming states {PS(1),…,PS(16)}.

[0072] Since the amount of charge in the memory cell may change over time due to some reasons, the programming state {PS(y)} in the memory cell group may change accordingly. When a read error occurs, the memory controller 110 may perform a read retry procedure to attempt to use one or more adjusted read voltages to read the non-volatile memory 120 to correct the read error. For example, the memory controller 110 may perform read voltage adjustment according to a read voltage scan control scheme to accurately determine the respective programming states {PS(y)} of the memory cells in the memory cell group, and thus may correctly determine the respective bit information of the memory cells in the memory cell group, but the present invention is not limited thereto. According to some embodiments, the memory controller 110 may establish a read voltage prediction model corresponding to the above-mentioned at least one read voltage control database (e.g., the read voltage control database 116D and / or the read voltage control database 120D), and perform read voltage prediction according to the read voltage prediction model to adjust the read voltage Vth without calculating the bit zero count change ΔBit0, so as to increase the overall performance.

[0073] Figure 5The present invention is a schematic diagram of a read voltage learning control scheme of a method for controlling data access of a memory device by using predicted information according to an embodiment of the present invention. The memory controller 110 can set or adjust the read voltage code Vc to set or adjust the read voltage Vth, and monitor the bit zero count Bit0 to perform a learning operation for an optimal read voltage code Vc_Opt(y) (e.g., an optimal value of the read voltage code Vc) corresponding to a reference bit zero count Bit0_ref(y) (e.g., a reference value of the bit zero count Bit0) and perform a learning operation for an optimal read voltage Vth_Opt(y) (e.g., an optimal value of the read voltage Vth) corresponding to the reference bit zero count Bit0_ref(y), wherein the reference bit zero count Bit0_ref(y) can be regarded as an ideal bit zero count (e.g., an ideal value of the bit zero count Bit0), and the reference bit zero count Bit0_ref(y) can be pre-determined according to a preset setting as a predetermined ideal value corresponding to a local minimum value of the bit zero count variation ΔBit0. For example, under the control of a production tool of the memory device 100, the memory controller 110 may have previously set the reference bit zero count Bit0_ref(y) to a fixed value (e.g., a preset bit zero count value corresponding to the encoding state index y) so that the memory device 100 can correctly read data for the host device 50, but the present invention is not limited thereto. According to some embodiments, the memory controller 110 can set the reference bit zero count Bit0_ref(y) to a fixed value (e.g., a preset bit zero count value corresponding to the encoding state index y) by itself without relying on the production tool of the memory device 100.

[0074] Figure 5The curve distribution shown can be regarded as an ideal distribution and may change over time for some reasons. Since the memory controller 110 may have set the reference bit zero count Bit0_ref(y) to a preset bit zero count value corresponding to the programming state index y, the memory controller 110 may need to perform one or more learning operations to correctly determine the optimal read voltage code Vc_Opt(y). In particular, the memory controller 110 may collect one or more data sets into the at least one read voltage control database (e.g., the read voltage control database 116D and / or the read voltage control database 120D) to establish a read voltage prediction model. For example, the memory controller 110 may collect the read voltage code correction information of the read voltage code Vc (e.g., read voltage code offset {Vc1(y), Vc2(y), Vc3(y)}) and / or the read voltage correction information of the read voltage Vth (e.g., read voltage offset {Vth1(y), Vth2(y), Vth3(y)}) into the at least one read voltage control database for generating prediction information, but the present invention is not limited thereto. According to some embodiments, the amount and data type of the correction information (e.g., read voltage code correction information of the read voltage code Vc or read voltage correction information of the read voltage Vth) collected in the learning operation, the range of the read voltage code Vc, the range of the bit zero count Bit0 and / or Figure 5 The curves shown may vary.

[0075] Since the curve of the bit zero count change ΔBit0 relative to the read voltage code Vth_Code (or read voltage Vth) can have (Y-1) local minima (without considering the endpoints of the overall curve), the memory controller 110 can perform learning operations for (Y-1) optimal read voltage codes {Vc_Opt(y)} (for example, the optimal read voltage code {Vc_Opt(1),…,Vc_Opt(Y-1)}) and perform learning operations for (Y-1) optimal read voltages {Vth_Opt(y)} (for example, the optimal read voltage {Vth_Opt(1),…,Vth_Opt(Y-1)}). Taking multiple memory cells 120C as four-level cells as an example, the memory controller 110 can perform a similar learning operation to determine 15 numerical values ​​on the Vc axis (or Vth axis) as 15 optimal read voltage codes {Vc_Opt(y)} (or 15 optimal read voltages {Vth_Opt(y)}) for distinguishing candidate programming states {PS(1),…,PS(16)}, wherein the 15 optimal read voltage codes {Vc_Opt(y)} (or 15 optimal read voltages {Vth_Opt(y)}) can correspond to 15 local minimum values ​​of the bit zero count change ΔBit0.

[0076] Figure 6 According to an embodiment of the present invention Figure 5 A schematic diagram showing some implementation details of the read voltage learning control scheme shown, where the symbols "y1", "y2", and "y3" may represent three consecutive integers in the range [1, Y], and y1 < y2 < y3. For example, when y = y1, the memory controller 110 may perform a learning operation for the optimal read voltage code Vc_Opt(y1) and the optimal read voltage Vth_Opt(y1) to distinguish the candidate programming state PS(y1) from PS(y1 + 1); when y = y2, the memory controller 110 may perform a learning operation for the optimal read voltage code Vc_Opt(y2) and the optimal read voltage Vth_Opt(y2) to distinguish the candidate programming state PS(y2) from PS(y2 + 1); when y = y3, the memory controller 110 may perform a learning operation for the optimal read voltage code Vc_Opt(y3) and the optimal read voltage Vth_Opt(y3) to distinguish the candidate programming state PS(y3) from PS(y3 + 1); and so on for the rest. For the sake of brevity, similar content of this embodiment will not be described in detail again here.

[0077] According to some embodiments, the read voltage code Vc can be any integer in the range [Vc_min, Vc_max], where Vc_min = -128 and Vc_max = +128 (such as Figures 4 to 6 the range of the read voltage code Vc shown in any of the diagrams), but the present invention is not limited thereto. According to some embodiments, the minimum read voltage code Vc_min and the maximum read voltage code Vc_max can vary.

[0078] Figure 71 is a schematic diagram of a first database update control scheme of the method according to an embodiment of the present invention. For example, at least one firmware module executed by the memory controller 110 may include a scanning module 110S for controlling the memory controller 110 to operate according to the read voltage scanning control scheme. In the case where at least one decoding error (e.g., a hard decoding error and / or a soft decoding error) occurs during the reading of data from the non-volatile memory 120, the memory controller 110 executing the scanning module 110S may determine the latest best read voltage code Vc_Opt(y), and determine at least one new read voltage code offset Vc_new(y) of the read voltage code Vc according to the latest best read voltage code Vc_Opt(y) for collection into the read voltage control database 116D. The memory controller 110 may update the read voltage control database 116D using at least one new read voltage code offset Vc_new(y) obtained from the scan module 110S, and in particular, may collect the read voltage code correction information (e.g., at least one new read voltage code offset Vc_new(y)) as a part of the read voltage code offsets {Vc1(y), Vc2(y), Vc3(y)} in the read voltage control database 116D, and discard at least one old read voltage code offset in the read voltage control database 116D when necessary. Therefore, the memory controller 110 may perform read voltage prediction according to the read voltage prediction model to generate prediction information (e.g., a predicted read voltage code offset Vc_predict(y)) corresponding to the read voltage code offsets {Vc1(y), Vc2(y), Vc3(y)} for adjusting the read voltage Vth to perform a read retry to correctly and efficiently read data.

[0079] Figure 8FIG. 1 is a schematic diagram of a second database update control scheme of the method according to an embodiment of the present invention. For example, in the case where at least one decoding error (e.g., a hard decoding error and / or a soft decoding error) occurs during data reading from the non-volatile memory 120, the memory controller 110 running the scanning module 110S may determine the latest optimal read voltage Vth_Opt(y), and determine at least one new read voltage offset Vth_new(y) of the read voltage Vth according to the latest optimal read voltage Vth_Opt(y) for collection into the read voltage control database 116D. The memory controller 110 may update the read voltage control database 116D using at least one new read voltage offset Vth_new(y) obtained from the scan module 110S, and in particular, may collect the read voltage correction information (e.g., at least one new read voltage offset Vth_new(y)) as a part of the read voltage offset {Vth1(y), Vth2(y), Vth3(y)} in the read voltage control database 116D, and discard at least one old read voltage offset in the read voltage control database 116D when necessary. Therefore, the memory controller 110 may perform read voltage prediction according to the read voltage prediction model to generate prediction information (e.g., a predicted read voltage offset Vth_predict(y)) corresponding to the read voltage offset {Vth1(y), Vth2(y), Vth3(y)} for adjusting the read voltage Vth to perform a read retry to correctly and efficiently read data.

[0080] According to some embodiments, the read voltage code Vc and the read voltage Vth can be collectively referred to as a read voltage parameter V, the optimal read voltage code Vc_Opt(y) and the optimal read voltage Vth_Opt(y) can be collectively referred to as the optimal read voltage parameter V_Opt(y), and the read voltage code offset {Vc1(y), Vc2(y), Vc3(y)} and the read voltage offset {Vth1(y), Vth2(y), Vth3(y)} can be collectively referred to as a read voltage parameter offset {V1(y), V2(y), V3(y)}. For example, in the case where at least one decoding error (e.g., a hard decoding error and / or a soft decoding error) occurs during data reading from the non-volatile memory 120, the memory controller 110 running the scanning module 110S may determine the latest optimal read voltage parameter V_Opt(y), and determine at least one new read voltage parameter offset V_new(y) of the read voltage parameter V (e.g., the at least one new read voltage code offset Vc_new(y) and the at least one new read voltage offset Vth_new(y)) according to the latest optimal read voltage parameter V_Opt(y) for collection into the at least one read voltage control database (e.g., the read voltage control database 116D and / or the read voltage control database 120D). The memory controller 110 may use the at least one new read voltage parameter offset V_new(y) obtained from the scanning module 110S to update the at least one read voltage control database. In particular, the memory controller 110 may collect the read voltage correction information (e.g., the at least one new read voltage parameter offset V_new(y)) as a part of the read voltage parameter offset {V1(y), V2(y), V3(y)} in the at least one read voltage control database, and discard the at least one old read voltage parameter offset in the at least one read voltage control database when necessary. Therefore, the memory controller 110 may perform read voltage prediction according to the read voltage prediction model to generate prediction information (e.g., a predicted reading voltage parameter offset V_predict(y)) corresponding to the read voltage parameter offset {V1(y), V2(y), V3(y)} for adjusting the read voltage Vth to perform read retry to correctly and effectively read data.

[0081] Fig. 9Schematic diagram of a local linear regression control scheme of the method according to an embodiment of the present invention. For example, the horizontal axis may represent a bit zero count difference Bit0_diff(y) (e.g., a difference (Bit0-Bit0_ref(y)) between a bit zero count Bit0 and a reference bit zero count Bit0_ref(y)), and the vertical axis may represent a predicted read voltage parameter shift V_predict(y) corresponding to a read voltage parameter shift {V1(y), V2(y), V3(y)} (e.g., a predicted read voltage code shift Vc_predict(y) corresponding to a read voltage code shift {Vc1(y), Vc2(y), Vc3(y)} or a predicted read voltage shift Vth_predict(y) corresponding to a read voltage shift {Vth1(y), Vth2(y), Vth3(y)}), wherein for better understanding, the range of the predicted read voltage parameter shift V_predict(y) may be explained by the range of the predicted read voltage code shift Vc_predict(y), but the present invention is not limited thereto. According to some embodiments, the range of the predicted read voltage parameter offset V_predict(y), the distribution of the read voltage parameter offset {V1(y), V2(y), V3(y)} and / or Fig. 9 The curve shown is used to illustrate that the predicted read voltage parameter offset V_predict(y) can vary.

[0082] The memory controller 110 can store one or more data sets (e.g., Fig. 9 The data set of read voltage parameter offset {V1(y), V2(y), V3(y)} illustrated by the small circle shown in the figure) is collected into the at least one read voltage control database (e.g., the read voltage control database 116D and / or the read voltage control database 120D) to establish a read voltage prediction model, and the read voltage prediction is performed according to the read voltage prediction model to generate prediction information (e.g. Fig. 9 , V_predict(y) corresponding to the read voltage parameter offset {V1(y), V2(y), V3(y)}). For example, the memory controller 110 may Fig. 9 The read voltage parameter offsets {V1(y), V2(y), V3(y)} illustrated by the small circles shown are locally linearly regressed to generate Fig. 9In particular, a linear regression is performed on the read voltage parameter offsets {V1(y), V2(y), V3(y)} according to a predetermined weight function w to fit a local curve of the curve of the predicted read data parameter offset V_predict(y) to a corresponding local trend among a plurality of local trends of the read voltage parameter offsets {V1(y), V2(y), V3(y)}. Since the distribution of the read voltage parameter offsets {V1(y), V2(y), V3(y)} on the bit zero count difference Bit0_diff(y) may correspond to a nonlinear curve, the memory controller 110 may perform a local linear regression on the read voltage parameter offsets {V1(y), V2(y), V3(y)} to appropriately generate the predicted read voltage parameter offset V_predict(y) for adjusting the read voltage Vth for read retry to correctly and effectively read data.

[0083] Assuming that a candidate value index i of the multiple candidate values ​​of the bit zero count difference Bit0_diff(y) can be an integer, the multiple candidate values ​​can be written as multiple candidate values ​​{Bit0_diff(y,i)}, such as (i_max-i_min+1) candidate values ​​{Bit0_diff(y,i_min),…,Bit0_diff(y,i_max)}, and the read voltage parameter offset {V1(y), V2(y), V3(y)} corresponding to any candidate value Bit0_diff(y,i) (for example, one of the candidate values ​​{Bit0_diff(y,i)}) can be written as read voltage parameter offset {V1(y,i), V2(y,i), V3(y,i)}, where "i_max" and "i_min" can represent the maximum value and minimum value of the candidate value index i, respectively. Fig. 9As shown, for any candidate value Bit0_diff(y,i) among the candidate values ​​{Bit0_diff(y,i)}, the memory controller 110 may collect three read voltage parameter offsets V1(y,i), V2(y,i) and V3(y,i) corresponding to the candidate value Bit0_diff(y,i), but the present invention is not limited thereto. According to some embodiments, the number of read voltage parameter offsets V1(y,i) and the like corresponding to the same candidate value Bit0_diff(y,i) collected by the memory controller 110 may vary. For example, assuming that a read voltage parameter offset index j of a read voltage parameter offset V1(y,i) or the like can be a positive integer greater than one, and there can be m read voltage parameter offsets {Vj(y,i)} corresponding to the same candidate value Bit0_diff(y,i), such as the read voltage parameter offsets {V1(y,i),…,Vm(y,i)}. When m=3, the read voltage parameter offsets {V1(y,i),…,Vm(y,i)} can represent the read voltage parameter offsets {V1(y,i),V2(y,i),V3(y,i)}.

[0084] In addition, the memory controller 110 may perform a read parameter learning procedure to establish a data set among one or more data sets in the above-mentioned at least one read voltage control database (for example, the read voltage control database 116D and / or the read voltage control database 120D), and in particular, perform the above-mentioned local linear regression to generate prediction data {V_predict(y,i)|i=i_min,…,i_max} of the predicted read voltage parameter offset V_predict(y), such as prediction data {V_predict(y,i)} corresponding to multiple candidate values ​​{Bit0_diff(y,i)}, to complete the data set. Therefore, the data {(Bit0_diff(y,i),V_predict(y,i))|i=i_min,…,i_max} in the data set may indicate a nonlinear relationship between the bit zero count difference Bit0_diff(y) and the predicted read voltage parameter offset V_predict(y), such as Fig. 9In the process of performing local linear regression for a target candidate value Bit0_diff(y,i0) corresponding to i=i0 to make the relevant target data (Bit0_diff(y,i0), V_predict(y,i0)) in the data {(Bit0_diff(y,i), V_predict(y,i))} as accurate as possible, the memory controller 110 can determine the weight values ​​{wj(y,i)} of the read voltage parameter offsets {Vj(y,i)} corresponding to the plurality of candidate values ​​{Bit0_diff(y,i)} according to the predetermined weight function w. i For example, when the weight value {w i}, the memory controller 110 may perform the following operations:

[0085] (1) The memory controller 110 may shift the read voltage parameter corresponding to the target candidate value Bit0_diff(y, i0) by a weight value w of {V1(y, i0), ..., Vm(y, i0)} (for example, when m=3, the read voltage parameter shifts {V1(y, i0), V2(y, i0), V3(y, i0)}). i0 Configured as all weight values ​​{w i};

[0086] (2) The memory controller 110 may shift the read voltage parameter corresponding to at least one neighboring candidate value Bit0_diff(y, i1) by a weight value w {V1(y, i1), ..., Vm(y, i1)} (for example, when m=3, the read voltage parameter shifts {V1(y, i1), V2(y, i1), V3(y, i1)}) i1 Configured to be less than the weight value w i0 and is greater than all weight values ​​{w i}; and

[0087] (3) The memory controller 110 may shift the read voltage parameter corresponding to at least one further candidate value Bit0_diff(y, i2) by a weight value w {V1(y, i2), ..., Vm(y, i2)} (for example, when m=3, the read voltage parameter shifts {V1(y, i2), V2(y, i2), V3(y, i2)}) i2 Configured to be less than the weight value {w i0 ,w i1} and is greater than all weight values ​​{w i The remaining weight value among};

[0088] The rest can be deduced by analogy, but the present invention is not limited thereto. The at least one neighboring candidate value Bit0_diff(y, i1) may include two neighboring candidate values ​​{Bit0_diff(y, i1)} next to the target candidate value Bit0_diff(y, i0), such as the candidate values ​​Bit0_diff(y, (i0-1)) and Bit0_diff(y, (i0+1)) corresponding to i=(i0-1) and i=(i0+1), respectively, and the weight value w corresponding to the read voltage parameter offset {V1(y, (i0-1)), ..., Vm(y, (i0-1))} of the candidate value Bit0_diff(y, (i0-1)). i0-1 and the weight value w of the read voltage parameter offset {V1(y,(i0+1)),…,Vm(y,(i0+1))} corresponding to the candidate value Bit0_diff(y,(i0+1)) i0-1 can be equal to the weight value w i1 The at least one further candidate value Bit0_diff(y, i2) may include two further candidate values ​​{Bit0_diff(y, i2)} located next to the two adjacent candidate values ​​Bit0_diff(y, (i0-1)) and Bit0_diff(y, (i0+1)), such as the candidate values ​​Bit0_diff(y, (i0-2)) and Bit0_diff(y, (i0+2)) corresponding to i=(i0-2) and i=(i0+2), respectively, and the weight value w corresponding to the read voltage parameter offset {V1(y, (i0-2)),…,Vm(y, (i0-2))} of the candidate value Bit0_diff(y, (i0-2)). i0-2 and the weight value w of the read voltage parameter offset {V1(y,(i0+2)),…,Vm(y,(i0+2))} corresponding to the candidate value Bit0_diff(y,(i0+2)) i0+2 can be equal to the weight value w i2 .

[0089] Fig.10 According to an embodiment of the present invention, Fig. 9 The predetermined weight function w used for local linear regression can be implemented as a function of a predetermined parameter σ greater than zero by using a Gaussian kernel (for simplicity, in Fig.10 In the example, the sharpness of the center of the curve of the predetermined weight function w may vary with the predetermined parameter σ. Fig.10As shown in FIG. 1 , the horizontal axis represents the support index, and the vertical axis represents the kernel value. For example, the predetermined weight function w can be expressed as follows: w(x, x 0 )=exp(-1*((xx 0 ) 2 / (2*σ 2 )))=e^(-1*((xx 0 ) 2 / (2*σ 2 )));

[0090] Where "exp()" can represent the exponential function, "x 0 " can represent the target candidate value Bit0_diff(y,i0), and "x" can represent any of the above candidate values ​​Bit0_diff(y,i), but the present invention is not limited thereto. According to some viewpoints, the above formula can be rewritten as follows:

[0091] w(x,x 0 )=exp(-1*((||xx 0 || 2 ) / (2*σ 2 )))=e^(-1*((||xx 0 || 2 ) / (2*σ 2 ))).

[0092] In addition, the memory controller 110 may pre-set the predetermined parameter σ according to a user setting or a preset setting of the memory device 100 to control the sharpness of the center of the curve of the predetermined weight function w. For example, the memory controller 110 may set σ=0.1 to make the curve of the predetermined weight function w implemented by the Gaussian kernel become sharper. In some examples, the predetermined parameter σ may vary.

[0093] Fig. 9Some implementation details of the local linear regression control scheme shown can be further described as follows. According to some embodiments, for the same programming state index y, the bit zero count difference Bit0_diff(y) and multiple candidate values ​​{Bit0_diff(y,i)} can be rewritten as the bit zero count difference Bit0_diff (or "D") and multiple candidate values ​​{Bit0_diff(i)} (or {D(i)}), respectively, and the read voltage parameter offset {V1(y), V2(y), V3(y)} and the read voltage parameter offset {V1(y,i), ..., Vm(y,i)} (for example, the read voltage parameter offset {V1(y,i), V2(y,i), V3(y,i)}) can be rewritten as the read voltage parameter offset {V1, V2, V3} and the read voltage parameter offset {V1(i), ..., Vm(y,i)}. Vm(i)} (e.g., read voltage parameter offset {V1(i), V2(i), V3(i)}), read voltage code offset {Vc1(y), Vc2(y), Vc3(y)} and read voltage offset {Vth1(y), Vth2(y), Vth3(y)} may be rewritten as read voltage code offset {Vc1, Vc2, Vc3} and read voltage offset {Vth1, Vth2, Vth3}, respectively, and predicted read voltage parameter offset V_predict(y) and predicted data {V_predict(y,i)} may be rewritten as predicted read voltage parameter offset V_predict (or "P") and predicted data {V_predict(i)} (or {P(i)}), respectively. During the local linear regression, the memory controller 110 may generate a predicted read voltage parameter offset V_predict(y) according to a read voltage prediction function f(Bit0_diff) corresponding to the read voltage prediction model as follows:

[0094] P = f(Bit0_diff) = x 0 *β;

[0095] Where “P” can represent the predicted read voltage parameter offset V_predict(y), “x 0 " may represent a target candidate value Bit0_diff(y, i0) corresponding to i=i0 among a plurality of candidate values ​​{Bit0_diff(y, i)}, and β may represent a linear regression coefficient, but the present invention is not limited thereto. For example, the memory controller 110 may calculate the linear regression coefficient β as follows:

[0096] β(x 0 )=(X T WX) -1 X T Wv;

[0097] Wherein "X" may represent a bit zero count difference candidate value matrix, "W" may represent a weight matrix corresponding to a predetermined weight function w, and "v" may represent a read voltage parameter offset matrix. The bit zero count difference candidate value matrix X may be implemented as a matrix of multiple candidate values ​​{Bit0_diff(y,i)} of the bit zero count difference Bit0_diff(y), wherein the multiple candidate values ​​{Bit0_diff(y,i)} are arranged as elements of the bit zero count difference candidate value matrix X. The weight matrix W may be implemented as a weight value {w corresponding to the multiple candidate values ​​{Bit0_diff(y,i)} of the bit zero count difference Bit0_diff(y). i}, where the weight values ​​{w i}(For example, weight value {w i_min ,…,w i0-2 ,w i0-1 ,w i0 ,w i0+1 ,w i0+2 ,…,w i_max}) are arranged as diagonal elements of the weight matrix W, for example, starting from the upper left corner of the weight matrix W, and the remaining elements in the weight matrix W can be equal to 0. The read voltage parameter offset matrix v can be implemented as a matrix of read voltage parameter offsets {V1(y,i),…,Vm(y,i)} (for example, when m=3, read voltage parameter offsets {V1(y,i),V2(y,i),V3(y,i)}), where the read voltage parameter offsets {V1(y,i),…,Vm(y,i)} (for example Fig. 9 The read voltage parameter offsets {V1(y), V2(y), V3(y)}) illustrated by the small circles shown are arranged as elements of the read voltage parameter offset matrix v.

[0098] According to some embodiments, it may be assumed that the candidate programming states {PS(1), . . . , PS(Y)} are stable, in which case, Figure 5 The distribution illustrated by the curve may be stable and not change over time, and the read voltage parameter offsets {Vj(y,i)} corresponding to the same candidate value Bit0_diff(y,i) collected by the memory controller 110 (e.g., three read voltage parameter offsets V1(y,i), V2(y,i) and V3(y,i)) may be equal to each other and illustrated by an identical read voltage parameter offset V(y,i) corresponding to the candidate value Bit0_diff(y,i), which results in a curve of predicted read voltage parameter offset V_predict(y) passing through the identical read voltage parameter offset V(y,i), but the present invention is not limited thereto. In general, the candidate programming states {PS(1), ..., PS(Y)} may be unstable and Figure 5 The distribution shown in the curve may change over time. When necessary, the memory controller 110 may update any read voltage parameter offset Vj(y,i) among the read voltage parameter offsets {Vj(y,i)} in one or more data sets so that at least one of the read voltage control databases (e.g., the read voltage control database 116D and / or the read voltage control database 120D) is up-to-date to ensure overall performance.

[0099] Table 1

[0100] Bit0_diff(y) … V1(y) … V2(y) … V3(y) … V_predict(y) …

[0101] Table 1 illustrates an example of the form of any data in one or more data sets in the above-mentioned at least one read voltage control database (for example, the read voltage control database 116D and / or the read voltage control database 120D) at time point t1, wherein the symbol “…” may indicate that certain table contents are deleted, and for the programming state index y, the memory controller 110 may store the bit zero count difference Bit0_diff(y), the read voltage parameter offsets V1(y), V2(y) and V3(y) and the predicted read voltage parameter offset V_predict(y) in any data set of the above-mentioned at least one read voltage control database according to the form shown in Table 1, but the present invention is not limited to this. According to some embodiments, the form of the data set (e.g., table form) may vary. For example, the predetermined read voltage parameter offset count m, such as the number of read voltage parameter offsets {Vj(y,i)} in the read voltage parameter offsets {V1(y,i), ..., Vm(y,i)} corresponding to the same candidate value Bit0_diff(y,i) (e.g., when m=3, the read voltage parameter offsets {V1(y,i), V2(y,i), V3(y,i)}), may vary, and in particular, may be equal to any one of a plurality of positive integers (e.g., {2, 3, 4, ...}). In some examples, the memory controller 110 may generate the predicted read voltage parameter offset V_predict(y) in real time without storing the predicted read voltage parameter offset V_predict(y) in the at least one read voltage control database.

[0102] Table 2

[0103] Bit0_diff(y) … 500 … V1(y) … 2 … V2(y) … … V3(y) … … V_predict(y) … …

[0104] Table 3

[0105] Bit0_diff(y) … 500 1000 … V1(y) … 2 3 … V2(y) … 3 5 … V3(y) … 2 4 … V_predict(y) … 2 4 …

[0106] Table 4A

[0107]

[0108]

[0109] Table IV B

[0110]

[0111] Table IV C

[0112] D 500 1000 1500 2000 2500 3000 3500 4000 4500 5000 V1 4 4 6 8 10 12 14 24 22 20 V2 2 6 6 8 14 14 16 18 18 24 V3 2 6 8 10 12 18 18 20 22 20 P 2 5 6 8 12 14 16 20 20 21

[0113] Table IV D

[0114] D 5500 6000 6500 7000 7500 8000 8500 9000 9500 10000 V1 26 24 26 28 32 36 42 44 54 60 V2 22 24 28 28 32 38 40 54 50 58 V3 24 26 26 32 36 32 44 50 56 56 P 23 25 26 29 33 35 41 46 53 57

[0115] Table II illustrates an example of the latest information in any of the above data sets at time point t2, Table III illustrates an example of the latest information in the data set at time point t3, and Tables IV A to IV D illustrate examples of the latest information in the data set at time point t4, where t1 < t2 < t3 < t4. The symbol "…" may indicate that some table contents are deleted, and for better understanding, the read voltage parameter offsets {V1(y), V2(y), V3(y)} and the predicted read voltage parameter offset V_predict(y) can be respectively implemented as the read voltage code offsets {Vc1(y), Vc2(y), Vc3(y)} and the predicted read voltage code offset Vc_predict(y), but the present invention is not limited thereto. According to some embodiments, the latest information and / or the data volume in the data set at any one of the time points t1, t2, t3, and t4 can vary. For example, the memory controller 110 can pre-fill a preset value (e.g., 0xFFFF) into the data set so that Table I is filled with the preset value at time point t1, and the blank table contents shown in Tables II and III and the blank table contents starting from "500" in Table II can also be filled with the preset value. The preset value can indicate that an update with new information is required to complete the data set, and the memory controller 110 can update the data to the data set as shown in Tables IV A to IV D and replace all parts of the data set with the preset value with the latest information respectively. In some examples, the read voltage parameter offsets {V1(y), V2(y), V3(y)} and the predicted read voltage parameter offset V_predict(y) can be respectively implemented as the read voltage offsets {Vth1(y), Vth2(y), Vth3(y)} and the predicted read voltage offset Vth_predict(y). According to some views, Tables IV A to IV D can be regarded as multiple sub-tables of a table, and the table contents of the multiple sub-tables can be arranged in the table in the order of Table IV A, Table IV B, Table IV C, and Table IV D, where the table contents of Table IV B to Table IV D can be regarded as the subsequent table contents after the table contents of Table IV A.

[0116] During a predetermined period corresponding to an initial state of the memory device 100 (e.g., the period between two time points t0a and t0b when t0a < t0b < t1), the memory controller 110 may record (Y - 1) optimal read voltage parameters {V_Opt(y)|y = 1, …, (Y - 1)} (e.g., optimal read voltage parameters {V_Opt(1), …, V_Opt(Y - 1)}) of a predetermined period T0 as (Y - 1) preset read voltage parameters {V_Default(y)|y = 1, …, (Y - 1)} (e.g., preset read voltage parameters {V_Default(1), …, V_Default(Y - 1)}), respectively, and record (Y - 1) bit zero counts {Bit0} corresponding to the preset read voltage parameters {V_Default(y)|y = 1, …, (Y - 1)} as reference bit zero counts {Bit0_ref(y)|y = 1, …, (Y - 1)} (e.g., Figure 5 the reference bit zero count Bit0_ref(y) shown and Figure 6 the reference bit zero counts Bit0_ref(y1), Bit0_ref(y2), and Bit0_ref(y3) shown), where the initial state may include an initial distribution state of the bit zero count Bit0 with respect to the read voltage parameter V, such as Figure 5For example, when the read voltage code Vc is used as a representative of the read voltage Vth, the memory controller 110 may record (Y-1) optimal read voltage codes {Vc_Opt(y)|y=1,…,(Y-1)} (e.g., optimal read voltage code {Vc_Opt(1),…,Vc_Opt(Y-1)}) of the predetermined time period T0 as (Y-1) default read voltage codes {Vc_Default(y)|y=1,…,(Y-1)} (e.g., default read voltage code {Vc_Default(1),…,Vc_Default(Y-1)}) for performing a read retry procedure, but the present invention is not limited thereto. In some examples, the memory controller 110 may record (Y-1) optimal read voltages {Vth_Opt(y)|y=1,…,(Y-1)} (e.g., optimal read voltages {Vth_Opt(1),…,Vth_Opt(Y-1)}) of a predetermined time period T0 as (Y-1) default read voltages {Vth_Default(y)|y=1,…,(Y-1)} (e.g., default read voltages {Vth_Default(1),…,Vth_Default(Y-1)}) for performing a read retry procedure. In addition, the memory controller 110 may store (Y-1) preset read parameters {V_Default(y)|y=1,…,(Y-1)} and reference bit zero counts {Bit0_ref(y)|y=1,…,(Y-1)} in a predetermined area (e.g., a system area) in the non-volatile memory 120. For example, the distribution state of the bit zero count Bit0 relative to the read voltage parameter V may change due to some reasons, and the (Y-1) optimal read voltage parameters {V_Opt(y)|y=1,…,(Y-1)} may also become different from the optimal read voltage parameters in the predetermined time period T0. The memory controller 110 may refer to the pre-stored (Y-1) preset read voltage parameters {V_Default(y)|y=1,…,(Y-1)} and reference bit zero counts {Bit0_ref(y)|y=1,…,(Y-1)} to perform related operations.

[0117] When the read retry procedure is started, for any of the cases of y=1, ... and y=(Y-1), the memory controller 110 may use the default read voltage code Vc_Default(y) to control the non-volatile memory 120 to attempt to perform a read operation according to the default read voltage Vth_Default(y) corresponding to the default read voltage code Vc_Default(y) to obtain the bit zero count Bit0, and calculate the bit zero count difference Bit0_diff(y), in particular, a pre-filtered value Bit0_diff of the bit zero count difference Bit0_diff(y). Pre-filtering (y) (e.g., the difference between the bit zero count Bit0 and the reference bit zero count Bit0_ref(y) (Bit0-Bit0_ref(y))) is filtered to generate the filtered value of the bit zero count difference Bit0_diff(y) as follows:

[0118] Bit0_diff(y)=((Bit0_diff Pre-filtering (y) / M)*M)=(((Bit0-Bit0_ref(y)) / M)*M);

[0119] The memory controller 110 may perform integer calculations in the above formula to make the operation “ / ” an integer division (integer division; discarding the decimal part (or remainder)), and “M” may be a predetermined bit zero count difference filter parameter of the bit zero count difference Bit0_diff(y), and the predetermined bit zero count difference filter parameter M may be a positive integer greater than one, but the present invention is not limited thereto. In addition, the memory controller 110 can perform a scanning operation according to the read voltage scanning control scheme to determine a value V(y) on the V-axis corresponding to a local minimum value of the bit zero count change ΔBit0 (e.g., a value Vc(y) on the Vc-axis or a value Vth(y) on the Vth-axis) as the latest optimal read voltage parameter V_Opt(y) (e.g., the latest optimal read voltage code Vc_Opt(y) or the latest optimal read voltage Vth_Opt(y)), and calculate a best value V_best(y) (e.g., the difference (V_Opt(y)-V_Default(y)) between the latest optimal read voltage parameter V_Opt(y) and the default read voltage parameter V_Default(y)) as the read voltage parameter offset Vj(y,i).

[0120] For better understanding, when the read voltage parameter offset {V1(y), V2(y), V3(y)} and the predicted read voltage parameter offset V_predict(y) are respectively implemented as the read voltage code offset {Vc1(y), Vc2(y), Vc3(y)} and the predicted read voltage code offset Vc_predict(y), the value V(y) on the V axis, the latest optimal read voltage parameter V_Opt(y), the best value V_best(y), the preset read voltage parameter V_Default(y) and the read voltage parameter offset Vj(y,i) can respectively represent the value Vc(y) on the Vc axis, the latest optimal read voltage code Vc_Opt(y), the best value Vc_best(y), the preset read voltage code Vc_Default(y) and the read voltage code offset Vc_j(y,i), but the present invention is not limited to this. According to certain embodiments, when the read voltage parameter offset {V1(y), V2(y), V3(y)} and the predicted read voltage parameter offset V_predict(y) are respectively implemented as the read voltage offset {Vth1(y), Vth2(y), Vth3(y)} and the predicted read voltage offset Vth_predict(y), the value V(y) on the V axis, the latest optimal read voltage parameter V_Opt(y), the best value V_best(y), the preset read voltage parameter V_Default(y) and the read voltage parameter offset Vj(y,i) may respectively represent the value Vth(y) on the Vth axis, the latest optimal read voltage Vth_Opt(y), the best value Vth_best(y), the preset read voltage Vth_Default(y) and the read voltage offset Vth_j(y,i).

[0121] For example, when Bit0=74327, Bit0_ref(y)=73728, M=500 and V_best(y)=2, the memory controller 110 may determine Bit0_diff(y)=(((74327-73728) / 500)*500)=500 and V1(y)=V_best(y)=2, and in particular, obtain the latest information (Bit0_diff(y)=500, V1(y)=2) and fill {500,2} into the predetermined column corresponding to Bit0_diff(y)=500 shown in Table 2. In addition, the memory controller 110 can perform the read retry procedure multiple times in response to multiple errors. For example, when Bit0=75327, Bit0_ref(y)=73728, M=500 and V_best(y)=3, the memory controller 110 can determine Bit0_diff(y)=(((75327-73728) / 500)*500)=500 and V2(y)=V_best(y)=3, and in particular, obtain the latest information (Bit0_diff(y)=500, V2(y)=3) and fill {500,2,3} into the predetermined column corresponding to Bit0_diff(y)=500, and the rest can be deduced in the same way. Therefore, the memory controller 110 can perform similar operations to obtain the latest information {{(Bit0_diff(y)=500, V1(y)=2), (Bit0_diff(y)=500, V2(y)=3), (Bit0_diff(y)=500, V3(y)=2)}, {(Bit0_diff(y)=1000, V1(y)=3), (Bit0_diff(y)=1000, V2(y)=5), (Bit0_diff(y)=1000, V3(y)=4)}, dynamically generate or update the predicted read voltage parameter offset V_predict(y), and fill {500,2,3,2,2} and {1000,3,5,4,4} into the predetermined columns corresponding to Bit0_diff(y)=500 and Bit0_diff(y)=1000 shown in Table 3, respectively.

[0122] In the example shown in Table 3, the memory controller 110 may dynamically generate or update the predicted read voltage parameter offset V_predict(y) at any time point, and in particular, generate or update the predicted read voltage parameter offset V_predict(y) when a cumulative read voltage parameter offset count CNT(Vj(y,i)) (e.g., the number of read voltage parameter offsets {Vj(y,i)} corresponding to the same candidate value Bit0_diff(y,i)) reaches a predetermined read voltage parameter offset count m, but the present invention is not limited thereto. According to some embodiments, the memory controller 110 may generate or update the predicted read voltage parameter offset V_predict(y) at one or more subsequent time points, for example, generate or update the predicted read voltage parameter offset V_predict(y) when the memory controller 110 has completed filling a plurality of candidate values ​​{Bit0_diff(y,i)} and all read voltage parameter offsets {Vj(y,i)} corresponding to the candidate values ​​{Bit0_diff(y,i)} into the form shown in Table 1.

[0123] Regardless of whether the memory controller 110 generates the predicted read voltage parameter offset V_predict(y) in the example shown in Table 3, the memory controller 110 can perform read retry procedures multiple times in response to multiple errors, and in particular, perform similar operations to obtain the latest information {{(Bit0_diff(y)=-10000, V1(y)=-58),(Bit0_diff(y)=-10000, V2(y)=-56),(Bit0_diff(y)=-10000, V3(y)=-56)},…,{(Bit0_diff(y)= 10000, V1(y)=60),(Bit0_diff(y)=10000, V2(y)=58),(Bit0_diff(y)=10000, V3(y)=56)}, dynamically generate or update the predicted read voltage parameter offset V_predict(y), and fill {{-10000,-58,-56,-56,-56},…,{10000,60,58,56,57}} into the predetermined columns corresponding to Bit0_diff(y)={-10000,…,10000} shown in Tables 4A to 4D respectively. For example, for example, the memory controller 110 may have generated a portion of the predicted data {V_predict(y,i)} for predicting the read voltage parameter offset V_predict(y) at time point t3 (e.g., the predicted data “2” in the column corresponding to Bit0_diff(y)=500 and the predicted data “4” in the column corresponding to Bit0_diff(y)=1000 as shown in Table 3), and may have updated the predicted data {V_predict(y,i)} for predicting the read voltage parameter offset V_predict(y) at time point t4 (e.g., the predicted data “2” in the column corresponding to Bit0_diff(y)=500 and the predicted data “5” in the column corresponding to Bit0_diff(y)=1000 as shown in Tables 4A to 4D).

[0124] In the examples shown in Tables 4A to 4D, the memory controller 110 may prevent any information from being stored in any row corresponding to Bit0_diff(y)=0, but the present invention is not limited thereto. According to some embodiments, the memory controller 110 may store the central information {0,0,0,0,0} in a predetermined central row corresponding to Bit0_diff(y)=0, wherein the predetermined central row may be located next to the rightmost row of Table 4B, and in particular, may be inserted between the row corresponding to Bit0_diff(y)=-500 shown in Table 4B and the row corresponding to Bit0_diff(y)=500 shown in Table 4C. For the sake of brevity, similar contents of these embodiments will not be described in detail again.

[0125] Fig.11 This is a schematic diagram of the workflow of the method according to an embodiment of the present invention, wherein a read parameter learning procedure for establishing and updating one or more data sets in at least one read voltage control database (e.g., read voltage control database 116D and / or read voltage control database 120D) can be integrated into a read retry procedure to increase overall performance. The memory controller 110 can receive a plurality of host commands from the host device 50 through the transmission interface circuit 118, so as to access data (e.g., data reading and data writing / programming) to the non-volatile memory 120 according to the plurality of host commands, and perform a read parameter learning procedure to generate or update prediction data {V_predict(y,i)} of the predicted read voltage parameter offset V_predict(y) adjusted for the read voltage parameter V (e.g., the read voltage code Vc and the read voltage Vth), such as the prediction data shown in Tables 4A to 4D, so as to determine the latest optimal read voltage parameter V_Opt(y) in real time by predicting the predicted read voltage parameter offset V_predict(y), so as to accurately determine the respective programming states {PS(y)} of the memory cells in the memory cell group, and thus maintain the accuracy of data reading. For example, the latest optimal read voltage parameter V_Opt(y) can represent the latest and best value of the read voltage parameter V for distinguishing two adjacent candidate programming states {PS(y)} among multiple candidate programming states {PS(1),…,PS(Y)} for the memory cell group, such as any group of adjacent candidate programming states among the group of candidate programming states PS(y1), PS(y1+1)}, the group of candidate programming states {PS(y2), PS(y2+1)} and the group of candidate programming states {PS(y3), PS(y3+1)}.

[0126] In step S11, when the read retry procedure is started, for any of the cases y=1, ... and y=(Y-1), the memory controller 110 may use the preset read voltage code Vc_Default(y) to control the non-volatile memory 120 to attempt to perform a read operation according to the preset read voltage code Vc_Default(y) to obtain the bit zero count Bit0, and calculate the bit zero count difference Bit0_diff(y) to determine Bit0_diff(y)=(((Bit0-Bit0_ref(y)) / M)*M) (for simplicity, in Fig.11 It is marked as "Bit0_diff = (Bit0-Bit0_ref) / M*M").

[0127] In step S12, the memory controller 110 may determine whether the accumulated read voltage parameter shift count CNT(Vj(y,i)), such as the number of read voltage parameter shifts {Vj(y,i)} corresponding to the same candidate value Bit0_diff(y,i), reaches a predetermined read voltage parameter shift count m (for simplicity, in Fig.11 If yes, go to step S13; if no, go to step S16.

[0128] In step S13, the memory controller 110 may update the read voltage prediction function f(Bit0_diff) corresponding to the read voltage prediction model according to the data set, in particular, by updating P=f(Bit0_diff)=x 0 *β to implement the read voltage prediction model (e.g. β(x 0 )=(X T WX) -1 X T Wv; for brevity, Fig.11 , labeled as "P = f(Bit0_diff)") in the data set to fit a local curve of the predicted read voltage parameter offset V_predict(y) to the corresponding local trend of the data set. The data set may include collected data for adjustments to the read voltage parameter V in the data set, such as the read voltage parameter offset {Vj(y,i)}, and the corresponding local trend of the data set may represent the corresponding local trend of the collected data. Fig. 9 Taking the curve shown as an example, the local curve of the predicted read voltage parameter offset V_predict(y) may represent a portion of the curve of the predicted read voltage parameter offset V_predict(y) relative to the bit zero count difference Bit0_diff(y), wherein the curve of the predicted read voltage parameter offset V_predict(y) may be a nonlinear curve.

[0129] In step S14, the memory controller 110 may perform a prediction of the predicted read voltage parameter offset V_predict(y) to generate or update the predicted read voltage parameter offset V_predict(y) prediction data {V_predict(y,i)} according to the read voltage prediction function f(Bit0_diff) updated in step S13 (for simplicity, in Fig.11 In particular, a read retry operation is performed to attempt to read data according to the prediction data V_predict(y,i) corresponding to the bit zero count difference Bit0_diff(y) among the prediction data {V_predict(y,i)}.

[0130] In step S15, the memory controller 110 may determine whether the decoding operation (e.g., hard decoding operation and / or soft decoding operation) performed using the predicted read voltage parameter offset V_predict(y) generated (or updated) in step S14 is successful. If yes (e.g., no hard / soft decoding error occurs), the process proceeds to step S18; if no (e.g., at least one hard / soft decoding error occurs), the process proceeds to step S17.

[0131] In step S16, the memory controller 110 may scan the optimal value V_best(y) for the adjustment of the read voltage parameter V. In particular, the memory controller 110 may perform a scanning operation according to the read voltage scanning control scheme to determine the latest optimal read voltage parameter V_Opt(y). The optimal value V_best(y) is calculated according to the latest optimal read voltage parameter V_Opt(y) and the default read voltage parameter V_Default(y). The latest information (Bit0_diff(y)=Bit0_diff(y,i), Vj(y)=V_best(y)) (for simplicity, in Fig.11 ((Bit0_diff, V_best)) is added to the data set and attempts to read data based on the best value V_best(y) (for brevity, in Fig.11 ” is marked as “Read operation according to V_best”).

[0132] In step S17, the memory controller 110 may scan the optimal value V_best(y) for the adjustment of the read voltage parameter V. In particular, the memory controller 110 may perform a scanning operation according to the read voltage scanning control scheme to determine the latest optimal read voltage parameter V_Opt(y). The optimal value V_best(y) is calculated according to the latest optimal read voltage parameter V_Opt(y) and the default read voltage parameter V_Default(y). The latest information (Bit0_diff(y)=Bit0_diff(y,i), Vj(y)=V_best(y)) (for simplicity, in Fig.11 The data set is marked as "(Bit0_diff, V_best)" in the figure, and the old collected data (for example, the read voltage parameter offset Vj(y,i) farthest from the best value V_best among all read voltage parameter offsets {Vj(y,i)} corresponding to the same candidate value Bit0_diff(y,i) in the data set) is added to the data set, and the old collected data is deleted, and the read voltage parameter offset Vj(y,i) farthest from the best value V_best is tried according to the best value V_best (for simplicity, in Fig.11 ” is marked as “Read operation according to V_best”).

[0133] In step S18, the memory controller 110 may selectively return data (e.g., error-free data). For example, when step S18 is performed after step S15, the memory controller 110 may have obtained error-free data from a decoding operation (e.g., a hard decoding operation and / or a soft decoding operation) performed using the predicted read voltage parameter offset V_predict(y), and may return the error-free data to the host device 50. For another example, when step S18 is performed after any one of step S16 and step S17 is performed, if no uncorrectable ECC (UECC) error occurs when reading data from the non-volatile memory 120 according to the best value V_best(y), the memory controller 110 may return the error-free data to the host device 50; otherwise, the memory controller 110 may execute an error handling procedure and return an error message to the host device 50 to indicate the occurrence of an uncorrectable ECC error.

[0134] For example, one or more data sets of the at least one read voltage control database (e.g., the read voltage control database 116D and / or the read voltage control database 120D) may include multiple data sets corresponding to cases y=1,… and y=(Y-1), respectively. The memory controller 110 may establish and update a data set corresponding to any one of the multiple data sets corresponding to cases y=1,… and y=(Y-1), respectively. In particular, local linear regression may be performed to generate and update prediction data {V_predict(y,i)|i=i_min,…,i_max} of the predicted read voltage parameter offset V_predict(y), such as prediction data {V_predict(y,i)} corresponding to multiple candidate values ​​{Bit0_diff(y,i)}, respectively. Since the memory controller 110 can update any one of the read voltage parameter offsets {Vj(y,i)} in the data set to make the at least one read voltage control database the latest version, the memory controller can refer to the at least one read voltage control database to correctly and effectively read data without errors in the read retry procedure, wherein the data {(Bit0_diff(y,i), V_predict(y,i))|i=i_min,…,i_max} in the data set can accurately indicate the nonlinear relationship between the bit zero count difference Bit0_diff(y) and the predicted read voltage parameter offset V_predict(y) (e.g. Fig. 9 Therefore, the memory controller 110 can use the prediction information to perform data access control of the memory device 100 to ensure the overall performance.

[0135] In addition, the memory controller 110 may perform the above-mentioned local linear regression to update the read voltage prediction model (eg, using P = f(Bit0_diff) = x 0 *β(eg,β(x 0 )=(X T WX) -1 X T Wv) is used to implement the model), and during the local linear regression, a predetermined weight function w is used to fit the local curve of the predicted read voltage parameter offset V_predict(y) to the corresponding local trend of the collected data (e.g., read voltage parameter offset {Vj(y,i)}) for the adjustment of the read voltage parameter V in the data set, so as to maintain the accuracy of the prediction of the predicted read voltage parameter offset V_predict(y), so as to ensure the correctness of the read data obtained from any read retry operation in the read retry procedure (e.g., the read retry operation in step S14). For the sake of brevity, similar contents of this embodiment will not be described in detail again.

[0136] For a better understanding, this method can be Fig.10 The process is illustrated in the flowchart, but the present invention is not limited thereto. According to some embodiments, one or more steps may be performed in Fig.10 The memory controller 110 may add, delete or modify the workflow shown. For example, the memory controller 110 may perform a read parameter learning procedure (or related operations related to the read parameter learning) separately without integrating the read parameter learning procedure into the read retry procedure. For another example, as long as the computing power of the memory controller 110 is sufficient, the memory controller 110 may perform a prediction of the predicted read voltage parameter offset V_predict(y) in step S14 to generate or update more predicted data of the predicted read voltage parameter offset V_predict(y), especially, the pre-filtered value Bit0_diff of the reference bit zero count difference Bit0_diff(y) Pre-filtering (y) (e.g., the difference (Bit0-Bit0_ref(y)) between the bit zero count Bit0 and the reference bit zero count Bit0_ref(y)) is used to calculate a predicted value of the predicted read voltage parameter offset V_predict(y) according to the read voltage prediction function f(Bit0_diff) updated in step S13 to obtain a pre-filtered value Bit0_diff from the bit zero count difference Bit0_diff(y) Pre-filtering (y) to the predicted value of the predicted read voltage parameter offset V_predict(y), such as Fig. 9The continuous mapping illustrated by the curve shown. For the sake of brevity, similar contents of these embodiments will not be described in detail again.

[0137] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made according to the scope of the patent application of the present invention should fall within the scope of the present invention.

Claims

1. A method for controlling data access of a memory device by using prediction information, the method being applied to a memory controller of the memory device, the memory device comprising the memory controller and a non-volatile memory, the non-volatile memory comprising at least one non-volatile memory element, the method comprising: receiving a plurality of host commands from a host device for performing data access to the non-volatile memory according to the plurality of host commands, wherein the data access includes data reading; and A read parameter learning procedure is performed to generate prediction data of a predicted read voltage parameter offset for adjusting a read voltage parameter to maintain the accuracy of the data reading, wherein the read parameter learning procedure includes: Scanning an optimal value for the adjustment of the read voltage parameter and adding latest information including the optimal value to a data set among one or more data sets in at least one read voltage control database; Performing local linear regression according to the data set to update a read voltage prediction function corresponding to a read voltage prediction model for fitting a local curve of the predicted read voltage parameter offset to a corresponding local trend of the data set; and The prediction data of the predicted read voltage parameter deviation is generated or updated according to the read voltage prediction function.

2. The method according to claim 1, characterized in that The read parameter learning procedure is integrated into a read retry procedure, and the memory controller is used for performing read retry and read parameter learning in the read retry procedure.

3. The method according to claim 1, characterized in that The memory controller is used to perform the read parameter learning procedure to generate or update the prediction data of the predicted read voltage parameter offset, so as to determine a latest optimal read voltage parameter in real time by predicting the predicted read voltage parameter offset, wherein the latest optimal read voltage parameter represents a latest and optimal value of the read voltage parameter.

4. The method according to claim 1, characterized in that The memory controller is used to perform the local linear regression to update the read voltage prediction model, and during the local linear regression, a predetermined weight function is used to fit the local curve of the predicted read voltage parameter offset to the corresponding local trend of the data set to maintain the accuracy of the prediction of the predicted read voltage parameter offset to ensure the correctness of the read data obtained from a read retry operation.

5. The method according to claim 4, characterized in that The data set includes collected data for the adjustment of the read voltage parameter within the data set, and the corresponding local trend of the data set represents the corresponding local trend of the collected data.

6. The method according to claim 1, characterized in that The local curve of the predicted read voltage parameter shift represents a portion of a curve of the predicted read voltage parameter shift, wherein the curve of the predicted read voltage parameter shift is a non-linear curve.

7. The method according to claim 1, characterized in that The reading parameter learning program also includes: In response to reaching a predetermined criterion, old collected data farthest from the optimal value among a set of collected data for the adjustment of the read voltage parameter in the data set is deleted.

8. The method according to claim 7, characterized in that The read voltage prediction function is a function of a bit zero count difference; the data set includes collected data for the adjustment of the read voltage parameter in the data set, the collected data corresponds to multiple candidate values ​​of the bit zero count difference, and the group of collected data represents collected data corresponding to a same candidate value among the multiple candidate values.

9. The method according to claim 1, characterized in that The read voltage prediction function is a function of a bit zero count difference; the data set includes collected data for the adjustment of the read voltage parameter in the data set, and the collected data corresponds to a plurality of candidate values ​​of the bit zero count difference.

10. A memory controller of a memory device, the memory device comprising the memory controller and a non-volatile memory, the non-volatile memory comprising at least one non-volatile memory element, the memory controller comprising: a processing circuit for controlling the memory controller according to a plurality of host commands from a host device to allow the host device to access the non-volatile memory through the memory controller; as well as a transmission interface circuit for communicating with the host device; in: The memory controller receives the plurality of host commands from the host device through the transmission interface circuit of the memory controller, so as to perform data access to the non-volatile memory according to the plurality of host commands, wherein the data access includes data reading; and The memory controller performs a read parameter learning procedure to generate prediction data of a predicted read voltage parameter offset for adjusting a read voltage parameter so as to maintain the accuracy of the data reading, wherein the read parameter learning procedure includes: Scanning an optimal value for the adjustment of the read voltage parameter and adding latest information including the optimal value to a data set among one or more data sets in at least one read voltage control database; Performing local linear regression according to the data set to update a read voltage prediction function corresponding to a read voltage prediction model for fitting a local curve of the predicted read voltage parameter offset to a corresponding local trend of the data set; and The prediction data of the predicted read voltage parameter deviation is generated or updated according to the read voltage prediction function.

11. A memory device comprising the memory controller according to claim 10, wherein the memory device comprises: The non-volatile memory is used to store information; and The memory controller is coupled to the non-volatile memory and is used to control the operation of the memory device.

12. An electronic device comprising the memory device of claim 11, and further comprising: The host device is coupled to the memory device, wherein the host device includes: at least one processor for controlling the operation of the host device; as well as a power supply circuit coupled to the at least one processor and configured to provide power to the at least one processor and the memory device; The memory device provides storage space for the host device.

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