Integrated circuit testing method
By using a median board in integrated circuit testing, the integrated circuits of different connection methods can be tested by the same circuit board, solving the problem of the need for different circuit boards in the prior art, and achieving cost reduction and testing simplification.
Patent Information
- Application Number
- CN202311163023.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-09-11
- Publication Date
- 2025-03-11
AI Technical Summary
In the prior art, it is necessary to provide different circuit boards for integrated circuits of different connection modes, resulting in high manufacturing costs, increased testing complexity and time costs.
By providing at least one intermediary board, the integrated circuit with different connection methods can be tested by the same circuit board, the specific method is to electrically connect the circuit board to the first integrated circuit, and then electrically connect the second integrated circuit through the first adapter board, and test both by controlling the integrated circuit.
The test method of using integrated circuits with different connection methods to share the same circuit board is realized, which reduces manufacturing costs, simplifies the test process, and reduces time costs.
Smart Images
Figure CN119597564A_ABST
Abstract
Description
Technical Field
[0001] The invention relates to an integrated circuit testing method, in particular to an integrated circuit testing method which can use the same circuit board to test integrated circuits with different connection modes. Background Art
[0002] In the prior art, after packaging the memory, the memory manufacturer needs to provide different circuit boards in order to test different memories. For example, if the fourth-generation double data rate synchronous dynamic random access memory (DDR4 memory) and the third-generation double data rate synchronous dynamic random access memory (DDR3 memory) are to be tested, because the distribution or number of connection points or pins of the DDR4 memory and the DDR3 memory are different, the memory manufacturer needs to provide circuit boards with different layouts. Otherwise, the DDR4 memory and the DDR3 memory may not be correctly electrically connected to the same circuit board for testing. However, this method not only increases the manufacturing cost, but also requires the design of new test methods for different circuit boards, thereby increasing the complexity and time cost of the test. Summary of the invention
[0003] An object of the present invention is to provide an integrated circuit testing method that allows integrated circuits with different connection methods to share a circuit board.
[0004] Another object of the present invention is to provide an integrated circuit testing system that allows integrated circuits with different connection methods to share a circuit board.
[0005] An embodiment of the present invention provides an integrated circuit testing method, comprising: electrically connecting a circuit board to a first integrated circuit; testing the first integrated circuit through a control integrated circuit; electrically connecting the circuit board to a first adapter board, and electrically connecting a second integrated circuit to the first adapter board, wherein a first connection method between the first integrated circuit and the circuit board is different from a second connection method between the second integrated circuit and the first adapter board; and testing the second integrated circuit through the control integrated circuit.
[0006] Another embodiment of the present invention provides an integrated circuit testing system, including: a circuit board, which can be electrically connected to a first integrated circuit; a first adapter board, which can be electrically connected to the circuit board and a second integrated circuit, wherein a first connection method between the first integrated circuit and the circuit board is different from a second connection method between the second integrated circuit and the first adapter board; and a control integrated circuit, which can test the first integrated circuit through the circuit board or test the second integrated circuit through the circuit board and the first adapter board.
[0007] According to the above embodiments, by providing at least one intermediate board, integrated circuits with different connection modes can be tested through the same circuit board, which can solve the problem in the prior art that two different circuit boards need to be prepared for integrated circuits with different connection modes. BRIEF DESCRIPTION OF THE DRAWINGS
[0008] Figure 1 as well as Figure 2 A schematic diagram of an integrated circuit testing system according to an embodiment of the present invention is shown;
[0009] Figure 3 A schematic diagram showing different integrated circuits having different connection modes according to an embodiment of the present invention is shown;
[0010] Figure 4 A schematic diagram of an integrated circuit testing system according to another embodiment of the present invention is shown;
[0011] Figure 5 A schematic diagram of an integrated circuit testing system according to another embodiment of the present invention is shown;
[0012] Figure 6 A flow chart of an integrated circuit testing method according to an embodiment of the present invention is shown.
[0013] Description of reference numerals:
[0014] 100: Circuit board 101: Control integrated circuit I_1: First integrated circuit
[0015] I_2: second integrated circuit I_3: third integrated circuit 401: DDR4 memory
[0016] 403: DDR3 memory L_1, L_2: wire ML_1: first adapter board
[0017] ML_2: Second adapter board 601-607: Steps P_11, P_12, P_21, P_22: Pins DETAILED DESCRIPTION
[0018] The content of the present invention will be described below with multiple embodiments. The "first", "second" and similar descriptions in the following description of the specification are only used to define different elements, parameters, data, signals or steps, and are not used to limit their order. For example, the first device and the second device can be different devices with the same structure.
[0019] Figure 1 as well as Figure 2 FIG. 1 is a schematic diagram of an integrated circuit (IC) testing system according to an embodiment of the present invention. Figure 1 as well as Figure 2 To further understand the content of the present invention. Figure 1 As shown, the first integrated circuit I_1 and the second integrated circuit I_2 can be tested by a control integrated circuit 101 disposed on the circuit board 100. The circuit board 100 has a predetermined layout, for example, including a plurality of wires (only two wires L_1 and L_2 are marked in the figure). The first integrated circuit I_1 can be directly electrically connected to the circuit board 100, while the second integrated circuit I_2 cannot be directly electrically connected to the circuit board 100, but needs to be electrically connected to the circuit board 100 through a first adapter board ML_1. A first connection method between the first integrated circuit I_1 and the circuit board 100 and a second connection method between the second integrated circuit I_2 and the first adapter board ML_1 are different. Details about the connection method will be described in detail in Figure 3 Describe. Figure 1 as well as Figure 2 The architecture can be used to test the first integrated circuit I_1 and the second integrated circuit I_2 by controlling the integrated circuit 101.
[0020] Figure 3 FIG. 1 is a schematic diagram showing different integrated circuits having different connection modes according to an embodiment of the present invention. Figure 3 In the embodiment, the number of first pins (only labeled P_11 and P_12 for illustration) of the first integrated circuit I_1 is different from the number of second pins (only labeled P_21 and P_22 for illustration) of the second integrated circuit I_2, wherein the first integrated circuit I_1 is electrically connected to the first transfer board ML_1 through the first pins P_11 and P_21, and the second integrated circuit I_2 is electrically connected to the first transfer board ML_1 through the second pins P_21 and P_22. For example, Figure 3 As shown in the figure above, the first integrated circuit I_1 has 8 pins, and the predetermined layout of the circuit board 100 enables the circuit board 100 to be directly electrically connected to the first integrated circuit I_1 having 8 pins. Figure 3 As shown in the figure below, the second integrated circuit I_2 has only 6 pins and cannot be directly electrically connected to the circuit board 100. Therefore, the second integrated circuit I_2 needs to be first set on the first adapter board ML_1 with 8 pins, and then electrically connected to the circuit board 100 through the first adapter board ML_1. However, the electrical connection between the first integrated circuit I_1, the second integrated circuit I_2 and the circuit board 100 can be achieved through other connection interfaces and is not limited to pins. In addition, in one embodiment, the first integrated circuit I_1 and the second integrated circuit I_2 have the same number of pins, but their distribution positions are different, or have the same number of pins and the same pin distribution position, but the pins at the same position receive different signals.
[0021] As mentioned above, the first adapter board ML_1 can provide an electrical connection between the second integrated circuit I_2 and the circuit board 100. In one embodiment, the first adapter board ML_1 has a plurality of electronic components that can provide electrical connection and appropriate impedance matching, such as wires, resistors, capacitors or inductors. In other words, the first adapter board ML_1 can also be regarded as a circuit board. In one embodiment, a first resistance value, a first capacitance value and a first inductance value of the first adapter board ML_1 are lower than a second resistance value, a second capacitance value and a second inductance value of the circuit board 100. That is, the first adapter board ML_1 has a lower resistance value, capacitance value and inductance value. In this way, when the second integrated circuit I_2 is tested with the control integrated circuit 101, the test signal may have less signal offset or cause less electrical characteristic changes to the entire system, which is less likely to affect the test results.
[0022] The first integrated circuit I_1 and the second integrated circuit I_2 may have various structures. In one embodiment, the first integrated circuit I_1 and the second integrated circuit I_2 are integrated circuits of the same type, that is, they have the same functions. For example, the first integrated circuit I_1 and the second integrated circuit I_2 are both memories, both image sensors, both amplifier circuits, or both display driver circuits. In one embodiment, a data output rate of the first integrated circuit I_1 is higher than a data output rate of the second integrated circuit I_2. For example, if Figure 4 As shown in the embodiment of FIG. 4 , the first integrated circuit I_1 is a DDR4 memory 401 and the second integrated circuit I_2 is a DDR3 memory 403. Figure 4 In the embodiment, the data output rate of the DDR4 memory 401 is higher than that of the DDR3 memory 403, and the accuracy of the clock signal for transmitting and receiving data is required to be higher. Therefore, the tolerance of the DDR3 memory 403 to the signal deviation generated by the first adapter board ML_1 is higher than the tolerance of the DDR4 memory 401 to the signal deviation generated by the first adapter board ML_1. Therefore, in such an example, the circuit board 100 is designed for the first integrated circuit I_1 with a lower tolerance for signal deviation, so that when the first integrated circuit I_1 is tested, inaccurate test results will not be obtained due to the first adapter board ML_1.
[0023] In one embodiment, the above test includes functional verification of the first integrated circuit I_1 and the second integrated circuit I_2. For example, verify whether the data output rate of the first integrated circuit I_1 and the second integrated circuit I_2 is within a predetermined range. If the first integrated circuit I_1 and the second integrated circuit I_2 are DDR4 memory 401 and DDR3 memory 403, respectively, it can be verified whether the access rate of the DDR4 memory 401 and the DDR3 memory 403 is within a predetermined range. The above test may also include testing the output signal quality of the first integrated circuit I_1 and the second integrated circuit I_2, for example, after providing input signals to the first integrated circuit I_1 and the second integrated circuit I_2, observe whether the eye diagram of the output signal is clear.
[0024] In one embodiment, after the first integrated circuit I_1 and the second integrated circuit I_2 are tested and the test results of the first integrated circuit I_1 and the second integrated circuit I_2 indicate that they can operate normally, the integrated circuit manufacturer will provide the reference control parameters of the first integrated circuit I_1 and the second integrated circuit I_2 to the customer when delivering the first integrated circuit I_1 and the second integrated circuit I_2 to the customer. In this way, after the customer assembles the first integrated circuit I_1 and the second integrated circuit I_2 into other electronic devices, the customer can directly control the first integrated circuit I_1 and the second integrated circuit I_2 with the reference control parameters, or generate the control parameters required by the customer according to the reference control parameters to control the first integrated circuit I_1 and the second integrated circuit I_2.
[0025] However, the second integrated circuit I_2 is electrically connected to the circuit board 100 through the first adapter board ML_1, and the first adapter board ML_1 may cause the signal to generate a signal offset or the electrical characteristics of the entire system (such as resistance value, capacitance value or inductance value). Therefore, in one embodiment, a first resistance value, a first capacitance value or a first inductance value generated by the first adapter board ML_1 is first calculated, and the integrated circuit 101 is controlled to generate at least one reference control parameter of the second integrated circuit I_2 according to the first resistance value, the first capacitance value or the first resistance value. For example, the first resistance value, the first capacitance value or the first resistance value can be obtained by measuring the resistance value, the capacitance value or the inductance value of the circuit board or the electronic device in the prior art. Then, the integrated circuit 101 is controlled to generate a reference control parameter according to the signal offset that may be generated by the first resistance value, the first capacitance value or the first inductance value. In another embodiment, a signal offset caused by the first adapter board ML_1 is calculated, and the integrated circuit 101 is controlled to generate at least one reference control parameter of the second integrated circuit I_2 according to the signal offset. For example, a signal input point and a signal output point may be preset on the first adapter board ML_1, and then an input signal may be provided to the signal input point. Then, the difference between the frequency, amplitude or phase of the output signal and the frequency, amplitude or phase of the input signal may be measured to calculate the signal deviation caused by the first adapter board ML_1.
[0026] The above embodiments are all described with reference to two different integrated circuits and one adapter board. However, the concepts disclosed in the above embodiments can be applied to more than two different integrated circuits and more than one adapter board. Figure 5 FIG. 2 shows a schematic diagram of an integrated circuit testing system according to another embodiment of the present invention. Figure 5 As shown, except Figure 1 In addition to the first integrated circuit I_1, the second integrated circuit I_2 and the first adapter board ML_1, a second adapter board ML_2 is also provided for testing the third integrated circuit I_3.
[0027] The third integrated circuit I_3 needs to be electrically connected to the circuit board 100 through a second adapter board ML_2. The third connection method between the third integrated circuit I_3 and the circuit board 100 is different from the first connection method between the first integrated circuit I_1 and the circuit board 100 and the second connection method between the second integrated circuit I_2 and the circuit board 100. The details of the connection method are described in Figure 3 Describe. Figure 5 The architecture can respectively test the first integrated circuit I_1, the second integrated circuit I_2 and the third integrated circuit I_3 by controlling the integrated circuit 101.
[0028] The second adapter board ML_2 can provide an electrical connection between the third integrated circuit I_3 and the circuit board 100. The second adapter board ML_2 can have a plurality of electronic components that can provide electrical connection and appropriate impedance matching, such as resistors, capacitors, and inductors. In other words, the second adapter board ML_2 can also be regarded as a circuit board. In one embodiment, the resistance value, capacitance value, and inductance value of the second adapter board ML_2 are lower than a second resistance value, a second capacitance value, and a third inductance value of the circuit board 100. That is, the second adapter board ML_2 has a lower resistance value, capacitance value, and inductance value. In this way, when the third integrated circuit I_3 is tested with the control integrated circuit 101, the test signal can have less signal offset and is less likely to affect the test results.
[0029] The first integrated circuit I_1, the second integrated circuit I_2, and the third integrated circuit I_3 may have various structures. In one embodiment, the first integrated circuit I_1, the second integrated circuit I_2, and the third integrated circuit I_3 are integrated circuits of the same type, that is, they have the same functions. For example, the first integrated circuit I_1, the second integrated circuit I_2, and the third integrated circuit I_3 are all memories, all image sensors, all amplifier circuits, or all display driver circuits. In one embodiment, a data output rate of the first integrated circuit I_1 is higher than a data output rate of the third integrated circuit I_3.
[0030] The aforementioned circuit board 100 and the control integrated circuit 101 can be regarded as an integrated circuit testing system, and an integrated circuit testing method can be obtained according to the aforementioned embodiments. Figure 6 A flow chart of an integrated circuit testing method according to an embodiment of the present invention is shown, which comprises the following steps:
[0031] Step 601:
[0032] A circuit board (eg, circuit board 100 ) is electrically connected to a first integrated circuit (eg, first integrated circuit I_1 ).
[0033] Step 603:
[0034] The first integrated circuit is tested by a control integrated circuit (eg, control integrated circuit 101 ).
[0035] Step 605:
[0036] The circuit board is electrically connected to a first transfer board (eg, the first transfer board ML_1 ), and a second integrated circuit (eg, the second integrated circuit I_2 ) is electrically connected to the first transfer board.
[0037] A first connection method between the first integrated circuit I_1 and the circuit board 100 is different from a second connection method between the second integrated circuit I_2 and the first adapter board.
[0038] Step 607:
[0039] The second integrated circuit is tested by the control integrated circuit.
[0040] Other detailed steps can be deduced based on the above-mentioned embodiments, and thus will not be described in detail here.
[0041] According to the above embodiments, by providing at least one intermediate board, integrated circuits with different connection modes can be tested through the same circuit board, which can solve the problem in the prior art that two different circuit boards need to be prepared for integrated circuits with different connection modes.
[0042] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made according to the scope of the patent application of the present invention should fall within the protection scope of the present invention.
Claims
1. An integrated circuit testing method, characterized in that: include: Electrically connecting a circuit board to a first integrated circuit; Testing the first integrated circuit by a control integrated circuit; electrically connecting the circuit board to a first adapter board, and electrically connecting a second integrated circuit to the first adapter board, wherein a first connection method between the first integrated circuit and the circuit board is different from a second connection method between the second integrated circuit and the first adapter board; and The second integrated circuit is tested by the control integrated circuit.
2. The integrated circuit testing method according to claim 1, characterized in that: A data output rate of the first integrated circuit is higher than a data output rate of the second integrated circuit.
3. The integrated circuit testing method according to claim 1, characterized in that: The first integrated circuit is a fourth generation double data rate synchronous dynamic random access memory, and the second integrated circuit is a third generation double data rate synchronous dynamic random access memory.
4. The integrated circuit testing method according to claim 1, characterized in that: The first integrated circuit and the second integrated circuit are of the same type.
5. The integrated circuit testing method according to claim 1, characterized in that: The number of at least one first pin of the first integrated circuit is different from the number of at least one second pin of the second integrated circuit, wherein the first integrated circuit is electrically connected to the first adapter board through the first pin and the second integrated circuit is electrically connected to the first adapter board through the second pin.
6. The integrated circuit testing method according to claim 1, characterized in that: A first resistance value, a first capacitance value, and a first inductance value of the first adapter board are lower than a second resistance value, a second capacitance value, and a second inductance value of the circuit board.
7. The integrated circuit testing method according to claim 1, characterized in that: Also includes: A first resistance value, a first capacitance value or a first inductance value generated by the first adapter board is calculated, and at least one reference control parameter of the second integrated circuit is generated by the control integrated circuit according to the first resistance value, the first capacitance value or the first resistance value.
8. The integrated circuit testing method according to claim 1, characterized in that: Also includes: A signal deviation caused by the first adapter plate is calculated, and at least one reference control parameter of the second integrated circuit is generated by the control integrated circuit according to the signal deviation.
9. The integrated circuit testing method according to claim 1, characterized in that: Also includes: The circuit board is electrically connected to a second adapter board, and a third integrated circuit is electrically connected to the second adapter board, wherein a third connection mode between the third integrated circuit and the circuit board is different from the first connection mode and the second connection mode; and The third integrated circuit is tested by the control integrated circuit.
10. An integrated circuit testing system, characterized in that: include: a circuit board, electrically connected to a first integrated circuit; a first adapter board, capable of electrically connecting the circuit board and a second integrated circuit, wherein a first connection method between the first integrated circuit and the circuit board is different from a second connection method between the second integrated circuit and the first adapter board; as well as A control integrated circuit can test the first integrated circuit through the circuit board or test the second integrated circuit through the circuit board and the first adapter board.