Output load circuit of display panel and display panel

Abstract

The invention discloses an output on-load circuit of a display panel and the display panel. The output on-load circuit comprises a load resistor, a load switch and a control circuit. Wherein the target voltage source is connected with the load resistor through the load switch. The control circuit comprises a first signal end and a second signal end. The first signal end and the second signal end are connected with the main control chip, and the control circuit is configured to control the load switch to be switched on under the condition that a termination signal is accessed to the first signal end and control the load switch to be switched off under the condition that a starting signal is accessed to the second signal end. According to the output load circuit, under the condition that the display mode is switched to the low-power-consumption mode, the target voltage source is connected with an additional load resistor, so that the load of the target voltage source in the low-power-consumption mode is improved, the difference between the voltage source connected loads in the display mode and the low-power-consumption mode is reduced, and the display effect is improved. The jump values of the corresponding voltage signals and current signals are reduced, and noise and electromagnetic interference generated by the display panel are reduced.

Description

Technical Field

[0001] The present application relates to the technical field of display panels, and more specifically, to an output load circuit of a display panel and a display panel. Background Art

[0002] For each pixel of the display panel, when the display panel displays a frame, the driving circuit will output the data voltage according to the picture data to drive the pixel display and enter the display mode. Then, the driving circuit stops outputting the data voltage and enters the low power mode. That is to say, the display panel will experience two time periods, the display mode and the low power mode, when displaying each frame. The load difference of the driving circuit in the display mode and the low power mode is large. Especially when the display panel displays the heaviest load picture, the corresponding voltage signal and current signal may jump, causing the display panel to generate more serious noise and electromagnetic interference. Summary of the invention

[0003] Embodiments of the present application provide an output load circuit of a display panel and a display panel.

[0004] The output load circuit of the display panel provided in the embodiment of the present application. The driving circuit of the display panel includes a target voltage source and a main control chip, and the driving circuit drives the display panel to work in a display mode or a low power consumption mode. In the display mode, the target voltage source is connected to a first load. In the low power consumption mode, the target voltage source is connected to a second load, and the first load is greater than the second load. In the case where the display mode is switched to the low power consumption mode, the main control chip is configured to provide a termination signal. In the case where the low power consumption mode is switched to the display mode, the main control chip is configured to provide a start signal. The output load circuit includes a load resistor, a load switch and a control circuit. Among them, the target voltage source is connected to the load resistor through the load switch. The control circuit includes a first signal terminal and a second signal terminal. The first signal terminal and the second signal terminal are connected to the main control chip, and the control circuit is configured to control the load switch to be closed when the first signal terminal is connected to the termination signal, and to control the load switch to be disconnected when the second signal terminal is connected to the start signal.

[0005] In the output load circuit provided in the embodiment of the present application, when the display mode is switched to the low power consumption mode, the target voltage source is connected to an additional load resistor, so that the load of the target voltage source in the low power consumption mode is increased, the difference in the load connected to the voltage source in the display mode and the low power consumption mode is reduced, the jump value of the corresponding voltage signal and current signal is reduced, and the noise and electromagnetic interference generated by the display panel are reduced.

[0006] In some embodiments, the control circuit includes a control unit, a pull-up unit, and a pull-down unit. The control unit is connected to the controlled end of the load switch. The pull-up unit is connected to the first signal end, and the pull-up unit and the control unit are connected to a control node. The pull-up unit is configured to write a first voltage signal to the control node when the first signal end is connected to the termination signal, so that the control unit controls the load switch to close. The pull-down unit is connected to the second signal end, and the pull-down unit and the control unit are connected to the control node. The pull-down unit is configured to write a second voltage signal to the control node when the second signal end is connected to the start signal, so that the control unit controls the load switch to open.

[0007] In some embodiments, the pull-up unit includes a first voltage source, a first transistor, and a second transistor, the control electrode of the first transistor is connected to the first signal terminal, the first electrode of the first transistor is grounded, the second electrode of the first transistor is connected to the control electrode of the second transistor, the first electrode of the second transistor is connected to the first voltage source, the second electrode of the second transistor is connected to the control node, and the first voltage source is configured to provide the first voltage signal.

[0008] In some embodiments, within a preset time period after the first signal terminal is connected to the termination signal, the second transistor is closed so that the first voltage source writes the first voltage signal into the control node.

[0009] In some embodiments, the pull-down unit includes a third transistor, a control electrode of the third transistor is connected to the second signal terminal, a first electrode of the third transistor is grounded, a second electrode of the third transistor is connected to the control node, and a ground terminal is configured to provide the second voltage signal.

[0010] In some implementations, when the second signal terminal is connected to the start signal, the third transistor is closed so that the ground terminal writes the second voltage signal into the control node.

[0011] In some embodiments, the control unit includes a fourth transistor, a control electrode of the fourth transistor is connected to the control node, a first electrode of the fourth transistor is grounded, and a second electrode of the fourth transistor is connected to the control end of the load switch.

[0012] The display panel provided in the present application includes the output load circuit provided in the embodiment of the present application.

[0013] In some embodiments, within a second preset period before the display mode is switched to the low power consumption mode, the main control chip is configured to provide a pre-trigger signal to the control circuit so that the control circuit controls the load switch to close.

[0014] In some embodiments, the display panel further includes a loop capacitor, and the target voltage source is grounded through the loop capacitor.

[0015] In the output load circuit and display panel of the display panel provided in the embodiment of the present application, when the display mode is switched to the low power consumption mode, the target voltage source is connected to an additional load resistor in the output load circuit, so that the load of the target voltage source in the low power consumption mode is increased, the difference in the load connected to the voltage source in the display mode and the low power consumption mode is reduced, the jump value of the corresponding voltage signal and current signal is reduced, and the noise and electromagnetic interference generated by the display panel are reduced.

[0016] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0018] Figure 1 is a schematic diagram of an output carrier circuit and a display panel of certain embodiments of the present application;

[0019] Figure 2 is a schematic diagram of an output load circuit of certain embodiments of the present application;

[0020] Figure 3 It is a schematic diagram of an output load circuit and a display panel of certain embodiments of the present application.

[0021] Explanation of main component symbols: target voltage source 110, main control chip 120, output load circuit 200, load switch 211, load resistor 212, control circuit 220, first signal terminal 221, second signal terminal 222, pull-up unit 223, pull-down unit 224, control unit 225, display panel 1000. DETAILED DESCRIPTION

[0022] The embodiments of the present application are described in detail below, and the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.

[0023] For each pixel of the display panel, when the display panel displays a frame, the driving circuit will output the data voltage according to the picture data to drive the pixel display and enter the display mode. Then, the driving circuit stops outputting the data voltage and enters the low power mode. That is to say, the display panel will experience two time periods, the display mode and the low power mode, when displaying each frame. The load difference of the driving circuit in the display mode and the low power mode is large. Especially when the display panel displays the heaviest load picture, the corresponding voltage signal and current signal may jump, causing the display panel to generate more serious noise and electromagnetic interference.

[0024] In order to solve the above technical problems, the embodiments of the present application provide an output load circuit of a display panel and a display panel. In the output load circuit provided in the embodiments of the present application, when the display mode is switched to the low power consumption mode, the target voltage source is connected to an additional load resistor, so that the load of the target voltage source in the low power consumption mode is increased, the difference in the load connected to the voltage source in the display mode and the low power consumption mode is reduced, the jump value of the corresponding voltage signal and current signal is reduced, and the noise and electromagnetic interference generated by the display panel are reduced.

[0025] Reference Figure 1 , the output carrier circuit 200 of the display panel 1000 provided in the embodiment of the present application. The driving circuit of the display panel 1000 includes a target voltage source 110 and a main control chip 120, and the driving circuit drives the display panel 1000 to operate in a display mode or a low power consumption mode. In the display mode, the target voltage source 110 is connected to a first load. In the low power consumption mode, the target voltage source 110 is connected to a second load, and the first load is greater than the second load. When the display mode is switched to the low power consumption mode, the main control chip 120 is configured to provide a termination signal. When the low power consumption mode is switched to the display mode, the main control chip 120 is configured to provide a start signal.

[0026] The output loaded circuit 200 includes a load resistor 212, a load switch 211, and a control circuit. The target voltage source 110 is connected to the load resistor 212 through the load switch 211. The control circuit includes a first signal terminal 221 and a second signal terminal 222. The first signal terminal 221 and the second signal terminal 222 are connected to the main control chip 120, and the control circuit is configured to control the load switch 211 to be closed when the first signal terminal 221 is connected to a termination signal, and to control the load switch 211 to be opened when the second signal terminal 222 is connected to a start signal.

[0027] Specifically, when the display panel 1000 displays dynamic content or static content, the refresh rate and brightness of the display panel 1000 may change according to the technical type of the display panel 1000 and the usage scenario of the device. In order to optimize the display effect, performance and power consumption of the display panel 1000, the display panel 1000 usually switches the working mode when displaying a frame of the picture.

[0028] The image displayed by the display panel 1000 may be scanned line by line. Each time the display panel 1000 completes scanning of a frame of image (scanning each line from the top to the bottom of the screen), it takes a short time to "return to the top" to prepare for displaying the next frame of image. This period of time is the vertical retrace or vertical blanking period (V-Blanking). V-Blanking refers to the time interval when the display panel 1000 returns to the top of the screen to start displaying the next frame of image after completing scanning of a frame of image.

[0029] When the display panel 1000 is scanning an image, the display panel 1000 operates in a display mode, and the driving circuit can output a corresponding data voltage to the pixel. During the V-Blanking period when the display panel 1000 completes a frame of image scanning, the display panel 1000 can operate in a low power consumption mode, which can ensure that the display panel 1000 displays an image while reducing power consumption as much as possible.

[0030] It is understandable that the load of the target voltage source 110 in the display mode and the low power mode of the driving circuit in the display panel 1000 is quite different. The driving circuit needs to provide data voltage to drive the pixels in the display mode, especially when the display panel 1000 displays the heaviest load picture, the display mode needs to drive the pixel load is relatively large, and the corresponding voltage signal and current signal may jump, causing the display panel 1000 to generate more serious noise and electromagnetic interference.

[0031] The target voltage source 110 may be a voltage source to which the display panel 1000 is connected when switching the working mode, and the load difference is large. The target voltage source 110 may be an input voltage source Vin, a high level voltage source VGH or a low level voltage source VGL in a gate drive circuit (GOA). In the display mode, the target voltage source 110 is connected to a first load. In the low power consumption mode, the target voltage source 110 is connected to a second load, and the first load is greater than the second load.

[0032] The main control chip 120 may be an integrated circuit chip (Timing Controller IC, Tcon IC) in the display panel 1000. The Tcon IC may generate and adjust the timing signals required by the display panel 1000. The timing signals are used to control the scanning sequence, row and column signals, and the synchronization mode of driving pixels of the display panel 1000, and may accurately control the display of each frame of an image on each row and each column to ensure that the image does not tear or misalign. The Tcon IC transmits the control signal to the driving circuit of the display panel 1000 to ensure that the voltage of each pixel is properly adjusted, thereby forming an accurate image.

[0033] The termination signal and the start signal may be timing control signals output by the main control chip 120. When the display mode is switched to the low power consumption mode, the main control chip 120 is configured to provide a termination signal. When the low power consumption mode is switched to the display mode, the main control chip 120 is configured to provide a start signal.

[0034] When the display mode is switched to the low power mode, the main control chip 120 outputs a termination signal, and the control circuit controls the load switch 211 to close, so that the target voltage source 110 is connected to the additional load resistor 212, so that the load of the target voltage source 110 in the low power mode is increased, and the difference in the load connected to the target voltage source 110 in the display mode and the low power mode is reduced, the corresponding voltage signal and current signal jump value is reduced, and the noise and electromagnetic interference generated by the display panel 1000 are reduced.

[0035] by Figure 1 For example, the load switch 211 may be a switch device M1, the load resistor 212 may be a resistor device R1, and the target voltage source 110 may be a voltage source AVDDS. The switch device M1 may be a transistor, the voltage source AVDDS is connected to a first electrode of the switch device M1, a second electrode of the switch device M1 is connected to a first end of the resistor device R1, a second end of the resistor device R1 is grounded, and the control circuit is connected to a control electrode of the switch device M1.

[0036] When the display mode is switched to the low power mode, the main control chip 120 outputs a termination signal, the control circuit controls the switch device M1 to close, and the voltage source AVDDS is connected to the resistor device R1. When the low power mode is switched to the display mode, the main control chip 120 outputs a start signal, the control circuit controls the switch device M1 to open, and the voltage source AVDDS is disconnected from the resistor device R1.

[0037] In this way, in the low power consumption mode, the voltage source AVDDS is connected to the additional resistor device R1, which reduces the difference in the load connected to the voltage source AVDDS in the display mode and the low power consumption mode, reduces the jump values ​​of the voltage signal and the current signal corresponding to the voltage source AVDDS, and reduces the noise and electromagnetic interference generated by the display panel 1000.

[0038] Reference Figure 2 In some embodiments, the control circuit includes a control unit 225, a pull-up unit 223, and a pull-down unit 224. The control unit 225 is connected to the controlled end of the load switch 211. The pull-up unit 223 is connected to the first signal end 221, and the pull-up unit 223 and the control unit 225 are connected to the control node. The pull-up unit 223 is configured to write a first voltage signal to the control node when the first signal end 221 is connected to the termination signal, so that the control unit 225 controls the load switch 211 to close. The pull-down unit 224 is connected to the second signal end 222, and the pull-down unit 224 and the control unit 225 are connected to the control node. The pull-down unit 224 is configured to write a second voltage signal to the control node when the second signal end 222 is connected to the start signal, so that the control unit 225 controls the load switch 211 to open.

[0039] Specifically, Figure 2 For example, the control node may be node N. The pull-down unit 224 , the pull-up unit 223 and the control unit 225 are connected to the node N. The control unit 225 may control the switch device M1 to be closed or opened according to the voltage signal written into the node N.

[0040] The first signal terminal 221 may be a signal terminal Teninate, and the pull-up unit 223 may be connected to the signal terminal Teninate. When the display mode is switched to the low power mode, the main control chip 120 outputs a termination signal to the signal terminal Teninate, and the pull-up unit 223 provides the first voltage signal to the control unit 225, so that the control unit 225 controls the switch device M1 to close.

[0041] The second signal terminal 222 may be a signal terminal STV1, and the pull-down unit 224 may be connected to the signal terminal STV1. When the low power mode is switched to the display mode, the main control chip 120 outputs a start signal to the signal terminal STV1, and the pull-up unit 223 provides the first voltage signal to the control unit 225, so that the control unit 225 controls the switch device M1 to be disconnected.

[0042] In some embodiments, the pull-up unit 223 includes a first voltage source, a first transistor, and a second transistor, the control electrode of the first transistor is connected to the first signal terminal 221, the first electrode of the first transistor is grounded, the second electrode of the first transistor is connected to the control electrode of the second transistor, the first electrode of the second transistor is connected to the first voltage source, the second electrode of the second transistor is connected to the control node, and the first voltage source is configured to provide a first voltage signal.

[0043] Specifically, Figure 2 For example, the first voltage source may be a voltage source HVDD, the first transistor may be a transistor Q1, and the second transistor may be a transistor Q2. The control electrode of the transistor Q1 is connected to the signal terminal Teninate, the first electrode of the transistor Q1 is grounded, the second electrode of the transistor Q1 is connected to the control electrode of the transistor Q2, the first electrode of the transistor Q2 is connected to the voltage source HVDD, the second electrode of the transistor Q2 is connected to the node N, and the voltage source HVDD is configured to provide a first voltage signal.

[0044] When the signal terminal Teninate is connected to the termination signal, the transistor Q1 is closed, so that the control electrode of the transistor Q2 is grounded through the transistor Q1, and the transistor Q2 is closed. The closing of the transistor Q2 causes the first voltage source provided by the voltage source HVDD to be written into the node N.

[0045] In some embodiments, the transistor Q1 is an NMOS transistor, and the transistor Q2 is a PMOS transistor. When the signal terminal Teninate is connected to a termination signal, the signal terminal Teninate is connected to a high level voltage.

[0046] In some embodiments, the pull-up unit 223 further includes a resistor device R2 , and the second electrode of the transistor Q1 may also be connected to the voltage source HVDD through the resistor device R2 .

[0047] In some embodiments, within a preset time period after the first signal terminal 221 is connected to the termination signal, the second transistor is closed so that the first voltage source writes the first voltage signal into the control node.

[0048] Specifically, within the first preset time period after the signal terminal Teninate receives the termination signal, due to the parasitic capacitance between the gate and source of the transistor Q2, the transistor Q2 can be maintained in a closed state, so that the first voltage source writes the first voltage signal into the control node, thereby ensuring that the target voltage source 110 receives the load difference within the preset time period after the display mode is switched to the low power consumption mode, thereby reducing the noise and electromagnetic interference generated by the display panel 1000.

[0049] Reference Figure 2In some embodiments, the pull-down unit 224 includes a third transistor, a control electrode of the third transistor is connected to the second signal terminal 222, a first electrode of the third transistor is grounded, a second electrode of the third transistor is connected to the control node, and the ground terminal is configured to provide a second voltage signal.

[0050] Specifically, Figure 2 For example, the third transistor may be transistor Q3. The control electrode of transistor Q3 is connected to the signal terminal STV1, the first electrode of transistor Q3 is grounded, the second electrode of transistor Q3 is connected to the node N, and the ground terminal is configured to provide a second voltage signal.

[0051] In some embodiments, the transistor Q3 is an NMOS transistor. When the signal terminal STV1 is connected to the start signal, the signal terminal STV1 is connected to the high level voltage.

[0052] In some implementations, when the second signal terminal 222 is connected to a start signal, the third transistor is closed so that the ground terminal writes the second voltage signal into the control node.

[0053] Specifically, when the signal terminal STV1 is connected to the start signal, the transistor Q3 is closed. At this time, no matter the transistor Q2 is in the open or closed state, the second voltage signal provided by the ground terminal can be written into the node N, ensuring that the switch device M1 is opened when the display panel 1000 is switched to the display mode.

[0054] In some embodiments, the control unit 225 includes a fourth transistor, a control electrode of the fourth transistor is connected to the control node, a first electrode of the fourth transistor is grounded, and a second electrode of the fourth transistor is connected to the control end of the load switch 211 .

[0055] Specifically, Figure 2 For example, the fourth transistor may be a transistor Q4. A control electrode of the transistor Q4 is connected to the node N, a first electrode of the transistor Q4 is grounded, and a second electrode of the transistor Q4 is connected to the control terminal of the switch device M1.

[0056] In some embodiments, the control unit 225 further includes a resistor device R4 , and the second electrode of the transistor Q4 can be connected to the voltage source AVDDS through the resistor device R4 .

[0057] In some embodiments, the control circuit further includes a resistor R3 and a capacitor C1, wherein a first end of the resistor R3 is connected to the node N and a second end of the resistor R3 is grounded, a first end of the capacitor C1 is connected to the node N and a second end of the capacitor C1 is grounded.

[0058] In some embodiments, the transistor Q4 may be a PMOS transistor, and the switch device M1 may be an NMOS transistor. The first voltage signal provided by the voltage source HVDD is a high level signal, and the second voltage signal provided by the ground terminal is a low level signal.

[0059] When the first voltage signal is written into the node N, the transistor Q4 is closed so that the control electrode of the switch device M1 is grounded, and the switch device M1 is closed so that the voltage source HVDD is connected to the resistor device R1.

[0060] When the second voltage signal is written to the node N, the transistor Q4 is turned off to disconnect the control electrode of the switch device M1 from the ground terminal, and the switch device M1 is turned off to disconnect the voltage source HVDD from the resistor R1.

[0061] The display panel 1000 provided in the present application includes the output carrier circuit 200 provided in the embodiment of the present application.

[0062] Specifically, Figure 2 For example, when the display panel 1000 works in the display mode, the signal terminal Teminate in the output carrier circuit 200 is connected to a low level signal, and the transistors Q1 and Q2 are disconnected. The signal terminal STV1 is connected to a low level signal, and the transistor Q3 is disconnected. The transistor Q4 and the switch device M1 are disconnected.

[0063] When the display panel 1000 switches from the display mode to the low power mode, the signal terminal Teninate in the output load circuit 200 receives a high level signal, and the transistors Q1 and Q2 are closed. The signal terminal STV1 receives a low level signal, and the transistor Q3 is turned off. The transistor Q4 and the switch device M1 are closed.

[0064] When the display panel 1000 works in the low power consumption mode, the signal terminal Teninate in the output load circuit 200 is connected to a low level signal, the transistor Q1 is turned off, and due to the parasitic capacitance between the gate and source of the transistor Q2, the transistor Q2 is turned on. The signal terminal STV1 is connected to a low level signal, the transistor Q3 is turned off, and the transistor Q4 and the switch device M1 are turned on.

[0065] When the display panel 1000 switches from the low power consumption mode to the display mode, the signal terminal Teninate in the output carrier circuit 200 is connected to a low level signal, the transistor Q1 is disconnected, and due to the parasitic capacitance between the gate and source of the transistor Q2, the transistor Q2 is closed. The signal terminal STV1 is connected to a high level signal, the transistor Q3 is closed, and the transistor Q4 and the switch device M1 are disconnected.

[0066] In some embodiments, within a second preset period before the display mode is switched to the low power consumption mode, the main control chip 120 is configured to provide a pre-trigger signal to the control circuit so that the control circuit controls the load switch 211 to be closed.

[0067] Specifically, the main control chip 120 can provide a pre-trigger signal to the signal terminal Teninate within a second preset time period before the display mode is switched to the low power consumption mode, so that the target voltage source 110 is connected to the load resistor 212 in advance, which is beneficial to reducing the jump amount of the current signal and the voltage signal corresponding to the target voltage source 110.

[0068] In some embodiments, the level signal of the termination signal may be pulled high in advance to obtain a pre-trigger signal.

[0069] In some embodiments, the display panel 1000 further includes a loop capacitor, and the target voltage source 110 is grounded through the loop capacitor.

[0070] Specifically, the noise on the display panel 1000 is mainly caused by the piezoelectric effect of the loop capacitor in the voltage loop. When a large voltage change is applied to both ends of the loop capacitor, the ceramic produces an inverse piezoelectric effect, causing the circuit board to resonate, thereby generating noise. The greater the voltage change, the greater the noise.

[0071] The display panel 1000 of the embodiment of the present application is additionally provided with an output carrier circuit, which can effectively reduce the voltage signal corresponding to the target voltage source 110 and reduce the voltage change across the loop capacitor, thereby reducing the noise on the display panel 1000.

[0072] An embodiment of the present invention provides a display device, and the display device includes the display panel 1000 of any one of the above embodiments.

[0073] Specifically, the display device can be any device that displays whether it is moving (e.g., video) or fixed (e.g., still image) and whether it is text or image. More specifically, the display device can be one of a variety of electronic devices, and the embodiment can be implemented in or associated with a variety of electronic devices. A variety of electronic devices such as (but not limited to) mobile phones, wireless devices, personal data assistants (PS1), handheld or portable computers, GPS receivers / navigators, cameras, MP4 video players, cameras, game consoles, watches, clocks, calculators, TV monitors, flat panel displays, computer monitors, car displays (e.g., odometer displays, etc.), navigators, cockpit controllers and / or displays, camera view displays (e.g., displays of rearview cameras in vehicles), electronic photos, electronic billboards or signs, projectors, architectural structures, packaging and aesthetic structures (e.g., displays of images of a piece of jewelry), etc. The embodiments of the present disclosure do not place special restrictions on the specific form of the above-mentioned display devices.

[0074] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples" or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiments or examples are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. In addition, those skilled in the art may combine and combine different embodiments or examples described in this specification and the features of different embodiments or examples without contradiction.

[0075] In addition, the term "connection" should be understood in a broad sense, for example, it can include fixed connection, detachable connection, or integral connection; it can include direct connection, indirect connection through an intermediate medium, and internal communication between two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0076] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of this application, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0077] Any process or method description in a flowchart or otherwise described herein may be understood to represent a module, fragment or portion of code that includes one or more executable instructions for implementing the steps of a specific logical function or process, and the scope of the preferred embodiments of the present application includes alternative implementations in which functions may not be performed in the order shown or discussed, including performing functions in a substantially simultaneous manner or in reverse order depending on the functions involved, which should be understood by technicians in the technical field to which the embodiments of the present application belong.

[0078] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in the field can change, modify, replace and modify the above embodiments within the scope of the present application.

Claims

1. An output load circuit of a display panel, characterized in that: The driving circuit of the display panel includes a target voltage source and a main control chip, the driving circuit drives the display panel to work in a display mode or a low power consumption mode, in the display mode, the target voltage source is connected to a first load, in the low power consumption mode, the target voltage source is connected to a second load, the first load is greater than the second load, in the case where the display mode is switched to the low power consumption mode, the main control chip is configured to provide a termination signal, and in the case where the low power consumption mode is switched to the display mode, the main control chip is configured to provide a start signal; The output load circuit comprises: Load resistance; A load switch, wherein the target voltage source is connected to the load resistor through the load switch; The control circuit includes a first signal terminal and a second signal terminal, wherein the first signal terminal and the second signal terminal are connected to the main control chip, and the control circuit is configured to control the load switch to be closed when the first signal terminal is connected to the termination signal, and to control the load switch to be opened when the second signal terminal is connected to the start signal.

2. The output carrier circuit of the display panel according to claim 1, characterized in that: The control circuit comprises: A control unit connected to the controlled end of the load switch; a pull-up unit connected to the first signal terminal and connected to a control node with the control unit, and configured to write a first voltage signal into the control node when the first signal terminal is connected to the termination signal, so that the control unit controls the load switch to be closed; The pull-down unit, the second signal terminal, and the control unit are connected to the control node, and are configured to write a second voltage signal into the control node when the second signal terminal is connected to the start signal, so that the control unit controls the load switch to be disconnected.

3. The output carrier circuit of the display panel according to claim 2, characterized in that: The pull-up unit includes a first voltage source, a first transistor, and a second transistor. The control electrode of the first transistor is connected to the first signal terminal, the first electrode of the first transistor is grounded, the second electrode of the first transistor is connected to the control electrode of the second transistor, the first electrode of the second transistor is connected to the first voltage source, the second electrode of the second transistor is connected to the control node, and the first voltage source is configured to provide the first voltage signal.

4. The output carrier circuit of the display panel according to claim 3, characterized in that: Within a first preset time period after the first signal terminal is connected to the termination signal, the second transistor is closed, so that the first voltage source writes the first voltage signal into the control node.

5. The output carrier circuit of the display panel according to claim 2, characterized in that: The pull-down unit includes a third transistor, a control electrode of the third transistor is connected to the second signal terminal, a first electrode of the third transistor is grounded, a second electrode of the third transistor is connected to the control node, and a ground terminal is configured to provide the second voltage signal.

6. The output carrier circuit of the display panel according to claim 5, characterized in that: When the second signal terminal is connected to the start signal, the third transistor is closed, so that the ground terminal writes the second voltage signal into the control node.

7. The output carrier circuit of the display panel according to claim 2, characterized in that: The control unit includes a fourth transistor, a control electrode of the fourth transistor is connected to the control node, a first electrode of the fourth transistor is grounded, and a second electrode of the fourth transistor is connected to the control end of the load switch.

8. A display panel, characterized in that: The display panel comprises the output carrier circuit according to any one of claims 1 to 7.

9. The display panel according to claim 8, characterized in that: In a second preset period before the display mode is switched to the low power consumption mode, the main control chip is configured to provide a pre-trigger signal to the control circuit, so that the control circuit controls the load switch to be closed.

10. The display panel according to claim 8, characterized in that: The display panel further includes a loop capacitor, and the target voltage source is grounded through the loop capacitor.

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