Driving method of display panel

Abstract

The invention discloses a driving method of a display panel. The display panel comprises a pixel driving circuit, and the pixel driving circuit comprises a light-emitting device. One-frame display time of the display panel comprises a writing frame stage and one or more holding frame stages, the display panel writes and displays a picture in the writing frame stage, and the display panel displays the picture in the holding frame stage. The driving method comprises the following steps: resetting an anode end of the light-emitting device in a first time period of a write-in frame stage; the anode terminal of the light emitting device is reset during a second period of time of the at least one hold frame stage. Wherein the initial moment of the first time period and the initial moment of the frame writing stage are spaced by a first interval duration, the initial moment of the second time period and the initial moment of the corresponding frame maintaining stage are spaced by a second interval duration, and the first interval duration is different from the second interval duration. Dark bands can be prevented from being overlapped at the same position, the dark band degree is reduced, and the display effect of the display panel is improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a method for driving a display panel. Background Art

[0002] With the development of display technology, users have higher and higher requirements for the display effect of display panels. Related technologies use timing signals that reset the pixel driving circuit multiple times to improve visual effects such as flickering and afterimages. Figure 1 As shown, the display panel includes a display area 110 and a blanking area 120. The blanking area 120 is actually unloaded, that is, the load of the reset signal in the blanking area 120 is smaller than the load in the display area 110, so that the actual voltage is negative when the reset signal enters the blanking area 120. If the reset signal enters the display area 110, the anode terminal potential of the light-emitting device in the pixel driving circuit will be negative, resulting in a dark band 130 in the display screen. Summary of the invention

[0003] The embodiment of the present application provides a method for driving a display panel, wherein the display panel includes a pixel driving circuit, and the pixel driving circuit includes a light-emitting device; a frame display time of the display panel includes a frame writing phase and one or more frame holding phases, in which the display panel writes and displays a picture in the frame writing phase, and in which the display panel displays the picture in the frame holding phase;

[0004] The driving method comprises:

[0005] Resetting the anode terminal of the light emitting device within a first time period of the writing frame phase;

[0006] Resetting the anode terminal of the light emitting device in a second time period of at least one of the holding frame phases;

[0007] Among them, there is a first interval between the starting time of the first time period and the starting time of the writing frame phase, and there is a second interval between the starting time of the second time period and the corresponding starting time of the keeping frame phase, and the first interval is different from the second interval.

[0008] The beneficial effects provided by the embodiments of the present application include at least:

[0009] In the driving method provided in the embodiment of the present application, at least one of the anode terminal reset time of the light-emitting device in the maintaining frame stage is different from the anode terminal reset time of the light-emitting device in the writing frame stage, so as to avoid the overlapping of dark bands at the same position, reduce the degree of dark bands, and improve the display effect of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 It is a schematic diagram of a dark band;

[0011] Figure 2 is a schematic diagram of a pixel driving circuit;

[0012] Figure 3 It is a schematic diagram of the driving timing;

[0013] Figure 4 This is another schematic diagram of the drive timing;

[0014] Figure 5 is a flow chart of a method for driving a display panel provided in an embodiment of the present application;

[0015] Figure 6 is a schematic diagram of a driving timing provided by an embodiment of the present application;

[0016] Figure 7 is a schematic diagram of another driving timing provided by an embodiment of the present application;

[0017] Figure 8 is a schematic diagram of another driving timing provided by an embodiment of the present application;

[0018] Fig. 9 It is a schematic diagram of the dark band formation process;

[0019] Fig.10 It is a schematic diagram of a dark band improvement effect provided by an embodiment of the present application. DETAILED DESCRIPTION

[0020] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. The described technical solutions are only used to explain and illustrate the ideas of the present application and should not be regarded as limiting the scope of protection of the present application.

[0021] In addition, the "plurality" in the embodiments of the present application refers to two or more. The "first" and "second" in the embodiments of the present application are used to distinguish different technical features, and do not indicate any order, quantity or importance.

[0022] The various embodiments provided in this application are similar, and features in different embodiments may be combined with each other.

[0023] The order of description of the following embodiments is not intended to limit the preferred order of the embodiments.

[0024] See also Figure 2 , Figure 2The present invention is a schematic diagram of a pixel driving circuit. The pixel driving circuit may include a driving transistor T1, a switching transistor T2, a compensation transistor T3, a first reset transistor T4, a first light-emitting control transistor T5, a second light-emitting control transistor T6, a second reset transistor T7, a third reset transistor T8, a storage capacitor Cst, a boost capacitor Cboost, and a light-emitting device.

[0025] The driving transistor T1 includes a first electrode connected to the first node A, a second electrode connected to the second node B, and a control electrode connected to the third node Q. The switching transistor T2 includes a first electrode connected to the data signal DATA, a second electrode connected to the first node A, and a control electrode connected to the first scan control signal PSCAN. The compensation transistor T3 includes a first electrode connected to the second node B, a second electrode connected to the third node Q, and a control electrode connected to the second scan control signal NSCAN_T3. The first reset transistor T4 includes a first electrode connected to the first reset signal Vi_G, a second electrode connected to the third node Q, and a control electrode connected to the third scan control signal NSCAN_T4. The first light-emitting control transistor T5 includes a first electrode connected to the high potential signal VDD, a second electrode connected to the first node A, and a control electrode connected to the light-emitting control signal EM. The second light-emitting control transistor T6 includes a first electrode connected to the second node B, a second electrode connected to the fourth node C, and a control electrode connected to the light-emitting control signal EM. The second reset transistor T7 includes a first electrode connected to the second reset signal VI_ANO, a second electrode connected to the fourth node C, and a control electrode connected to the fourth scan control signal PSCAN2. The third reset transistor T8 includes a first electrode connected to the third reset signal VI_T8, a second electrode connected to the first node A, and a control electrode connected to the fourth scan control signal PSCAN2. The storage capacitor Cst includes an end connected to the high potential signal and the other end connected to the third node Q. The boost capacitor Cboost includes an end connected to the first scan control signal PSCAN and the other end connected to the third node Q. The light emitting device includes an anode end connected to the fourth node C and a cathode end connected to the low potential signal VSS.

[0026] In some embodiments, the control electrode may be a gate electrode, the first electrode may be one of a source electrode and a drain electrode, and the second electrode may be the other of the source electrode and the drain electrode.

[0027] It should be understood that Figure 2In the example, the switch transistor T2, the driving transistor T1, the second reset transistor T7, the third reset transistor T8, the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are P-type thin film transistors (PTFT), and the compensation transistor T3 and the first reset transistor T4 are N-type thin film transistors (NTFT), but this does not constitute a limitation on the embodiments of the present application. In actual applications, each transistor can be arbitrarily set to an N-type thin film transistor or a P-type thin film transistor in accordance with the driving timing.

[0028] See also Figure 3 , Figure 3 It is a schematic diagram of the driving timing. Figure 3 The drive timing shown can be used to drive Figure 2 The corresponding devices in the pixel driving circuit shown.

[0029] like Figure 3 As shown, one frame of picture display time may include one writing frame stage and two holding frame stages. In the writing frame stage, the picture may be written and displayed, and in the holding frame stage, the picture may be displayed. In other words, in the holding frame stage, no new picture needs to be written, but the picture written in the writing frame stage is displayed.

[0030] like Figure 3 As shown, one level cycle of the light emitting control signal EM corresponds to a writing frame stage or a holding frame stage, and one level cycle of the light emitting control signal EM includes a high level duration and a low level duration. If the light emitting control signal EM is at a high level, the first light emitting control transistor T5 and the second light emitting control transistor T6 are turned off, and the light emitting device does not emit light. If the light emitting control signal EM is at a low level, the first light emitting control transistor T5 and the second light emitting control transistor T6 are turned on, and the current flowing through the driving transistor T1 can pass through the second node B and the fourth node C, thereby driving the light emitting device to emit light.

[0031] like Figure 3 As shown, during the high level duration of the light emitting control signal EM, the first scanning control signal PSCAN can be at a low level for a period of time to control the switching transistor T2 to be turned on, so that the data signal DATA can be written into the third node Q. Figure 3 As shown, during the high level duration of the light emitting control signal EM, the fourth scanning control signal PSCAN2 can be at a low level for a period of time to control the second reset transistor T7 to be turned on, thereby resetting the fourth node C. Since the fourth node C is connected to the anode terminal of the light emitting device, resetting the fourth node C is also resetting the anode terminal of the light emitting device.

[0032] Generally, for the writing frame stage, during the high level duration of the light emitting control signal EM, the first scanning control signal PSCAN is set low before the fourth scanning control signal PSCAN2. That is, for the writing frame stage, after the data signal DATA is written into the third node Q, the fourth node C is reset, and then the light emitting device is driven to emit light. For the holding frame stage, after resetting the fourth node C, the light emitting device is driven to emit light.

[0033] See also Figure 4 , Figure 4 This is another schematic diagram of the drive timing. Figure 4 The drive timing shown can be used to drive Figure 2 The corresponding devices in the pixel driving circuit shown.

[0034] Figure 4 Example and Figure 3 The difference between the embodiments is that Figure 3 In the embodiment, the display time of one frame includes one writing frame phase and two holding frame phases. Figure 4 In the embodiment, the display time of one frame includes a writing frame phase and a holding frame phase. Figure 4 For an introduction to each signal in the embodiment, see Figure 3 The embodiments are not described in detail here.

[0035] See also Figure 5 , Figure 5 1 is a flow chart of a method for driving a display panel provided by an embodiment of the present application. The display panel includes a pixel driving circuit, and the pixel driving circuit includes a light emitting device. For example, the pixel driving circuit can be as follows: Figure 2 As shown. The display panel's one-frame display time includes a writing frame phase and one or more holding frame phases. In the writing frame phase, the display panel writes and displays the picture, and in the holding frame phase, the display panel displays the picture. Figure 5 As shown, the driving method may include the following steps:

[0036] Step 510: resetting the anode terminal of the light emitting device within the first time period of the writing frame phase;

[0037] Step 520: Reset the anode terminal of the light emitting device within a second time period of at least one holding frame phase.

[0038] In an embodiment of the present application, the pixel driving circuit includes a second reset transistor T7 and a light emitting device. The second reset transistor T7 includes a first electrode connected to the second reset signal VI_ANO, a second electrode connected to the fourth node C, and a control electrode connected to the fourth scan control signal PSCAN2. The light emitting device includes an anode terminal connected to the fourth node C and a cathode terminal connected to the low potential signal VSS. Thus, resetting the anode terminal of the light emitting device is also resetting the fourth node C. Therefore, the above step 510 can be implemented as: resetting the fourth node C in the first time period of the writing frame stage; the above step 520 can be implemented as: resetting the fourth node C in the second time period of at least one frame holding stage.

[0039] In some embodiments, when the fourth scan control signal PSCAN2 is at the first level, the second reset transistor T7 is controlled to be turned off; when the fourth scan control signal PSCAN2 is at the second level, the second reset transistor T7 is controlled to be turned on. When the second reset transistor T7 is turned on, the second reset signal VI_ANO can reach the fourth node C through the second reset transistor T7, thereby resetting the fourth node C. Therefore, the above step 510 can be implemented as follows: in the first time period of the write frame stage, the fourth scan control signal PSCAN2 is at the second level, and the second reset transistor T7 is controlled to be turned on; the above step 520 can be implemented as follows: in the second time period of at least one hold frame stage, the fourth scan control signal PSCAN2 is at the second level, and the second reset transistor T7 is controlled to be turned on. Optionally, in the case where the second reset transistor T7 is a P-type thin film transistor, the first level of the fourth scan control signal PSCAN2 is a high level, and the second level of the fourth scan control signal PSCAN2 is a low level; in the case where the second reset transistor T7 is an N-type thin film transistor, the first level of the fourth scan control signal PSCAN2 is a low level, and the second level of the fourth scan control signal PSCAN2 is a high level.

[0040] In the embodiment of the present application, the start time of the first time period is separated from the start time of the writing frame stage by a first interval time, and the start time of the second time period is separated from the start time of the corresponding holding frame stage by a second interval time, and the first interval time is different from the second interval time. Since in the first time period and the second time period, the fourth scanning control signal PSCAN2 is at the second level, the second reset transistor T7 is turned on, and the fourth node C and the anode end of the light emitting device are reset, so the anode end reset time of the light emitting device in the writing frame stage is different from the anode end reset time of the light emitting device in the holding frame stage.

[0041] In some embodiments, the first interval duration is greater than the second interval duration. That is, the moment when the fourth scan control signal PSCAN2 is converted to the second level in the frame holding stage is earlier than the moment when the fourth scan control signal PSCAN2 is converted to the second level in the frame writing stage, so that the start-on moment of the second reset transistor T7 in the frame holding stage is earlier than the start-on moment of the second reset transistor T7 in the frame writing stage, and therefore the anode terminal reset time of the light emitting device in the frame holding stage is earlier than the anode terminal reset time of the light emitting device in the frame writing stage.

[0042] In some embodiments, the first interval duration differs from the second interval duration by a target interval duration, and the target interval duration is positively correlated with the width of the blanking area of ​​the display panel. The blanking area may also be referred to as a Blanking area or a Porch area. The embodiment of the present application does not limit the specific proportional relationship between the target interval duration and the width of the blanking area, and can be flexibly set in combination with the display effect in practical applications. For example, one frame display time of the display panel includes a write frame stage and two hold frame stages, and the target interval duration is greater than or equal to one third of the width of the blanking area. For another example, one frame display time of the display panel includes a write frame stage and a hold frame stage, and the target interval duration is greater than or equal to one quarter of the width of the blanking area.

[0043] For the case where one frame display time includes multiple holding frame stages, compared with the writing frame stage, the embodiment of the present application can advance the turn-on time of the second reset transistor T7 in each holding frame stage, thereby advancing the anode end reset time of the light-emitting device in each holding frame stage; or, the turn-on time of the second reset transistor T7 in part of the holding frame stages can be advanced, thereby advancing the anode end reset time of the light-emitting device in part of the holding frame stages, and the anode end reset time of the light-emitting device in other holding frame stages can be consistent with the anode end reset time of the light-emitting device in the writing frame stage.

[0044] In some embodiments, one frame display time of the display panel includes one writing frame stage and at least two holding frame stages; the above step 520 includes: resetting the anode end of the light emitting device in the second time period of each holding frame stage. That is, the anode end reset time of the light emitting device in each holding frame stage can be moved forward.

[0045] In some embodiments, one frame display time of the display panel includes one writing frame stage and at least two holding frame stages; the above step 520 includes: resetting the anode terminal of the light emitting device in the second time period of the first holding frame stage. The first holding frame stage is a holding frame stage adjacent to the writing frame stage. That is, the anode terminal reset time of the light emitting device in the holding frame stage adjacent to the writing frame stage can be moved forward.

[0046] Based on the method of "resetting the anode end of the light-emitting device in the second time period of the first holding frame stage", the driving method of the embodiment of the present application may also include: resetting the anode end of the light-emitting device in the first time period of the second holding frame stage. The second holding frame stage is a holding frame stage that is not adjacent to the writing frame stage. That is, the anode end reset time of the light-emitting device in the holding frame stage adjacent to the writing frame stage can be moved forward, however, the anode end reset time of the light-emitting device in the holding frame stage that is not adjacent to the writing frame stage is the same as the anode end reset time of the light-emitting device in the writing frame stage.

[0047] Based on the method of "resetting the anode end of the light-emitting device in the second time period of the first holding frame stage", the driving method of the embodiment of the present application may also include: resetting the anode end of the light-emitting device in the third time period of the second holding frame stage. Wherein, the second holding frame stage is a holding frame stage that is not adjacent to the writing frame stage; the starting time of the third time period is separated from the starting time of the corresponding second holding frame stage by a third interval time length, the third interval time length is different from the first interval time length, and the third interval time length is different from the second interval time length. That is, the anode end reset time of the light-emitting device in the holding frame stage adjacent to the writing frame stage can be moved forward, however, the anode end reset time of the light-emitting device in the holding frame stage that is not adjacent to the writing frame stage is different from the anode end reset time of the light-emitting device in the writing frame stage and the anode end reset time of the light-emitting device in the holding frame stage adjacent to the writing frame stage. Among them, compared with the anode end reset time of the light-emitting device in the writing frame stage, the anode end reset time of the light-emitting device in the holding frame stage which is not adjacent to the writing frame stage can be advanced, and the degree of advancement can be greater than or less than the degree of advancement in the holding frame stage adjacent to the writing frame stage.

[0048] In some embodiments, one frame display time of the display panel includes one writing frame stage and at least two holding frame stages; the above step 520 includes: resetting the anode end of the light-emitting device in the second time period of the second holding frame stage. The second holding frame stage is a holding frame stage that is not adjacent to the writing frame stage. That is, the anode end reset time of the light-emitting device in the holding frame stage that is not adjacent to the writing frame stage can be moved forward. In this case, compared with the writing frame stage, the anode end reset time of the light-emitting device in the holding frame stage adjacent to the writing frame stage can be moved forward, maintained unchanged, or moved backward, and the embodiments of the present application are not limited to this.

[0049] In summary, the driving method provided by the embodiment of the present application is different from the anode end reset time of the light-emitting device in at least one frame holding stage and the anode end reset time of the light-emitting device in the frame writing stage, so as to avoid the overlap of dark bands at the same position, reduce the degree of dark bands, and improve the display effect of the display panel. In addition, in the embodiment of the present application, compared with the frame writing stage, it is not necessary to perform the writing screen before resetting the anode end of the light-emitting device in the frame holding stage, so the anode end reset time of the light-emitting device in at least one frame holding stage can be moved forward, so as to achieve different anode end reset times while also avoiding affecting the light emission of the light-emitting device, ensuring that the display effect of the display panel is effectively improved. In addition, the embodiment of the present application can flexibly choose to adjust the anode end reset time of the light-emitting device in one or more frame holding stages, as well as the adjustment duration of the anode end reset time, in combination with actual needs, to achieve different improvement effects and degrees of improvement of the dark band.

[0050] The driving method provided in the embodiment of the present application is introduced and explained below in combination with several driving timing examples.

[0051] See also Figures 6 to 8 , Figures 6 to 8 They are respectively schematic diagrams of a driving timing provided in an embodiment of the present application. Figures 6 to 8 The drive timing shown can be used to drive Figure 2 The corresponding devices in the pixel driving circuit shown.

[0052] like Figures 6 to 8 As shown, the display time of one frame of the display panel may include a writing frame stage and one or more holding frame stages. The picture can be written and displayed in the writing frame stage, and the picture can be displayed in the holding frame stage. One level cycle of the light-emitting control signal EM corresponds to one writing frame stage or one holding frame stage, and one level cycle of the light-emitting control signal EM includes a high level duration and a low level duration. Taking the first light-emitting control transistor T5 and the second light-emitting control transistor T6 as P-type thin film transistors as an example, if the light-emitting control signal EM is at a high level, the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are turned off, and the light-emitting device is turned off and does not emit light; if the light-emitting control signal EM is at a low level, the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are turned on, and the light-emitting device is turned on and emits light.

[0053] Take the switch transistor T2 as a P-type thin film transistor as an example. Figures 6 to 8 As shown, in the writing frame stage, within the high level duration of the light emitting control signal EM, the first scanning control signal PSCAN can maintain a low level for a period of time to control the switching transistor T2 to be turned on, so that the data signal DATA can be written into the third node Q.

[0054] Taking the second reset transistor T7 as a P-type thin film transistor as an example, Figures 6 to 8 As shown, in the writing frame stage and the holding frame stage, during the high level duration of the light emitting control signal EM, the fourth scanning control signal PSCAN2 can be respectively at a low level for a period of time to control the second reset transistor T7 to be turned on, so as to reset the anode end of the light emitting device. For the writing frame stage, during the high level duration of the light emitting control signal EM, the first scanning control signal PSCAN can be set low before the fourth scanning control signal PSCAN2; that is, for the writing frame stage, after the data signal DATA is written to the third node Q, the fourth node C is reset, and then the light emitting device is driven to emit light.

[0055] like Figure 6 As shown, one frame display time includes one writing frame stage and two holding frame stages. Compared with the writing frame stage, the anode end reset time of the light-emitting device in each holding frame stage can be moved forward. Among them, the amount of advance can be greater than or equal to one third of the width of the blanking area. That is, in the writing frame stage, the anode end of the light-emitting device starts to reset at a first interval time length from the start time of the writing frame stage, and in each holding frame stage, the anode end of the light-emitting device starts to reset at a second interval time length from the start time of the holding frame stage; the first interval time length is greater than the second interval time length, and the difference between the first interval time length and the second interval time length is greater than or equal to one third of the width of the blanking area.

[0056] like Figure 7 As shown, one frame display time includes one writing frame stage and two holding frame stages. Compared with the writing frame stage, the anode end reset time of the light-emitting device in the holding frame stage adjacent to the writing frame stage can be moved forward, and the anode end reset time of the light-emitting device in the holding frame stage not adjacent to the writing frame stage remains unchanged. That is, the anode end reset moment of the light-emitting device in the writing frame stage is separated from the start moment of the writing frame stage by a first interval time length, the anode end reset moment of the light-emitting device in the holding frame stage adjacent to the writing frame stage is separated from the start moment of the holding frame stage by a second interval time length, and the anode end reset moment of the light-emitting device in the holding frame stage not adjacent to the writing frame stage is separated from the start moment of the holding frame stage by a first interval time length; the first interval time length is greater than the second interval time length.

[0057] like Figure 8As shown, one frame display time includes a writing frame stage and a holding frame stage. Compared with the writing frame stage, the anode end reset time of the light-emitting device in the holding frame stage can be advanced. The advance amount can be greater than or equal to one quarter of the width of the blanking area. That is, in the writing frame stage, the anode end of the light-emitting device starts to reset at a first interval time length from the start time of the writing frame stage, and in the holding frame stage, the anode end of the light-emitting device starts to reset at a second interval time length from the start time of the holding frame stage; the first interval time length is greater than the second interval time length, and the difference between the first interval time length and the second interval time length is greater than or equal to one quarter of the width of the blanking area.

[0058] See also Fig. 9 , one frame display time includes one writing frame phase and two holding frame phases. Fig. 9 As shown, the anode end reset time of the light emitting device in the holding frame stage is the same as the anode end reset time of the light emitting device in the writing frame stage, that is, the interval between the anode end reset moment of the light emitting device in the holding frame stage and the start moment of the holding frame stage is equal to the interval between the anode end reset moment of the light emitting device in the writing frame stage and the start moment of the writing frame stage. When entering the blanking area, the load of the second reset signal VI_ANO changes, and the voltage becomes lower to a greater extent, thereby forming a dark band. Due to Fig. 9 In the process, the anode terminal reset time of the light-emitting device in the frame stage is kept the same as the anode terminal reset time of the light-emitting device in the write frame stage, so that the dark bands overlap and the dark bands are deeper. Fig. 9 Each dark band shown is an overlap of three dark bands.

[0059] See also Fig.10 , Fig.10 It is a schematic diagram of a dark band improvement effect provided by an embodiment of the present application. Fig.10 The improvement in dark bands shown can be based on Figure 6 The driving timing is shown in Figure 1. Fig.10 As shown, in the display area 110, the dark bands 130 cannot overlap at the same position, but are staggered. This is because Figure 6 Compared with the writing frame stage, the anode end reset time of the light emitting device in each holding frame stage is moved forward. Figure 1 and Fig. 9 The dark band shown, Fig.10 The degree of each dark band in the image is reduced, which improves the display effect of the display panel. Fig.10 The width of the blanking area 120 is marked in FIG. The width of the blanking area described in the above embodiment can be referred to in FIG. Fig.10 Notes on annotations in .

[0060] The specific implementation methods and corresponding beneficial effects of the above operations can be found in the above detailed description of the pixel driving circuit, driving timing and display panel driving method, which will not be elaborated here.

[0061] The above is a detailed introduction to a display panel driving method provided in an embodiment of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for technical personnel in this field, according to the idea of ​​the present application, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A method for driving a display panel, characterized in that: The display panel comprises a pixel driving circuit, and the pixel driving circuit comprises a light-emitting device; a frame display time of the display panel comprises a frame writing phase and one or more frame holding phases, in which the display panel writes and displays a picture in the frame writing phase, and in which the display panel displays the picture in the frame holding phase; The driving method comprises: Resetting the anode terminal of the light emitting device within a first time period of the writing frame phase; Resetting the anode terminal of the light emitting device in a second time period of at least one of the holding frame phases; Among them, there is a first interval between the starting time of the first time period and the starting time of the writing frame phase, and there is a second interval between the starting time of the second time period and the corresponding starting time of the keeping frame phase, and the first interval is different from the second interval.

2. The driving method according to claim 1, characterized in that: The first interval duration is greater than the second interval duration.

3. The driving method according to claim 1, characterized in that: The first interval duration differs from the second interval duration by a target interval duration, and the target interval duration is positively correlated with a width of a blanking area of ​​the display panel.

4. The driving method according to claim 3, characterized in that: One frame display time of the display panel includes one writing frame phase and two holding frame phases; the target interval duration is greater than or equal to one third of the width of the blanking area.

5. The driving method according to claim 3, characterized in that: One frame display time of the display panel includes one writing frame phase and one holding frame phase; the target interval duration is greater than or equal to one quarter of the width of the blanking area.

6. The driving method according to claim 1, characterized in that: One frame display time of the display panel includes one frame writing phase and at least two frame holding phases; The resetting of the anode end of the light emitting device within the second time period of at least one of the holding frame stages comprises: In the second time period of each of the holding frame phases, the anode terminal of the light emitting device is reset.

7. The driving method according to claim 1, characterized in that: One frame display time of the display panel includes one frame writing phase and at least two frame holding phases; The resetting of the anode end of the light emitting device within the second time period of at least one of the holding frame stages comprises: Resetting the anode terminal of the light emitting device in the second time period of the first holding frame stage; The first holding frame phase is the holding frame phase adjacent to the writing frame phase.

8. The driving method according to claim 7, characterized in that: The method further comprises: Resetting the anode terminal of the light emitting device within the first time period of the second holding frame stage; The second holding frame phase is the holding frame phase that is not adjacent to the writing frame phase.

9. The driving method according to claim 7, characterized in that: The method further comprises: In a third time period of the second holding frame phase, resetting the anode terminal of the light emitting device; Among them, the second holding frame phase is the holding frame phase that is not adjacent to the writing frame phase; the starting time of the third time period is separated from the corresponding starting time of the second holding frame phase by a third interval length, the third interval length is different from the first interval length, and the third interval length is different from the second interval length.

10. The driving method according to claim 1, characterized in that: One frame display time of the display panel includes one frame writing phase and at least two frame holding phases; The resetting of the anode end of the light emitting device within the second time period of at least one of the holding frame stages comprises: Resetting the anode terminal of the light emitting device in the second time period of the second holding frame stage; The second holding frame phase is the holding frame phase that is not adjacent to the writing frame phase.

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