Driving method of display panel

Abstract

The application discloses a driving method of a display panel. The display panel comprises a pixel driving circuit, and the pixel driving circuit comprises a light emitting device. One frame display time of the display panel comprises one write frame stage and one or more holding frame stages. In the write frame stage, the display panel writes and displays a picture. In the holding frame stage, the display panel displays the picture. The driving method comprises the following steps: in a first time period of the write frame stage, resetting an anode end of the light emitting device; in a second time period of at least one holding frame stage, resetting the anode end of the light emitting device. The starting time of the first time period is separated from the starting time of the write frame stage by a first interval time length. The starting time of the second time period is separated from the starting time of the corresponding holding frame stage by a second interval time length. The first interval time length is different from the second interval time length. The application can avoid the overlapping of dark bands in the same position, reduce the degree of dark bands, and improve the display effect of the display panel.

Description

Technical Field

[0001] This application relates to the field of display technology, and more specifically to a driving method for a display panel. Background Technology

[0002] With the development of display technology, users have increasingly higher requirements for the display effect of display panels. Related technologies employ timing signals that repeatedly reset the pixel driving circuit to improve visual effects such as flicker and image retention. However, as... Figure 1 As shown, the display panel includes a display area 110 and a blanking area 120. The blanking area 120 is actually unloaded; that is, the load of the reset signal in the blanking area 120 is less than the load in the display area 110. Therefore, when the reset signal enters the blanking area 120, the actual voltage is negative. If the reset signal then enters the display area 110, it will cause the anode potential of the light-emitting device in the pixel driving circuit to become negative, resulting in a dark band 130 appearing in the displayed image. Summary of the Invention

[0003] This application provides a driving method for a display panel, the display panel including a pixel driving circuit, the pixel driving circuit including a light-emitting device; one frame display time of the display panel includes a write frame stage and one or more hold frame stages, in the write frame stage the display panel writes and displays the image, and in the hold frame stage the display panel displays the image;

[0004] The driving method includes:

[0005] During the first time period of the write frame phase, the anode of the light-emitting device is reset;

[0006] During a second time period of at least one of the holding frame phases, the anode of the light-emitting device is reset;

[0007] The first time period is separated from the start time of the first time period by a first interval, and the second time period is separated from the start time of the corresponding hold frame phase by a second interval. The first interval and the second interval are different.

[0008] The beneficial effects provided by the embodiments of this application include at least the following:

[0009] The driving method provided in this application embodiment has at least one holding frame stage where the reset time of the anode end of the light-emitting device is different from the reset time of the anode end of the light-emitting device in the write frame stage, so as to avoid the overlap of dark bands at the same position, reduce the degree of dark bands, and improve the display effect of the display panel. Attached Figure Description

[0010] Figure 1 This is a schematic diagram of a dark band;

[0011] Figure 2 This is a schematic diagram of a pixel driving circuit;

[0012] Figure 3 This is a schematic diagram of the driving timing;

[0013] Figure 4 This is a schematic diagram of another driving timing;

[0014] Figure 5 This is a flowchart of a display panel driving method provided in an embodiment of this application;

[0015] Figure 6 This is a schematic diagram of a driving timing provided in an embodiment of this application;

[0016] Figure 7 This is a schematic diagram of another driving timing provided in an embodiment of this application;

[0017] Figure 8 This is a schematic diagram of another driving timing provided in an embodiment of this application;

[0018] Figure 9 This is a schematic diagram of the dark band formation process;

[0019] Figure 10 This is a schematic diagram illustrating the dark band improvement effect provided in an embodiment of this application. Detailed Implementation

[0020] The technical solutions of the embodiments of this application will now be described with reference to the accompanying drawings. The described technical solutions are for illustrative purposes only and should not be construed as limiting the scope of protection of this application.

[0021] Furthermore, in the embodiments of this application, "multiple" refers to two or more. The terms "first" and "second," etc., in the embodiments of this application are used to distinguish different technical features and do not indicate any order, quantity, or importance.

[0022] The various embodiments provided in this application are similar, and features in different embodiments can be combined with each other.

[0023] The order in which the following embodiments are described is not intended to limit the preferred order of the embodiments.

[0024] Please see Figure 2 , Figure 2This is a schematic diagram of a pixel driving circuit. The pixel driving circuit may include a driving transistor T1, a switching transistor T2, a compensation transistor T3, a first reset transistor T4, a first light-emitting control transistor T5, a second light-emitting control transistor T6, a second reset transistor T7, a third reset transistor T8, a storage capacitor Cst, a boost capacitor Cboost, and a light-emitting device.

[0025] The driving transistor T1 includes a first terminal connected to the first node A, a second terminal connected to the second node B, and a control terminal connected to the third node Q. The switching transistor T2 includes a first terminal connected to the data signal DATA, a second terminal connected to the first node A, and a control terminal connected to the first scan control signal PSCAN. The compensation transistor T3 includes a first terminal connected to the second node B, a second terminal connected to the third node Q, and a control terminal connected to the second scan control signal NSCAN_T3. The first reset transistor T4 includes a first terminal connected to the first reset signal Vi_G, a second terminal connected to the third node Q, and a control terminal connected to the third scan control signal NSCAN_T4. The first light-emitting control transistor T5 includes a first terminal connected to the high-potential signal VDD, a second terminal connected to the first node A, and a control terminal connected to the light-emitting control signal EM. The second light-emitting control transistor T6 includes a first terminal connected to the second node B, a second terminal connected to the fourth node C, and a control terminal connected to the light-emitting control signal EM. The second reset transistor T7 includes a first terminal connected to the second reset signal VI_ANO, a second terminal connected to the fourth node C, and a control terminal connected to the fourth scan control signal PSCAN2. The third reset transistor T8 includes a first terminal connected to the third reset signal VI_T8, a second terminal connected to the first node A, and a control terminal connected to the fourth scan control signal PSCAN2. The storage capacitor Cst includes one end connected to a high-potential signal and the other end connected to the third node Q. The boost capacitor Cboost includes one end connected to the first scan control signal PSCAN and the other end connected to the third node Q. The light-emitting device includes an anode connected to the fourth node C and a cathode connected to a low-potential signal VSS.

[0026] In some embodiments, the control electrode may be the gate, the first electrode may be one of the source or the drain, and the second electrode may be the other of the source or the drain.

[0027] It should be understood that Figure 2Taking the switching transistor T2, driving transistor T1, second reset transistor T7, third reset transistor T8, first light-emitting control transistor T5 and second light-emitting control transistor T6 as P-type thin film transistors (PTFTs), and the compensation transistor T3 and first reset transistor T4 as N-type thin film transistors (NTFTs), this does not constitute a limitation on the embodiments of this application. In practical applications, each transistor can be arbitrarily set as an N-type thin film transistor or a P-type thin film transistor in conjunction with the driving timing.

[0028] Please see Figure 3 , Figure 3 This is a schematic diagram of a driving timing. Figure 3 The driving timing shown can be used for driving. Figure 2 The corresponding components in the pixel driving circuit shown.

[0029] like Figure 3 As shown, the display time for one frame can include one write frame phase and two hold frame phases. The frame can be written and displayed during the write frame phase, and the frame can be displayed during the hold frame phase. That is, no new frame needs to be written during the hold frame phase; instead, display is performed based on the frame written during the write frame phase.

[0030] like Figure 3 As shown, one level cycle of the light emission control signal EM corresponds to one write frame phase or one hold frame phase. One level cycle of the light emission control signal EM includes a high level duration and a low level duration. If the light emission control signal EM is high, the first light emission control transistor T5 and the second light emission control transistor T6 are turned off, and the light-emitting device does not emit light. If the light emission control signal EM is low, the first light emission control transistor T5 and the second light emission control transistor T6 are turned on, and the current flowing through the driving transistor T1 can pass through the second node B and the fourth node C, thereby driving the light-emitting device to emit light.

[0031] like Figure 3 As shown, during the high-level duration of the light emission control signal EM, the first scan control signal PSCAN can remain at a low level for a period of time to control the switching transistor T2 to turn on, so that the data signal DATA can be written to the third node Q. Figure 3 As shown, during the high-level duration of the light-emitting control signal EM, the fourth scan control signal PSCAN2 can remain at a low level for a period of time to control the second reset transistor T7 to conduct, thereby resetting the fourth node C. Since the fourth node C is connected to the anode of the light-emitting device, resetting the fourth node C is equivalent to resetting the anode of the light-emitting device.

[0032] Typically, during the write frame phase, the first scan control signal PSCAN is set low before the fourth scan control signal PSCAN2 during the high-level duration of the light-emitting control signal EM. That is, during the write frame phase, the fourth node C is reset after the data signal DATA is written to the third node Q, and then the light-emitting device is driven to emit light. During the hold frame phase, the light-emitting device is driven to emit light after the fourth node C is reset.

[0033] Please see Figure 4 , Figure 4 This is a schematic diagram of another driving timing. Figure 4 The driving timing shown can be used for driving. Figure 2 The corresponding components in the pixel driving circuit shown.

[0034] Figure 4 Examples and Figure 3 The difference in the embodiments is that, Figure 3 In this embodiment, the display time of one frame includes one write frame phase and two hold frame phases, while Figure 4 In this embodiment, the display time of one frame includes a write frame phase and a hold frame phase. (Related information...) Figure 4 For a description of each signal in the embodiment, please refer to [link / reference]. Figure 3 Examples are not detailed here.

[0035] Please see Figure 5 , Figure 5 This is a flowchart illustrating a driving method for a display panel according to an embodiment of this application. The display panel includes a pixel driving circuit, which includes light-emitting devices. For example, the pixel driving circuit can be as follows: Figure 2 As shown. One frame display time of this display panel includes a write frame phase and one or more hold frame phases. During the write frame phase, the display panel writes and displays the image; during the hold frame phase, the display panel displays the image. For example... Figure 5 As shown, the driving method may include the following steps:

[0036] Step 510: During the first time period of the write frame phase, reset the anode of the light-emitting device;

[0037] Step 520: During the second time period of at least one holding frame phase, reset the anode of the light-emitting device.

[0038] In this embodiment, the pixel driving circuit includes a second reset transistor T7 and a light-emitting device. The second reset transistor T7 includes a first terminal connected to the second reset signal VI_ANO, a second terminal connected to the fourth node C, and a control terminal connected to the fourth scan control signal PSCAN2. The light-emitting device includes an anode terminal connected to the fourth node C and a cathode terminal connected to the low-potential signal VSS. Therefore, resetting the anode terminal of the light-emitting device is also resetting the fourth node C. Thus, step 510 can be implemented as resetting the fourth node C during the first time period of the write frame phase; step 520 can be implemented as resetting the fourth node C during the second time period of at least one hold frame phase.

[0039] In some embodiments, when the fourth scan control signal PSCAN2 is at a first level, the second reset transistor T7 is turned off; when the fourth scan control signal PSCAN2 is at a second level, the second reset transistor T7 is turned on. When the second reset transistor T7 is turned on, the second reset signal VI_ANO can reach the fourth node C through the second reset transistor T7, thereby resetting the fourth node C. Therefore, step 510 can be implemented as follows: during the first time period of the write frame phase, the fourth scan control signal PSCAN2 is at a second level, and the second reset transistor T7 is turned on; step 520 can be implemented as follows: during the second time period of at least one hold frame phase, the fourth scan control signal PSCAN2 is at a second level, and the second reset transistor T7 is turned on. Optionally, when the second reset transistor T7 is a P-type thin-film transistor, the first level of the fourth scan control signal PSCAN2 is high, and the second level of the fourth scan control signal PSCAN2 is low; when the second reset transistor T7 is an N-type thin-film transistor, the first level of the fourth scan control signal PSCAN2 is low, and the second level of the fourth scan control signal PSCAN2 is high.

[0040] In this embodiment, the start time of the first time period is separated from the start time of the write frame stage by a first interval, and the start time of the second time period is separated from the start time of the corresponding hold frame stage by a second interval. The first interval and the second interval are different. Since the fourth scan control signal PSCAN2 is at the second level during both the first and second time periods, the second reset transistor T7 is turned on, and the fourth node C and the anode of the light-emitting device are reset, the reset time of the anode of the light-emitting device during the write frame stage is different from that during the hold frame stage.

[0041] In some embodiments, the first interval duration is longer than the second interval duration. That is, the moment when the fourth scan control signal PSCAN2 changes to the second level in the hold frame phase is earlier than the moment when the fourth scan control signal PSCAN2 changes to the second level in the write frame phase. Therefore, the moment when the second reset transistor T7 starts to conduct in the hold frame phase is earlier than the moment when the second reset transistor T7 starts to conduct in the write frame phase. Consequently, the anode reset time of the light-emitting device in the hold frame phase is earlier than the anode reset time of the light-emitting device in the write frame phase.

[0042] In some embodiments, the difference between the first interval duration and the second interval duration is a target interval duration, and the target interval duration is positively correlated with the width of the blanking region of the display panel. The blanking region can also be referred to as the Blanking region or Porch region. This application does not limit the specific proportional relationship between the target interval duration and the width of the blanking region; in practical applications, it can be flexibly set according to the display effect. For example, if one frame display time of the display panel includes one write frame phase and two hold frame phases, the target interval duration is greater than or equal to one-third of the width of the blanking region. Another example is that if one frame display time of the display panel includes one write frame phase and one hold frame phase, the target interval duration is greater than or equal to one-quarter of the width of the blanking region.

[0043] In cases where a single display frame includes multiple hold frame phases, compared to the write frame phase, this embodiment can advance the conduction time of the second reset transistor T7 in each hold frame phase, thereby advancing the anode reset time of the light-emitting device in each hold frame phase; alternatively, the conduction time of the second reset transistor T7 in some hold frame phases can be advanced, thereby advancing the anode reset time of the light-emitting device in some hold frame phases, while the anode reset time of the light-emitting device in other hold frame phases can be consistent with the anode reset time of the light-emitting device in the write frame phase.

[0044] In some embodiments, a display frame time of the display panel includes a write frame phase and at least two hold frame phases; step 520 above includes: resetting the anode terminal of the light-emitting device during a second time period of each hold frame phase. That is, the reset time of the anode terminal of the light-emitting device in each hold frame phase can be shifted forward.

[0045] In some embodiments, a display frame time of the display panel includes a write frame phase and at least two hold frame phases; step 520 above includes: resetting the anode terminal of the light-emitting device during a second time period of the first hold frame phase. The first hold frame phase is a hold frame phase adjacent to the write frame phase. That is, the reset time of the anode terminal of the light-emitting device in the hold frame phase adjacent to the write frame phase can be shifted forward.

[0046] Based on the method of "resetting the anode of the light-emitting device during the second time period of the first holding frame phase," the driving method of this application embodiment may further include: resetting the anode of the light-emitting device during the first time period of the second holding frame phase. The second holding frame phase is a holding frame phase that is not adjacent to the write frame phase. That is, the reset time of the anode of the light-emitting device in the holding frame phase adjacent to the write frame phase can be shifted forward; however, the reset time of the anode of the light-emitting device in the holding frame phase that is not adjacent to the write frame phase is the same as the reset time of the anode of the light-emitting device in the write frame phase.

[0047] Based on the method of "resetting the anode of the light-emitting device during the second time period of the first holding frame phase," the driving method of this application embodiment may further include: resetting the anode of the light-emitting device during the third time period of the second holding frame phase. The second holding frame phase is a holding frame phase that is not adjacent to the write frame phase; the start time of the third time period is separated from the start time of the corresponding second holding frame phase by a third interval duration, which is different from both the first and second interval durations. That is, the reset time of the anode of the light-emitting device in the holding frame phase adjacent to the write frame phase can be shifted forward; however, the reset time of the anode of the light-emitting device in the holding frame phase that is not adjacent to the write frame phase is different from both the reset time of the anode of the light-emitting device in the write frame phase and the reset time of the anode of the light-emitting device in the holding frame phase adjacent to the write frame phase. Specifically, compared to the anode reset time of the light-emitting device in the write frame stage, the anode reset time of the light-emitting device in the hold frame stage, which is not adjacent to the write frame stage, can be shifted forward. The degree of this forward shift can be greater or less than the degree of forward shift in the hold frame stage, which is adjacent to the write frame stage.

[0048] In some embodiments, a display frame time of the display panel includes a write frame phase and at least two hold frame phases; step 520 above includes: resetting the anode terminal of the light-emitting device during a second time period of the second hold frame phase. The second hold frame phase is a hold frame phase that is not adjacent to the write frame phase. That is, the reset time of the anode terminal of the light-emitting device in the hold frame phase that is not adjacent to the write frame phase can be shifted forward. In this case, compared to the write frame phase, the reset time of the anode terminal of the light-emitting device in the hold frame phase adjacent to the write frame phase can be shifted forward, remain unchanged, or be shifted backward; this application embodiment does not limit this.

[0049] In summary, the driving method provided in this application ensures that the reset time of the anode end of the light-emitting device in at least one hold frame stage is different from that in the write frame stage. This avoids overlapping of dark bands at the same location, reduces the severity of dark bands, and improves the display effect of the display panel. Furthermore, in this application embodiment, compared to the write frame stage, no image writing is required before resetting the anode end of the light-emitting device in the hold frame stage. Therefore, the reset time of the anode end of the light-emitting device in at least one hold frame stage can be moved forward. This achieves different anode end reset times while avoiding affecting the light emission of the light-emitting device, ensuring an effective improvement in the display effect of the display panel. In addition, this application embodiment allows for flexible adjustment of the anode end reset time of one or more hold frame stages, as well as the adjustment duration of the anode end reset time, to achieve different improvement effects and degrees of dark bands.

[0050] The driving method provided in the embodiments of this application will be described below with reference to several examples of driving timing.

[0051] Please see Figures 6 to 8 , Figures 6 to 8 These are schematic diagrams of a driving timing provided in the embodiments of this application. Figures 6 to 8 The driving timing shown can be used for driving. Figure 2 The corresponding components in the pixel driving circuit shown.

[0052] like Figures 6 to 8 As shown, the display time of one frame of the display panel can include a write frame phase and one or more hold frame phases. During the write frame phase, the image can be written and displayed; during the hold frame phase, the image can be displayed. One level cycle of the light emission control signal EM corresponds to one write frame phase or one hold frame phase. One level cycle of the light emission control signal EM includes a high-level duration and a low-level duration. Taking the first light emission control transistor T5 and the second light emission control transistor T6 as both being P-type thin-film transistors as an example, if the light emission control signal EM is high, the first light emission control transistor T5 and the second light emission control transistor T6 are turned off, and the light-emitting device is off and does not emit light; if the light emission control signal EM is low, the first light emission control transistor T5 and the second light emission control transistor T6 are turned on, and the light-emitting device is on and emits light.

[0053] Taking the switching transistor T2 as a P-type thin-film transistor as an example, such as Figures 6 to 8 As shown, during the frame writing stage, during the high-level duration of the light emission control signal EM, the first scan control signal PSCAN can remain at a low level for a period of time to control the switching transistor T2 to turn on, so that the data signal DATA can be written to the third node Q.

[0054] Taking the second reset transistor T7 as a P-type thin-film transistor as an example, such as Figures 6 to 8 As shown, during the write frame stage and the hold frame stage, during the high-level duration of the light emission control signal EM, the fourth scan control signal PSCAN2 can remain at a low level for a period of time to control the second reset transistor T7 to turn on, thereby resetting the anode of the light-emitting device. During the write frame stage, during the high-level duration of the light emission control signal EM, the first scan control signal PSCAN can be set low before the fourth scan control signal PSCAN2; that is, during the write frame stage, the fourth node C is reset after the data signal DATA is written to the third node Q, and then the light-emitting device is driven to emit light.

[0055] like Figure 6 As shown, a display frame consists of one write frame phase and two hold frame phases. Compared to the write frame phase, the reset time of the anode of the light-emitting device in each hold frame phase can be shifted forward. The forward shift can be greater than or equal to one-third of the width of the blanking region. That is, in the write frame phase, the time between the start of the anode reset of the light-emitting device and the start time of the write frame phase is a first interval duration, and in each hold frame phase, the time between the start of the anode reset of the light-emitting device and the start time of the hold frame phase is a second interval duration; the first interval duration is longer than the second interval duration, and the difference between the first interval duration and the second interval duration is greater than or equal to one-third of the width of the blanking region.

[0056] like Figure 7 As shown, one frame display time includes one write frame phase and two hold frame phases. Compared to the write frame phase, the reset time of the anode of the light-emitting device in the hold frame phase adjacent to the write frame phase can be shifted forward, while the reset time of the anode of the light-emitting device in the hold frame phase not adjacent to the write frame phase remains unchanged. That is, in the write frame phase, the time between the start of the reset of the anode of the light-emitting device and the start time of the write frame phase is a first interval duration; in the hold frame phase adjacent to the write frame phase, the time between the start of the reset of the anode of the light-emitting device and the start time of that hold frame phase is a second interval duration; and in the hold frame phase not adjacent to the write frame phase, the time between the start of the reset of the anode of the light-emitting device and the start time of that hold frame phase is a first interval duration; the first interval duration is longer than the second interval duration.

[0057] like Figure 8As shown, a display frame includes a write frame phase and a hold frame phase. Compared to the write frame phase, the reset time of the anode of the light-emitting device in the hold frame phase can be shifted forward. The forward shift can be greater than or equal to one-quarter of the width of the blanking region. That is, in the write frame phase, the time between the start of the anode reset of the light-emitting device and the start time of the write frame phase is a first interval duration, and in the hold frame phase, the time between the start of the anode reset of the light-emitting device and the start time of the hold frame phase is a second interval duration; the first interval duration is longer than the second interval duration, and the difference between the first interval duration and the second interval duration is greater than or equal to one-quarter of the width of the blanking region.

[0058] Please see Figure 9 A single frame display time includes one write frame phase and two hold frame phases. For example... Figure 9 As shown, the reset time of the anode of the light-emitting device in the hold frame phase is the same as the reset time of the anode of the light-emitting device in the write frame phase. That is, the interval between the start of the anode reset in the hold frame phase and the start of the hold frame phase is equal to the interval between the start of the anode reset in the write frame phase and the start of the write frame phase. Upon entering the blanking region, the load on the second reset signal VI_ANO changes, and the voltage drops significantly, thus forming a dark band. Because... Figure 9 In the process of maintaining the same reset time of the anode of the light-emitting device during the frame-keeping stage and the same reset time of the anode of the light-emitting device during the write-frame stage, the dark bands overlap and the dark bands are deeper. Figure 9 Each of the dark bands shown is formed by the overlap of three dark bands.

[0059] Please see Figure 10 , Figure 10 This is a schematic diagram illustrating the dark band improvement effect provided in an embodiment of this application. Figure 10 The dark band improvement effect shown can be based on Figure 6 The driving timing is shown below. Figure 10 As shown, in display area 110, the dark bands 130 will not overlap at the same position, but will be staggered. This is because... Figure 6 Compared to the write frame stage, the reset time of the anode of the light-emitting device in each hold frame stage is moved forward. Figure 1 and Figure 9 The dark band shown Figure 10 The severity of each dark band is reduced, improving the display panel's display effect. Additionally, in Figure 10 The width of the hidden area 120 is marked in the figure. The width of the hidden area described in the above embodiment can be found in [reference]. Figure 10 The annotations in the text are explained.

[0060] For the specific implementation methods of each of the above operations and their corresponding beneficial effects, please refer to the detailed description of the pixel driving circuit, driving timing and display panel driving method above, which will not be repeated here.

[0061] The above provides a detailed description of a display panel driving method provided by the embodiments of this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A driving method for a display panel, characterized in that, The display panel includes a pixel driving circuit, which includes a light-emitting device; one frame display time of the display panel includes a write frame stage and one or more hold frame stages, in which the display panel writes and displays the image, and in the hold frame stage the display panel displays the image; The driving method includes: During the first time period of the write frame phase, the anode of the light-emitting device is reset; During a second time period of at least one of the holding frame phases, the anode of the light-emitting device is reset; Wherein, the start time of the first time period is separated from the start time of the write frame stage by a first interval duration, the start time of the second time period is separated from the start time of the corresponding hold frame stage by a second interval duration, and the first interval duration is longer than the second interval duration. The first interval duration differs from the second interval duration by a target interval duration, and the target interval duration is positively correlated with the width of the blanking area of ​​the display panel.

2. The driving method according to claim 1, characterized in that, The display panel's display time for one frame includes one write frame phase and two hold frame phases; the target interval duration is greater than or equal to one-third of the width of the blanking region.

3. The driving method according to claim 1, characterized in that, The display panel's display time for one frame includes a write frame phase and a hold frame phase; the target interval duration is greater than or equal to one-quarter of the width of the blanking region.

4. The driving method according to claim 1, characterized in that, One frame display time of the display panel includes one write frame phase and at least two hold frame phases; Resetting the anode of the light-emitting device during a second time period at least one of the holding frame phases includes: During the second time period of each of the holding frame phases, the anode of the light-emitting device is reset.

5. The driving method according to claim 1, characterized in that, One frame display time of the display panel includes one write frame phase and at least two hold frame phases; Resetting the anode of the light-emitting device during a second time period at least one of the holding frame phases includes: During the second time period of the first holding frame phase, the anode of the light-emitting device is reset; The first holding frame phase is the holding frame phase adjacent to the write frame phase.

6. The driving method according to claim 5, characterized in that, The method further includes: During the first time period of the second hold frame phase, the anode of the light-emitting device is reset; The second hold frame phase is a hold frame phase that is not adjacent to the write frame phase.

7. The driving method according to claim 5, characterized in that, The method further includes: During the third time period of the second holding frame phase, the anode of the light-emitting device is reset; The second hold frame phase is a hold frame phase that is not adjacent to the write frame phase; the start time of the third time period is separated from the start time of the corresponding second hold frame phase by a third interval, the third interval being different from the first interval and different from the second interval.

8. The driving method according to claim 1, characterized in that, One frame display time of the display panel includes one write frame phase and at least two hold frame phases; Resetting the anode of the light-emitting device during a second time period at least one of the holding frame phases includes: During the second time period of the second hold frame phase, the anode of the light-emitting device is reset; The second hold frame phase is a hold frame phase that is not adjacent to the write frame phase.

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