Display panel and display device

Abstract

The present application provides a display panel and a display device, which belong to the field of display driver technology. The display panel includes a power management circuit, a driver circuit and at least one AND gate circuit. Among them, the power management circuit is used to output a logic voltage. Each AND gate circuit includes a voltage input terminal, a signal input terminal and a signal output terminal. The voltage input terminal is connected to the power management circuit. The signal input terminal is used to receive a first digital signal. The AND gate circuit is used to convert the first digital signal into a second digital signal after the logic voltage is powered on. The driver circuit is connected to the signal output terminal of the AND gate circuit and the power management circuit, and operates based on the logic voltage and the second digital signal. In this way, it is avoided that the driver circuit mistakenly receives and processes the second digital signal when the logic voltage is not established, thereby ensuring that the power-on timing of the driver circuit is correct and avoiding abnormalities or damage to the driver circuit that may be caused by confusion in the power-on timing.

Description

Technical Field

[0001] The present application relates to the field of display driving technology, and in particular to a display panel and a display device. Background Art

[0002] Liquid Crystal Display (LCD) technology is a widely used display technology in modern electronic devices. Through the action of an external electric field, the arrangement direction of liquid crystal molecules can be precisely controlled, thereby modulating light and achieving the purpose of displaying images.

[0003] Currently, each driver integrated circuit (IC) in an LCD display panel must meet a specific timing when powered on. For example, before the driver IC recognizes and processes digital signals, it must first establish a logic voltage as a reference to ensure that the driver IC operates within the correct voltage and signal environment. Otherwise, the driver IC will not function properly. If a digital signal is input before the logic voltage is established, not only will the digital signal not be correctly recognized and processed, but it may also cause voltage anomalies within the driver IC, shortening the driver IC's lifespan or even permanently damaging it.

[0004] Therefore, how to ensure that the driver integrated circuit is powered on at the correct timing is a problem that needs to be solved urgently. Summary of the Invention

[0005] In view of the deficiencies in the prior art, the present application provides a display panel and a display device.

[0006] In a first aspect, the present application provides a display panel comprising:

[0007] A power management circuit for outputting logic voltage;

[0008] At least one AND gate circuit, each of the AND gate circuits comprising a voltage input terminal, a signal input terminal, and a signal output terminal; the voltage input terminal being connected to the power management circuit; the signal input terminal being configured to receive a first digital signal; and the AND gate circuit being configured to convert the first digital signal into the second digital signal after the logic voltage is powered on;

[0009] The driving circuit is connected to the signal output terminal of the AND gate circuit and the power management circuit, and operates based on the logic voltage and the second digital signal.

[0010] Optionally, the AND gate circuit includes a switch tube, and the switch tube includes a control electrode connected to the voltage input end, a first electrode connected to the signal input end, and a second electrode connected to the signal output end.

[0011] Optionally, the AND gate circuit includes a clamping subcircuit and a voltage divider subcircuit;

[0012] The voltage divider subcircuit is connected to the voltage input terminal and the signal output terminal;

[0013] The clamping subcircuit is connected to the voltage dividing subcircuit, the signal input terminal and the signal output terminal, and is configured to be turned on or off according to the first digital signal and the logic voltage;

[0014] When the clamping sub-circuit is turned on, the potential of the signal output end is clamped to a first potential; when the clamping sub-circuit is turned off, the potential of the signal output end is a second potential obtained by the voltage divider sub-circuit dividing the logic voltage to form the second digital signal.

[0015] Optionally, the voltage divider subcircuit includes a first resistor and a second resistor;

[0016] The first end of the first resistor is connected to the voltage input end, and the second end is connected to the signal output end and the clamping sub-circuit at a voltage dividing node;

[0017] A first end of the second resistor is connected to the voltage division node, and a second end of the second resistor is grounded.

[0018] Optionally, the clamping sub-circuit includes a first diode; the first diode includes an anode connected to the voltage dividing node and a cathode connected to the signal input end.

[0019] Optionally, the AND gate circuit further includes a second diode; the second diode includes an anode connected to the voltage dividing node and a cathode connected to the voltage input terminal.

[0020] Optionally, the driving circuit is a source driving circuit, and the first digital signal and the second digital signal include image signals;

[0021] The display panel further includes a timing controller;

[0022] The timing controller is connected to the signal input terminal and is used to output the first digital signal to the signal input terminal;

[0023] The source driving circuit is connected to the signal output terminal, and is configured to generate a data signal according to the second digital signal and output the data signal to the pixel circuit.

[0024] Optionally, the display panel further includes an equalizer disposed between the timing controller and the signal input end, and the equalizer is configured to amplify the first digital signal.

[0025] Optionally, the driving circuit is a timing controller, and the first digital signal and the second digital signal include one of a horizontal synchronization signal, a vertical synchronization signal, and a data enable signal.

[0026] In a second aspect, in one embodiment, the present application provides a display device comprising the display panel as described above.

[0027] In summary, the present application first outputs a logic voltage through the power management circuit. Then, the AND gate circuit converts the first digital signal into a second digital signal when the logic voltage is powered on, and outputs the second digital signal through its signal output terminal. When the logic voltage is not powered on, the logic state of the second digital signal remains at 0. This prevents the driver circuit from erroneously receiving and processing the second digital signal when the logic voltage is not established, thereby ensuring the correct power-on timing of the driver circuit and avoiding driver circuit anomalies or damage that may be caused by a disrupted power-on timing. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0029] Figure 1 This is a schematic diagram of the power-on timing of logic voltages and digital signals in one embodiment of the present application.

[0030] Figure 2 This is a schematic diagram of a display panel in one embodiment of the present application;

[0031] Figure 3 This is a connection diagram of an AND gate circuit in one embodiment of the present application;

[0032] Figure 4 This is a connection diagram of an AND gate circuit in another embodiment of the present application;

[0033] Figure 5 This is an architectural diagram of an AND gate circuit application scenario in one embodiment of the present application;

[0034] Figure 6 This is a schematic diagram of an equalizer in one embodiment of the present application;

[0035] Figure 7 This is an architectural diagram of an AND gate circuit application scenario in another embodiment of the present application.

[0036] Explanation of the accompanying symbols: 1. Power management circuit; 2. AND gate circuit; 21. Voltage divider sub-circuit; 22. Clamp sub-circuit; 3. Drive circuit; 31. Source drive circuit; 32. Timing controller; 4. Gate drive circuit. DETAILED DESCRIPTION

[0037] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without making creative efforts are within the scope of protection of this application.

[0038] In the description of this application, it should be understood that the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly specifying the number of the technical features indicated. Therefore, features specified as "first" or "second" may explicitly or implicitly include one or more of the described features. In the description of this application, "plurality" means two or more, unless otherwise specifically qualified. In this application, the word "exemplary" is used to mean "serving as an example, illustration, or illustration." Any embodiment described in this application as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments. The following description is provided to enable anyone skilled in the art to implement and use the present application. In the following description, details are listed for illustrative purposes. It should be understood that one of ordinary skill in the art will recognize that the present application can be implemented without these specific details. In other instances, well-known structures and processes are not described in detail to avoid obscuring the description of this application with unnecessary detail. Therefore, this application is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features disclosed herein.

[0039] First, based on the content of the background technology of this application, the background of this application is further explained. Figure 1 , Figure 1 Schematic diagram of the power-on timing of the logic voltage VDD1 and the digital signal DIG.

[0040] Figure 1 The figure shows a normal power-on sequence, that is, the logic voltage VDD1 is established first, and after a time interval t1, the digital signal DIG to be processed is provided after the logic voltage VDD1 is stabilized. Figure 1(b) illustrates an abnormal power-up sequence. For example, if the logic voltage VDD1 is delayed or the digital signal DIG is advanced, the digital signal DIG is connected first, and the logic voltage VDD1 is not fully established until time interval t2 has passed. In this case, the logic voltage VDD1 cannot serve as a reference voltage for the digital signal DIG, making it difficult for the driver circuit to correctly process the digital signal DIG.

[0041] At present, the related art usually adopts the method of setting a delay circuit to adjust the timing between the logic voltage VDD1 and the digital signal DIG, that is, a delay circuit is set at the digital signal DIG input terminal DIGin of the driving circuit, so that the digital signal DIG is delayed by the delay circuit before being input to the driving circuit, thereby providing more time to establish a stable logic voltage VDD1, so as to achieve the adjustment of the power-on timing. However, on the one hand, in the field of display driving, if the digital signal DIG is delayed, especially real-time signals such as image signals, it is easy to cause problems such as delay in the display screen. On the other hand, the delay circuit can only solve short-term timing problems. For example, when the delay time of the delay circuit is less than Figure 1 During the time interval t2 shown in (b), even if a delay circuit is provided, ideal power-on timing control cannot be achieved. Alternatively, when the voltage source of the logic voltage VDD1 fails and cannot output the logic voltage VDD1, the digital signal DIG after passing through the delay circuit will continue to be input to the driver circuit, causing abnormal operation or even damage to the driver circuit.

[0042] Based on the above problems, this application is proposed. Figure 2 As shown, in one embodiment, the present application provides a display panel, which includes a power management circuit 1, a driving circuit 3, and at least one AND gate circuit 2. The power management circuit 1 is used to output a logic voltage VDD1. At least one AND gate circuit 2 is provided, and each AND gate circuit 2 includes a voltage input terminal VDD, a signal input terminal DIGin, and a signal output terminal DIGout. The voltage input terminal VDD is connected to the power management circuit 1. The signal input terminal DIGin is used to receive a first digital signal DIG. The AND gate circuit 2 is used to convert the first digital signal DIG into a second digital signal DIG after the logic voltage VDD1 is powered on. The driving circuit 3 is connected to the signal output terminal DIGout of the AND gate circuit 2 and the power management circuit 1, and operates based on the logic voltage VDD1 and the second digital signal DIG.

[0043] As an example, the real relationship between the two input terminals (voltage input terminal VDD and signal input terminal DIGin) and the signal output terminal DIGout of the AND gate circuit 2 is shown in Table 1.

[0044]

[0045] The logic voltage being powered on means that the potential of the logic voltage is greater than a preset value, in which case the logic state of the logic voltage is determined to be 1; otherwise, the logic state of the logic voltage is 0. When the logic voltage is not powered on, the logic state of the second digital signal is always 0 through the AND gate circuit 2. When the logic voltage is powered on, the AND gate circuit 2 converts the first digital signal into a second digital signal having the same logic state.

[0046] As an example, the power management circuit 1 inputs the logic voltage to the AND gate circuit 2 and the drive circuit 3 respectively, so that the AND gate circuit 2 obtains the second digital signal according to the logic voltage, and the drive circuit 3 uses the logic voltage as a reference voltage to identify and process the second digital signal.

[0047] In the above embodiment, a logic voltage is first outputted by power management circuit 1. Then, AND gate circuit 2 successfully converts the first digital signal into a second digital signal when the logic voltage is applied, and outputs the second digital signal through its signal output terminal DIGout. When the logic voltage is not applied, the logic state of the second digital signal remains at 0. This prevents driver circuit 3 from erroneously receiving and processing the second digital signal when the logic voltage is not applied, thereby ensuring the correct power-up sequence for driver circuit 3 and preventing possible abnormalities or damage to driver circuit 3 caused by a disrupted power-up sequence.

[0048] Reference Figure 3 As an implementation of the AND gate circuit 2, the AND gate circuit 2 includes a switch tube Q1, which includes a control electrode connected to the voltage input terminal VDD, a first electrode connected to the signal input terminal DIGin, and a second electrode connected to the signal output terminal DIGout.

[0049] As an example, the switch Q1 can be an N-type transistor. When the logic voltage is applied, the switch Q1 is turned on. The first digital signal input to the signal input terminal DIGin is converted into a second digital signal after passing through the conduction voltage drop of the switch Q1. The second digital signal is then output to the signal output terminal DIGout. When the logic voltage is not applied, the switch Q1 is turned off. The first digital signal at the signal input terminal DIGin cannot be transmitted, causing the logic state of the signal output terminal DIGout to remain 0.

[0050] In the above embodiment, the logic voltage is used as the control electrode signal of the switch tube Q1, so that the switch tube Q1 can conduct between the signal input terminal DIGin and the signal output terminal DIGout only after the logic voltage is powered on, thereby ensuring that the second digital signal is output after the logic voltage is powered on.

[0051] Reference Figure 4As another embodiment of the AND gate circuit 2, the AND gate circuit 2 includes a clamping subcircuit 22 and a voltage divider subcircuit 21. The voltage divider subcircuit 21 is connected to the voltage input terminal VDD and the signal output terminal DIGout. The clamping subcircuit 22 is connected to the voltage divider subcircuit 21, the signal input terminal DIGin, and the signal output terminal DIGout, and is configured to be turned on or off according to the first digital signal and the logic voltage. When the clamping subcircuit 22 is turned on, the potential of the signal output terminal DIGout is clamped to the first potential. When the clamping subcircuit 22 is turned off, the potential of the signal output terminal DIGout is the second potential obtained by dividing the logic voltage by the voltage divider subcircuit 21, thereby forming a second digital signal.

[0052] As an example, logical states are typically represented by different levels of voltage or current. For example, when the voltage or current level of a signal is higher than a preset logical threshold, the logical state can be determined to be 1 (or a high level); when the voltage or current level of the signal is lower than the preset logical threshold, the logical state can be determined to be 0 (or a low level). In this embodiment, the first potential and the second potential respectively represent two logical states of the second digital signal. The first potential can be lower than the preset logical threshold, and its corresponding logical state is 0. The second potential can be higher than the preset logical threshold, and its corresponding logical state is 1.

[0053] In the above embodiment, the clamping sub-circuit 22 is turned on or off based on the first digital signal and the logic voltage, thereby providing two logical states. When the clamping sub-circuit 22 is turned on, the potential of the signal output terminal DIGout is clamped to a preset first potential. After the clamping sub-circuit 22 is turned off, the voltage divider sub-circuit 21 divides the logic voltage to obtain a second potential. The first potential and the second potential respectively represent the two logical states of the second digital signal, thereby enabling the generation of the second digital signal. The logic voltage participates in the generation of the second digital signal, so that the second digital signal cannot be generated before the logic voltage is established, thereby ensuring a power-up timing sequence in which the logic voltage is established first and then the second digital signal is generated.

[0054] Reference Figure 4 As one embodiment of the voltage divider sub-circuit 21, the voltage divider sub-circuit 21 includes a first resistor R1 and a second resistor R2. The first resistor R1 has a first end connected to the voltage input terminal VDD, a second end connected to the signal output terminal DIGout, and a clamp sub-circuit 22 connected to the voltage divider node A. The second resistor R2 has a first end connected to the voltage divider node A, and a second end connected to ground.

[0055] Reference Figure 4 As an embodiment of the clamping sub-circuit 22, the clamping sub-circuit 22 includes a first diode Di1. The first diode Di1 includes an anode connected to the voltage dividing node A and a cathode connected to the signal input terminal DIGin.

[0056] As an example, a logic voltage serves as the voltage source for the voltage divider subcircuit 21. When the logic voltage is not established, the potential at the voltage divider node A is 0, thereby causing the potential at the signal output terminal DIGout to be 0. When the logic voltage is applied, if the logic state of the first digital signal is 1, the voltage difference between the potential at the voltage divider node A and the first digital signal after voltage division is small, causing the voltage difference across the first diode Di1 to be less than the conduction voltage of the first diode Di1, rendering the first diode Di1 non-conductive. At this point, the potential at the voltage divider node A is equal to the second point obtained by dividing the logic voltage by the first resistor R1 and the second resistor R2. That is, the potential at the signal output terminal DIGout is the second potential, which should be greater than a preset logic threshold, so that the logic state of the second digital signal outputted by the signal output terminal DIGout is 1. When the logic voltage is powered on, if the logic state of the first digital signal is 0, the voltage difference between the potential of the voltage divider node A and the first digital signal after the logic voltage is divided is large, thereby causing the first diode Di1 to be turned on. Since the cathode of the first diode Di1 is connected to the first digital signal with a logic state of 0, the potential of the anode of the first diode Di1 is clamped to the sum of its cathode potential and the conduction voltage of the first diode Di1. This sum is the first potential, and the first potential should be less than the preset logic threshold, so that the logic state of the second digital signal output by the signal output terminal DIGout is 0.

[0057] Furthermore, by adjusting the resistance values ​​of the first resistor R1 and the second resistor R2, the voltage division value of the voltage division node A can be changed to match different preset logic thresholds of the driving circuit 3. For example, if the preset logic threshold of the first digital signal is 5V, that is, a value greater than 5V in the first digital signal is determined to be a logic state of 1, and a value less than 5V is determined to be a logic state of 0. If the preset logic threshold of the driving circuit 3 is different from the preset logic threshold of the first digital signal, for example, the preset logic threshold of the driving circuit 3 is 3V, then the voltage division value of the voltage division node A can be adjusted to be greater than 3V by adjusting the resistance values ​​of the first resistor R1 and the second resistor R2, so that the driving circuit 3 can correctly identify the logic state of the second digital signal.

[0058] In the above embodiment, when the first diode Di1 is turned on, its anode potential can be clamped according to its cathode potential, so as to provide a stable first potential, so that the logic state of the second digital signal output by the signal output terminal DIGout is 0; at the same time, when the first diode Di1 is turned off, the potential of the signal output terminal DIGout is determined by the voltage divider of the first resistor R1 and the second resistor R2, so as to output a suitable second level, so that the logic state of the second digital signal output by the signal output terminal DIGout is 1.

[0059] Reference Figure 4 As a further embodiment of the AND gate circuit 2, the AND gate circuit 2 further includes a second diode Di2. The second diode Di2 includes an anode connected to the voltage dividing node A and a cathode connected to the voltage input terminal VDD.

[0060] In the above embodiment, the second diode Di2 helps to absorb the interference signal, thereby preventing the interference signal from being erroneously transmitted to the signal output terminal DIGout.

[0061] Reference Figure 6 As a first embodiment of the driving circuit 3, the driving circuit 3 may be a source driving circuit 31, and the first digital signal and the second digital signal may include an image signal. Based on this embodiment, the display panel further includes a timing controller 32. The timing controller 32 is connected to the signal input terminal DIGin and is configured to output the first digital signal to the signal input terminal DIGin. The source driving circuit 31 is connected to the signal output terminal DIGout and is configured to generate a data signal based on the second digital signal and output the data signal to the pixel circuit.

[0062] The image signal may be in various formats, which are not specifically limited here, such as low-voltage differential signaling (LVDS) signals, DPI (Digital Panel Interface) signals, and the like.

[0063] Figure 6 Schematic diagram of a display panel in an embodiment of the present application, the display panel also includes a gate drive circuit 43. The display area 5 of the display panel may include a plurality of scan lines G1 to Gn, a plurality of data lines D1 to Dm intersecting the plurality of scan lines G1 to Gn, and a plurality of pixel units respectively arranged in a plurality of areas defined by the intersection of the scan lines G1 to Gn and the data lines D1 to Dm. For example, the pixel unit may include a thin film transistor (TFT), which includes a gate and a source electrode respectively connected to the scan line and the data line corresponding thereto. When a scan line is selected from the plurality of scan lines G1 to Gn, the thin film transistor of the pixel unit connected to the selected scan line is turned on, and then the source drive circuit 31 can apply a voltage to the plurality of data lines D1 to Dm, thereby displaying an image.

[0064] Among them, the power management circuit 1 provides power supply for the timing controller 32, the source driver circuit 31 and the gate driver circuit 43. The timing controller 32 receives image data and control signals, and performs pre-processing on the image data such as format conversion and data sorting to obtain an image signal. At the same time, the timing controller 32 also generates a control signal and a clock signal. Then, the image signal and the control signal are sent to the source driver circuit 31 and the gate driver circuit 43 respectively. The gate driver circuit 43 receives the control signal and clock signal from the timing controller 32 to generate a gate drive signal for line-by-line scanning, and sequentially turns on or off the thin film transistor switches in the display area 5 through the gate drive signal to control the selection of the scan line. After receiving the image signal from the timing controller 32, the source driver circuit 31 converts the image signal into a data signal and stores it in an internal register, and outputs it synchronously according to the scan signal of the gate driver circuit 43.

[0065] In the above embodiment, the driving circuit 3 is a source driving circuit 31, and the first digital signal and the second digital signal include an image signal, which ensures that the source driving circuit 31 first establishes a logic voltage and then receives the image signal, thereby ensuring that the source driving circuit 31 can work normally, and then the display panel can display the picture normally.

[0066] In some embodiments, the display panel further includes an equalizer EQ disposed between the timing controller 32 and the signal input terminal DIGin, for amplifying the first digital signal.

[0067] Reference Figure 7 As a second implementation of the driving circuit 3, the driving circuit 3 can also be a timing controller 32. In this case, the first digital signal and the second digital signal include one of a horizontal synchronization signal, a vertical synchronization signal and a data enable signal.

[0068] Among them, the horizontal synchronization signal (Horizontal Synchronization, HSYNC) is used to indicate the start and end of a row of pixel data. The vertical synchronization signal (Vertical Synchronization, VSYNC) is used to indicate the start and end of a frame of image, marking the end of the image data transmission of the current frame and the start of data transmission of a new frame. The data enable signal (Data Enable, DE) is used to indicate whether the currently transmitted pixel data is valid. When the data enable signal is high, it indicates that the currently transmitted image signal is valid; when the data enable signal is low, it indicates that the currently transmitted image signal is invalid and should be ignored. The horizontal synchronization signal, vertical synchronization signal and data enable signal can be sent to the timing controller 32 by the front end of the display panel or components such as the graphics processing unit (GPU).

[0069] As an example, the second embodiment of the driving circuit 3 has the same display panel architecture as the first embodiment of the driving circuit 3 and is not further described here. Unlike the first embodiment, in this embodiment, the AND gate circuit 2 is provided between the timing controller 32 and the power management circuit 1, thereby ensuring that the logic voltage is established first and then the horizontal synchronization signal, vertical synchronization signal, or data enable signal is connected to ensure the normal operation of the timing controller 32.

[0070] It should be noted that the driving circuit 3 can be any circuit in the display panel that requires power-on timing control, and is not specifically limited here.

[0071] In a second aspect, in one embodiment, the present application provides a display device comprising the display panel as described above.

[0072] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0073] The embodiments, implementation methods and related technical features of the present application can be combined and replaced with each other without conflict.

[0074] The above are merely preferred embodiments of the present application and do not constitute any form of limitation to the present application. However, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are still within the scope of the technical solution of the present application.

Claims

1. A display panel, characterized in that: include: A power management circuit for outputting logic voltage; At least one AND gate circuit, each of the AND gate circuits comprising a voltage input terminal, a signal input terminal, and a signal output terminal; The voltage input terminal is connected to the power management circuit; the signal input terminal is used to receive a first digital signal; the AND gate circuit is used to convert the first digital signal into a second digital signal after the logic voltage is powered on; The driving circuit is connected to the signal output terminal of the AND gate circuit and the power management circuit, and operates based on the logic voltage and the second digital signal.

2. The display panel according to claim 1, wherein: The AND gate circuit includes a switch tube, and the switch tube includes a control electrode connected to the voltage input end, a first electrode connected to the signal input end, and a second electrode connected to the signal output end.

3. The display panel according to claim 1, wherein: The AND gate circuit includes a clamping subcircuit and a voltage dividing subcircuit; The voltage divider subcircuit is connected to the voltage input terminal and the signal output terminal; The clamping subcircuit is connected to the voltage dividing subcircuit, the signal input terminal and the signal output terminal, and is configured to be turned on or off according to the first digital signal and the logic voltage; When the clamping sub-circuit is turned on, the potential of the signal output end is clamped to a first potential; when the clamping sub-circuit is turned off, the potential of the signal output end is a second potential obtained by the voltage divider sub-circuit dividing the logic voltage to form the second digital signal.

4. The display panel according to claim 3, wherein: The voltage divider subcircuit includes a first resistor and a second resistor; The first end of the first resistor is connected to the voltage input end, and the second end is connected to the signal output end and the clamping sub-circuit at a voltage dividing node; A first end of the second resistor is connected to the voltage division node, and a second end of the second resistor is grounded.

5. The display panel according to claim 4, wherein: The clamping sub-circuit includes a first diode; the first diode includes an anode connected to the voltage dividing node and a cathode connected to the signal input terminal.

6. The display panel according to claim 4, wherein: The AND gate circuit further includes a second diode; the second diode includes an anode connected to the voltage dividing node and a cathode connected to the voltage input terminal.

7. The display panel according to any one of claims 1 to 6, characterized in that: The driving circuit is a source driving circuit, and the first digital signal and the second digital signal include image signals; The display panel further includes a timing controller; The timing controller is connected to the signal input terminal, and is used to output the first digital signal to the signal input terminal; The source driving circuit is connected to the signal output terminal, and is configured to generate a data signal according to the second digital signal, and output the data signal to the pixel circuit, so that the display panel performs display based on the data signal.

8. The display panel according to claim 7, wherein: The display panel further includes an equalizer disposed between the timing controller and the signal input terminal, and the equalizer is configured to amplify the first digital signal.

9. The display panel according to any one of claims 1 to 6, characterized in that The driving circuit is a timing controller, and the first digital signal and the second digital signal include one of a horizontal synchronization signal, a vertical synchronization signal, and a data enable signal.

10. A display device, characterized in that: include: The display panel according to any one of claims 1 to 9.

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