Shift register unit and driving method, gate driving circuit, display panel

Abstract

The shift register unit and the driving method, the gate driving circuit and the display panel provided by the embodiments of the present disclosure comprise: a first shift register circuit configured to output a cascade signal through a cascade output end in response to a signal of a first input signal end; a second shift register circuit configured to output a gate driving signal through a driving output end in response to a signal of a second input signal end; and a switch circuit connected between the cascade output end and the second input signal end, the switch circuit being configured to turn on the cascade output end and the second input signal end in response to a signal of a gate-on control signal end.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, and particularly relates to a shift register unit and a driving method, a gate driving circuit and a display panel. BACKGROUND

[0002] Generally, a display panel is refreshed in a full-screen refresh mode, when a local display area of the display panel needs to be refreshed, a black picture is used to cover the display area which does not need to be refreshed, but the display panel still updates the picture of the whole screen in the full-screen refresh mode, which causes unnecessary power consumption. SUMMARY

[0003] Embodiments of the present disclosure provide a shift register unit, comprising:

[0004] a first shift register circuit configured to output a cascade signal through a cascade output end in response to a signal of a first input signal end;

[0005] a second shift register circuit configured to output a gate driving signal through a driving output end in response to a signal of a second input signal end;

[0006] a switch circuit connected between the cascade output end and the second input signal end, the switch circuit being configured to turn on the cascade output end and the second input signal end in response to a signal of a gate control signal end.

[0007] In some possible implementation manners, the switch circuit comprises at least one first transistor, a first electrode of the first transistor being coupled with the cascade output end, a second electrode of the first transistor being coupled with the second input signal end, and a control electrode of the first transistor being coupled with the gate control signal end.

[0008] In some possible implementation manners, the first shift register circuit is further connected with a first clock signal end and a first reset signal end, and is configured to provide a signal of the first input signal end to a first node in response to the signal of the first input signal end, provide a signal of the first clock signal end to the cascade output end in response to a signal of the first node, and provide a signal of a first reference signal end to the first node and the cascade output end in response to a signal of the first reset signal end.

[0009] The second shift register circuit is also connected with a second clock signal end and a second reset signal end, and is configured to, in response to a signal of the second input signal end, provide the signal of the second input signal end to a second node, in response to a signal of the second node, provide a signal of the second clock signal end to the driving output end, and in response to a signal of the second reset signal end, provide a signal of a second reference signal end to the second node and the driving output end.

[0010] In some possible implementation manners, the first clock signal end and the second clock signal end are different signal ends.

[0011] In some possible implementation manners, the first reference signal end and the second reference signal end are the same signal end.

[0012] In some possible implementation manners, the first shift register circuit and the second shift register circuit are of the same structure.

[0013] The embodiments of the present disclosure further provide a gate drive circuit including a plurality of the above-described shift register units connected in cascade.

[0014] The first input signal end of the first shift register circuit in the first shift register unit is connected with a frame trigger signal end.

[0015] The cascade output end of the first shift register circuit in the n th shift register unit is connected with the first input signal end of the first shift register circuit in the n+m th shift register unit, and the first reset signal end of the first shift register circuit in the n th shift register unit is connected with the cascade output end of the first shift register circuit in the n+i th shift register unit; wherein m, n and i are positive integers.

[0016] In some possible implementation manners, the gate control signal ends to which the switch circuits in the shift register units are connected are the same signal end.

[0017] In some possible implementation manners, the second reset signal end of the second shift register circuit in the n th shift register unit is connected with the cascade output end of the first shift register circuit in the n+k th shift register unit; wherein k is a positive integer.

[0018] The embodiments of the present disclosure further provide a driving method of the above-described shift register unit, including:

[0019] The first shift register circuit outputs a cascade signal through the cascade output end in response to a signal of the first input signal end;

[0020] The switch circuit connects the cascade output end with the second input signal end in response to a signal of the gate control signal end.

[0021] Alternatively, the switch circuit disconnects the cascade output end from the second input signal end in response to a signal of the gate control signal end.

[0022] The disclosure also provides a driving method of the gate drive circuit.

[0023] In a frame time, the first shift register circuit in each shift register unit outputs a cascade signal through a cascade output end in response to a signal of a first input signal end;

[0024] The switch circuit in at least one shift register unit connects a cascade output end in the at least one shift register unit with a second input signal end in the at least one shift register unit in response to a signal of a gate control signal end, and a second shift register circuit in the at least one shift register unit outputs a gate drive signal through a driving output end in response to a signal of the second input signal end.

[0025] The disclosure also provides a display panel comprising a plurality of gate lines and the gate drive circuit.

[0026] A driving output end of an xth shift register unit in the gate drive circuit is connected with a yth gate line in the plurality of gate lines, and x and y are both positive integers.

[0027] The disclosure also provides a display device comprising the display panel. BRIEF DESCRIPTION OF DRAWINGS

[0028] Figure 1 Some structural diagrams of the shift register unit provided by the disclosure are shown;

[0029] Figure 2 Some structural diagrams of the shift register unit provided by the disclosure are shown;

[0030] Figure 3 Some structural diagrams of the shift register unit provided by the disclosure are shown;

[0031] Figure 4 Some structural diagrams of the shift register unit provided by the disclosure are shown;

[0032] Figure 5 Some structural diagrams of the gate drive circuit provided by the disclosure are shown;

[0033] Figure 6 Some structural schematic diagrams of the gate drive circuit provided by the embodiments of the present disclosure are provided.

[0034] Figures 7-10 Some signal timing diagrams of the gate drive circuit provided by the embodiments of the present disclosure are provided. DETAILED DESCRIPTION

[0035] In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all the embodiments. And the embodiments in the present disclosure and the features in the embodiments can be combined with each other without conflict. Based on the described embodiments of the present disclosure, all other embodiments obtained by those of ordinary skill in the art without creative labor fall within the scope of protection of the present disclosure.

[0036] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood as the common meanings of the technical terms or scientific terms by those of ordinary skill in the art to which the present disclosure belongs. The terms "first", "second" and similar terms used in the present disclosure do not represent any order, number or importance, but are only used to distinguish different parts. The terms "include" or "contain" and similar terms mean that the elements or objects before the terms cover the elements or objects listed after the terms and their equivalents, and do not exclude other elements or objects. The terms "connect" or "connected" and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect.

[0037] It should be noted that the size and shape of each figure in the drawings do not reflect the true proportions, but only serve to illustrate the present disclosure. And the same or similar reference numbers represent the same or similar elements or elements with the same or similar functions throughout.

[0038] Generally, the gate drive circuit can include a plurality of shift register units in cascade, an input signal end of a first stage shift register unit is connected with a frame trigger signal end STV, and an input signal end of a current stage shift register unit is connected with a signal output end of a previous stage shift register unit. That is, the first stage shift register unit can be controlled by the frame trigger signal stv, and the input signal end is controlled by the signal of the signal output end of the previous stage shift register unit from the second stage shift register unit, so that the signal is output stage by stage, and the pixels in the display panel are driven row by row. Thus, it is caused that the gate drive circuit can only control the shift register units to output the gate drive signal stage by stage when working, and cannot control only part of the shift register units to output the gate drive signal, so that the display panel can only be refreshed in full screen, and cannot be refreshed locally, causing unnecessary power consumption.

[0039] To solve the above problems, the shift register unit provided by the embodiments of the present disclosure can control the on-off of the cascade output end of the first shift register circuit and the second input signal end of the second shift register circuit based on the switch circuit, and then control the second shift register circuit to output or not output the gate drive signal, so that the corresponding pixels can be selectively driven, the local refresh of the display panel screen is realized, and power consumption is saved.

[0040] In the embodiments of the present disclosure, as shown in Figure 1 The shift register unit can include a first shift register circuit 10, a second shift register circuit 20, and a switch circuit 30.

[0041] The first shift register circuit 10 is configured to output a cascade signal through a cascade output end O(n) in response to a signal of a first input signal end INPUT1;

[0042] The second shift register circuit 20 is configured to output a gate drive signal through a driving output end G(n) in response to a signal of a second input signal end INPUT2;

[0043] The switch circuit 30 is connected between the cascade output end O(n) and the second input signal end INPUT2, and the switch circuit 30 is configured to turn on the cascade output end O(n) and the second input signal end INPUT2 in response to a signal of a gate control signal end EN.

[0044] The shift register unit provided by the embodiments of the present disclosure can turn on or turn off the cascade output end and the second input signal end through the switch circuit, so that the signal of the cascade output end can be selectively provided to the second input signal end to control the second shift register circuit to output or not output the gate drive signal, and then the corresponding pixels can be selectively driven, the local refresh of the display panel screen is realized, and power consumption is saved.

[0045] In some embodiments of the present disclosure, as shown in Figure 2 The switch circuit 30 includes at least one first transistor T, a first electrode of the first transistor T is coupled to the cascade output terminal O(n), a second electrode of the first transistor T is coupled to the second input signal terminal INPUT2, and a control electrode of the first transistor T is coupled to the gating control signal terminal EN.

[0046] Exemplarily, the first transistor T is turned on under the control of the active level of the signal of the gating control signal terminal, and is turned off under the control of the inactive level of the signal of the gating control signal terminal. As shown in Figure 2 The first transistor T can be an N-type transistor, and the active level of the signal of the gating control signal terminal is high, and the inactive level is low. Of course, the first transistor T can also be a P-type transistor, and the active level of the signal of the gating control signal terminal is low, and the inactive level is high. In actual application, the specific implementation of the first transistor T can be determined according to the requirements of actual application, which is not limited here.

[0047] In some embodiments of the present disclosure, as shown in Figure 1 The first shift register circuit 10 can also be connected to the first clock signal terminal CK1 and the first reset signal terminal RESET1, and is configured to provide the signal of the first input signal terminal INPUT1 to the first node in response to the signal of the first input signal terminal INPUT1, provide the signal of the first clock signal terminal CK1 to the cascade output terminal O(n) in response to the signal of the first node, and provide the signal of the first reference signal terminal VSS1 to the first node and the cascade output terminal O(n) in response to the signal of the first reset signal terminal RESET1.

[0048] The second shift register circuit 20 can also be connected to the second clock signal terminal CK2 and the second reset signal terminal RESET2, and is configured to provide the signal of the second input signal terminal INPUT2 to the second node in response to the signal of the second input signal terminal INPUT2, provide the signal of the second clock signal terminal CK2 to the driving output terminal G(n) in response to the signal of the second node, and provide the signal of the second reference signal terminal VSS2 to the second node and the driving output terminal G(n) in response to the signal of the second reset signal terminal RESET2.

[0049] In some embodiments of the present disclosure, the first clock signal terminal CK1 and the second clock signal terminal CK2 are different signal terminals, and different clock signals are provided. Exemplarily, the signal of the first clock signal terminal CK1 and the signal of the second clock signal terminal CK2 are opposite in phase.

[0050] In some embodiments of the present disclosure, the first reference signal end VSS1 and the second reference signal end VSS2 can be the same signal end. Of course, the first reference signal end VSS1 and the second reference signal end VSS2 can also be different signal ends.

[0051] Exemplarily, the signal of the first reference signal end VSS1 and the signal of the second reference signal end VSS2 are both low-level signals.

[0052] In some embodiments of the present disclosure, as shown in Figure 2 The first shift register circuit 10 and the second shift register circuit 20 have the same structure.

[0053] Exemplarily, the first shift register circuit and the second shift register circuit can both be 4T1C circuits, 4T2C circuits, 8T1C circuits, 12T3C circuits, etc., which are not limited herein.

[0054] Exemplarily, as shown in Figure 2 The first shift register circuit and the second shift register circuit can both include transistors T1-T4 and a capacitor C1. The types of the transistors T1-T4 can be N-type transistors or P-type transistors. In the first shift register circuit, the gate, the first electrode and the second electrode of the transistor T1 are coupled with the first input signal end INPUT1, the first node Q1 and the first reference signal end VSS1 respectively; the gate, the first electrode and the second electrode of the transistor T2 are coupled with the first node Q1, the first clock signal end CK1 and the cascaded output end O(n) respectively; the gate, the first electrode and the second electrode of the transistor T3 are coupled with the first reset signal end RESET1, the first reference signal end VSS1 and the first node Q1 respectively; the gate, the first electrode and the second electrode of the transistor T4 are coupled with the first reset signal end RESET1, the first reference signal end VSS1 and the cascaded output end O(n) respectively; and the first electrode and the second electrode of the capacitor C1 are coupled with the first node Q1 and the cascaded output end O(n) respectively.

[0055] In the second shift register circuit, the gate, the first electrode and the second electrode of the transistor T1 are coupled with the second input signal end INPUT2, the second node Q2 and the second reference signal end VSS2 respectively; the gate, the first electrode and the second electrode of the transistor T2 are coupled with the second node Q2, the second clock signal end CK2 and the driving output end G(n) respectively; the gate, the first electrode and the second electrode of the transistor T3 are coupled with the second reset signal end RESET2, the second reference signal end VSS2 and the second node Q2 respectively; the gate, the first electrode and the second electrode of the transistor T4 are coupled with the second reset signal end RESET2, the second reference signal end VSS2 and the driving output end G(n) respectively; and the first electrode and the second electrode of the capacitor C1 are coupled with the second node Q2 and the driving output end G(n) respectively.

[0056] Exemplarily, according to the type of the transistor and the signal of the gate of the transistor, the first electrode of the transistor can be taken as the source electrode of the transistor and the second electrode of the transistor can be taken as the drain electrode of the transistor, or vice versa. The design can be determined according to the actual application environment, and specific differentiation is not made herein.

[0057] The embodiment of the present disclosure further provides a driving method of the shift register unit, which can include the following steps: Figure 3

[0058] S101, the first shift register circuit outputs a cascade signal through the cascade output end in response to the signal of the first input signal end;

[0059] S102, the switch circuit turns on the cascade output end and the second input signal end in response to the signal of the gating control signal end, and the second shift register circuit outputs a gate driving signal through the driving output end in response to the signal of the second input signal end; or the switch circuit turns off the cascade output end and the second input signal end in response to the signal of the gating control signal end.

[0060] The driving method of the shift register unit provided by the embodiment of the present disclosure can selectively provide the signal of the cascade output end to the second input signal end by loading high and low level signals to the gating control signal end to turn on or turn off the cascade output end and the second input signal end, so as to control the second shift register circuit to output or not to output the gate driving signal, and then to selectively drive the corresponding pixel, to realize the local refresh of the display panel screen and save power consumption.

[0061] The following will take the shift register unit shown in Figure 2 as an example, and describe the working process of the above-mentioned shift register unit provided by the embodiment of the present disclosure in combination with the signal timing diagram shown in Figure 4 .

[0062] Specifically, the first stage, the second stage and the third stage in the signal timing diagram shown in Figure 4 are selected. It should be noted that, Figure 4 the signal timing diagram shown inis only the working process of a certain shift register unit in one frame of time. The working processes of the shift register unit in other frames are basically the same as that in the frame, and thus will not be described herein.

[0063] In the first stage T1, the signal input1 of the first input signal end is high level, the signal ck1 of the first clock signal end is low level, the signal reset1 of the first reset signal end is low level, the signal en of the gating control signal end is high level, the signal ck2 of the second clock signal end is low level, and the signal reset2 of the second reset signal end is low level.

[0064] The first shift register circuit provides the signal input1 of the first input signal terminal at high level to the first node Q1 in response to the signal of the first input signal terminal, and provides the signal ck1 of the first clock signal terminal at low level to the cascade output terminal O(n) in response to the signal of the first node Q1, and the cascade output terminal O(n) outputs the cascade signal output at low level.

[0065] The switch circuit turns on the cascade output terminal O(n) and the second input signal terminal INPUT2 in response to the signal en of the gate control signal terminal, and provides the cascade signal output at low level to the second input signal terminal INPUT2.

[0066] In the second stage T2, the signal input1 of the first input signal terminal is at low level, the signal ck1 of the first clock signal terminal is at high level, the signal reset1 of the first reset signal terminal is at low level, the signal en of the gate control signal terminal is at high level, the signal ck2 of the second clock signal terminal is at low level, and the signal reset2 of the second reset signal terminal is at low level.

[0067] In the first shift register circuit, the first node Q1 is kept at high level due to the bootstrap effect of the capacitor C1, and the first shift register circuit provides the signal ck1 of the first clock signal terminal at high level to the cascade output terminal O(n) in response to the signal of the first node Q1, and the cascade output terminal O(n) outputs the cascade signal output at high level.

[0068] The switch circuit turns on the cascade output terminal O(n) and the second input signal terminal INPUT2 in response to the signal en of the gate control signal terminal, and provides the cascade signal output at high level to the second input signal terminal INPUT2.

[0069] The second shift register circuit provides the signal of the second input signal terminal INPUT2 at high level to the second node Q2 in response to the signal of the second input signal terminal INPUT2, and provides the signal ck2 of the second clock signal terminal at low level to the drive output terminal G(n) in response to the signal of the second node Q2, and the drive output terminal G(n) outputs the gate drive signal gate at low level.

[0070] In the third stage T3, the signal input1 of the first input signal terminal is at low level, the signal ck1 of the first clock signal terminal is at low level, the signal reset1 of the first reset signal terminal is at high level, the signal en of the gate control signal terminal is at high level, the signal ck2 of the second clock signal terminal is at high level, and the signal reset2 of the second reset signal terminal is at low level.

[0071] The first shift register circuit provides a low level signal of the reference signal terminal VSS to the first node Q1 and the cascade output terminal O(n) in response to a signal reset1 of the first reset signal terminal, and the cascade output terminal O(n) outputs a low level cascade signal output.

[0072] The switch circuit turns on the cascade output terminal O(n) and the second input signal terminal INPUT2 in response to a signal of the gate control signal terminal, and provides the low level cascade signal output to the second input signal terminal INPUT2.

[0073] In the second shift register circuit, the second node Q2 is kept at a high level due to the bootstrap effect of the capacitor C1, and the second shift register circuit provides a high level signal ck2 of the second clock signal terminal to the drive output terminal G(n) in response to a signal of the second node Q2, and the drive output terminal G(n) outputs a high level gate drive signal gate.

[0074] In the above-mentioned second stage T2, when the cascade output terminal outputs a high level cascade signal output, the switch circuit turns off the cascade output terminal O(n) and the second input signal terminal INPUT2 in response to a signal of the gate control signal terminal, and the high level cascade signal output cannot be provided to the second input signal terminal INPUT2, the transistor T1 in the second shift register circuit is turned off, so that the second node Q2 cannot be charged, and in the third stage T3, even if the signal of the gate control signal terminal is high level, since the cascade output terminal O(n) outputs a low level cascade signal output in this working stage, a low level signal is provided to the second input signal terminal INPUT2, the transistor T1 in the second shift register circuit is turned off, the second node Q2 is not high level, the transistor T2 is turned off, and the signal ck2 of the second clock signal terminal cannot be provided to the drive output terminal G(n); at the same time, the signal reset1 of the second reset signal terminal RESET2 in the second shift register circuit is low level, the transistor T4 is turned off, the signal of the second reference signal terminal VSS2 cannot be provided to the drive output terminal G(n), and the drive output terminal G(n) has no gate drive signal output.

[0075] The embodiments of the present disclosure also provide a gate drive circuit, as shown in Figure 5 The gate drive circuit can include a plurality of cascaded shift register circuits as shown in Figure 1The shift register unit is shown. Wherein, ck represents the signal of the first clock signal end, xck represents the signal of the second clock signal end, vss1 represents the signal of the first reference signal end, vss2 represents the signal of the second reference signal end, en represents the signal of the gate control signal end; Q(n) represents the cascade output end of the nth shift register unit S(n), and G(n) represents the driving output end of the nth shift register unit S(n).

[0076] The first input signal end INPUT1 of the first shift register circuit in the first shift register unit is connected with the frame trigger signal end STV (not shown in the figure); Figure 5

[0077] The cascade output end O(n) of the first shift register circuit in the nth shift register unit is connected with the first input signal end of the first shift register circuit in the nth+m shift register unit, and the first reset signal end of the first shift register circuit in the nth shift register unit is connected with the cascade output end O(n+i) of the first shift register circuit in the nth+i shift register unit; wherein, m, n and i are all positive integers.

[0078] Exemplarily, m and i can be natural numbers such as 1, 2, 3, 4 and the like. Exemplarily, m and i can be the same or different. For example, m and i are both 1, and in the adjacent two shift register units, the signal of the first input signal end of the next shift register unit is provided by the cascade output end of the previous shift register unit, and the signal of the first reset signal end of the previous shift register unit is provided by the cascade output end of the next shift register unit. For example, m and i are both 2, the cascade output end of the nth-2 shift register unit is connected with the first input signal end of the nth shift register unit, and the cascade output end of the nth-1 shift register unit is connected with the first input signal end of the nth+1 shift register unit; the first reset signal end of the nth-2 shift register unit is connected with the cascade output end of the nth shift register unit, and the first reset signal end of the nth-1 shift register unit is connected with the cascade output end of the nth+1 shift register unit; the other shift register units have the same connection logic, which is not described here.

[0079] Specifically, in the above-mentioned gate drive circuit provided by the embodiments of the present disclosure, the signals of the first reference signal ends of the shift register units are all provided by the same first direct current signal end, and the signals of the second reference signal ends of the shift register units are all provided by the same second direct current signal end. Exemplarily, the first direct current signal end and the second direct current signal end can be the same direct current signal end.

[0080] In the embodiments of the present disclosure, as Figure 5 ​As shown, the gating control signal terminals connected to the switch circuits in each level of shift register units are the same signal terminal.

[0081] In an embodiment of the present disclosure, the second reset signal terminal of the second shift register circuit in the nth stage shift register unit is connected to the cascade output terminal O(n+k) of the first shift register circuit in the n+kth stage shift register unit; where k is a positive integer.

[0082] Exemplarily, k can be a natural number such as 2, 3, or 4. For example, when k is 2, the second reset signal terminal of the n-1th stage shift register unit is connected to the cascade output terminal of the n+1th stage shift register unit; the second reset signal terminal of the nth stage shift register unit is connected to the cascade output terminal of the n+2th stage shift register unit; the second reset signal terminal of the n+1th stage shift register unit is connected to the cascade output terminal of the n+3th stage shift register unit. The other stages of the shift register unit have the same connection logic and are not further described here.

[0083] In an embodiment of the present disclosure, in the above-mentioned gate drive circuit, the first clock signal end of the first shift register circuit in the odd-numbered shift register unit and the second clock signal end of the second shift register circuit in the even-numbered shift register unit are connected to the same first clock signal, and the first clock signal end of the first shift register circuit in the even-numbered shift register unit and the second clock signal end of the second shift register circuit in the odd-numbered shift register unit are connected to the same second clock signal.

[0084] For example, Figure 5 As shown, in the n-th stage shift register unit, the first clock signal end of the first shift register circuit is connected to the first clock signal ck, and the second clock signal end of the second shift register circuit is connected to the second clock signal xck; in the n+1-th stage shift register unit, the first clock signal end of the first shift register single channel is connected to the second clock signal xck, and the second clock signal end of the second shift register circuit is connected to the first clock signal ck.

[0085] It should be noted that the transistors mentioned in the above embodiments of the present disclosure may be TFTs or metal oxide semiconductor field effect transistors (MOS), which are not limited here.

[0086] In order to simplify the preparation process, in the specific implementation, in the embodiment of the present disclosure, as Figure 1 As shown, all transistors can be N-type transistors. Of course, all transistors can also be P-type transistors, which is not limited here.

[0087] The above is only an example of the specific structure of the gate drive circuit provided by the embodiments of the present disclosure, and in specific implementation, the specific structure of each circuit is not limited to the above structure provided by the embodiments of the present disclosure, but can also be other structures known to those skilled in the art, which are not limited herein.

[0088] The embodiments of the present disclosure also provide a driving method of the gate drive circuit, which can include the following steps: in a frame time, the first shift register circuit in each stage of the shift register unit outputs a cascade signal through the cascade output end in response to the signal of the first input signal end; the switch circuit in at least one shift register unit turns on the cascade output end in the at least one shift register unit and the second input signal end in the at least one shift register unit in response to the signal of the gate control signal end; and the second shift register circuit in the at least one shift register unit outputs a gate drive signal through the driving output end in response to the signal of the second input signal end.

[0089] The driving method of the gate drive circuit provided by the embodiments of the present disclosure can selectively turn on the cascade output end of part of the shift register unit and the second input signal end by loading an effective level signal to part of the gate control signal end, so as to control the second shift register circuit of part of the shift register unit to output a gate drive signal, and further selectively drive the corresponding pixel, realize local refresh of the display panel screen, and save power consumption.

[0090] The following will take the gate drive circuit shown in Figure 6 as an example, and describe the working process of the above gate drive circuit provided by the embodiments of the present disclosure in combination with the signal timing diagram shown in Figures 7-10 .

[0091] Specifically, as shown in the gate drive circuit shown in Figure 6 , the first input signal end of the second stage shift register unit S(2) is connected with the cascade output end O(1) of the first stage shift register unit S(1), and the first input signal end of the third stage shift register unit S(3) is connected with the cascade output end O(2) of the second stage shift register unit S(2); the first reset signal end of the first stage shift register unit S(1) is connected with the cascade output end O(2) of the second stage shift register unit S(2), and the first reset signal end of the second stage shift register unit S(2) is connected with the cascade output end O(3) of the third stage shift register unit S(3); the second reset signal end of the first stage shift register unit S(1) is connected with the cascade output end O(3) of the third stage shift register unit S(3), and the second reset signal end of the second stage shift register unit S(2) is connected with the cascade output end O(4) of the fourth stage shift register unit S(4). Each stage of the shift register unit has the same connection logic, which is not described herein again.

[0092] Specifically, the first stage, the second stage, the third stage, the fourth stage and the fifth stage in the signal timing diagram shown in the figure are selected. Figure 7 It should be noted that the signal timing diagram shown in the figure is only the working process of the gate drive circuit in a frame time. The working processes of the gate drive circuit in other frames are basically the same as that in the frame, and will not be repeated here. Figure 7

[0093] In the first stage T1, the signal stv of the frame trigger signal end is high, the signal ck of the first clock signal end is low, the signal en of the gate control signal end is high, and the signal xck of the second clock signal end is low.

[0094] In the first stage T1, the signal stv of the frame trigger signal end is high, the signal ck of the first clock signal end is low, the signal en of the gate control signal end is high, and the signal xck of the second clock signal end is low.

[0095] In the second stage T2, the signal stv of the frame trigger signal end is low, the signal ck of the first clock signal end is high, the signal en of the gate control signal end is high, and the signal xck of the second clock signal end is low.

[0096] In the first stage T1, the signal stv of the frame trigger signal end is high, the signal ck of the first clock signal end is low, the signal en of the gate control signal end is high, and the signal xck of the second clock signal end is low.

[0097] In the second stage T2, the signal stv of the frame trigger signal end is low, the signal ck of the first clock signal end is high, the signal en of the gate control signal end is high, and the signal xck of the second clock signal end is low.

[0098] ​In the third stage T3, the signal stv at the frame trigger signal terminal is low, the signal ck at the first clock signal terminal is low, the signal en at the gate control signal terminal is high, and the signal xck at the second clock signal terminal is high.

[0099] In the first stage of the shift register unit, the second node Q2 is kept at high level due to the bootstrap effect of the capacitor C1 in the second shift register circuit, and the second shift register circuit provides the signal xck at the second clock signal terminal at high level to the driving output terminal G(1) in response to the signal of the second node Q2, and the driving output terminal G(1) outputs the gate driving signal g(1) at high level.

[0100] In the second stage of the shift register unit, the first node Q1 is kept at high level due to the bootstrap effect of the capacitor C1 in the first shift register circuit, and the first shift register circuit provides the signal xck at the second clock signal terminal at high level to the cascade output terminal O(2) in response to the signal of the first node Q1, and the cascade output terminal O(2) outputs the cascade signal o(2) at high level; the switch circuit provides the cascade signal o(2) at high level to the second input signal terminal in response to the signal at the gate control signal terminal, and the second shift register circuit provides the signal at the second input signal terminal at high level to the second node Q2 in response to the signal at the second input signal terminal.

[0101] In the third stage of the shift register unit, the first shift register circuit provides the signal at the cascade output terminal O(2) at high level to the first node Q1 in response to the signal at the cascade output terminal O(2).

[0102] In the first stage of the shift register unit, the first shift register circuit provides the signal at the reference signal terminal at low level to the first node Q1 and the cascade output terminal O(1) in response to the signal at the cascade output terminal O(2), and the cascade output terminal O(1) outputs the cascade signal o(1) at low level.

[0103] In the fourth stage T4, the signal stv at the frame trigger signal terminal is low, the signal ck at the first clock signal terminal is high, the signal en at the gate control signal terminal is high, and the signal xck at the second clock signal terminal is low.

[0104] In the second stage of the shift register unit, the second node Q2 is kept at high level due to the bootstrap effect of the capacitor C1 in the second shift register circuit, and the second shift register circuit provides the signal ck at the first clock signal terminal at high level to the driving output terminal G(2) in response to the signal of the second node Q2, and the driving output terminal G(2) outputs the gate driving signal g(2) at high level.

[0105] In the third stage shift register unit, the first node Q1 is kept at high level due to the bootstrap effect of the capacitor C1 in the first shift register circuit, the first shift register circuit provides the signal ck of the first clock signal end at high level to the cascade output end O(3) in response to the signal of the first node Q1, and the cascade output end O(3) outputs the cascade signal o(3) at high level; the switch circuit provides the cascade signal o(3) at high level to the second input signal end in response to the signal of the gating control signal end, and the second shift register circuit provides the signal of the second input signal end at high level to the second node Q2 in response to the signal of the second input signal end.

[0106] In the fourth stage shift register unit, the first shift register circuit provides the signal of the cascade output end O(3) at high level to the first node Q1 in response to the signal of the cascade output end O(3).

[0107] In the second stage shift register unit, the first shift register circuit provides the signal of the reference signal end at low level to the first node Q1 and the cascade output end O(2) in response to the signal of the cascade output end O(3), and the cascade output end O(2) outputs the cascade signal o(2) at low level.

[0108] In the fifth stage T5, the signal stv of the frame trigger signal end is at low level, the signal ck of the first clock signal end is at low level, the signal en of the gating control signal end is at high level, and the signal xck of the second clock signal end is at high level.

[0109] In the third stage shift register unit, the second node Q2 is kept at high level due to the bootstrap effect of the capacitor C1 in the second shift register circuit, the second shift register circuit provides the signal xck of the second clock signal end at high level to the drive output end G(3) in response to the signal of the second node Q2, and the drive output end G(3) outputs the gate drive signal g(3) at high level.

[0110] In the fourth stage shift register unit, the first node Q1 is kept at high level due to the bootstrap effect of the capacitor C1 in the first shift register circuit, the first shift register circuit provides the signal xck of the second clock signal end at high level to the cascade output end O(4) in response to the signal of the first node Q1, and the cascade output end O(4) outputs the cascade signal o(4) at high level; the switch circuit provides the cascade signal o(4) at high level to the second input signal end in response to the signal of the gating control signal end, and the second shift register circuit provides the signal of the second input signal end at high level to the second node Q2 in response to the signal of the second input signal end.

[0111] In the 5th stage shift register unit, the first shift register circuit provides the signal of the cascade output end O(4) with high level to the first node Q1 in response to the signal of the cascade output end O(4).

[0112] In the 3rd stage shift register unit, the first shift register circuit provides the signal of the reference signal end with low level to the first node Q1 and the cascade output end O(3) in response to the signal of the cascade output end O(4), and the cascade output end O(3) outputs the cascade signal o(3) with low level.

[0113] Through the above-mentioned driving method of the gate driving circuit, each stage shift register unit in the gate driving circuit outputs the gate driving signal stage by stage to drive all the pixels, and full screen refresh of the display panel screen is realized.

[0114] Specifically, the first stage, the second stage, the third stage, the fourth stage and the fifth stage in the signal timing diagram as shown in Figure 8 It should be noted that, Figure 8 The signal timing diagram as shown in the figure is only the working process of the gate driving circuit in one frame time. The working processes of the gate driving circuit in other frames are basically the same as that in the frame, and are not described here.

[0115] In the first stage T1, the signal stv of the frame trigger signal end is high level, the signal ck of the first clock signal end is low level, the signal en of the gate control signal end is low level, and the signal xck of the second clock signal end is low level.

[0116] In the 1st stage shift register unit, the first shift register circuit provides the signal stv of the frame trigger signal end with high level to the first node Q1 in response to the signal stv of the frame trigger signal end, and provides the signal ck of the first clock signal end with low level to the cascade output end O(1) in response to the signal of the first node Q1, and the cascade output end O(1) outputs the cascade signal o(1) with low level; the switch circuit disconnects the cascade output end from the second input signal end in response to the signal en of the gate control signal end.

[0117] In the second stage T2, the signal stv of the frame trigger signal end is low level, the signal ck of the first clock signal end is high level, the signal en of the gate control signal end is low level, and the signal xck of the second clock signal end is low level.

[0118] In the first stage shift register unit, the first node Q1 is kept at high level due to the bootstrap effect of the capacitor C1 in the first shift register circuit, the first shift register circuit provides the signal ck of the high level first clock signal end to the cascade output end O(1) in response to the signal of the first node Q1, and the cascade output end O(1) outputs the cascade signal o(1) of the high level; the switch circuit disconnects the cascade output end from the second input signal end in response to the signal of the gating control signal end, and the cascade signal o(1) cannot be provided to the second input signal end, and the second node Q2 cannot be charged.

[0119] In the second stage shift register unit, the first shift register circuit provides the signal of the high level cascade output end O(1) to the first node Q1 in response to the signal of the cascade output end O(1).

[0120] In the third stage T3, the signal stv of the frame trigger signal end is low, the signal ck of the first clock signal end is low, the signal en of the gating control signal end is low, and the signal xck of the second clock signal end is high.

[0121] In the first stage shift register unit, the second node Q2 is not at high level, the transistor T2 in the second shift register circuit is controlled to be cut off, so that the gate driving signal g(1) is not output from the driving output end G(1).

[0122] In the second stage shift register unit, the first node Q1 is kept at high level due to the bootstrap effect of the capacitor C1 in the first shift register circuit, the first shift register circuit provides the signal xck of the high level second clock signal end to the cascade output end O(2) in response to the signal of the first node Q1, and the cascade output end O(2) outputs the cascade signal o(2) of the high level; the switch circuit disconnects the cascade output end from the second input signal end in response to the signal of the gating control signal end.

[0123] In the third stage shift register unit, the first shift register circuit provides the signal of the high level cascade output end O(2) to the first node Q1 in response to the signal of the cascade output end O(2).

[0124] In the first stage shift register unit, the first shift register circuit provides the signal of the low level reference signal end to the first node Q1 and the cascade output end O(1) in response to the signal of the cascade output end O(2), and the cascade output end O(1) outputs the cascade signal o(1) of the low level.

[0125] In the fourth stage T4, the signal stv of the frame trigger signal end is low, the signal ck of the first clock signal end is high, the signal en of the gating control signal end is high, and the signal xck of the second clock signal end is low.

[0126] In the second stage shift register unit, since the second node Q2 is not high, the transistor T2 in the second shift register circuit is turned off, so that the gate driving signal g(2) is not output from the driving output end G(2).

[0127] In the third stage shift register unit, due to the bootstrap effect of the capacitor C1 in the first shift register circuit, the first node Q1 is kept high, the first shift register circuit provides the high level signal ck of the first clock signal end to the cascade output end O(3) in response to the signal of the first node Q1, the cascade output end O(3) outputs the high level cascade signal o(3); the switch circuit provides the high level cascade signal o(3) to the second input signal end in response to the signal of the gate control signal end, and the second shift register circuit provides the high level signal of the second input signal end to the second node Q2 in response to the signal of the second input signal end.

[0128] In the fourth stage shift register unit, the first shift register circuit provides the high level signal of the cascade output end O(3) to the first node Q1 in response to the signal of the cascade output end O(3).

[0129] In the second stage shift register unit, the first shift register circuit provides the low level signal of the reference signal end to the first node Q1 and the cascade output end O(2) in response to the signal of the cascade output end O(3), and the cascade output end O(2) outputs the low level cascade signal o(2).

[0130] In the fifth stage T5, the signal stv of the frame trigger signal end is low, the signal ck of the first clock signal end is low, the signal en of the gate control signal end is high, and the signal xck of the second clock signal end is high.

[0131] In the third stage shift register unit, due to the bootstrap effect of the capacitor C1 in the second shift register circuit, the second node Q2 is kept high, and the second shift register circuit provides the high level signal xck of the second clock signal end to the driving output end G(3) in response to the signal of the second node Q2, and the driving output end G(3) outputs the high level gate driving signal g(3).

[0132] In the fourth-stage shift register unit, the first node Q1 is kept at a high level due to the bootstrap effect of the capacitor C1 in the first shift register circuit, the first shift register circuit provides the signal xck of the second clock signal end at a high level to the cascade output end O(4) in response to the signal of the first node Q1, and the cascade output end O(4) outputs the cascade signal o(4) at a high level; the switch circuit provides the cascade signal o(4) at a high level to the second input signal end in response to the signal of the gate control signal end, and the second shift register circuit provides the signal of the second input signal end at a high level to the second node Q2 in response to the signal of the second input signal end.

[0133] In the fifth-stage shift register unit, the first shift register circuit provides the signal of the cascade output end O(4) at a high level to the first node Q1 in response to the signal of the cascade output end O(4).

[0134] In the third-stage shift register unit, the first shift register circuit provides the signal of the reference signal end at a low level to the first node Q1 and the cascade output end O(3) in response to the signal of the cascade output end O(4), and the cascade output end O(3) outputs the cascade signal o(3) at a low level.

[0135] Through the driving method of the above-described gate driving circuit, the gate driving circuit can output the gate driving signal from the third-stage shift register unit to drive the corresponding pixels, so as to realize the local refresh of the display panel screen and save the power consumption.

[0136] Specifically, the first stage, the second stage, the third stage, the fourth stage, the fifth stage and the sixth stage in the signal timing diagram shown in FIG. 8 are selected. Figure 9 It should be noted that, Figure 9 The signal timing diagram shown in FIG. 8 is only the working process of the gate driving circuit in one frame. The working processes of the gate driving circuit in other frames are basically the same as that in the frame, and are not described herein.

[0137] In the first stage T1, the signal stv of the frame trigger signal end is at a high level, the signal ck of the first clock signal end is at a low level, the signal en of the gate control signal end is at a high level, and the signal xck of the second clock signal end is at a low level.

[0138] In the first stage T1, the signal stv of the frame trigger signal terminal is low level, the signal ck of the first clock signal terminal is high level, the signal en of the gate control signal terminal is low level, and the signal xck of the second clock signal terminal is high level.

[0139] In the second stage T2, the signal stv of the frame trigger signal terminal is low level, the signal ck of the first clock signal terminal is high level, the signal en of the gate control signal terminal is high level, and the signal xck of the second clock signal terminal is low level.

[0140] In the first stage T1, the signal stv of the frame trigger signal terminal is low level, the signal ck of the first clock signal terminal is high level, the signal en of the gate control signal terminal is low level, and the signal xck of the second clock signal terminal is high level.

[0141] In the second stage T2, the signal stv of the frame trigger signal terminal is low level, the signal ck of the first clock signal terminal is high level, the signal en of the gate control signal terminal is high level, and the signal xck of the second clock signal terminal is low level.

[0142] In the third stage T3, the signal stv of the frame trigger signal terminal is low level, the signal ck of the first clock signal terminal is low level, the signal en of the gate control signal terminal is high level, and the signal xck of the second clock signal terminal is high level.

[0143] In the first stage T1, the signal stv of the frame trigger signal terminal is low level, the signal ck of the first clock signal terminal is high level, the signal en of the gate control signal terminal is low level, and the signal xck of the second clock signal terminal is high level.

[0144] In the second stage shift register unit, the first node Q1 is kept at high level due to the bootstrap effect of the capacitor C1 in the first shift register circuit, the first shift register circuit provides the signal xck of the high level second clock signal end to the cascade output end O(2) in response to the signal of the first node Q1, the cascade output end O(2) outputs the cascade signal o(2) of the high level; the switch circuit provides the cascade signal o(2) of the high level to the second input signal end in response to the signal of the gate control signal end, and the second shift register circuit provides the signal of the second input signal end of the high level to the second node Q2 in response to the signal of the second input signal end.

[0145] In the third stage shift register unit, the first shift register circuit provides the signal of the cascade output end O(2) of the high level to the first node Q1 in response to the signal of the cascade output end O(2).

[0146] In the first stage shift register unit, the first shift register circuit provides the signal of the reference signal end of the low level to the first node Q1 and the cascade output end O(1) in response to the signal of the cascade output end O(2), and the cascade output end O(1) outputs the cascade signal o(1) of the low level.

[0147] In the fourth stage T4, the signal stv of the frame trigger signal end is low level, the signal ck of the first clock signal end is high level, the signal en of the gate control signal end is low level, and the signal xck of the second clock signal end is low level.

[0148] In the second stage shift register unit, the second node Q2 is kept at high level due to the bootstrap effect of the capacitor C1 in the second shift register circuit, and the second shift register circuit provides the signal ck of the first clock signal end of the high level to the drive output end G(2) in response to the signal of the second node Q2, and the drive output end G(2) outputs the gate drive signal g(2) of the high level.

[0149] In the third stage shift register unit, the first node Q1 is kept at high level due to the bootstrap effect of the capacitor C1 in the first shift register circuit, and the first shift register circuit provides the signal ck of the first clock signal end of the high level to the cascade output end O(3) in response to the signal of the first node Q1, and the cascade output end O(3) outputs the cascade signal o(3) of the high level; the switch circuit disconnects the cascade output end and the second input signal end in response to the signal of the gate control signal end, and the cascade signal o(3) of the high level cannot be provided to the second input signal end.

[0150] In the fourth stage shift register unit, the first shift register circuit provides the signal of the cascade output end O(3) of the high level to the first node Q1 in response to the signal of the cascade output end O(3).

[0151] In the second stage shift register unit, the first shift register circuit provides the signal of the reference signal end at low level to the first node Q1 and the cascade output end O(2) in response to the signal of the cascade output end O(3), and the cascade output end O(2) outputs the cascade signal at low level.

[0152] In the fifth stage T5, the signal stv of the frame trigger signal end is at low level, the signal ck of the first clock signal end is at low level, the signal en of the gating control signal end is at low level, and the signal xck of the second clock signal end is at high level.

[0153] In the third stage shift register unit, the transistor T2 in the second shift register circuit is turned off in response to the signal of the second node Q2 not being at high level, so that the gate drive signal g(3) is not output from the drive output end G(3).

[0154] In the fourth stage shift register unit, the first node Q1 is kept at high level in response to the bootstrap effect of the capacitor C1 in the first shift register circuit, the first shift register circuit provides the signal xck of the second clock signal end at high level to the cascade output end O(4) in response to the signal of the first node Q1, the cascade output end O(4) outputs the cascade signal o(4) at high level, and the switch circuit disconnects the cascade output end from the second input signal end in response to the signal of the gating control signal end, so that the cascade signal o(4) at high level cannot be provided to the second input signal end.

[0155] In the fifth stage shift register unit, the first shift register circuit provides the signal of the cascade output end O(4) at high level to the first node Q1 in response to the signal of the cascade output end O(4).

[0156] In the third stage shift register unit, the first shift register circuit provides the signal of the reference signal end at low level to the first node Q1 and the cascade output end O(3) in response to the signal of the cascade output end O(4), and the cascade output end O(3) outputs the cascade signal o(3) at low level.

[0157] In the sixth stage T6, the signal stv of the frame trigger signal end is at low level, the signal ck of the first clock signal end is at high level, the signal en of the gating control signal end is at low level, and the signal xck of the second clock signal end is at low level.

[0158] In the fourth stage shift register unit, the transistor T2 in the second shift register circuit is turned off in response to the signal of the second node Q2 not being at high level, so that the gate drive signal g(4) is not output from the drive output end G(4).

[0159] In the 5th stage shift register unit, the first node Q1 is kept at high level due to the bootstrap effect of the capacitor C1 in the first shift register circuit, and the first shift register circuit provides the signal ck of the first clock signal terminal at high level to the cascade output terminal O(5) in response to the signal of the first node Q1, and the cascade output terminal O(5) outputs the cascade signal o(5) at high level; the switch circuit disconnects the cascade output terminal from the second input signal terminal in response to the signal of the gate control signal terminal, and the cascade signal o(5) at high level cannot be provided to the second input signal terminal.

[0160] In the 6th stage shift register unit, the first shift register circuit provides the signal of the cascade output terminal O(5) at high level to the first node Q1 in response to the signal of the cascade output terminal O(5).

[0161] In the 4th stage shift register unit, the first shift register circuit provides the signal of the reference signal terminal at low level to the first node Q1 and the cascade output terminal O(4) in response to the signal of the cascade output terminal O(5), and the cascade output terminal O(4) outputs the cascade signal o(4) at low level.

[0162] Through the driving method of the above-mentioned gate driving circuit, the gate driving circuit starts from the 3rd stage shift register unit without outputting the gate driving signal to drive the corresponding pixels, so as to realize the local refresh of the display panel screen and save the power consumption.

[0163] Specifically, the first stage, the second stage, the third stage, the fourth stage, the fifth stage and the sixth stage in the signal timing diagram as shown in Figure 10 It should be noted that, Figure 10 The signal timing diagram as shown in the above is only the working process of the gate driving circuit in one frame. The working processes of the gate driving circuit in other frames are basically the same as that in the frame, and will not be repeated here.

[0164] In the first stage T1, the signal stv of the frame trigger signal terminal is at high level, the signal ck of the first clock signal terminal is at low level, the signal en of the gate control signal terminal is at low level, and the signal xck of the second clock signal terminal is at low level.

[0165] In the 1st stage shift register unit, the first shift register circuit provides the signal stv of the frame trigger signal terminal at high level to the first node Q1 in response to the signal of the frame trigger signal terminal, and provides the signal ck of the first clock signal terminal at low level to the cascade output terminal O(1) in response to the signal of the first node Q1, and the cascade output terminal O(1) outputs the cascade signal o(1) at low level; the switch circuit disconnects the cascade output terminal from the second input signal terminal in response to the signal en of the gate control signal terminal.

[0166] In the second stage T2, the signal stv at the frame trigger signal terminal is low, the signal ck at the first clock signal terminal is high, the signal en at the gate control signal terminal is low, and the signal xck at the second clock signal terminal is low.

[0167] In the first stage of the shift register unit, the first node Q1 is kept at high level due to the bootstrap effect of the capacitor C1 in the first shift register circuit, the first shift register circuit provides the signal ck at the first clock signal terminal at high level to the cascade output terminal O(1) in response to the signal at the first node Q1, and the cascade output terminal O(1) outputs the cascade signal o(1) at high level; the switch circuit disconnects the cascade output terminal from the second input signal terminal in response to the signal at the gate control signal terminal, and the cascade signal o(1) at high level cannot be provided to the second input signal terminal.

[0168] In the second stage of the shift register unit, the first shift register circuit provides the signal at the cascade output terminal O(1) at high level to the first node Q1 in response to the signal at the cascade output terminal O(1).

[0169] In the third stage T3, the signal stv at the frame trigger signal terminal is low, the signal ck at the first clock signal terminal is low, the signal en at the gate control signal terminal is high, and the signal xck at the second clock signal terminal is high.

[0170] In the first stage of the shift register unit, the second node Q2 is not at high level, the transistor T2 in the second shift register circuit is turned off, and thus the gate driving signal g(1) is not output from the driving output terminal G(1).

[0171] In the second stage of the shift register unit, the first node Q1 is kept at high level due to the bootstrap effect of the capacitor C1 in the first shift register circuit, the first shift register circuit provides the signal xck at the second clock signal terminal at high level to the cascade output terminal O(2) in response to the signal at the first node Q1, the cascade output terminal O(2) outputs the cascade signal o(2) at high level, the switch circuit provides the cascade signal o(2) at high level to the second input signal terminal in response to the signal at the gate control signal terminal, and the second shift register circuit provides the signal at the second input signal terminal at high level to the second node Q2.

[0172] In the third stage of the shift register unit, the first shift register circuit provides the signal at the cascade output terminal O(2) at high level to the first node Q1 in response to the signal at the cascade output terminal O(2).

[0173] In the first stage shift register unit, the first shift register circuit provides the signal of the low level reference signal end to the first node Q1 and the cascade output end O(1) in response to the signal of the cascade output end O(2), and the cascade output end O(1) outputs the low level cascade signal o(1).

[0174] In the fourth stage T4, the signal stv of the frame trigger signal end is low level, the signal ck of the first clock signal end is high level, the signal en of the gate control signal end is low level, and the signal xck of the second clock signal end is low level.

[0175] In the second stage shift register unit, the second node Q2 is kept high level due to the bootstrap effect of the capacitor C1 in the second shift register circuit, and the second shift register circuit provides the signal of the high level first clock signal end ck to the driving output end G(2) in response to the signal of the second node Q2, and the driving output end G(2) outputs the high level gate driving signal g(2).

[0176] In the third stage shift register unit, the first node Q1 is kept high level due to the bootstrap effect of the capacitor C1 in the first shift register circuit, and the first shift register circuit provides the signal of the high level first clock signal end ck to the cascade output end O(3) in response to the signal of the first node Q1, and the cascade output end O(3) outputs the high level cascade signal o(3); the switch circuit disconnects the cascade output end and the second input signal end in response to the signal of the gate control signal end, and the high level cascade signal o(3) cannot be provided to the second input signal end.

[0177] In the fourth stage shift register unit, the first shift register circuit provides the signal of the high level cascade output end O(3) to the first node Q1 in response to the signal of the cascade output end O(3).

[0178] In the second stage shift register unit, the first shift register circuit provides the signal of the low level reference signal end to the first node Q1 and the cascade output end O(2) in response to the signal of the cascade output end O(3), and the cascade output end O(2) outputs the low level cascade signal o(2).

[0179] In the fifth stage T5, the signal stv of the frame trigger signal end is low level, the signal ck of the first clock signal end is low level, the signal en of the gate control signal end is high level, and the signal xck of the second clock signal end is high level.

[0180] In the third stage shift register unit, the second node Q2 is not high level, the transistor T2 in the second shift register circuit is controlled to be cut off, and thus the driving output end G(3) has no gate driving signal g(3) output.

[0181] In the fourth stage shift register unit, the first node Q1 is kept at high level due to the bootstrap effect of the capacitor C1 in the first shift register circuit, the first shift register circuit provides the signal xck of the high level second clock signal end to the cascade output end O(4) in response to the signal of the first node Q1, the cascade output end O(4) outputs the cascade signal o(4) of high level; the switch circuit provides the cascade signal o(4) of high level to the second input signal end in response to the signal of the gating control signal end, the second shift register circuit provides the signal of the second input signal end of high level to the second node Q2 in response to the signal of the second input signal end.

[0182] In the fifth stage shift register unit, the first shift register circuit provides the signal of the cascade output end O(4) of high level to the first node Q1 in response to the signal of the cascade output end O(4).

[0183] In the third stage shift register unit, the first shift register circuit provides the signal of the reference signal end of low level to the first node Q1 and the cascade output end O(3) in response to the signal of the cascade output end O(4), the cascade output end O(3) outputs the cascade signal o(3) of low level.

[0184] In the sixth stage T6, the signal stv of the frame trigger signal end is low level, the signal ck of the first clock signal end is high level, the signal en of the gating control signal end is high level, and the signal xck of the second clock signal end is low level.

[0185] In the fourth stage shift register unit, the second node Q2 is kept at high level due to the bootstrap effect of the capacitor C1 in the second shift register circuit, the second shift register circuit provides the signal ck of the first clock signal end of high level to the driving output end G(4) in response to the signal of the second node Q2, the driving output end G(4) outputs the cascade signal g(4) of high level.

[0186] In the fifth stage shift register unit, the first node Q1 is kept at high level due to the bootstrap effect of the capacitor C1 in the first shift register circuit, the first shift register circuit provides the signal ck of the first clock signal end of high level to the cascade output end O(5) in response to the signal of the first node Q1, the cascade output end O(5) outputs the cascade signal o(5) of high level; the switch circuit provides the cascade signal o(5) of high level to the second input signal end in response to the signal of the gating control signal end, the second shift register circuit provides the signal of the second input signal end of high level to the second node Q2 in response to the signal of the second input signal end.

[0187] In the 6th stage shift register unit, the first shift register circuit provides the signal of the high level cascade output terminal O(5) to the first node Q1 in response to the signal of the cascade output terminal O(5).

[0188] In the 4th stage shift register unit, the first shift register circuit provides the signal of the low level reference signal terminal to the first node Q1 and the cascade output terminal O(4) in response to the signal of the cascade output terminal O(5), and the cascade output terminal O(4) outputs the low level cascade signal o(4).

[0189] By the above-mentioned driving method of the gate driving circuit, the 2nd stage and the 4th-Nth stage shift register units in the gate driving circuit output the gate driving signals to drive the corresponding pixels, realize the local refresh of the display panel screen, and save the power consumption.

[0190] The display panel provided by the embodiments of the present disclosure comprises a plurality of gate lines and the above-mentioned gate driving circuit.

[0191] The driving output terminal of the xth stage shift register unit in the gate driving circuit is connected with the yth gate line in the plurality of gate lines, and x and y are both positive integers.

[0192] Exemplarily, the display panel comprises an LCD display panel, an OLED display panel, an LED display panel, and an MLED display panel.

[0193] The display device provided by the embodiments of the present disclosure comprises the above-mentioned display panel.

[0194] Specifically, the display device can further comprise a control mainboard configured to acquire an image picture to be displayed, determine image data of the image picture to be displayed according to the image picture to be displayed, and send the image data to the display panel. The display panel determines a target gate line requiring to load the gate driving signal according to the image data, adjusts a time period of loading the effective level of the gate control signal terminal, and drives the shift register unit in the gate driving circuit connected with the target gate line to output the gate driving signal, so as to drive the pixel row connected with the target gate line to emit light and display the image picture to be displayed.

[0195] In the embodiments of the present disclosure, the display device can be any product or component with display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like. Other essential components of the display device are understood by those skilled in the art, and are not described herein or should not be regarded as a limitation on the present disclosure.

[0196] The shift register unit and driving method, gate driving circuit, and display panel provided in the embodiments of the present disclosure control the conduction between the cascade output terminal and the second input signal terminal in all or part of the shift register units through the switching circuits in the shift register units at each level, so that the driving output terminals of all or part of the shift register units can output gate driving signals to drive the corresponding pixels, thereby achieving full-screen refresh or partial refresh of the display panel screen and saving power consumption.

[0197] Although the preferred embodiments of the present disclosure have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present disclosure.

[0198] Obviously, those skilled in the art may make various changes and modifications to the embodiments of the present disclosure without departing from the spirit and scope of the embodiments of the present disclosure. Thus, if such changes and modifications of the embodiments of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is intended to include such changes and modifications.

Claims

1. A shift register unit, characterized in that: include: a first shift register circuit configured to output a cascade signal through a cascade output terminal in response to a signal at a first input signal terminal; a second shift register circuit configured to output a gate driving signal through a driving output terminal in response to a signal at a second input signal terminal; a switch circuit connected between the cascade output terminal and the second input signal terminal, the switch circuit being configured to connect the cascade output terminal to the second input signal terminal in response to a signal from a strobe control signal terminal; The switch circuit includes at least one first transistor, a first electrode of the first transistor is coupled to the cascade output terminal, a second electrode of the first transistor is coupled to the second input signal terminal, and a control electrode of the first transistor is coupled to the selection control signal terminal; The first shift register circuit is further connected to a first clock signal terminal and a first reset signal terminal, and is configured to provide a signal from the first input signal terminal to a first node in response to a signal from the first input signal terminal, provide a signal from the first clock signal terminal to the cascade output terminal in response to a signal from the first node, and provide a signal from the first reference signal terminal to the first node and the cascade output terminal in response to a signal from the first reset signal terminal; The second shift register circuit is also connected to the second clock signal terminal and the second reset signal terminal, and is configured to provide the signal of the second input signal terminal to the second node in response to the signal of the second input signal terminal, provide the signal of the second clock signal terminal to the driving output terminal in response to the signal of the second node, and provide the signal of the second reference signal terminal to the second node and the driving output terminal in response to the signal of the second reset signal terminal.

2. The shift register unit according to claim 1, wherein: The first clock signal terminal and the second clock signal terminal are different signal terminals.

3. The shift register unit according to claim 1, wherein: The first reference signal terminal and the second reference signal terminal are the same signal terminal.

4. The shift register unit according to claim 1, wherein: The first shift register circuit and the second shift register circuit have the same structure.

5. A gate drive circuit, characterized in that: comprising a plurality of cascaded shift register units according to any one of claims 1 to 4; The first input signal terminal of the first shift register circuit in the first stage shift register unit is connected to the frame trigger signal terminal; The cascade output end of the first shift register circuit in the n-th stage shift register unit is connected to the first input signal end of the first shift register circuit in the n+m-th stage shift register unit, and the first reset signal end of the first shift register circuit in the n-th stage shift register unit is connected to the cascade output end of the first shift register circuit in the n+i-th stage shift register unit; wherein m, n, and i are all positive integers.

6. The gate driving circuit according to claim 5, wherein: The gating control signal terminals connected to the switch circuits in the shift register units at each level are the same signal terminal.

7. The gate driving circuit according to claim 5, wherein: The second reset signal terminal of the second shift register circuit in the nth stage shift register unit is connected to the cascade output terminal of the first shift register circuit in the (n+k)th stage shift register unit; wherein k is a positive integer.

8. A driving method for a shift register unit according to any one of claims 1 to 4, characterized in that: include: The first shift register circuit outputs a cascade signal through a cascade output terminal in response to a signal at a first input signal terminal; The switch circuit connects the cascade output terminal and the second input signal terminal in response to the signal of the selection control signal terminal, and the second shift register circuit outputs the gate driving signal through the driving output terminal in response to the signal of the second input signal terminal; Alternatively, the switch circuit disconnects the cascade output terminal from the second input signal terminal in response to a signal at the selection control signal terminal.

9. A driving method for a gate driving circuit according to any one of claims 5 to 7, characterized in that: include: In one frame time, the first shift register circuit in each shift register unit responds to the signal at the first input signal terminal and outputs the cascade signal through the cascade output terminal; The switching circuit in at least one shift register unit responds to the signal at the selection control signal terminal to connect the cascade output terminal in the at least one shift register unit and the second input signal terminal in the at least one shift register unit, and the second shift register circuit in the at least one shift register unit responds to the signal at the second input signal terminal to output the gate drive signal through the driving output terminal.

10. A display panel, characterized in that: comprising a plurality of gate lines and a gate driving circuit as claimed in any one of claims 5 to 7; The driving output end of the x-th stage shift register unit in the gate driving circuit is connected to the y-th gate line among the multiple gate lines, and x and y are both positive integers.

11. A display device, characterized in that: The device comprises the display panel as claimed in claim 10.

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