Package structure and method of forming the same

Abstract

The application provides a packaging structure and a forming method thereof. In the forming method, a bridge chip assembly is formed first. The silicon through hole of the bridge chip is exposed by depositing a protective layer first and then thinning the silicon through hole. The protective layer can protect the substrate during the thinning process, so that the migration and diffusion of metal ions generated by the thinning of the silicon through hole into the substrate can be avoided, and the reliability failure problem of the packaging structure caused by the migration and diffusion of the metal ions can be avoided. Meanwhile, when the bridge chip assembly is molded, the bottom surface of the bridge chip assembly has an adhesive layer. The adhesive layer is removed after the molding, so that the bottom surface of the bridge chip assembly is higher than the bottom surface of the first molding layer. After the bottom redistribution layer is formed on the bottom surface of the first molding layer and the bottom surface of the bridge chip assembly, the thickness of the bottom redistribution layer on the bottom surface of the bridge chip assembly is greater than the thickness of the bottom redistribution layer on the bottom surface of the first molding layer, that is, the bottom of the bridge chip assembly has a thicker dielectric layer, so that the connection strength of each connection point of the bridge chip assembly is ensured, and higher stress buffering is provided for the bridge chip, and the reliability of the packaging structure is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor packaging, and in particular to a packaging structure and a forming method thereof. BACKGROUND

[0002] Advanced packaging is a new type of electronic packaging technology, which aims to integrate multiple chips or other electronic components together with higher integration, smaller size, lower power consumption and higher reliability through innovative technical means.

[0003] Wafer Level Package (WLP) is a packaging process in which most of the processes are performed on wafers. The demand for wafer level packaging not only requires smaller packaging size and height, but also must meet the requirements of simplifying the supply chain and reducing overall costs, and improving overall performance.

[0004] Fan-out wafer level packaging can be divided into die first and die last according to the process. The die first process is to place the chip first, and then make the redistribution layer (RDL). The die last process is to make the redistribution layer first, and then place the chip on the tested unit. In the advanced packaging structure of the die last process, a bridge chip (Si Bridge Die) needs to be embedded in the interposer. The bridge chip is a structure with TSV and DTC functions. However, the reliability of this advanced packaging structure needs to be improved.

[0005] Therefore, how to improve the reliability of the packaging structure with embedded bridge chip has become the focus of current research. SUMMARY

[0006] The technical problem to be solved by the present application is to provide a packaging structure and a forming method thereof, which can improve the reliability of the packaging structure.

[0007] To solve the above problems, the embodiment of the present application provides a forming method of a packaging structure, comprising: forming a bridge chip assembly, the bridge chip assembly comprising: a bridge chip, a protective layer and an adhesive layer, the bridge chip comprising a substrate and a through-substrate via, the protective layer being arranged on the bottom surface of the substrate and exposing the bottom surface of the through-substrate via, wherein the bottom surface of the through-substrate via is flush with the bottom surface of the protective layer by depositing the protective layer first and then thinning the through-substrate via, and the adhesive layer covers the bottom surface of the protective layer and the bottom surface of the through-substrate via; arranging the bridge chip assembly on the top surface of a carrier, the adhesive layer being in contact with the top surface of the carrier; plastic packaging to form a first plastic packaging layer, the first plastic packaging layer covering the side surface of the bridge chip assembly and the top surface of the carrier; forming a chip packaging assembly on the top surface of the first plastic packaging layer and the top surface of the bridge chip assembly, the bridge chip assembly being electrically connected with the chip packaging assembly; removing the carrier and the adhesive layer of the bridge chip assembly, wherein the bottom surface of the bridge chip assembly is higher than the bottom surface of the first plastic packaging layer; forming a bottom redistribution layer on the bottom surface of the first plastic packaging layer and the bottom surface of the bridge chip assembly, wherein the thickness of the bottom redistribution layer on the bottom surface of the bridge chip assembly is greater than the thickness of the bottom redistribution layer on the bottom surface of the first plastic packaging layer, and the bridge chip assembly is electrically connected with the bottom redistribution layer.

[0008] The embodiment of the present application also provides a packaging structure, comprising: a bridge chip assembly, the bridge chip assembly comprising a bridge chip and a protective layer, the bridge chip comprising a substrate and a through-substrate via, the protective layer being arranged on the bottom surface of the substrate and exposing the bottom surface of the through-substrate via, and the bottom surface of the through-substrate via being flush with the bottom surface of the protective layer; a first plastic packaging layer, the first plastic packaging layer covering the side surface of the bridge chip assembly, and the bottom surface of the bridge chip assembly being higher than the bottom surface of the first plastic packaging layer; a chip packaging assembly, arranged on the top surface of the first plastic packaging layer and the top surface of the bridge chip assembly, the bridge chip assembly being electrically connected with the chip packaging assembly; and a bottom redistribution layer, arranged on the bottom surface of the first plastic packaging layer and the bottom surface of the bridge chip assembly, wherein the thickness of the bottom redistribution layer on the bottom surface of the bridge chip assembly is greater than the thickness of the bottom redistribution layer on the bottom surface of the first plastic packaging layer, and the bridge chip assembly is electrically connected with the bottom redistribution layer.

[0009] The packaging structure and the forming method thereof provided by the embodiment of the present application, the bridge chip assembly is formed first, wherein the through silicon via of the bridge chip is exposed by depositing a protective layer first and then thinning the through silicon via, so that the protective layer can protect the substrate during the thinning process, and the migration and diffusion of metal ions (such as copper ions) generated by the thinning of the through silicon via into the substrate can be avoided, and then the reliability failure problem of the packaging structure caused by the migration and diffusion of the metal ions can be avoided; at the same time, when the bridge chip assembly is molded, the bottom surface of the bridge chip assembly has an adhesive layer, the adhesive layer is removed after the molding, so that the bottom surface of the bridge chip assembly is higher than the bottom surface of the first molding layer, and then the bottom redistribution layer is formed on the bottom surface of the bridge chip assembly and the bottom surface of the first molding layer, the thickness of the bottom redistribution layer on the bottom surface of the bridge chip assembly is greater than the thickness of the bottom redistribution layer on the bottom surface of the first molding layer, that is, the bottom of the bridge chip assembly has a thicker dielectric layer, so that the connection strength of each connection point of the bridge chip assembly is ensured, and higher stress buffering is provided for the bridge chip, and the reliability of the packaging structure is improved. BRIEF DESCRIPTION OF DRAWINGS

[0010] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor on the basis of these drawings.

[0011] Figure 1 is a step schematic diagram of the forming method of the packaging structure provided by an embodiment of the present application;

[0012] Figures 2 to 16 is a process flow chart of the forming method of the packaging structure provided by an embodiment of the present application;

[0013] Figure 17 is a semiconductor structure schematic diagram in the forming method of the packaging structure provided by an embodiment of the present application; DETAILED DESCRIPTION

[0014] The specific embodiments of the packaging structure and the forming method thereof provided by the present application will be described in detail below with reference to the drawings.

[0015] Figure 1 is a step schematic diagram of the forming method of the packaging structure provided by an embodiment of the present application, please refer to Figure 1The forming method comprises the following steps: S10, forming a bridge chip assembly, the bridge chip assembly comprises a bridge chip, a protective layer and an adhesive layer, the bridge chip comprises a substrate and a through silicon via penetrating through the substrate, the protective layer is arranged on the bottom surface of the substrate, and the bottom surface of the through silicon via is exposed, wherein the bottom surface of the through silicon via is flush with the bottom surface of the protective layer by depositing the protective layer first and then thinning the through silicon via, and the adhesive layer covers the bottom surface of the protective layer and the bottom surface of the through silicon via; S11, arranging the bridge chip assembly on the top surface of a carrier, and the adhesive layer is in contact with the top surface of the carrier; S12, plastic packaging, forming a first plastic packaging layer, the first plastic packaging layer covers the side surface of the bridge chip assembly and the top surface of the carrier; S13, forming a chip package assembly on the top surface of the first plastic packaging layer and the top surface of the bridge chip assembly, and the bridge chip assembly is electrically connected with the chip package assembly; S14, removing the carrier and the adhesive layer of the bridge chip assembly, wherein the bottom surface of the bridge chip assembly is higher than the bottom surface of the first plastic packaging layer; S15, forming a bottom redistribution layer on the bottom surface of the first plastic packaging layer and the bottom surface of the bridge chip assembly, wherein the thickness of the bottom redistribution layer located on the bottom surface of the bridge chip assembly is greater than the thickness of the bottom redistribution layer located on the bottom surface of the first plastic packaging layer, and the bridge chip assembly is electrically connected with the bottom redistribution layer.

[0016] The packaging structure and the forming method thereof provided by the embodiment of the application first form a bridge chip assembly, wherein the through silicon via of the bridge chip is exposed by depositing the protective layer first and then thinning the through silicon via, so that the protective layer can protect the substrate during the thinning process, and the migration and diffusion of metal ions (for example, copper ions) generated in the process of thinning the through silicon via into the substrate can be avoided, and the reliability failure problem of the packaging structure caused by the migration and diffusion of the metal ions can be avoided. Meanwhile, when the bridge chip assembly is plastic packaged, the bottom surface of the bridge chip assembly has the adhesive layer, the adhesive layer is removed after the plastic packaging, so that the bottom surface of the bridge chip assembly is higher than the bottom surface of the first plastic packaging layer, and after the bottom redistribution layer is formed on the bottom surface of the first plastic packaging layer and the bottom surface of the bridge chip assembly, the thickness of the bottom redistribution layer located on the bottom surface of the bridge chip assembly is greater than the thickness of the bottom redistribution layer located on the bottom surface of the first plastic packaging layer, that is, the bottom of the bridge chip assembly has a thicker dielectric layer, so that the connection strength of each connection point of the bridge chip assembly is guaranteed, and higher stress buffering is provided for the bridge chip, and the reliability of the packaging structure is improved.

[0017] Figures 2 to 16 It is a process flow chart of the forming method of the packaging structure provided by an embodiment of the application.

[0018] Please refer to Figure 1 and Figure 10, step S10, a bridge chip assembly 100 is formed, the bridge chip assembly 100 comprising: a bridge chip 110, a protective layer 120 and an adhesive layer 140, the bridge chip 110 comprising a substrate 111 and a through-silicon via 112 penetrating the substrate 111, the protective layer 120 being disposed on the bottom surface of the substrate 111 and exposing the bottom surface of the through-silicon via 112, wherein the bottom surface of the through-silicon via 112 is flush with the bottom surface of the protective layer 120 by depositing the protective layer 120 first and then thinning the through-silicon via 112, and the adhesive layer 140 covering the bottom surface of the protective layer 120 and the bottom surface of the through-silicon via 112.

[0019] In the bridge chip assembly 100 provided by the embodiment of the present application, the bottom surface of the through-silicon via 112 is flush with the bottom surface of the protective layer 120, and when the bridge chip assembly 100 is manufactured, the protective layer 120 is deposited first and then the bottom surface of the through-silicon via 112 is ground, so that the protective layer 120 can protect the substrate 111 during the grinding process, and the migration and diffusion of metal ions (for example, copper ions) generated by grinding the through-silicon via 112 into the substrate 111 can be avoided, thereby avoiding the reliability failure problem of the packaging structure caused by the migration and diffusion of metal ions.

[0020] In an embodiment, the substrate 111 is a silicon substrate, the through-silicon via 112 is a copper pillar, and the protective layer 120 is a single-layer structure or a composite layer structure, and the material thereof includes but is not limited to silicon nitride, silicon dioxide or silicon nitride dioxide. In an embodiment, the through-silicon via 112 is further provided with a passivation layer 113 (indicated in Figure 2 ), which is used to isolate the through-silicon via 112 from the substrate 111 to avoid the diffusion of metal ions in the through-silicon via 112 into the substrate 111.

[0021] In an embodiment, the bridge chip assembly 100 further comprises a bottom solder pad 130, which is disposed on the bottom surface of the through-silicon via 112 and is electrically connected with the through-silicon via 112. In an embodiment, the bottom solder pad 130 is a micro solder pad (μPad). The disposition of the bottom solder pad 130 on the bottom surface of the through-silicon via 112 can reduce the thickness of the first plastic encapsulation layer 401 (refer to Figure 12 ) covering the bridge chip assembly 100 in the packaging structure using the bridge chip assembly 100, thereby reducing the warping of this part of the structure and being more conducive to production and yield. In this embodiment, the cross-sectional area of the bottom solder pad 130 is greater than the cross-sectional area of the through-silicon via 112, so as to ensure that the through-silicon via 112 can be in full contact with the bottom solder pad 130, reduce the contact resistance, and thereby make the delay of the electrical signal smaller.

[0022] The embodiment of the present application also provides a method for forming the bridge chip assembly 100, and particularly, the steps for forming the bridge chip assembly 100 include:

[0023] Referring to Figure 2 , a device wafer is provided, which includes a bridge chip 110, the bridge chip 110 includes an initial substrate 300, an initial through silicon via 310 extending from a top surface of the initial substrate 300 to an interior of the initial substrate 300, and a side surface and a bottom surface of the initial through silicon via 310 are covered with a passivation layer 113. The passivation layer 113 includes, but is not limited to, silicon oxide, silicon nitride, and a combination thereof.

[0024] In some embodiments, the bridge chip 110 further includes a deep trench capacitor 180, and the deep trench capacitor 180 is disposed in the initial substrate 300. In some embodiments, the deep trench capacitor 180 extends from a top surface of the initial substrate 300 to an interior of the initial substrate 300. In an embodiment, the device wafer further includes an internal redistribution layer 160 disposed on the top surface of the initial substrate 300 and a conductive pillar 170 disposed on a top surface of the internal redistribution layer 160, and the deep trench capacitor 180 is electrically connected to the internal redistribution layer 160.

[0025] In some embodiments, the step of providing the device wafer specifically includes: providing an initial wafer, which includes an initial substrate 300, an initial through silicon via 310 extending from a top surface of the initial substrate 300 to an interior of the initial substrate 300, and a deep trench capacitor 180; forming an internal redistribution layer 160 on the top surface of the initial substrate 300 and a conductive pillar 170 disposed on a top surface of the internal redistribution layer 160, the internal redistribution layer 160 is electrically connected to a top surface of the initial through silicon via 310, and the conductive pillar 170 is electrically connected to the internal redistribution layer 160. The internal redistribution layer 160 includes a dielectric layer and a conductive circuit in the dielectric layer, one side of the conductive circuit is electrically connected to the top surface of the initial through silicon via 310, and the other side of the conductive circuit is electrically connected to the conductive pillar 170. The initial through silicon via 310 includes, but is not limited to, a copper pillar, the conductive pillar 170 includes, but is not limited to, a copper pillar, and the dielectric layer includes, but is not limited to, a silicon dioxide layer or a silicon nitride layer. The initial substrate 300 includes, but is not limited to, a silicon substrate. In some embodiments, the top surfaces of the initial through silicon via 310 and the deep trench capacitor 180 are flush with the top surface of the initial substrate 300.

[0026] Optionally, in some embodiments, in order to support the device wafer in subsequent steps of processing the bottom surface of the device wafer (e.g. thinning the initial substrate 300), the step of providing the device wafer further comprises: Figure 3 bonding the support substrate 320 to the front surface of the device wafer. The support substrate 320 includes, but is not limited to, a glass substrate. Further, the step of bonding the support substrate 320 to the front surface of the device wafer includes bonding the support substrate 320 to the side of the device wafer having the conductive pillars 170. Specifically, the step includes forming a capping layer 330 on the front surface of the device wafer, the capping layer 330 covering the conductive pillars 170 and covering the surface of the internal redistribution layer 160; and bonding the support substrate 320 to the device wafer with the surface of the support substrate 320 and the surface of the capping layer 330 as the bonding surfaces.

[0027] Referring to Figure 4 and Figure 5 , removing part of the initial substrate 300 from the bottom surface of the initial substrate 300 to form the substrate 111, the initial through-silicon via 310 protruding from the bottom surface of the substrate 111.

[0028] In some embodiments, the step can include the following two steps:

[0029] Referring to Figure 4 , removing part of the initial substrate 300 from the bottom surface of the initial substrate 300 to a set distance from the passivation layer 113 at the bottom surface of the initial through-silicon via 310. Specifically, the initial substrate 300 is thinned and planarized from the bottom surface of the initial substrate 300 to near the initial through-silicon via 310, the initial through-silicon via 310 being covered by the passivation layer 113, the passivation layer 113 being covered by the initial substrate 300, and the initial through-silicon via 310 still not exposed, which can avoid the initial through-silicon via 310 from exposing copper ions to contaminate the substrate 111. During the thinning process, the support substrate 320 supports the device wafer. As shown in Figure 4 , at this step, the support substrate 320 is facing downwards, and the device wafer is above the support substrate 320.

[0030] Referring to Figure 5 , continuing to remove part of the initial substrate 300 from the bottom surface of the initial substrate 300 to form the substrate 111, the initial through-silicon via 310 protruding from the bottom surface of the substrate 111. As shown in Figure 5As shown, during this step, the support substrate 320 faces downwards, and the device wafer is positioned above the support substrate 320. In this step, the initial through-silicon via (TSV) 310 is not removed, causing the TSV 310 to protrude from the bottom surface of the substrate 111. In some embodiments, a dry etching process can be used to remove part of the initial substrate 300. The dry etching material can etch the initial substrate 300 without etching the passivation layer 113 on the surface of the initial TSV 310, thereby preventing copper ion contamination of the substrate 111 and the cavity for subsequent processes.

[0031] Please see Figure 6 A protective layer 120 is formed on the bottom surface of the substrate 111. In this embodiment, the protective layer 120 also covers the surface of the passivation layer 113. In this step, the protective layer 120 can be formed using processes such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), and low-pressure chemical vapor deposition (LPCVD). The protective layer 120 can be a single-layer structure or a composite layer structure, and its material includes, but is not limited to, silicon nitride, silicon dioxide, or nitrogen-silicon dioxide. In other embodiments, the protective layer 120 may only cover the bottom surface of the substrate 110.

[0032] Please see Figure 7 The passivation layer 113 and the initial through-silicon via (TSV) 310 are thinned from the bottom surface to form a TSV 112, thereby making the bottom surface of the TSV 112 flush with the bottom surface of the protective layer 120. The side surface of the TSV 112 is covered by the passivation layer 113. In this step, when thinning the initial TSV 310, the passivation layer 113 on the bottom surface of the initial TSV 310 is thinned first. When the initial TSV 310 is further thinned, the passivation layer 113 on the side surface of the initial TSV 310 is also removed simultaneously. In this step, the initial TSV 310 can be polished using a chemical mechanical polishing process until the formed TSV 112 meets the preset height requirements. In some embodiments, the bottom surface of the protective layer 120 is also polished to provide a flat surface for subsequent processes. In this step, when grinding the initial through-silicon via 310, the surface of the substrate 111 is covered by the protective layer 120. The metal ions generated during grinding cannot diffuse into the substrate 111, thereby avoiding reliability failures caused by the migration and diffusion of metal ions in the packaging structure.

[0033] In some embodiments, after the step of thinning the passivation layer 113 and the initial through-silicon via 310 from the bottom surface of the initial through-silicon via 310 to form the through-silicon via 112, the method further includes: Please refer to Figure 8A bottom pad 130 is formed, which is disposed on the bottom surface of the through-silicon via 112 and electrically connected to the through-silicon via 112. The bottom pad 130 serves as a structure for external connection of the through-silicon via 112. In one embodiment, the bottom pad 130 is a micropad (μPad). The bottom pad 130 can be formed by photolithography and electroplating processes.

[0034] In some embodiments, the step of forming the bottom pad 130 further includes: forming a seed layer 150 on the bottom surface of the protective layer 120 and the bottom surface of the through-silicon via 112; and forming the bottom pad 130 on the seed layer 150 on the bottom surface of the through-silicon via 112 using an electroplating process. The seed layer 150 may be a copper layer, a titanium layer, or a multilayer metal layer. In one embodiment, such as... Figure 8 As shown, the formation method further includes: removing the seed layer 150 not covered by the bottom pad 130, retaining only the seed layer 150 located in the area of ​​the bottom pad 130. In other embodiments, please refer to... Figure 17 Alternatively, the seed layer 150 may not be removed after the bottom pad 130 is formed, but may be removed during subsequent processes.

[0035] Please see Figure 9 An adhesion layer 140 is formed, which covers the bottom surface of the protective layer 120 and the bottom surface of the bottom pad 130. Specifically, in this step, an adhesion layer 140 is formed on the bottom surface of the protective layer 120 and the bottom surface of the bottom pad 130. The bridging chip assembly 100 is fixed to the wafer ring 350 by the adhesion layer 140. In some embodiments, the bottom surface of the device wafer is fixed to the wafer ring 350 by the adhesion layer 140, with the support substrate 320 facing upward. The adhesion layer 140 is made of a material with a certain degree of adhesion, such as acrylic resin. In some embodiments, the adhesion layer 140 is a die attachment film (DAF), which has excellent thermal conductivity and adhesion. In some embodiments, such as Figure 17 After the bottom pad 130 is formed, the seed layer 150 is not removed, and the adhesion layer 140 covers the bottom surface of the seed layer 150 and the bottom surface of the bottom pad 130.

[0036] In some embodiments, the step of forming the adhesion layer 140 is followed by: See [link to relevant documentation] Figure 10, the support substrate 320 is debonded, and the device wafer is singulated to form the bridge chip assembly 100. In this step, after the support substrate 320 is debonded, the cover layer 330 on the front side of the device wafer is also removed, and the conductive pillars 170 are exposed. In some embodiments, a suitable debonding process can be selected according to the properties of the temporary bonding glue, such as laser debonding, thermal debonding, etc. The device wafer is singulated to form a plurality of independent bridge chip assemblies 100.

[0037] The above is one embodiment of forming a bridge chip assembly 100.

[0038] Referring to Figure 1 and Figure 11 , in step S11, the bridge chip assembly 100 is arranged on the top surface of a carrier board 600, and the adhesive layer 140 is in contact with the top surface of the carrier board 600.

[0039] In some embodiments, the carrier board 600 is a glass substrate, and the surface thereof has a temporary bonding layer 601 and a buffer metal layer 602. The bridge chip assembly 100 is arranged on the buffer metal layer 602 by a die attach (DA) process. In some embodiments, this step also arranges metal pillars 402 on the surface of the carrier board 600.

[0040] Referring to Figure 1 and Figure 12 , in step S12, plastic packaging is performed to form a first plastic packaging layer 401 covering the side surface of the bridge chip assembly 100 and the top surface of the carrier board 600. Specifically, this step further includes: coating the bridge chip assembly 100, the metal pillars 402, and the surface of the buffer metal layer 602 covering the carrier board 600 with plastic packaging material; initially thinning the plastic packaging material to expose the metal pillars 402 and the conductive pillars 170 on the top surface of the bridge chip assembly 100; etching the metal pillars 402 and the conductive pillars 170 on the top surface of the bridge chip assembly 100 to a predetermined height; continuing to thin the plastic packaging material to form the first plastic packaging layer 401, the top surface of the first plastic packaging layer 401 being flush with the top surfaces of the metal pillars 402 and the conductive pillars 170, and the top surfaces of the metal pillars 402 and the conductive pillars 170 not being covered by the first plastic packaging layer 401. After initially thinning the plastic packaging material, etching the metal pillars 402 and the conductive pillars 170 can form a predetermined height, and on the other hand, can remove the oxide layer on the surfaces of the metal pillars 402 and the conductive pillars 170 to expose the substrate, thereby reducing the contact resistance between the metal pillars 402 and the conductive pillars 170 and other device layers (such as the top redistribution layer 430).

[0041] Referring to Figure 1 andFigure 13 In step S13, a chip package assembly 400 is formed on the top surface of the first encapsulation layer 401 and the top surface of the bridge chip assembly 100, and the bridge chip assembly 100 is electrically connected to the chip package assembly 400.

[0042] In an embodiment, the chip package assembly 400 includes a top redistribution layer 430, a top solder pad 440, and a top device 450. The step of forming the chip package assembly 400 on the top surface of the first encapsulation layer 401 and the top surface of the bridge chip assembly 100 includes:

[0043] The top redistribution layer 430 is formed on the top surface of the first encapsulation layer 401 and the top surface of the bridge chip assembly 100. The top redistribution layer 430 includes a dielectric layer 431 and plated conductive lines 432 in the dielectric layer 431, and the plated conductive lines 432 are in contact with the conductive pillars 170 of the bridge chip assembly 100. In an embodiment, the top redistribution layer 430 is formed by a photolithography process and a plating process. For example, the top redistribution layer 430 is formed by coating, exposure, development, plating, and stripping.

[0044] The top solder pad 440 is formed on the top surface of the top redistribution layer 430 and is electrically connected to the top redistribution layer 430.

[0045] The top device 450 is disposed on the top redistribution layer 430 and is soldered to the top solder pad 440. In some embodiments, the top device 450 is flip-chip mounted on the top redistribution layer 430. The top device 450 is soldered to the top solder pad 440 by conductive bumps.

[0046] The top device 450 is encapsulated to form a second encapsulation layer 470, and the second encapsulation layer 470 covers the top device 450. In some embodiments, before encapsulating the top device 450, a filling layer 460 is formed by filling between the bottom of the top device 450 and the top redistribution layer 430, and the second encapsulation layer 470 also covers the filling layer 460.

[0047] Please refer to Figure 1 and Figure 14 In step S14, the adhesive layer 140 of the carrier board 600 and the bridge chip assembly 100 is removed, and the bottom surface of the bridge chip assembly 100 is higher than the bottom surface of the first encapsulation layer 401. The bottom surface of the first encapsulation layer 401, the bottom surface of the metal column 402, and the bottom surface of the bridge chip 110 are also exposed.

[0048] In this step, according to the temporary bonding glue characteristics, a suitable debonding process is selected, such as laser debonding, thermal debonding, etc. to remove the carrier plate 600. After removing the carrier plate 600, the buffer metal layer 602 on the surface of the substrate is also removed by etching. In this step, according to the material characteristics and molecular system of the adhesive layer 140, a suitable etching process is selected to remove the adhesive layer 140, and the bottom pads 130 on the back of the bridge chip 110 are exposed.

[0049] Optionally, in some embodiments, the bridge chip assembly 100 further comprises a seed layer 150, which covers the bottom surface of the protective layer 120 and the bottom surface of the through silicon via 112 of the bridge chip assembly 100. The bottom pads 130 are arranged on the seed layer 150, and the adhesive layer 140 also covers the bottom surface of the seed layer 150 (see Figure 17 After the step of removing the adhesive layer 140, the seed layer 150 outside the area of the bottom pads 130 is also removed, so that the residual adhesive layer 140 can be completely removed, and the reliability of the packaging structure is improved.

[0050] Optionally, after removing the carrier plate 600, the adhesive layer 140 or the seed layer 150, a cleaning process is further included to remove the residues.

[0051] Optionally, in the step of removing the adhesive layer 140 and the seed layer 150, if a dry etching process is used, the bottom surface of the first plastic package layer 401 will be too rough. Therefore, the forming method further comprises polishing the bottom surface of the first plastic package layer 401 to form a surface with a required roughness.

[0052] Please refer to Figure 1 and Figure 15 , in step S15, a bottom redistribution layer 410 is formed on the bottom surface of the first plastic package layer 401 and the bottom surface of the bridge chip assembly 100. The thickness of the bottom redistribution layer 410 on the bottom surface of the bridge chip assembly 100 is greater than the thickness of the bottom redistribution layer 410 on the bottom surface of the first plastic package layer 401. The bridge chip assembly 100 is electrically connected to the bottom redistribution layer 410. The through silicon via 112 of the bridge chip 110 is electrically connected to the bottom redistribution layer 410.

[0053] In this step, the thickness of the bottom redistribution layer 410 on the bottom surface of the bridge chip assembly 100 is greater than the thickness of the bottom redistribution layer 410 on the bottom surface of the first plastic package layer 401. The bottom of the bridge chip assembly 100 has a thicker dielectric layer, so that the connection strength of each connection point of the bridge chip assembly 100 is guaranteed, and higher stress buffering is provided for the bridge chip 110, thereby improving the reliability of the packaging structure.

[0054] In some embodiments, the step of forming a bottom redistribution layer 410 on the bottom surface of the first encapsulation layer 401 and the bottom surface of the bridge chip assembly 100 further comprises:

[0055] forming a dielectric layer 411 on the bottom surface of the first encapsulation layer 401 and the bottom surface of the bridge chip assembly 100.

[0056] forming a via on the dielectric layer 411 to expose the bottom solder pad 130 on the bottom surface of the bridge chip 110. In some embodiments, if the distance between the surface of the bottom solder pad 130 and the bottom surface of the first encapsulation layer 401 is too far, the via formed by the one-time exposure process may not be able to completely expose the bottom solder pad 130. In this case, a two-time exposure process can be used to form a via on the dielectric layer 411 to expose the bottom solder pad 130 on the bottom surface of the bridge chip 110, so that the via can completely expose the bottom solder pad 130. In some embodiments, if the bottom surface of the through silicon via 112 is not provided with the bottom solder pad 130, then whether to use the one-time exposure process or the two-time exposure process to form a via on the dielectric layer 411 to expose the bottom surface of the through silicon via 112 is determined according to the distance between the bottom surface of the through silicon via 112 and the bottom surface of the first encapsulation layer 401.

[0057] sputtering and / or electroplating to form an electroplated bump 412 in the via, wherein the electroplated bump 412 is in contact with the bottom solder pad 130 of the bridge chip 110. In this step, the electroplated bump 412 is formed by sputtering and electroplating, without using tin (Sn) soldering. This eliminates the aging problem of tin soldering in the process, eliminates the problem of voids and cracks in the soldering points, improves the reliability of the packaging structure, and combines the efficiency and cost of sputtering and electroplating.

[0058] Optionally, after the step of forming a bottom redistribution layer 410 on the bottom surface of the first encapsulation layer 401 and the bottom surface of the bridge chip assembly 100, the method further comprises: Figure 16 forming a conductive connection structure 630 on the bottom surface of the bottom redistribution layer 410. In some embodiments, the conductive connection structure 630 is formed on the bottom surface of the bottom redistribution layer 410. The conductive connection structure 630 is electrically connected to the bottom redistribution layer 410. In some embodiments, the conductive connection structure 630 includes, but is not limited to, a controllable collapse chip connection bump (C4).

[0059] Optionally, after or before forming the conductive connection structure 630, the second plastic encapsulation layer 470 is thinned to expose the top surface of the top device 450 for heat dissipation. Optionally, after forming the conductive connection structure 630, singulation is performed to form a plurality of independent packaging structures, each of which can include a plurality of bridge chip assemblies 100 and a plurality of top devices 450.

[0060] The forming method of the packaging structure provided by the embodiment of the present application first forms a bridge chip assembly. The silicon through hole of the bridge chip is exposed by first depositing a protective layer and then thinning the silicon through hole. The protective layer can protect the substrate during the thinning process, so that the migration and diffusion of metal ions (such as copper ions) generated by the thinning of the silicon through hole into the substrate can be avoided, and the reliability failure problem of the packaging structure caused by the migration and diffusion of the metal ions can be avoided. At the same time, when the bridge chip assembly is plastic encapsulated, the bottom surface of the bridge chip assembly has an adhesive layer. After the plastic encapsulation, the adhesive layer is removed, so that the bottom surface of the bridge chip assembly is higher than the bottom surface of the first plastic encapsulation layer. After the bottom redistribution layer is formed on the bottom surface of the first plastic encapsulation layer and the bottom surface of the bridge chip assembly, the thickness of the bottom redistribution layer located on the bottom surface of the bridge chip assembly is greater than the thickness of the bottom redistribution layer located on the bottom surface of the first plastic encapsulation layer. That is, the bottom of the bridge chip assembly has a thicker dielectric layer, so that the connection strength of each connection point of the bridge chip assembly is guaranteed, and higher stress buffering is provided for the bridge chip, thereby improving the reliability of the packaging structure.

[0061] Based on the same inventive concept, the embodiment of the present application also provides a packaging structure formed by the above forming method. As shown in Figures 2 to 16 The packaging structure includes: a bridge chip assembly 100, the bridge chip assembly 100 includes a bridge chip 110 and a protective layer 120, the bridge chip 110 includes a substrate 111 and a silicon through hole 112 penetrating through the substrate 111; the protective layer 120 is arranged on the bottom surface of the substrate 111 and exposes the bottom surface of the silicon through hole 112, wherein the bottom surface of the silicon through hole 112 is flush with the bottom surface of the protective layer 120; a first plastic encapsulation layer 401 covering the side surface of the bridge chip assembly 100, and the bottom surface of the bridge chip assembly 100 is higher than the bottom surface of the first plastic encapsulation layer 401; a chip packaging assembly 400 arranged on the top surface of the first plastic encapsulation layer 401 and the top surface of the bridge chip assembly 100, the bridge chip assembly 100 and the chip packaging assembly 400 are electrically connected; a bottom redistribution layer 410 arranged on the bottom surface of the first plastic encapsulation layer 401 and the bottom surface of the bridge chip assembly 100, wherein the thickness of the bottom redistribution layer 410 located on the bottom surface of the bridge chip assembly 100 is greater than the thickness of the bottom redistribution layer 410 located on the bottom surface of the first plastic encapsulation layer 401, and the bridge chip assembly 100 and the bottom redistribution layer 410 are electrically connected.

[0062] In the packaging structure provided by the embodiment of the present application, the bottom surface of the through silicon via 112 is flush with the bottom surface of the protective layer 120. In the manufacturing of the bridge chip assembly 100, the protective layer 120 is formed first, and then the bottom surface of the through silicon via 112 is polished. During the polishing process, the protective layer 120 can protect the substrate 111, so that the migration and diffusion of metal ions (e.g. copper ions) generated in the polishing of the through silicon via 112 into the substrate 111 can be avoided, thereby avoiding the reliability failure problem of the packaging structure caused by the migration and diffusion of metal ions. Moreover, the thickness of the bottom redistribution layer located at the bottom surface of the bridge chip assembly is greater than the thickness of the bottom redistribution layer located at the bottom surface of the first plastic encapsulation layer, i.e. the bridge chip assembly has a thicker dielectric layer at the bottom, so that the connection strength of each connection point of the bridge chip assembly is ensured, and the bridge chip is provided with higher stress buffering, thereby improving the reliability of the packaging structure.

[0063] In an embodiment, the substrate 111 is a silicon substrate, the through silicon via 112 is a copper pillar, and the protective layer 120 is a single-layer structure or a composite layer structure, and the material thereof includes but is not limited to silicon nitride, silicon dioxide or silicon nitride dioxide.

[0064] In an embodiment, the bridge chip assembly 100 further comprises a bottom solder pad 130, which is arranged at the bottom surface of the through silicon via 112 and is electrically connected with the through silicon via 112. The bottom redistribution layer 410 is electrically connected with the bottom solder pad 130, i.e. the through silicon via 112 is electrically connected with the bottom redistribution layer 410 through the bottom solder pad 130. In an embodiment, the bottom solder pad 130 is a micro solder pad (μPad). The arrangement of the bottom solder pad 130 at the bottom surface of the through silicon via 112 can reduce the thickness of the first plastic encapsulation layer 401 covering the bridge chip assembly 100 in the packaging structure using the bridge chip assembly 100, thereby reducing the warping of this part of the structure, which is more conducive to production and yield. In this embodiment, the cross-sectional area of the bottom solder pad 130 is greater than the cross-sectional area of the through silicon via 112, so as to ensure that the through silicon via 112 can be in full contact with the bottom solder pad 130, reduce the contact resistance, and thereby make the delay of electrical signals smaller.

[0065] In an embodiment, the bridge chip assembly 100 further comprises a seed layer 150 arranged between the bottom solder pad 130 and the bottom surface of the through silicon via 112, and the bottom solder pad 130 is formed by electroplating on the surface of the seed layer 150. The seed layer 150 can be a copper layer or a titanium layer or a multi-layer metal layer. As shown in FIG. 1, the seed layer 150 is arranged between the bottom solder pad 130 and the bottom surface of the through silicon via 112, and the bottom solder pad 130 is formed by electroplating on the surface of the seed layer 150. The seed layer 150 can be a copper layer or a titanium layer or a multi-layer metal layer. Figure 8As shown, the seed layer 150 is located in the area corresponding to the bottom pad 130, and the bottom pad 130 is disposed on the seed layer 150, i.e. the seed layer 150 is not disposed in other areas of the protective layer 120.

[0066] In an embodiment, the through-silicon via 112 is further provided with a passivation layer 113, which is used to isolate the through-silicon via 112 from the substrate 111 to avoid diffusion of metal ions in the through-silicon via into the substrate 111.

[0067] In an embodiment, the bridge chip assembly 100 further includes an internal redistribution layer 160 and a conductive pillar 170. The internal redistribution layer 160 is disposed on the top surface of the substrate 111 and is electrically connected to the top surface of the through-silicon via 112. The conductive pillar 170 is disposed on the top surface of the internal redistribution layer 160 and is electrically connected to the internal redistribution layer 160. The chip package assembly 400 is electrically connected to the conductive pillar 170. The internal redistribution layer 160 includes a dielectric layer and a conductive circuit in the dielectric layer, one side of the conductive circuit being electrically connected to the top surface of the through-silicon via 112 and the other side being electrically connected to the conductive pillar 170. The conductive pillar 170 includes but is not limited to a copper pillar, and the dielectric layer can be a silicon dioxide layer or a silicon nitride layer, etc.

[0068] In an embodiment, the bridge chip 110 further includes a deep trench capacitor (DTC) 180 disposed in the substrate 111. In some embodiments, the deep trench capacitor 180 extends from the top surface of the substrate 111 to the inside of the substrate 111, and the deep trench capacitor 180 is electrically connected to the internal redistribution layer 160.

[0069] In an embodiment, the bottom surface of the through-silicon via 112 is electrically connected to other structural layers (such as a bottom redistribution layer 410) through the bottom pad 130, which reduces the thickness of the first plastic encapsulation layer 401 covering the bridge chip assembly 100, thereby reducing the warpage of this part of the structure, which is more conducive to production and yield.

[0070] In some embodiments, the first plastic encapsulation layer 401 covers the side surface of the bridge chip assembly 100, the surface of the internal redistribution layer 160, and the side surface of the conductive pillar 170.

[0071] In some embodiments, the package structure further comprises a metal pillar 402 penetrating through the first molding layer 401, and the bottom surface of the metal pillar 402 is flush with the bottom surface of the first molding layer 401. In an embodiment, the top surface of the metal pillar 402 is flush with the top surface of the conductive pillar 170. The metal pillar 402 and the conductive pillar 170 can be made of the same material, for example, both are made of copper. The package structure can comprise a plurality of the bridge chip assembly 100 and a plurality of the metal pillar 402 distributed around the bridge chip assembly 100 and between two adjacent bridge chip assemblies 100.

[0072] In some embodiments, the bottom redistribution layer 410 further covers the bottom surface of the metal pillar 402, and the metal pillar 402 is electrically connected to the bottom redistribution layer 410. The thickness of the bottom redistribution layer 410 in the region of the metal pillar 402 is the same as the thickness of the bottom redistribution layer 410 in the region of the first molding layer 401.

[0073] In some embodiments, the bottom redistribution layer 410 comprises a dielectric layer 411 and a plated bump 412 in the dielectric layer 411, and the plated bump 412 is in contact with the bottom pad 130 of the bridge chip 110. The material of the dielectric layer 411 can be a high polymer material such as polystyrene butyl (PBO) or polyimide (PI) to further relieve stress. The plated bump 412 refers to a bump formed by an electroplating process. In an embodiment, the plated bump 412 is formed on the surface of the bottom pad 130 by an electroplating process, without using tin (Sn) soldering. This eliminates the aging problem in the soldering process and eliminates the problem of voids and cracks in the soldering points, thereby improving the reliability of the package structure.

[0074] In some embodiments, the chip package assembly 400 comprises a top redistribution layer 430, a top pad 440, a top device 450, and a second molding layer 470.

[0075] The top redistribution layer 430 is disposed on the top surface of the first molding layer 401 and the top surface of the bridge chip assembly 100. The top redistribution layer 430 includes a dielectric layer 431 and plated conductive lines 432 in the dielectric layer 431. The plated conductive lines 432 are in contact with the conductive pillars 170 of the bridge chip assembly 100. In some embodiments, the top surface of the metal pillars 402 is in contact with the plated conductive lines 432. In some embodiments, the material of the dielectric layer 431 can be a high molecular material such as polystyrene butyl (PBO), polyimide (PI), etc. The plated conductive lines 432 are conductive lines formed by electroplating process. In an embodiment, the plated conductive lines 432 are formed on the surfaces of the through silicon vias 112 and the metal pillars 402 by electroplating process, without using tin (Sn) soldering. The electroplating process eliminates the aging problem in the soldering process, and eliminates the problems of void and crack in the soldering points, thereby improving the reliability of the packaging structure.

[0076] The top solder pad 440 is disposed on the top surface of the top redistribution layer 430 and is electrically connected to the top redistribution layer 430. In an embodiment, the top solder pad 440 is a micro solder pad (μPad).

[0077] The top device 450 is disposed on the top redistribution layer 430 and is soldered to the top solder pad 440. The top device 450 can be flip-chip disposed on the top redistribution layer 430 and soldered to the top solder pad 440. The top device 450 can be a SOC device, etc.

[0078] The second molding layer 470 covers the top device 450. In some embodiments, the packaging structure further includes a filling layer 460 filled between the bottom of the top device 450 and the top redistribution layer 430. The filling layer 460 is used to protect the conductive structure of the top device 450 and the top solder pad 440. The second molding layer 470 covers the top device 450, the surface of the top redistribution layer 430, and the surface of the filling layer 460.

[0079] Optionally, the packaging structure further includes a conductive connection structure 630 disposed on the bottom surface of the bottom redistribution layer 410. In some embodiments, the conductive connection structure 630 includes, but is not limited to, a controllable collapse chip connection bump (C4).

[0080] The packaging structure provided by the embodiment of the present application avoids the migration and diffusion of metal ions (for example, copper ions) generated by grinding the through silicon via 112 into the substrate by arranging the protective layer 120, thereby improving the reliability of the packaging structure. In the packaging structure provided by the embodiment of the present application, the bridge chip adopts a normal mounting mode, the thickness of the chip is thinner, the thickness of the first plastic encapsulation layer is thinner, the length of the through silicon via and the metal column is shorter, the electrical signal delay is smaller, and the limitation on the size and aspect ratio of the bridge chip is smaller. At the same time, the thickness of the bottom redistribution layer located at the bottom surface of the bridge chip assembly is greater than the thickness of the bottom redistribution layer located at the bottom surface of the first plastic encapsulation layer, that is, the bridge chip assembly has a thicker dielectric layer at the bottom, so that the connection strength of each connection point of the bridge chip assembly is guaranteed, and higher stress buffering is provided for the bridge chip, thereby improving the reliability of the packaging structure.

[0081] It should be noted that the terms "comprising" and "having" and their conjugates involved in the present application are intended to cover the non-exclusive inclusion. The terms "first", "second" and the like are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence, unless the context clearly indicates otherwise, and it should be understood that the data thus used can be interchanged under appropriate circumstances. The term "one or more" depends at least partially on the context, and can be used to describe a feature, structure or characteristic in singular sense, or can be used to describe a combination of features, structures or characteristics in plural sense. The term "based on" can be understood as not necessarily expressing a set of exclusive factors, but can instead, depending at least partially on the context, allow the presence of other factors not necessarily explicitly described. In addition, the embodiments in the present application and the features in the embodiments can be combined with each other without conflict. Furthermore, in the above description, the description of well-known components and technologies is omitted to avoid unnecessary confusion of the concept of the present application. In each of the above embodiments, each embodiment focuses on the difference from other embodiments, and the same / similar parts between the embodiments can be referred to each other.

[0082] The above only describes the preferred embodiments of the present application, and it should be noted that those skilled in the art can make several improvements and refinements without departing from the principles of the present application, and these improvements and refinements should be considered as the protection scope of the present application.

Claims

1. A method for forming a package structure, the method comprising: The method comprises the following steps: forming a bridge chip assembly, the bridge chip assembly comprising a bridge chip, a protection layer and an adhesive layer, the bridge chip comprising a substrate and a through-silicon via penetrating through the substrate, the protection layer being arranged on the bottom surface of the substrate and exposing the bottom surface of the through-silicon via, wherein the bottom surface of the through-silicon via is flush with the bottom surface of the protection layer by depositing the protection layer first and then thinning the through-silicon via, and the adhesive layer covers the bottom surface of the protection layer and the bottom surface of the through-silicon via; forming the bridge chip assembly comprises the following steps: providing the bridge chip, the bridge chip comprising an initial substrate, an initial through-silicon via extending from the top surface of the initial substrate to the interior of the initial substrate, and the side surface and the bottom surface of the initial through-silicon via being covered with a passivation layer; removing part of the initial substrate from the bottom surface of the initial substrate to form the substrate, and the initial through-silicon via protruding from the bottom surface of the substrate; forming the protection layer on the bottom surface of the substrate; thinning the passivation layer and the initial through-silicon via from the bottom surface of the initial through-silicon via to form the through-silicon via, so that the bottom surface of the through-silicon via is flush with the bottom surface of the protection layer, and the side surface of the through-silicon via is covered with the passivation layer; and forming the adhesive layer; arranging the bridge chip assembly on the top surface of a carrier, and the adhesive layer being in contact with the top surface of the carrier; forming a first plastic encapsulation layer, the first plastic encapsulation layer covering the side surface of the bridge chip assembly and the top surface of the carrier; forming a chip package assembly on the top surface of the first plastic encapsulation layer and the top surface of the bridge chip assembly, and the bridge chip assembly being electrically connected to the chip package assembly; removing the carrier and the adhesive layer of the bridge chip assembly, wherein the bottom surface of the bridge chip assembly is higher than the bottom surface of the first plastic encapsulation layer; 2. The method of claim 1, wherein forming a bottom redistribution layer on the bottom surface of the first plastic encapsulation layer and the bottom surface of the bridge chip assembly, wherein the thickness of the bottom redistribution layer on the bottom surface of the bridge chip assembly is greater than the thickness of the bottom redistribution layer on the bottom surface of the first plastic encapsulation layer, and the bridge chip assembly is electrically connected to the bottom redistribution layer.

3. The method of claim 2, wherein The step of providing the bridge chip comprises the following step: providing a device wafer, the device wafer comprising the bridge chip. After the step of thinning the passivation layer and the initial through-silicon via from the bottom surface of the initial through-silicon via to form the through-silicon via, the method further comprises the following steps: forming a bottom solder pad arranged on the bottom surface of the through-silicon via and electrically connected to the through-silicon via; in the step of forming the adhesive layer, the adhesive layer covers the surface of the bottom solder pad and the bottom surface of the protection layer; 4. The method of claim 3, wherein in the step of forming the bottom redistribution layer on the bottom surface of the first plastic encapsulation layer and the bottom surface of the bridge chip assembly, the through-silicon via is electrically connected to the bottom redistribution layer through the bottom solder pad.

5. The method of claim 4, wherein The step of forming the bottom solder pad further comprises the following steps: forming a seed layer on the bottom surface of the protection layer and the bottom surface of the through-silicon via; and forming the bottom solder pad on the seed layer on the bottom surface of the through-silicon via by using an electroplating process. After the step of forming the bottom solder pad, the method further comprises the following step: removing the seed layer not covered by the bottom solder pad.

6. The method of claim 4, wherein The step of forming the adhesion layer, the adhesion layer covers the bottom pad surface and the seed layer bottom surface; The step of removing the adhesion layer further comprises: removing the seed layer.

7. The method of claim 2, wherein The step of providing the device wafer further comprises: bonding a support substrate to the front surface of the device wafer; and the step of forming the adhesion layer further comprises: debonding the support substrate and singulating the device wafer to form the bridge chip assembly.

8. The method of claim 7, wherein The step of providing the device wafer further comprises: forming an internal redistribution layer on the top surface of the initial substrate, the internal redistribution layer being electrically connected to the top surface of the initial through-silicon via, and forming a conductive pillar on the top surface of the internal redistribution layer and electrically connected to the internal redistribution layer; The step of bonding a support substrate to the front surface of the device wafer comprises: bonding a support substrate to the side of the device wafer having the conductive pillar.

9. The method of claim 1, wherein The step of arranging the bridge chip assembly on the top surface of a carrier further comprises: arranging a metal pillar on the top surface of the carrier; and the first encapsulation layer further encapsulates the side surface of the metal pillar during the step of encapsulating.

10. The method of claim 1, wherein The step of forming a chip package assembly on the top surface of the first encapsulation layer and the top surface of the bridge chip assembly comprises: forming a top redistribution layer on the top surface of the first encapsulation layer and the top surface of the bridge chip assembly, the top redistribution layer comprising a dielectric layer and electroplated conductive lines in the dielectric layer, the electroplated conductive lines being electrically connected to the bridge chip assembly, wherein the electroplated conductive lines are formed by an electroplating process; forming a top pad on the top surface of the top redistribution layer, the top pad being electrically connected to the top redistribution layer; arranging a top device on the top redistribution layer, the top device being soldered to the top pad; encapsulating to form a second encapsulation layer encapsulating the top device.

11. The method of claim 1, wherein The step of forming a bottom redistribution layer on the bottom surface of the first encapsulation layer and the bottom surface of the bridge chip assembly comprises: forming a dielectric layer on the bottom surface of the first encapsulation layer and the bottom surface of the bridge chip assembly; forming a via exposing the bottom surface of the through-silicon via or a bottom pad of the through-silicon via on the dielectric layer by a one-time exposure or two-time exposure process; sputtering and / or electroplating to form an electroplated bump in the via, the electroplated bump being in contact with the through-silicon via or the bottom pad.

12. The method of claim 1, wherein The step of forming a bottom redistribution layer on the bottom surface of the first encapsulation layer and the bottom surface of the bridge chip assembly further comprises: forming a conductive connection structure on the bottom surface of the bottom redistribution layer.

13. A package structure, comprising: The chip package assembly comprises: a bridge chip assembly comprising a bridge chip and a protective layer, the bridge chip comprising a substrate and a through-silicon via penetrating through the substrate, the protective layer being arranged on the bottom surface of the substrate and exposing the bottom surface of the through-silicon via, and the bottom surface of the through-silicon via being flush with the bottom surface of the protective layer; a first encapsulation layer encapsulating the side surface of the bridge chip assembly, and the bottom surface of the bridge chip assembly being higher than the bottom surface of the first encapsulation layer; a chip package assembly arranged on the top surface of the first encapsulation layer and the top surface of the bridge chip assembly, the bridge chip assembly being electrically connected to the chip package assembly. A bottom redistribution layer is arranged on the bottom surface of the first plastic encapsulation layer and the bottom surface of the bridge chip assembly, wherein the thickness of the bottom redistribution layer arranged on the bottom surface of the bridge chip assembly is greater than the thickness of the bottom redistribution layer arranged on the bottom surface of the first plastic encapsulation layer, and the bridge chip assembly is electrically connected with the bottom redistribution layer.

14. The package structure of claim 13, wherein, The bridge chip assembly further comprises a bottom solder pad arranged on the bottom surface of the through silicon via and electrically connected with the through silicon via, and the bottom redistribution layer is electrically connected with the bottom solder pad.

15. The package structure of claim 14, wherein, The bridge chip assembly further comprises a seed layer arranged between the bottom solder pad and the bottom surface of the through silicon via.

16. The package structure of claim 13, wherein, The side surface of the through silicon via is further provided with a passivation layer.

17. The package structure of claim 13, wherein, The bridge chip assembly further comprises: An internal redistribution layer arranged on the top surface of the substrate and electrically connected with the top surface of the through silicon via; A conductive pillar arranged on the top surface of the internal redistribution layer and electrically connected with the internal redistribution layer, and the chip package assembly is electrically connected with the conductive pillar.

18. The package structure of claim 13, wherein, The bridge chip further comprises a deep trench capacitor arranged in the substrate.

19. The package structure of claim 13, wherein, The bottom redistribution layer comprises a dielectric layer and a plated bump arranged in the dielectric layer, and the plated bump is in contact with the bottom surface of the through silicon via or the bottom surface of the bottom solder pad.

20. The package structure of claim 13, wherein, The chip package assembly comprises: A top redistribution layer arranged on the top surface of the first plastic encapsulation layer and the top surface of the bridge chip assembly, wherein the top redistribution layer comprises a dielectric layer and a plated conductive wire arranged in the dielectric layer, and the plated conductive wire is electrically connected with the bridge chip assembly; A top solder pad arranged on the top redistribution layer and electrically connected with the top redistribution layer; A top device arranged on the top redistribution layer, and the top device is soldered with the top solder pad; A second plastic encapsulation layer covering the top device.

21. The package structure of claim 13, wherein, The packaging structure further comprises a metal pillar penetrating through the first plastic encapsulation layer, and the bottom surface of the metal pillar is flush with the bottom surface of the first plastic encapsulation layer.

22. The package structure of claim 13, wherein, The packaging structure further comprises a conductive connection structure arranged on the bottom surface of the bottom redistribution layer.

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