Direct chip-on-array for multi-dimensional transducer array

Abstract

For a direct on-array chip for a multi-dimensional transducer array, a generally rigid and conductive de-matching layer extends beyond the footprint of the transducer array. The ASIC is directly connected to the de-matching layer on one side, while the other side provides electrical connections to elements of the array, and I / O pads for connections to an ultrasound imaging system (e.g., flexible to the de-matching layer). By using the de-matching layer stiffness, the ASIC may be protected during formation of the acoustic stack. By using the de-matching layer conductivity, any misalignment is compensated for by routing through the de-matching layer, and / or a large flat area is provided for the I / O, allowing for good low temperature rough contact connections having a larger area than flip chip solder bumps. By providing I / O for system connections on a different side of the de-matching layer than the ASIC, large prohibited access distances due to underfill may be avoided.

Description

[0001] This case is a divisional application. The invention name of the parent case is "Direct array-on-chip for multi-dimensional transducer arrays", the application date is July 15, 2021, and the application number is 202110800289.5.

[0002] This application is a continuation of U.S. application serial number 16 / 947,018 filed on July 15, 2020, the entire contents of which are incorporated herein by reference. Background Art

[0003] The present embodiment relates to the interconnection of a multi-dimensional transducer array with electronics. Achieving interconnection between an acoustic array and associated transmit and / or receive electronics is a technical challenge for multi-dimensional (matrix) transducers. Hundreds or thousands (e.g., up to 10,000) of different elements distributed in two dimensions (azimuth and elevation) require interconnection along the z-axis (depth or range), at least for elements surrounded by other elements. Since these elements are small (e.g., 100-500 μm), there is limited space for individual electrical connections to each element.

[0004] A typical ultrasound imaging system has a limited number of channels, from 64 up to 256, determined by the number of cables through which the system communicates with the ultrasound transducer. The limited number of cables is not capable of transmitting voltage from the system to all acoustic elements in the matrix transducer and then receiving signals back from these elements. In order to reduce the number of signals, a microbeamforming application-specific integrated circuit (ASIC) is used to perform beamforming in the transducer probe. The ASIC is placed as close as possible to the acoustic elements. In the chip-on-array (COA) approach, the acoustic array is built directly on the input / output (I / O) of the ASIC chip, such as using a flip-chip connection. The COA approach contains two key interconnects: (1) ASIC to acoustic element I / O in the middle area of ​​the ASIC; and (2) flex-to-ASIC interconnect in the peripheral area of ​​the ASIC. The 1:1 direct interconnect for ASIC to acoustic I / O is typically made by flip-chip technology. The flex-to-ASIC interconnect is used to send / receive power / ground, beamformed outputs, and control signals back and forth between the transducer and the ultrasound system.

[0005] In cases where the acoustic stack is built into only a portion of the ASIC, while areas around the periphery of the ASIC chip are reserved for flex-to-ASIC connections, the pressure applied when laminating the several acoustic layers together may damage the active transistor circuitry of the ASIC, such as cracking the chip at the boundary line where the acoustic stack ends and the peripheral flex-to-ASIC bonding area begins. The front side of the ASIC, which contains critical active circuitry, is directly exposed to mechanical stress, various chemicals (epoxies, underfills, solder flux, etc.), and electrostatic discharge (ESD) throughout the transducer formation process. Due to the capabilities of the die attach machines and the fluidity of the die attach materials, chip shifting or offsetting may not be avoided during the chip tiling (or die attach) process, which may result in inconsistent electrical pitch across the tiled chip for the flex-to-ASIC connection.

[0006] The flex-to-ASIC connection is made after the acoustic build process is completed, so the epoxy used to form the array, and the Curie temperature of the piezoelectrics limit the connection process to 100°C or less, however the ASIC has an uneven surface that is best electrically connected using a higher temperature process. The flex-to-ASIC connection requires a larger keep-out distance to avoid contamination from the underfill used in the flip-chip connection of the ASIC to the acoustic element I / O. Compared to the ASIC to acoustic I / O connection where both the acoustic stack and the ASIC are rigid and dimensionally stable, the flex-to-ASIC joint may require larger pads to obtain a reliable electrical connection due to the dimensional instability of the flex circuit. When considering solder joints for both the ASIC to acoustic stack and the flex to ASIC connection, it is not easy to grow solder bumps of different sizes on one wafer because the different pad sizes will change the bump plating process conditions. Summary of the invention

[0007] As an introduction, the preferred embodiments described below include methods, systems, transducer probes, and assemblies for direct COA of multidimensional transducer arrays. A dematching layer, which is typically rigid and conductive, extends beyond the footprint of the transducer array. The ASIC is directly connected to the dematching layer on one side, while the other side provides electrical connections to the elements of the array and I / O pads for connections to the ultrasound imaging system (e.g., flexible to the dematching layer). By using the rigidity of the dematching layer, the ASIC can be protected during the formation of the acoustic stack. By using the conductivity of the dematching layer, any misalignment can be compensated by routing through the dematching layer. By using the conductivity of the dematching layer, a large flat area is provided for the I / O, allowing good low temperature rough contact connections with a larger area than flip chip solder bumps. By providing I / O for system connections on a different side of the dematching layer from the ASIC, large forbidden entry distances due to bottom fillers can be avoided.

[0008] In a first aspect, a multidimensional transducer array system is provided. An acoustic array has transducer elements distributed in a grid in a first and a second dimension. The acoustic array has a first extent of transducer elements along the first dimension. A dematching layer is connected to the acoustic array in an acoustic stack. The dematching layer supports the transducer elements on a first side and extends along the first dimension in a second extent. The second extent is larger than the first extent. A chip of an application specific integrated circuit is directly bonded to a second side of the dematching layer. The second side is opposite to the first side. A flexible circuit is connected to the dematching layer on the first side.

[0009] In a second aspect, an ultrasound transducer probe is provided. A chip-on-array arrangement of a semiconductor chip electrically connected to a multidimensional transducer array is provided. The multidimensional transducer array is a quarter-wavelength transducer with a dematching layer. The semiconductor chip is electrically connected to the multidimensional transducer array through the dematching layer. Contact pads are on the dematching layer for signaling and grounding from the semiconductor chip to an ultrasound imaging system. The dematching layer provides signal routing from the contact pads to the semiconductor chip and from the semiconductor chip to the multidimensional transducer array.

[0010] In a third aspect, a method for connecting an electronic device to an array of acoustic elements is provided. An integrated circuit is directly connected to a first surface of a dematching layer of an acoustic element. A conductor is connected to a second surface of the dematching layer. The second surface is opposite to the first surface. The conductor is connected to a pad on the second surface outside of a footprint on the dematching layer of the acoustic element.

[0011] The present invention is defined by the appended claims, and nothing in this section should be considered as a limitation to these claims. Other aspects and advantages of the present invention are discussed below in conjunction with the preferred embodiments, and these other aspects and advantages may be claimed later independently or in combination. Different embodiments may achieve or fail to achieve different purposes or advantages. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The components and drawings are not necessarily drawn to scale, emphasis instead being placed upon illustrating the principles of the invention. Moreover, in the drawings, like reference numerals designate corresponding parts throughout the different views.

[0013] Figure 1A and Figure 1B are a cross-sectional view and a top area view, respectively, of a portion of one embodiment of a chip-on-array interconnect of an acoustic array to an integrated circuit; Figure 2A and Figure 2B They are Figure 1B and Figure 1A A top area view and a cross-sectional view of an embodiment of a chip-on-array interconnect; Figure 3A and Figure 3B A top area view and a cross-sectional view, respectively, of an ultrasound transducer system using a dematching layer for connection with multiple ASICs; Figure 4 shows an example of chip shifting allowed due to the use of an intermediate dematching layer; Figure 5 illustrates an example of a roughened contact provided on a surface of a dematching layer; Figure 6 illustrates an example ground path provided by using a dematching layer for signal routing; Figure 7 Another example ground path is illustrated; and Figure 8 is a flow chart of one embodiment of a method for connecting electronics to an array of acoustic elements. DETAILED DESCRIPTION

[0014] The dematching layer of the acoustic stack enables a quarter-wavelength acoustic design. The dematching layer is extended to cover more than the transducer element, such as being extended to cover the entire area of ​​one or more ASICs. The dematching layer is a rigid substrate that acts as a mechanical support for attaching to the ASIC and the rest of the acoustic stack, thereby allowing the use of thinner ASICs. The dematching layer also acts as an electrical routing layer for sending and / or receiving signals and grounding, such as providing a direct connection from the ASIC to the singulated element, and routing signals and grounding from the flexible circuit to the ASIC in the area of ​​the dematching layer that extends beyond the rest of the acoustic stack. Since the ASIC is bonded to the bottom of the dematching layer and the flexible circuit is connected to the top of the dematching layer, the flexible to ASIC bonding is more independent of the flip chip process and the larger pads formed by the dematching layer. By connecting the flexible circuit to the extended dematching layer, low temperature rough bonding (asperity bonding) can be used for flexible to ASIC electrical connection. Due to the hardness of the dematching layer, the ASIC and / or acoustic stack can be tested with less risk of the probe damaging the contact pad.

[0015] Figure 1A and Figure 1B One embodiment of the schematic concept of COA interconnect is shown. The dematching layer 12, which is the bottom layer of the acoustic stack (e.g., the dematching layer 12, the piezoelectric 14, one or more matching layers 16, 18, and the electrode 24), extends to cover the entire area of ​​the ASIC 26. All ASIC I / Os for both acoustic elements and peripheral connections are directly connected to the bottom of the dematching layer 12, so that all active circuits of the ASIC 26 are well fixed by being supported by the substrate of the dematching layer 12 and / or protected by it. During singulation or dicing of the acoustic stack, all ASIC I / Os (e.g., flip chip joints 34) become electrically separated by kerfs in the dematching layer. The separated I / Os in the peripheral area of ​​the dematching layer 12 (i.e., the area 38 extending beyond the footprint or area 40 of the acoustic stack) are connected to the flexible circuit 30. The flexible circuit 30 is electrically connected to send and / or receive various signals back and forth between the transducer and the ultrasound system. Example signals routed through the dematching layer include: power, ground, beamformed output signals, digital inputs and / or outputs, digital clocks, and / or temperature sensor signals.

[0016] The dematching layer 12 not only enables a quarter-wavelength acoustic design, but also acts as a mechanical support for the ASIC 26 and the acoustic stack. The dematching layer 12 even acts as an electrical routing layer to send and / or receive signals and grounds toward the flex circuit 30. The bonding process for connection from the flex circuit 30 to the components or I / O pads of the dematching layer 12 is less affected by the flip chip joint on the opposite side of the dematching layer 12. Since the dematching layer 12 provides a very flat surface, epoxy rough bonding, which is a low temperature bonding process (~60°C), can be utilized instead of flip chip or wire bonding pads, which have a topography around the pads protected by a passivation layer on the ASIC. Depending on the transducer, typical flip chip options such as solder, copper and gold pillars, ACF, NCF, NCP and Ag paste can be used.

[0017] Figure 1A is a cross-sectional view of one embodiment of a multidimensional transducer array system. The system is used in an ultrasound transducer probe, such as in a handheld probe for scanning from outside a patient or intra-cavity (e.g., a transthoracic or transesophageal transducer probe), or a catheter-based probe for scanning from within a patient. The system is a chip-on-array arrangement in which a semiconductor chip (e.g., ASIC 26) is electrically connected directly to the dematching layer 12 of the multidimensional transducer array 10. Due to the low parasitic, short electrical connections, improved scanning and imaging under ultrasound can be provided for medical diagnostics. The dematching layer 12 is extended to provide electrical connections to the flexible circuit 30 and to protect the semiconductor chip.

[0018] The array system and the corresponding probe are used Figure 8 The array system includes an array 10 formed by an acoustic stack, an ASIC 26, and a flexible circuit 30. Additional, different, or fewer components may be provided. For example, an acoustic backing 28 for absorbing acoustic energy is added to the back of the ASIC 26. As another example, a flexible circuit 30 is not provided, such as where wire bonds or other electrical connections are provided between the ASIC 26 and an ultrasound imaging system or scanner.

[0019] The acoustic array 10 has transducer elements 20 distributed in a grid in two dimensions. The multidimensional transducer array 10 is an array of piezoelectric or microelectromechanical (capacitive membrane) elements 20. Piezoelectric examples are used herein. The array 10 is flat, concave, or convex. The elements 20 are distributed along the azimuth and elevation dimensions. The elements 20 are distributed along the two dimensions at fully sampled intervals, at any of a variety of spacings, such as every 100, 150, 200, 250, 400, or 500 microns. Figure 1A and Figure 1B , the spacing of the transducer elements 20 is shown as the same spacing as the flip chip joints 34 (e.g., center-to-center spacing). Other spacings, or spacings that vary according to location, may be used. The spacing may be the same or different in different directions or dimensions, such as 300 microns along pitch and 600 microns in azimuth. A full sampling or sparse sampling of the placement of the elements 20 is provided.

[0020] The array 10 and corresponding transducer elements 20 include one or more impedance matching layers 16, 18, a piezoelectric layer 14, and a dematching layer 12. Each element 20 of the array 10 includes at least two electrodes. The element 20 converts between electrical energy and acoustic energy. Additional, different or fewer layers may be provided. For example, a backing block 28 may be positioned on one side of the array 10 to limit acoustic reflections from energy transmitted in undesirable directions. A lens, window, or other now known or later developed multidimensional transducer array component may be included.

[0021] The matching layers 16, 18 are 1 / 4 wavelength thick layers of material. The material has an acoustic impedance between the impedance of the patient and the piezoelectric layer 14. Multiple layers for gradual changes in acoustic impedance may be used, such as shown with high and low matching layers 16, 18. Only one matching layer 16, 18 may be used.

[0022] The piezoelectric layer 14 is a slab or plate of piezoelectric material. A solid piezoelectric (e.g., single crystal PZT) may be used. Single crystal or polycrystalline piezoelectric material may be used. In other embodiments, a composite of piezoelectric and epoxy or another polymer is used.

[0023] The ground plane may form an electrode. The ground plane may be provided by conductive matching layers 16, 18. Either or both of the matching layers 16, 18 may be conductive, such as to provide a ground plane as well as impedance matching. Alternatively or additionally, a separate metallization layer or foil layer is provided as a ground plane for the array 10. A conductive sheet is placed or deposited on, within or below one of the matching layers 16, 18, such as a ground return layer 32 between the matching layers 16, 18, such as Figure 1A shown.

[0024] Another conductor sheet provides a conductor for forming a signal electrode. A conductor deposited on the dematching layer 12 or the piezoelectric layer 14 may be used. Alternatively, a conductor placed or formed between the dematching layer 12 and the piezoelectric layer 14 is used. In yet other embodiments, the conductor is formed from the conductive material of the dematching layer 12. Once cut or separated, the conductor sheet provides separate signal electrodes for the transducer elements 20. An electrically separate signal electrode is provided for each transducer element 20.

[0025] The acoustic stack forms a quarter wavelength transducer. The elements 20 of the array 10 include a dematching layer 12 that allows the thickness of the piezoelectric layer 14 to be designed based on a quarter wavelength. An acoustic backing 28 may be added behind the ASIC 26.

[0026] The transducer elements 20 include a dematching layer 12. Slits 22 (cut cuts) that separate the elements 20 extend through the dematching layer 12. In an acoustic stack, the transducer elements 20 of the array 10 have a piezoelectric layer 14 connected to or stacked on one side of the dematching layer 12. The dematching layer 12 supports the transducer elements 20. The top or transducer facing the surface of the dematching layer 12 contacts the signal electrode and / or the piezoelectric layer 14, while the bottom or back facing the surface of the dematching layer 12 contacts the ASIC 26.

[0027] The dematching layer 12 is a 1 / 4 wavelength thick layer of material. Any material may be used, such as tungsten carbide, which provides a greater acoustic impedance than the piezoelectric body 14 of the element 20. The dematching layer 12 provides a clamped boundary condition, resulting in better sensitivity and wider bandwidth in the ultrasonic transducer.

[0028] refer to Figure 1B , Figure 2A and Figure 2B , the elements 20 of the acoustic stack 52 cover the array area 40. The elements 20 are distributed along the azimuth and elevation dimensions over the array area 40 to form the footprint of the array 10. The dematching layer 12 has a larger extent along at least one dimension. For example, Figure 1B A dematching layer 12 is shown covering both the acoustic stack region 40 and the dematching layer region 38 only. Rather than having the same footprint as the acoustic stack, the dematching layer 12 has a larger area and extends to have a greater length along the pitch or azimuth dimension. As another example, Figure 2A and Figure 2B Dematching layer 12 is shown having a slightly larger extent along one dimension (e.g., elevation) than acoustic stack 52, and a significantly larger extent (at least 10%) along another dimension (e.g., elevation) than acoustic stack 52. Array 10 has a smaller extent than dematching layer 12 in azimuth and / or elevation.

[0029] In one embodiment, the dematching layer 12 has the same area or size and shape as the ASIC 26. The ASIC 26 has a larger footprint than the acoustic stack 52 and therefore extends to a larger area along one or two dimensions than the array 10. The dematching layer 12 may have a smaller or larger area on the mating or contacting surface than the ASIC. Figure 2A and Figure 2B The ASIC 26 is shown as having a larger area (eg, length and width) than the acoustic stack 52 , and the dematching layer 12 is shown as having a larger area (eg, length and width) than the ASIC 26 .

[0030] The dematching layer 12 is rigid, such as having a hardness or elastic modulus greater than 400 GPa (e.g., >530 GPa in terms of elastic modulus). The dematching layer 12 is conductive, and / or plated, or has through holes formed therein for conducting electricity. The dematching layer 12 not only runs through the flip chip process of connecting the ASIC 26 to the acoustic element 20 (i.e., connecting the ASIC 26 to the acoustic stack 52), but also acts as a rigid and dimensionally stable substrate during the array lamination process. The ASIC 26 is attached to the lower surface of the dematching layer 12 by one of a variety of flip chip options, including solder, copper and gold pillars, epoxy rough bonding, ACF, NCF, NCP, and silver paste. During the flip chip process, the entire ASIC 26 is well supported by the rigid substrate (i.e., the dematching layer 12). Although the acoustic layers (e.g., piezoelectric 14, ground return, shield layer, and matching layers 16, 18) are laminated together on the upper surface of the dematching layer 12, the lamination pressure is well distributed on the ASIC 26 without stress concentration points through the extended rigid dematching layer 12. The rigid substrate provided by the dematching layer 12 supports the entire chip area of ​​the ASIC 26, thereby allowing a thinner ASIC 26 to avoid any unwanted ultrasonic reflections from the chip.

[0031] ASIC 26 is a semiconductor chip. The semiconductor chip includes an integrated circuit for signal processing. Transistor-based or switch-based devices are provided within the chip. The integrated circuit may be ASIC 26. In other embodiments, the chip or integrated circuit includes: analog circuits, digital circuits, switches, multiplexers, controllers, processors, digital signal processors, field programmable gate arrays, or other active electronic components now known or later developed. The integrated circuit or other circuit may take the form of a semiconductor chip as a circuit.

[0032] Semiconductor or active electronic devices include transmit and / or receive circuits for ultrasonic scanning using the acoustic array 10. For example, multiple transmit circuits, multiple receive circuits, and / or controllers are provided as semiconductor chips. The transmit component is separated from the receive component or can be integrated with the receive component. The transmit component includes: a high voltage pulse generator, a filter, a memory, a delay, a phase rotator, a multiplier, a combination thereof, or other transmit beamformer components known now or developed later. The receive component includes: a filter, an amplifier, a delay, an adder, a combination thereof, or other receive beamformer components known now or developed later. Since the receive beamformer component can operate at a lower voltage than the transmit component, the receive and transmit components are on separate devices or chips, but a combined device for transmit and receive operations can be provided. The integrated circuit includes: all or part of the transmit beamformer, pulse generator, receive beamformer, amplifier, phase rotator, delay, adder, or other active electronic devices for ultrasonic scanning. For example, ASIC 26 is a partial beamformer that is used to combine signals from different element groups and output a certain number of partial beamformed signals for different receive apertures to a corresponding number of traces on the flexible circuit 30 and the cables connecting the probe to the ultrasound system and the beamformer therein.

[0033] In one embodiment, Figure 2A and Figure 2B As shown, a single active electronic component, such as a single chip or ASIC 26, is provided. A larger number of acoustic elements 20 and corresponding apertures result in a larger size ASIC chip to process the acoustic signal. Larger ASIC chips are more expensive because larger chips are more likely to have defects during semiconductor processing. To reduce the size of the integrated circuit, two or more integrated circuits can be tiled. Figure 3A and Figure 3BAn example is shown in which four semiconductor chips or integrated circuits are tiled. Two or more semiconductor chips can be tiled or placed adjacent to each other. Each semiconductor or integrated circuit is positioned adjacent to the dematching layer 12. Instead of a single larger ASIC chip, two or more smaller sized chips are mounted to the dematching layer 12. Each integrated circuit is electrically connected to a different subset of the transducer elements 20. For example, four ASICs 26 are electrically connected to four groups of elements 20, with each element 20 in only one group. Whether tiled or not, the dematching layer 12 acts as a mechanical support for the attachment of the ASICs 26 and the acoustic stack, as well as an electrical routing layer for sending / receiving signals and grounding toward the flexible circuit 30.

[0034] As more ASICs 26 are mounted below the acoustic stack with increasing acoustic apertures, the continuity of the spacing is more likely to be disrupted due to chip shifting across the tiled chips. Figure 4 An example is shown in which the outlines of two ASICs 26 are shown with dashed lines. These ASICs 26 as tiled are displaced relative to each other and the dematching layer 12. Since the dematching layer 12 as cut creates a larger surface area of ​​pads or signal paths, some displacement can be provided while still connecting the flip chip joint 34 to the correct component 20, as well as the pads formed by the dematching layer 12 for connection to the flex circuit 30. Despite the displacement of the ASICs 26, the dematching layer 12 provides consistent spacing corresponding to the flex circuit pads and acoustic element 20. Despite the die attach displacement during ASIC tiling, the spacing for the flex to ASIC input / output and component to ASIC input / output can be reset and continuous through the dematching layer 12 as an input / output element.

[0035] refer to Figure 1A and Figure 1B , a semiconductor chip (e.g., ASIC 26) includes input / output pads. The semiconductor chip includes input / output conductors exposed on the largest surface, or exposed on the surface to be placed against the dematching layer 12. In an alternative embodiment, the pads are away from the chip along the edge and are routed to the distribution on the largest surface by wire bonding or redistribution layers including sequentially deposited metal traces and dielectrics. In order to connect to the dematching layer 12, a flip chip joint 34 is formed on the input / output pad. The flip chip joint 34 is a solder ball, a copper pillar, a gold bump, a silver paste, or an anisotropic conductive film (ACF).

[0036] A semiconductor chip (e.g., ASIC 26) is flip-chip bonded directly to the dematching layer 12. The chip is placed against the dematching layer 12 so that the flip-chip joint 34 contacts the dematching layer 12 without an intermediate layer. This direct connection may include an underfill 36 to support flip-chip bonding. Heat is applied to form a direct physical and electrical connection from the chip (e.g., from the input / output pads of the ASIC 26) to the dematching layer 12. The semiconductor chip is bonded directly to the bottom or side of the dematching layer 12 opposite the piezoelectric layer 14. This bonding may be performed before stacking the rest of the acoustic stack.

[0037] like Figure 2A and Figure 2B As shown, the semiconductor chip (e.g., ASIC 26) has a surface area that is larger than the footprint of the array 10. The acoustic stack 52 of the elements 20 forming the array 10 has a surface of a given size connected to the dematching layer 12. The semiconductor chip has a surface of a larger size connected to the dematching layer 12. The chip is larger along at least one dimension (such as, in azimuth or elevation). The chip can be larger in both azimuth and elevation. The chip has the same size (e.g., the same surface area) and shape as the dematching layer 12. Alternatively, and as Figure 2A and Figure 2B As shown, the contact surface of the chip is smaller than the contact surface of the dematching layer 12 .

[0038] In one embodiment, the dematching layer 12, the acoustic array 10 (e.g., the acoustic stack 52 without the dematching layer 12), and the chip (e.g., the ASIC 26) have an interval within 5% of each other along the pitch dimension (i.e., the shortest is within 5% of the longest along the pitch). Other relative sizes may be used, such as equal, within 2%, or within 10%. The dematching layer 12 and the chip are at least 10% larger than the length of the acoustic stack 52 along the azimuth dimension. Other relative sizes may be used, such as 5%, 15%, or 20%. Instead of or in addition to azimuth, the dematching layer 12 may extend in pitch. The dematching layer 12 and the chip have an interval within 5% of each other along the azimuth and / or pitch dimensions, and are at least 10% larger than the interval of the acoustic stack 52 along one or both dimensions. Other relative sizes may be used.

[0039] refer to Figure 1A and Figure 1B, flip chip connectors 34 are positioned to connect input / output pads of the ASIC 26 to the elements 20. Separate flip chip connectors 34 connect to separate elements 20 in the acoustic stack area 40. In the dematching layer only area 38 (i.e., without the piezoelectric layer 14 or outside the footprint of the array 10), other flip chip connectors 34 are positioned to make connections for communications or signals with the ultrasound scanner. For example, separate flip chip connectors 34 electrically connect power, ground, beamforming output, and clock signals to the flexible circuit 30 through the dematching layer 12. Some of the flip chip connectors 34 may be connected for the same signal, such as two or more flip chip connectors 34 being on the same input / output pad of the ASIC 26, or on different input / output pads of the ASIC for common signals. As Figure 1B As shown, some of the flip chip joints 34 may be connected to ground for the edge element 20 of the acoustic stack, and some of the flip chip joints 34 may be connected to ground for the flex circuit 30 .

[0040] Since the dematching layer 12 is conductive, the dematching layer 12 acts as an electrical routing layer to receive and transmit signals and ground from the elements 20 and the flexible circuit 30. The dematching layer 12 may be plated to facilitate electrical connections. The dematching layer 12 provides signal routing from the contact pads of the flexible circuit 30 to the semiconductor chip (e.g., ASIC 26), and from the semiconductor chip to the multidimensional transducer array 10. The dematching layer 12 provides pad redistribution, thereby acting as a redistribution layer. The semiconductor chip (e.g., ASIC 26) is electrically connected to the multidimensional transducer array 10 (i.e., electrically connected to the elements 20) and electrically connected to the flexible circuit 30 through the dematching layer 12.

[0041] Slits 22 (e.g., singulation or cutting cuts) are formed in the dematching layer 12. Layers of the acoustic stack are added to the dematching layer 12. Once added, the stack including the dematching layer 12 is cut. One or more matching layers 16, 18 and / or ground return layer 32 may not be cut. For the acoustic stack, the cut and the resulting slits 22 separate the acoustic elements 20 of the array 10. The slits 22 extend through the dematching layer 12 so that separate electrical connections from the ASIC 26 and the flip chip connector 34 are provided to the elements 20. Signals are transmitted through the separated conductive dematching layer 12. The transducer elements 20 formed by cutting the slits 22 have a first spacing along one or two dimensions. The spacing is equal along azimuth and pitch, but different spacings can be provided.

[0042] The cutting also forms slits 22 in the dematching layer regions 38 where there is no piezoelectric layer 14 (i.e., outside the footprint of the array 10). These slits 22 through the dematching layer 12 in regions extending beyond the transducer elements 12 form contact pads for the flex circuit 30. The spacing of the slits 22 and the resulting contact pads along one or more dimensions may be the same or different than the spacing of the elements 20. For example, for at least some of the pads formed from the dematching layer 12, the spacing is doubled along the azimuthal dimension.

[0043] In one embodiment, the separation of the dematching layer 12 by the slits 22 forms one or more ground pads 42, power pads, control signal pads, partial beamformer output pads, and / or transmit signal pads. The slits 22 form contact pads for the flex circuit 30. Although the acoustic elements 20 are created by singulating / cutting the laminated acoustic layer according to the ASIC pitch, only the peripheral areas of the dematching layer area 38 are also cut, which will in turn create contact pads or input / output elements. The ASIC peripheral input / outputs are connected to the pads on the flex circuit 30 through these dematching layer based input / outputs. The singulation / cutting is deep enough to cut through the dematching layer 12, but does not reach the top surface of the ASIC.

[0044] The contact pads formed by cutting the dematching layer 12 are larger than the flip chip joint 34. The separated portions of the dematching layer 12 are themselves contact pads for the flexible circuit 30 and the component 20. The metallization on the dematching layer 12 can be used to form a better conductive bond. The contact pads (e.g., 42, 44, 45, 46) used to connect to the flexible circuit 30 are on the same surface of the dematching layer 12 as the acoustic stack, which is opposite the surface of the dematching layer 12 used for flip chip bonding.

[0045] Slits 22 separate the dematching layer 12 to provide pads for signaling and grounding between the semiconductor chip and the ultrasound imaging system. Different arrangements can be used to form the pads. Figure 1BSome examples are shown, such as ground pads 42 formed to connect to flip chip joints 34, which are connected to the ground of ASIC 26. In another example, one or more of the flip chip joints 34 are dummy inputs / outputs. The pad size (e.g., pads 44) can be increased by merging identical ASIC inputs / outputs together, or incorporating some dummy inputs / outputs on ASIC 26. The resulting pads of the dematching layer 12 are connected to one or more dummy inputs / outputs of ASIC 26, as well as one or more signal inputs / outputs. The pads formed by the cuts 22 in the dematching layer 12 can have any of a variety of sizes, such as an original pad size 46 corresponding to the pitch of the flip chip joints 34 or components 20, or as a double pad size with an enlarged pad area 45. In Figure 1B In the example of FIG. 1 , the outermost pads 45 extend further beyond the ASIC input / output by using a dematching layer size that is slightly larger than the pitch of the input / output pads of the ASIC 26. The larger sized pads may be connected to one, two, or more flip chip joints 34. While the size and pitch of the contact pads formed from the dematching layer 12 may correspond to the input / output pads of the ASIC 26, the size and / or pitch may be different and / or varied. A semi-redistribution layer may be defined in the dematching layer 12, depending on the location of the saw cuts and resulting kerfs 22. This redistribution provides flexibility in pitch and pad size during ASIC bonding with the flexible circuit 30.

[0046] The flex circuit 30 is connected to the dematching layer 12 on the same side as the piezoelectric layer 14 and on the opposite side from the ASIC 26. The flex circuit 30 is an electrically insulating or dielectric material. In one embodiment, the flex circuit 30 is a flexible sheet of polyimide. Traces or other conductors, such as deposited and / or etched copper traces, may be included on and / or in the flex circuit 30. Passive and / or active electronics may or may not be attached. The traces route signals between the ASIC 26 and the ultrasound scanner or imaging system. For example, the flex circuit 30 is connected to a cable of a transducer probe, which is connected to an ultrasound scanner.

[0047] refer to Figure 5 , the flexible circuit 30 has traces or contact pads connected to contact pads formed on or by the dematching layer 12 . Figure 5 The use of vias through the flex circuit 30 is shown for routing signals from some of the contact pads of the dematching layer 12 .

[0048] The flexible circuit 30 is bonded to the dematching layer 12. Any material for bonding can be used. In one embodiment, the material is a low temperature curable polymer, such as epoxy, polyurethane, polyester, silver paste, or other polymer-based materials. The low temperature is relative to the transducer element 20. The Curie temperature of the piezoelectric layer 14 can be between 80-120°C. For example, a binary single piezoelectric crystal has a Curie temperature of 80°C, and a ternary single piezoelectric crystal has a Curie temperature of 120°C. Other Curie temperatures can be provided. Other temperatures related to the breakdown or operational changes of any layer in the acoustic stack can be used. It is not expected to reach or exceed this temperature when forming a COA transducer system. The material used for bonding or other interconnections allows connection without exceeding this low temperature.

[0049] In one embodiment, rough contact and bonding are provided. After the slit 22 is formed, the flexible circuit 30 is stacked with the dematching layer 12 or placed against the dematching layer 12. The material for bonding is added to the stack or added during the stacking. The material can be cured at room temperature or at an elevated temperature below the Curie temperature or other breakdown temperature. For example, two metal pads are in close contact with each other and then bonded together through a cured epoxy, through the two pads, or on the two pads. A low temperature bonding process of about ~60°C is used. The flexible circuit 30 is connected to the contact pad through a rough contact, thereby forming a close contact between the electrodes for conductivity. Alternatively, flip chip options (such as solder, copper and gold pillars, ACF, NCF, NCP, and silver paste) can be used to connect the flexible circuit 30 to the matching layer 12.

[0050] High temperature (e.g., >120°C) interconnects can be used for flip chip connections by performing such connections prior to connecting the acoustic stack or flex circuit 30. High temperature reliable electrical interconnects (>120°C) include lead and lead-free solders (>180°C), copper pillars with solder caps (>250°C), and high temperature anisotropic conductive films (ACF) (>120°C).

[0051] Since the flex circuit 30 connection is to the dematching layer 12 on the back side where the flip chip joint 34 is made, the flex circuit bonding process is less affected by the front side ASIC flip chip process. The back side pads have less chance of being contaminated by the underfill 36 flow dispensed in the front side during the flip chip process, and their pad metallurgy or finishing process does not need to be compatible with the front side. In addition, there is no need for any keep out areas to prevent the peripheral pads from being contaminated by the underfill 36 flow. Furthermore, independent of the ASIC flip chip joint 36, various joint options that are particularly suitable for flex circuit to dematching layer connection can be used, such as epoxy rough bonding. Since the dematching layer 12 provides a flat surface compared to the contact pads on the ASIC 26 where the passivation layer may interfere, the rough contact is more likely to be sufficient.

[0052] like Figure 1A , Figure 2B , Figure 3B , Figure 6 and Figure 7 As shown, the flex circuit 30 can be connected to the dematching layer 12 adjacent to the acoustic stack. Since the underfill 36 is on the opposite side of the dematching layer 12, there is no need for any area to allow the underfill 36 to flow. The flex circuit 30, and one or more contact pads of the flex circuit 30, can be connected to the dematching layer 12 within one element width of the acoustic stack. Greater or less separation with the flex circuit 30 and the piezoelectric layer 14 can be provided, such as adjacent or contacting each other.

[0053] Due to the conductivity of the dematching layer 12, one or more ground paths may be formed from the flex circuit 30 to the acoustic stack's ground return layer 32. One ground path may not pass through the semiconductor chip (ASIC 26). Figure 1B A ground pad 42 is shown formed from the dematching layer 12. A ground trace of the flex circuit 30 connects to the ground pad 42. A ground connection of the array 10 also connects to the ground pad 42, such as through a metal electrode 24 formed on one side of the edge element 20. Figure 6 Two ground paths are shown with dashed lines. One ground path goes from the ground return layer 32 through the conductive matching layer 18, along the electrode 24 on one side of the edge element 20, through the dematching layer 12, and to the flex circuit 30. The other path goes through one or more flip chip connectors 34, through the ASIC 26, back through one or more other flip chip connectors 34, through the dematching layer 12, and to the flex circuit 30.

[0054] In the acoustic stack, the piezoelectric element - a sandwich of two metal electrodes and a piezo between them - is operated by supplying power on the bottom electrode and returning a ground path on the top electrode. Power is provided by the ASIC 26 through the dematching layer 12. Many ground paths are linked directly to the ultrasound system through the flex circuit 30 and then through the coaxial cable.

[0055] Figure 7 An alternative or additional ground path is shown. Since the flex circuit 30 can be located close to the acoustic stack, a bridge can be formed from or by the ground return layer 32 to the flex circuit 30. This ground path does not pass through the dematching layer 12 or the ASIC 26. The ground return layer is directly connected to the flex circuit 30. The ground input / output of the ASIC 26 can be routed through the dematching layer 12 to the flex circuit 30.

[0056] Figure 8 One embodiment of a method for connecting electronics to an array of acoustic elements is shown. A dematching layer, which extends beyond the piezoelectric layer and / or the remainder of the acoustic stack, is used to connect directly to an integrated circuit and to form contact pads for connection to a flexible circuit or other conductor for electrical communication with a scanner.

[0057] The method is implemented as manufacturing of array systems and / or probes. A technician or robot such as using a guide post or frame performs stacking and alignment. An oven, an iron, an induction soldering machine or a wave bath is used to perform bonding or interconnection. A frame, housing or bracket is used to form and position in a probe housing. A press can be used to add pressure for bonding or lamination.

[0058] Additional, different or fewer actions may be used. For example, action 84 for cutting is not performed if the transducer stack has been previously cut. As another example, action 86 is not performed if a subassembly is created.

[0059] The actions are performed in the order shown (ie, numerical order or order from top to bottom) or in other orders. For example, action 80 is performed after action 84 or action 86.

[0060] In action 80, an integrated circuit is directly connected to a surface of a dematching layer of an acoustic element. The connection is made using flip chip bonding, but other connections, such as rough contacts, may also be used. The connection is made without an intermediate layer. The integrated circuit is physically connected to the dematching layer as a chip using a flip chip connection. For example, copper posts are provided on the integrated circuit. The copper posts are to be used to connect the chip to the dematching layer, such as to a deposited electrode sheet of the dematching layer.

[0061] Heat may be applied to form physical and electrical connections. For solders, heat is generated by a soldering iron, induction solder, oven, or wave bath. For VCF or polymers, an oven or soldering iron may be used. Heat forms the interconnect. Higher temperatures than allowed by the acoustic module may be used, such as forming reliable electrical bonds at temperatures above 120°C. Temperatures above the Curie temperature or breakdown temperature of any component of the acoustic module may be used. Interconnects are formed at higher temperatures. Lower temperatures may be used.

[0062] In act 82, other acoustic layers are stacked on the dematching layer. The piezoelectric layer, one or more matching layers, and / or ground foil are stacked. Using posts and / or frames, the layers of the acoustic module are aligned and positioned against each other. The layers of the transducer are stacked together, but not yet bonded together.

[0063] The layers of transducers are stacked on the opposite side of the dematching layer from the integrated circuit. The dematching layer can protect the integrated circuit during formation of the acoustic stack.

[0064] A polymer, paste or other material for bonding is added to the stack, such as between and / or around the layers of the stack. For example, the bottom layer of the transducer (e.g., the dematching layer) is coated with an epoxy. A low temperature (e.g., below the Curie temperature or breakdown temperature of a portion of the acoustic module) curable polymer may be used.

[0065] The stack is pressed together in a vise to form a rough contact for electrical connection. The compressed stack is heated, such as by being positioned in an oven. The temperature of the oven is below the lowest of the Curie temperature or breakdown temperature of any component of the stack. The heat increases the rate and / or strength of the bond. The heat can activate the bond.

[0066] In one embodiment, the ground foil and / or one or more matching layers are stacked after dicing in act 84. The ground foil and / or one or more matching layers are stacked after dicing and then bonded to the rest of the already bonded and diced stack.

[0067] In act 84, the transducer stack is cut. A saw or laser is used to form cuts in the stack, thereby separating the stack into transducer elements. The cutting forms an array of acoustic elements from the piezoelectric slab.

[0068] The cut extends through the dematching layer. The cut forms a separated element of the array. The dematching layer is also cut along a portion of the dematching layer that extends beyond the footprint of the acoustic element or array. This portion of the dematching layer is used to connect to the ultrasound scanner. The cut separates the dematching layer to form contact pads for connection. The integrated circuit is connected to the dematching layer in the footprint of the array for receiving and transmitting signals from these elements. The integrated circuit is connected to the dematching layer outside the footprint of the array for communicating with the ultrasound scanner through the contact pads formed by the cut dematching layer.

[0069] Conductors for communicating with the ultrasound scanner are connected to the dematching layer in act 86. For example, traces on a flex circuit are connected to the dematching layer.

[0070] The connection is on the portion of the dematching layer that is outside the footprint of the array. The connection is on the same side of the dematching layer as the piezoelectric (the side opposite to the side to which the integrated circuit is connected). The portion of the dematching layer that extends outside the footprint of the acoustic element (the side opposite to the integrated circuit) is used for connection to the conductor.

[0071] The connection is made by rough contact. For example, epoxy is applied. A conductor (e.g., a flexible circuit with traces) is pressed onto the dematching layer and the epoxy is cured. Heat may be applied. The connection may be made while the acoustic stack is also being formed (i.e., bonding at the same time). Alternatively, the connection is made later without using any heat, or using heat less than the melting temperature of the epoxy used for the acoustic stack.

[0072] For this COA type ultrasonic transducer, testing can be provided in a way that avoids replacing certain expensive parts. The test is performed before the connection of action 86 (i.e., before the acoustic stack and integrated circuit are integrated with expensive components, such as flexible circuits containing FPGA (field programmable gate array), MUX (multiplexer) and SMT (surface mount technology) components and even coaxial cables). Aluminum pads or solder are very soft and therefore may be easily damaged during test detection. By using a harder and more rigid pad formed by a dematching layer (for example, in terms of Vickers hardness, the hardness of tungsten carbide (WC) is 24 times and 260 times that of aluminum and solder, respectively), it is unlikely to create a detection mark that may affect the formation of the joint during the test.

[0073] Although the present invention has been described above with reference to various embodiments, many changes and modifications can be made without departing from the scope of the present invention. Therefore, the foregoing detailed description is intended to be regarded as illustrative rather than restrictive, and it is to be understood that it is intended to define the spirit and scope of the present invention is the appended claims including all equivalents.

Claims

1. A transducer array system, comprising: an acoustic array having a distribution of transducer elements, the acoustic array having a first footprint; a dematching layer stacked with the acoustic array, the dematching layer having the transducer elements on a first side of the dematching layer, wherein a second footprint of the dematching layer extends beyond a first footprint of the acoustic array; an application specific integrated circuit chip on a second side of the dematching layer, the second side being opposite to the first side; as well as A flexible circuit material is connected to the dematching layer at an area where the second footprint of the dematching layer extends beyond the first footprint of the acoustic array.

2. The transducer array system of claim 1, wherein an acoustic stack comprises at least one matching layer, the transducer elements, and the dematching layer, and wherein the slits separating the transducer elements also separate the dematching layer.

3. The transducer array system of claim 1, wherein the dematching layer comprises tungsten carbide having an acoustic impedance greater than that of the transducer element. 4 . The transducer array system of claim 1 , wherein the chip has a third footprint along a first dimension including the region that is equal to or longer than the second footprint, the third footprint extending into the region.

5. The transducer array system of claim 4, wherein the dematching layer, the acoustic array, and the chip have an interval within 5% of each other along a second dimension, and wherein the interval of the second footprint and the third footprint along a first dimension perpendicular to the second dimension are within 5% of each other and are at least 10% larger than the interval of the first footprint along the first dimension.

6. The transducer array system of claim 1, wherein the application specific integrated circuit includes a beam forming circuit, and wherein the chip is directly bonded to a flip chip connector, and separate flip chip connectors are electrically connected to separate ones of the transducer elements.

7. The transducer array system of claim 6, wherein additional separate flip chip contacts electrically connect power, ground, beamformed outputs, and clock signals to the flexible circuit material through the dematching layer.

8. The transducer array system of claim 1, wherein the flex circuit is connected to the dematching layer using a rough bond, the rough bond electrically connecting the flex circuit to the dematching layer, which is electrically connected to the ASIC.

9. The transducer array system of claim 1 , wherein a first cutting slit separating the transducer elements extends through the dematching layer, the transducer elements formed by the cutting slit having a first pitch along a first dimension, and wherein, A second cutting kerf through the dematching layer in a region extending beyond the transducer element along a first dimension forms contact pads for the flexible circuit material, the contact pads having a second pitch greater than the first pitch.

10. The transducer array system of claim 1, wherein the flexible circuit material electrically connects traces to the dematching layer within one element width of the acoustic array.

11. The transducer array system of claim 1 , wherein a first ground path from the acoustic array to the flexible circuit material is connected through the dematching layer without passing through the chip.

12. The transducer array system of claim 1, wherein at least one ground path bridges the acoustic array and connects to the flexible circuit material without passing through the dematching layer or the chip.

13. An ultrasonic transducer probe, comprising: a chip-on-array arrangement of semiconductor chips electrically connected to a transducer array including transducers having a dematching layer; as well as Contact pads are formed on the dematching layer for electrical connection to an ultrasound imaging system, the dematching layer providing signal routing from the contact pads to the semiconductor chip and from the semiconductor chip to the transducer.

14. The ultrasound transducer probe of claim 13, further comprising a flexible circuit material connected to the contact pads by a rough contact.

15. The ultrasound transducer probe of claim 13, wherein transducer elements of the transducer array are connected to a first surface of the dematching layer, wherein the contact pads are formed on the first surface of the dematching layer, and wherein the semiconductor chip is flip-chip mounted to the dematching layer on a second surface opposite to the first surface.

16. The ultrasound transducer probe of claim 13, wherein a first slit separates elements of the transducer and extends through the dematching layer, and wherein a second slit forms the contact pad and extends through the dematching layer, the first slit and the second slit separating portions of the dematching layer for signal routing.

17. The ultrasound transducer probe of claim 13, wherein a first one of the contact pads is a ground connection pad, wherein the dematching layer connects the ground connection pad to an element of the transducer using a path separate from the semiconductor chip.

18. A method for connecting an electronic device to an array of acoustic elements, the method comprising: electrically connecting a chip having the electronic device to the dematching layer on a first side of the dematching layer; as well as A conductor is electrically connected to a second side of the dematching layer, the second side being opposite the first side, the conductor being connected to the second surface outside of a footprint on the dematching layer of the acoustic element.

19. The method of claim 18, wherein a portion of the dematching layer extends outside of a footprint of the acoustic element, wherein the integrated circuit extends outside of the footprint along the first side, wherein connecting the conductor comprises: Connecting a trace on a flexible circuit to the portion of the dematching layer that extends outside of the footprint.

20. The method of claim 18, wherein connecting the chip comprises: The connections are made using flip chip bonding and without an intervening layer.

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