Three-dimensional packaging RDL layer signal integrity optimization structure and manufacturing method

Abstract

The invention discloses a three-dimensional packaging RDL layer signal integrity optimization structure and a manufacturing method, particularly relates to the technical field of three-dimensional packaging structures, and solves the technical problem of low signal quality caused by the fact that a three-dimensional packaging structure in the prior art cannot effectively shield signal crosstalk. According to the technical scheme, the signal transmission performance can be effectively optimized by accurately adjusting parasitic capacitance between circuits, so that signal delay and loss are reduced, and signal integrity is improved; high-frequency noise can be suppressed by reasonably controlling parasitic capacitance, impedance matching is improved, a reflection coefficient is reduced, the anti-interference capability of a system is enhanced, and high-speed signal transmission is more stable and reliable.

Description

Technical Field

[0001] The present invention relates to the technical field of three-dimensional packaging structures, and in particular to a three-dimensional packaging RDL layer signal integrity optimization structure and a manufacturing method thereof. Background Art

[0002] With the rapid development of integrated circuit technology, 3D packaging has gradually become an important solution for high-performance electronic devices. Among them, the redistribution layer (RDL) plays a key role in achieving effective connection and signal transmission between chips. However, the design and implementation of RDL has a significant impact on signal integrity (SI), and has therefore become a hot topic in current research.

[0003] In 3D packaging, the RDL layer is mainly used to connect chips and package pins at different levels. Due to its complex structure and longer signal transmission path, signal integrity issues are becoming increasingly prominent. Common problems include signal delay, reflection, crosstalk, etc., which may affect the performance of the overall system. Therefore, in-depth research on the signal integrity of the RDL layer is the key to improving the performance of 3D packaging.

[0004] Current research focuses on the following aspects. First, for the optimization design of RDL structure, researchers have proposed a variety of methods to reduce signal transmission delay and improve transmission efficiency. For example, by optimizing the geometry and material selection of the RDL layer, signal loss can be effectively reduced. At the same time, the use of low dielectric constant (Low-k) materials is also widely used to reduce parasitic capacitance, thereby improving the speed and quality of signal transmission. Secondly, the advancement of signal integrity simulation technology also provides strong support for RDL design. By using advanced electromagnetic simulation software, designers can predict and optimize signal transmission at an early stage. These simulation tools can effectively evaluate the signal integrity under different design schemes and predict the performance under different environmental conditions through models, thereby avoiding problems in actual manufacturing. In addition, for the crosstalk problem in RDL, researchers have proposed a variety of solutions, such as optimizing wiring spacing and adopting differential signal transmission technology. The application of these technologies can significantly reduce the impact of crosstalk on signals and improve the anti-interference ability of the system. Finally, with the continuous increase in signal frequency, the research on RDL signal integrity also needs to be deepened. The characteristics of high-frequency signal transmission pose challenges to traditional design and analysis methods.

[0005] The existing literature "Research and Design of High-Frequency Electromagnetic Characteristics of Vertical Interconnections in Three-Dimensional System-Level Packages" proposes a new structure based on the basic ground-signal-ground-signal-ground (GSGSG). The traditional structure has a SiO2 layer between the metal layer and the silicon substrate, while the grounding in the new structure is directly in contact with the silicon substrate to enhance the shielding effect. This model analyzes the impact of the GSGSG structure on RDL signal transmission by establishing a simulation model. The model sets different RDL widths, layer thicknesses, and oxide layer thicknesses, and analyzes the performance of factors such as electron penetration and transmission speed at different temperatures. However, the simulation results show that the near-end coupling in the signal transmission performance is indeed greatly reduced, but the insertion loss is on the rise.

[0006] The existing literature "Research on Warpage and Transmission Delay Characteristics Based on TSV-Less FOWLP" compares the GS structure and the CPW structure. From the S parameter delay simulation results, it is concluded that the CPW structure is better than the GS structure. At the same time, the CPW structure with ground and the CPW structure without ground are analyzed. The study found that the performance of the CPW structure with ground is better than that without ground. The impact of parallel wiring and cross wiring structures on interconnection transmission delay is also analyzed. Insertion loss (S21) and delay simulation results of the two wiring structures. From the simulation results, it is concluded that the loss of the parallel interconnection structure is much smaller than that of the cross structure, and the delay time of the parallel structure is larger than that of the cross structure. Although this study compares the signal transmission performance of various existing models, including the arrangement method, wiring structure, etc., it does not take into account the increase in packaging volume, does not achieve the optimization of the structure of the model itself, and increases the volume of the package to a certain extent, which is not conducive to high-density integration.

[0007] The existing literature "Design and Simulation Analysis of High-Speed ​​Signal Wiring of Thick-Line 2.5D Silicon Adapter" clearly states that differential transmission lines can effectively suppress common-mode signals, and are therefore widely used in circuits with high requirements for signal transmission quality. Four transmission structures were studied, including GSSG structure (basic shielding structure) and microstrip line structure. The specific characteristics of each structure are different, such as metal spacing, transmission line width, etc. According to the simulation results, the microstrip line structure exhibits good high-frequency performance, and the differential structure exhibits higher signal transmission density in high-density packaging applications. Although the insertion loss and return loss of various differential transmission pairs were studied, there is more than one signal line in the redistribution layer, and near-end coupling will occur during signal transmission. The coupling will have a significant impact on the quality of the signal. This study lacks analysis of near-end coupling of signal transmission.

[0008] In the existing literature "Research on RDL Technology Based on WLCSP Packaging", the optimization of RDL signal transmission is achieved by adding grounding holes on both sides of the coplanar waveguide to reduce interference in transmission and improve signal transmission quality. This design can effectively shield the interference of external devices on the signal and improve the reliability and stability of the system. The isolation hole is grounded to ensure the protection function, thereby reducing transmission loss and improving transmission performance. However, this structure is more common in the existing TSV application market. It uses the ground hole characteristics and adds reference planes to return to the ground to achieve transmission optimization, which lacks novelty; adding grounding holes will occupy limited space on the PCB. For small-size, high-density electronic product designs, space resources may be more scarce, which is not conducive to achieving smaller package sizes; the design and layout of grounding holes may increase process complexity, requiring more precise wiring and welding processes, and increasing manufacturing costs and difficulties.

[0009] In summary: the prior art has the following disadvantages:

[0010] First, in the existing redistribution layer (RDL) signal integrity research, the models used are mostly simple, and usually analyzed in the form of a single-ended transmission line. These studies mainly focus on key indicators in transmission performance, such as insertion loss and return loss, to evaluate the attenuation and reflection of the signal during transmission. However, with the development of advanced packaging technology, the application scenarios of RDL are becoming more and more complex, and its signal lines usually exist in the form of multi-terminal transmission lines. This structure needs to consider more complex electromagnetic coupling effects in the package, especially the shielding performance between signal lines, which has not received enough attention in existing research. Insufficient shielding performance may lead to aggravation of problems such as signal crosstalk and electromagnetic interference (EMI), bringing new challenges to the signal integrity of high-speed and high-density packaging. Therefore, the optimization research on RDL models and shielding performance for multi-terminal transmission line structures has important academic value and practical significance.

[0011] Second, at present, the research on the design of the redistribution layer (RDL) for high-frequency signals is relatively weak, and it is difficult to adapt to the growing demand for high-frequency applications. With the rapid development of technologies such as wireless communications, 5G, and the Internet of Things, the system signal frequency continues to rise, and the limitations of existing RDL designs in high-frequency signal transmission are gradually emerging. However, most studies still remain in the low-frequency or medium-frequency range, and the exploration of the transmission characteristics of high-frequency signals in RDL structures is still insufficient. This leads to the lack of a comprehensive understanding of the mechanism and impact of signal integrity issues such as insertion loss, reflection loss, and near-end coupling in high-frequency environments, which in turn restricts the optimization design of high-frequency signals. With the continuous increase in application frequency, it is urgent to conduct in-depth high-frequency signal transmission analysis on RDL design to overcome the shortcomings of existing technologies in the high-frequency field and provide reliable signal integrity guarantees for the new generation of high-frequency applications.

[0012] Third, most of the research on the optimization of high-frequency signal transmission in the redistribution layer (RDL) is based on existing traditional models, such as coplanar waveguide (CPW), microstrip lines and other common structures, resulting in relatively insufficient technical innovation. These models have been widely used and verified in improving signal integrity, but their optimization potential is close to saturation, so it is difficult to further improve performance under the existing high-frequency requirements. These models usually rely on standardized design and manufacturing processes, which limits the innovative exploration of new materials, new structures and tiny packaging volumes.

[0013] Fourth, the optimization of the transmission performance of the redistribution layer (RDL) usually needs to be achieved by designing numerous vias or introducing a return ground plane. Although these design methods can effectively improve signal integrity and electrical performance, they will also significantly increase the complexity of the manufacturing process. In addition, this process requires high-precision process control and material selection, and often requires high-cost equipment support and stricter quality management. Therefore, in practical applications, how to simplify the process difficulty while improving transmission performance has become an important challenge in research and engineering implementation. Summary of the invention

[0014] Therefore, the present invention solves the technical problem that the three-dimensional packaging structure in the prior art cannot effectively shield signal crosstalk, resulting in low signal quality; the three-dimensional packaging RDL layer signal integrity optimization structure and manufacturing method provided by the present invention effectively shield signal crosstalk and optimize signal transmission quality, thereby improving the stability and reliability of the system; by introducing innovative designs on the RDL layer structure, the transmission performance of the redistribution layer signal line in the three-dimensional packaging is significantly improved, and the signal coupling and interference problems are effectively reduced, making it more suitable for high-frequency application environments. By accurately adjusting the parasitic capacitance between circuits, the signal transmission performance can be effectively optimized, thereby reducing signal delay and loss and improving signal integrity. Reasonable control of parasitic capacitance can suppress high-frequency noise, improve impedance matching, reduce reflection coefficient, and enhance the system's anti-interference ability, making high-speed signal transmission more stable and reliable.

[0015] The present invention provides a three-dimensional packaging RDL layer signal integrity optimization structure, comprising a substrate, on which an RDL signal line and an RDL ground line are arranged; a shielding metal groove is opened in the substrate; and the shielding metal groove passes through the substrate from front to back.

[0016] Furthermore, the cross-sectional shape of the shielding metal slot is an inverted "T" shape.

[0017] Furthermore, the substrate is a silicon substrate.

[0018] Furthermore, an insulating layer is provided between the silicon substrate and the RDL signal line and the RDL ground line.

[0019] Furthermore, the substrate is a glass substrate.

[0020] Furthermore, there are three RDL signal lines and two RDL ground lines, and the RDL signal lines and the RDL ground lines are arranged at intervals to form a GSGSG structure.

[0021] Furthermore, there are two RDL signal lines and two RDL ground lines; the two RDL ground lines are arranged between the two RDL signal lines to form a GSSG structure.

[0022] Furthermore, the RDL signal lines and the RDL ground lines are spaced at equal intervals.

[0023] Based on the original GSGSG or GSSG signal transmission model, an inverted "T"-shaped shielding metal groove is buried in the substrate of the three-dimensional packaging structure to accurately adjust the parasitic capacitance between circuits, reduce high-frequency interference between signal lines, and suppress high-frequency noise. By balancing the capacitance characteristics, high-speed signals can be more reliably transmitted between multiple channels, which is particularly suitable for modern high-frequency and high-density packaging needs. It effectively optimizes signal transmission performance, thereby reducing signal delay and loss and improving signal integrity.

[0024] The present invention also provides a method for manufacturing the three-dimensional packaging RDL layer signal integrity optimization structure based on the above-mentioned Fig.29 As shown in the figure, the red color is the substrate, the orange color is the photoresist, and the yellow color is the metal copper. The method includes the following steps

[0025] S1: Select a substrate, clean it, use ultrasonic cleaning, deionized water rinsing and drying to ensure that there is no contaminant on the surface of the substrate;

[0026] S2: uniformly coating a layer of photoresist, using a spin coater to control the spin coating speed and time to obtain the desired thickness; soft-baking the coated substrate to remove the solvent and enhance the adhesion of the photoresist;

[0027] S3: using a mask to expose the photoresist, using an exposure machine to perform ultraviolet light exposure to form a pattern of lateral etching pits, developing with a developer to dissolve the photoresist in the exposed area, revealing the area to be etched, and performing hard baking;

[0028] S4: Using a deep reactive ion etching (DRIE) method, placing the substrate in a DRIE device, and using plasma etching technology to form lateral etching pits on the substrate; controlling the etching depth and sidewall shape through a Bosch process (alternating cycles of etching and passivation) to obtain lateral etching pits with a high aspect ratio;

[0029] S5: depositing metal copper in the etched pits using chemical vapor deposition (CVD), physical vapor deposition (PVD) or electroplating technology; ensuring that the copper completely fills the etched pits and forms a lateral metal groove, removing the photoresist on the surface of the substrate using a solvent or oxygen plasma, and cleaning the substrate again;

[0030] S6: Select bonding technology or adhesive to stack a second substrate on the surface of the original substrate, evenly coat photoresist on the second substrate, perform photolithography patterning to form a pattern of vertical etched pits, and repeat the exposure, development and baking steps in S3 to ensure the accuracy of the photolithography pattern;

[0031] S7: Use DRIE technology to etch vertical etching pits on the second substrate to control the etching depth and accuracy; use CVD, PVD or electroplating technology to fill the vertical etching pits with metal copper to form vertical metal grooves; use solvent or plasma etching again to remove the photoresist and thoroughly clean the substrate surface;

[0032] S8: When the substrate is a silicon substrate, an insulating layer is set and RDL signal lines and ground lines are laid, and an insulating layer of silicon oxide SiO is deposited on the surface of the vertical metal groove and the surface of the substrate. 2 , using technologies such as chemical vapor deposition or spin coating of insulating polymers to achieve insulation layer coverage; then using photolithography and metal sputtering processes to lay RDL signal lines and ground lines on the insulation layer; defining the signal line pattern through photolithography, and then using copper or aluminum metal deposition to form the required signal transmission path and ground line;

[0033] S9: When the substrate is a glass substrate, a third substrate is stacked to enhance structural stability; the third substrate is firmly attached to the second substrate through an adhesive or bonding technology; the photolithography and metal deposition processes are repeated on the third substrate to lay RDL signal lines and ground lines.

[0034] In the above technical solution, the technical effects and advantages provided by the present invention are:

[0035] 1. The three-dimensional packaging RDL layer signal integrity optimization structure provided by the present invention achieves a high-efficiency coupling shielding effect by burying an inverted "T"-shaped metal plate in the silicon substrate and arranging it between two signal lines. While reducing mutual interference, it also significantly reduces the transmission loss of each signal line.

[0036] 2. The three-dimensional packaging RDL layer signal integrity optimization structure provided by the present invention greatly improves the return loss and optimizes the signal reflection, thereby greatly improving the signal integrity problem in the redistribution layer (RDL). It can be seen that this design can not only effectively improve the transmission performance of high-frequency signals, but also make the signal transmission more stable and reliable.

[0037] 3. The signal integrity optimization structure of the three-dimensional packaging RDL layer provided by the present invention adopts an embedded process method without increasing the volume of the original packaging body, which is in line with the development direction of continuously reducing the volume and achieving high integration in the post-Moore era.

[0038] 4. The three-dimensional packaging RDL layer signal integrity optimization structure provided by the present invention adopts a regular pattern, has a simple process implementation, and has a low manufacturing difficulty, which is conducive to promotion and application in production and provides a high-quality solution for high-density interconnection technology. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For ordinary technicians in this field, other drawings can also be obtained based on these drawings.

[0040] Figure 1 This is a GSGSG shielding structure diagram of the silicon substrate of the present invention;

[0041] Figure 2 This is a comparison diagram before and after optimization of the proximal coupling (S12) of the silicon substrate GSGSG shielding structure of the present invention;

[0042] Figure 3 This is a comparison diagram of the insertion loss (S13) of the silicon substrate GSGSG shielding structure of the present invention before and after optimization;

[0043] Figure 4 This is a comparison diagram of the return loss (S11) of the silicon substrate GSGSG shielding structure of the present invention before and after optimization;

[0044] Figure 5 This is a diagram of the GSSG shielding structure of the silicon substrate of the present invention;

[0045] Figure 6 This is a comparison diagram before and after optimization of the proximal coupling (S12) of the silicon substrate GSSG shielding structure of the present invention;

[0046] Figure 7 This is a comparison diagram of the insertion loss (S13) of the silicon substrate GSSG shielding structure of the present invention before and after optimization;

[0047] Figure 8 This is a comparison diagram of the return loss (S11) of the silicon substrate GSSG shielding structure of the present invention before and after optimization;

[0048] Fig. 9 This is a GSGSG shielding structure diagram of the glass substrate of the present invention;

[0049] Fig.10This is a comparison diagram before and after optimization of the proximal coupling (S12) of the glass substrate GSGSG shielding structure of the present invention;

[0050] Fig.11 This is a comparison diagram of the insertion loss (S13) of the glass substrate GSGSG shielding structure of the present invention before and after optimization;

[0051] Fig.12 This is a comparison diagram of the return loss (S11) of the glass substrate GSGSG shielding structure of the present invention before and after optimization;

[0052] Fig.13 This is a GSSG shielding structure diagram of the glass substrate of the present invention;

[0053] Fig.14 This is a comparison diagram before and after optimization of the proximal coupling (S12) of the glass substrate GSSG shielding structure of the present invention;

[0054] Fig.15 This is a comparison diagram of the insertion loss (S13) of the glass substrate GSSG shielding structure of the present invention before and after optimization;

[0055] Fig.16 This is a comparison diagram of the return loss (S11) of the glass substrate GSSG shielding structure of the present invention before and after optimization;

[0056] Fig.17 It is a diagram of the RLGC analytical model of the silicon substrate GSGSG shielding structure of the present invention;

[0057] Fig.18 This is a diagram of the RDL edge capacitance coupling model of the present invention;

[0058] Fig.19 This is a diagram of the RDL-SUB capacitive coupling model of the present invention;

[0059] Fig. 20 It is a diagram of the RLGC analytical model of the silicon substrate GSSG shielding structure of the present invention;

[0060] Fig.21 The circuit diagram of GSGSG-GLASS of the present invention is as follows;

[0061] Fig. 22 This is the GSGSG-Si circuit diagram of the present invention;

[0062] Fig.23 The GSSG-GLASS circuit diagram of the present invention;

[0063] Fig.24 This is the GSSG-Si circuit diagram of the present invention;

[0064] Fig.25 This is the GSGSG-Si result curve fitting diagram of the present invention;

[0065] Fig.26 It is the GSGSG-GLASS result curve fitting diagram of the present invention;

[0066] Fig. 27 This is the GSSG-Si result curve fitting diagram of the present invention;

[0067] Fig.28 It is the GSSG-GLASS result curve fitting diagram of the present invention;

[0068] Fig.29 This is a flow chart of the structure manufacturing of the present invention.

[0069] Description of reference numerals:

[0070] 1. RDL signal line; 2. RDL ground line; 3. Insulation layer; 4. Substrate; 5. Shielding metal groove. DETAILED DESCRIPTION

[0071] In order to enable those skilled in the art to better understand the technical solution of the present invention, the present invention will be further described in detail below with reference to the accompanying drawings.

[0072] Embodiment 1:

[0073] The present embodiment provides a three-dimensional packaging RDL layer signal integrity optimization structure, including a substrate 4, on which an RDL signal line 1 and an RDL ground line 2 are arranged; a shielding metal groove 5 is opened in the substrate 4; the shielding metal groove 5 passes through the substrate 4 from front to back. The cross-sectional shape of the shielding metal groove 5 is an inverted "T" shape. The substrate 4 is a silicon substrate. An insulating layer is arranged between the silicon substrate and the RDL signal line 1 and the RDL ground line 2. When there are three RDL signal lines 1 and two RDL ground lines, the RDL signal lines and the RDL ground lines are arranged alternately to form a GSGSG structure, such as Figure 1 As shown; when there are two RDL signal lines and two RDL ground lines; the two RDL signal lines are arranged between the two RDL ground lines to form a GSSG structure, such as Figure 5 shown.

[0074] At the same time, the following simulation experiments were carried out on the above structure;

[0075] First, model and simulate in HFSS to analyze the electromagnetic characteristics of the shielding structure, then extract simulation parameters and convert them into equivalent circuit models. Finally, import the parameters in ADS for circuit-level simulation verification to ensure that the shielding effect meets the design requirements.

[0076] First: In the silicon substrate, three RDL signal lines 1 and two RDL ground lines 2 are used. The RDL signal lines 1 and the RDL ground lines 2 are arranged alternately to form a GSGSG shielding structure to optimize the signal integrity, such as Figure 1As shown, according to the set size parameters, the model parameter table is shown in Table 1;

[0077] Table 1: Silicon substrate GSGSG (ground-signal-ground-signal-ground) shielding model parameter table

[0078] <![CDATA[T RDL (RDL thickness)]]> 5um <![CDATA[W RDL (RDL width)]]> 30um <![CDATA[S RDL (RDL spacing)]]> 30um <![CDATA[L RDL (RDL length)]]> 1000um <![CDATA[T Si (Thickness of silicon substrate)]]> 100um <![CDATA[W Si (Silicon substrate width)]]> 270um <![CDATA[T SiO2 (Insulation thickness)]]> 10um <![CDATA[H SHIED (Height of the longitudinal metal groove)]]> 30um <![CDATA[T SHIED (thickness of transverse metal groove)]]> 10um <![CDATA[W SHIED (width of the transverse metal groove)]]> 90um

[0079] Through HFSS modeling, the proximal coupling (S12), insertion loss (S13), and return loss (S11) of the original model and the existing model are compared. According to the HFSS simulation results, Figure 2-4 , the output curve of the original model is 1, and the output curve of the optimized model is 2.

[0080] Proximal coupling comparison (S12) Figure 2 As shown: According to the simulation results, from 0 to 50 Hz, the near-end coupling of the original model is between -80 dB and -25 dB, and the near-end coupling of the optimized model is between -100 dB and -40 dB, which optimizes the loss by nearly 20 dB.

[0081] Insertion loss comparison (S13) Figure 3 As shown: According to the simulation results, from 0 to 50 Hz, the insertion loss of the original model is between -0.16 dB and 0 dB, and the insertion loss of the optimized model is between -0.10 dB and 0 dB. The optimization effect is not obvious in the low frequency band, but the loss is optimized by nearly 0.06 dB in the high frequency band.

[0082] Return loss comparison (S11) Figure 4 As shown: According to the simulation results, from 0 to 50 Hz, the return loss of the original model is between -80dB and -27dB, and the return loss of the optimized model is between -87.5dB and -37.5dB, which optimizes the loss by nearly 10dB.

[0083] Second: In the silicon substrate, two RDL signal lines 1 and two RDL ground lines 2 are used; the two RDL ground lines 2 are arranged between the two RDL signal lines 1 to form a GSSG shielding structure for signal integrity optimization, such as Figure 5 As shown, according to the set size parameters, the model parameter table is shown in Table 2;

[0084] Table 2: Parameters of Silicon Substrate GSSG (Ground-Signal-Signal-Ground) Shielding Model

[0085]

[0086]

[0087] Through HFSS modeling, the proximal coupling (S12), insertion loss (S13), and return loss (S11) of the original model and the existing model are compared. According to the HFSS simulation results, Figure 6-8 , the output curve of the original model is 1, and the output curve of the optimized model is 2.

[0088] Proximal coupling comparison (S12) Figure 6 As shown: According to the simulation results, from 0 to 50 Hz, the near-end coupling of the original model is between -80 dB and -10 dB, and the near-end coupling of the optimized model is between -90 dB and -23 dB, which optimizes the loss by nearly 10 dB.

[0089] Insertion loss comparison (S13) Figure 7 As shown: According to the simulation results, from 0 to 50 Hz, the insertion loss of the original model is between -1.5 dB and 0 dB, and the insertion loss of the optimized model is between -0.2 dB and 0 dB, and the loss is optimized by nearly 1 dB in the entire frequency band.

[0090] Return loss comparison (S11) Figure 8 As shown: According to the simulation results, from 0 to 50 Hz, the return loss of the original model is between -65dB and -10dB, and the return loss of the optimized model is between -58dB and -20dB, which optimizes the loss by nearly 10dB.

[0091] Embodiment 2:

[0092] Different from the above embodiment, the substrate 4 in this embodiment is a glass substrate, and no insulating layer is provided between the substrate 4 and the RDL signal line 1 and the RDL ground line 2. The following simulation experiment is conducted on the above structure using the same method;

[0093] First: In the glass substrate, three RDL signal lines 1 and two RDL ground lines 2 are used. The RDL signal lines 1 and the RDL ground lines 2 are arranged alternately to form a GSGSG shielding structure to optimize the signal integrity, such as Fig. 9 As shown, according to the set size parameters, the model parameter table is shown in Table 3;

[0094] Table 3: Glass substrate GSGSG (ground-signal-ground-signal-ground) shielding model parameter table

[0095]

[0096]

[0097] Through HFSS modeling, the proximal coupling (S12), insertion loss (S13), and return loss (S11) of the original model and the existing model are compared. According to the HFSS simulation results, Figure 10-12, the output curve of the original model is 1, and the output curve of the optimized model is 2.

[0098] Proximal coupling comparison (S12) Fig.10 As shown: According to the simulation results, from 0 to 50 Hz, the near-end coupling of the original model is between -83dB and -25dB, and the near-end coupling of the optimized model is between -100dB and -43dB, which optimizes the loss by nearly 20dB.

[0099] Insertion loss comparison (S13) Fig.11 As shown: According to the simulation results, from 0 to 50 Hz, the insertion loss of the original model is between -0.16 dB and 0 dB, and the insertion loss of the optimized model is between -0.1 dB and 0 dB. The optimization effect is not very obvious in the low frequency band, but the loss is optimized by nearly 0.05 dB in the high frequency band.

[0100] Return loss comparison (S11) Fig.12 As shown: According to the simulation results, from 0 to 50Hz, the return loss of the original model is between -52dB and -25dB, and the return loss of the optimized model is between -62dB and -25dB. The overall optimization effect is not obvious, but it is not worse than the original model.

[0101] Second: In the glass substrate, two RDL signal lines and two RDL ground lines are used; two RDL ground lines 2 are arranged between the two RDL signal lines 1 to form a GSSG shielding structure to optimize the signal integrity, such as Fig.13 As shown, according to the set size parameters, the model parameter table is shown in Table 4;

[0102] Table 4: Glass substrate GSSG (ground-signal-signal-ground) shielding model parameter table

[0103]

[0104]

[0105] Through HFSS modeling, the proximal coupling (S12), insertion loss (S13), and return loss (S11) of the original model and the existing model are compared. According to the HFSS simulation results, Figure 14-16 , the output curve of the original model is 1, and the output curve of the optimized model is 2.

[0106] Proximal coupling comparison (S12) Fig.14 As shown: According to the simulation results, from 0 to 50 Hz, the near-end coupling of the original model is -83dB to -12dB, and the near-end coupling of the optimized model is -94dB to -35dB, which optimizes the loss by nearly 20dB.

[0107] Insertion loss comparison (S13) Fig.15 As shown: According to the simulation results, from 0 to 50 Hz, the insertion loss of the original model is -1.2dB to 0dB, and the insertion loss of the optimized model is -0.1dB to 0dB. In the full frequency band, the optimization effect is a loss of nearly 1dB.

[0108] Return loss comparison (S11) Fig.16 As shown: According to the simulation results, from 0 to 50 Hz, the return loss of the original model is between -60dB and -15dB, and the return loss of the optimized model is between -112dB and -45dB, which is an improvement of 35dB.

[0109] Comparing the simulation results of the above-mentioned Example 1 and Example 2, it can be seen that after the shielded metal slot is introduced on the basis of the original model, the electrical performance has been significantly improved in multiple key indicators. Specifically, the three aspects of proximal coupling (S12), insertion loss (S13) and return loss (S11) all show obvious optimization effects. The introduction of the shielded slot effectively reduces the mutual interference between signal lines and reduces proximal coupling (S12), thereby enhancing the signal isolation capability. At the same time, the insertion loss (S13) is reduced, which means that the energy loss of the signal during transmission is reduced, and the integrity of the signal can be better maintained. In addition, the return loss (S11) is also significantly improved, reflecting the reduction of signal reflection, which helps to suppress unnecessary noise and signal reflection interference, thereby further optimizing the signal quality. These improvements illustrate the effectiveness of the design of the shielded metal slot in improving signal integrity and anti-interference capabilities, and provide a more ideal solution for high-performance signal transmission. Based on the original GSGSG or GSSG signal transmission model, an inverted "T"-shaped shielding metal groove is buried in the substrate of the three-dimensional packaging structure to accurately adjust the parasitic capacitance between circuits, reduce high-frequency interference between signal lines, and suppress high-frequency noise. By balancing the capacitance characteristics, high-speed signals can be more reliably transmitted between multiple channels, which is particularly suitable for modern high-frequency and high-density packaging needs. It effectively optimizes signal transmission performance, thereby reducing signal delay and loss and improving signal integrity.

[0110] Next, the model parameters will be extracted. The specific steps include building an equivalent circuit model of the single-ended redistribution layer (RDL) structure and deriving analytical equations for its RLGC (resistance, inductance, conductance and capacitance) parameters. Through these analytical equations, the electrical characteristics of the structure can be preliminarily evaluated, such as key parameters such as transmission loss, characteristic impedance and its frequency response. In addition, the design will be verified with the help of ADS (Advanced Design System) simulation software, and an accurate simulation model will be established. By comparing the simulation results with the theoretical analysis, the accuracy of the analytical model will be verified, and the structure will be further optimized to ensure that the design can meet the performance requirements in practical applications.

[0111] GSGSG-RDL modeling parameter extraction: GSGSG on glass substrate and silicon substrate

[0112] In the (Ground-Signal-Ground-Signal-Ground) structure, the analytical models of the parasitic parameters of RLGC (resistance, inductance, conductance and capacitance) are highly similar. The main difference lies in the dielectric properties of the glass substrate. Since the glass substrate is an insulator, there is no coupling of parasitic conductance and capacitance between the redistribution layer (RDL) and the substrate, so there is no need to consider the conductance (G) and capacitance (C) components between the RDL layer and the substrate. In contrast, the silicon substrate has semiconductor properties, and its higher dielectric loss leads to an increase in the conductance path, while forming a parasitic capacitance between the RDL and the silicon substrate. This parasitic capacitance and conductance will significantly affect the loss and characteristic impedance of signal transmission, bringing certain challenges to the transmission performance of high-frequency signals.

[0113] Therefore, when extracting parameters, we can focus on the RLGC analytical model of the silicon substrate, because this model contains complete parasitic parameter information and can fully reflect the electrical characteristics of the RDL structure on the silicon substrate, such as Fig.17 As shown in the figure, the glass substrate can be regarded as a simplified version of the silicon substrate model. Only the conductance and capacitance coupling terms between the RDL and the substrate need to be removed, and the other parameters remain the same. Through this parameter extraction method, the electrical characteristics of the GSGSG structure of different substrate materials can be analyzed and compared more efficiently.

[0114] For RDL structure RDL , because the frequency band of this design will have a high frequency band in the range of 0 to 50 Hz, and high frequency will cause the skin effect of current, so the influence of frequency can be calculated by calculating the skin effect, so R RDL The analytical formula is:

[0115]

[0116]

[0117] Among them, R dc,RDL is the DC resistance of RDL, R ac,RDL is the AC resistance of RDL, ρ RDL is the resistivity of the RDL, δ skindepth,RDL is the skin depth of RDL, f is the signal frequency, μ RDL is the magnetic permeability of the RDL, σ RDL is the conductivity of the RDL.

[0118] For the RDL structure L RDL , because this design is based on a model similar to the loop inductance of a two-conductor transmission line model, so LRDL The analytical formula is:

[0119]

[0120] Where L signal is the self-inductance of the RDL signal line, L ground is the self-inductance of the RDL ground line, M is the mutual inductance between the RDL signal line and the ground line, μ 0 is the vacuum permeability, μ r,RDL is the relative permeability of the RDL.

[0121] Because the RDL structure is in contact with the silicon substrate and the insulating layer in the substrate, the edge capacitance in the air and the insulating layer must be considered, such as Fig.18 Here, the conformal transformation method is used to calculate these edge capacitances. RDL That is the superposition of these parallel capacitors.

[0122] C RDL =C air +C SiO2

[0123]

[0124] Among them, ε 0 is the dielectric constant of vacuum, ε r,air is the relative permittivity of air, ε r,SiO2 is the relative dielectric constant of the insulating layer, sinh is the hyperbolic sine function, and K is the complete elliptic integral function of the first kind.

[0125] Since the RDL is formed on a conductive silicon substrate, a capacitance C will appear between the RDL and the silicon substrate. RDL-SUB , respectively, the bottom capacitor C b and the fringe capacitance C f It should be noted that due to the position relationship between the G line in the middle and the shield structure, the C shied can be ignored, so solve for C RDL-SUB like Fig.19 shown.

[0126]

[0127] in,

[0128] But at the same time, the signal generates an electric field, which will cross into the silicon substrate. At the same time, the capacitance and conductivity in the silicon substrate need to appear. SUB and G SUB . Add a new parameter H eff is the effective penetration depth of the silicon substrate.

[0129]

[0130] in,

[0131]

[0132] h=H SiO2 +H Si ;

[0133] ε r,eff is the effective relative dielectric constant of the substrate in signal transmission, σ Si is the conductivity of the substrate, σ eff is the effective conductivity of the substrate, H eff is the effective penetration depth.

[0134] Since there is a horizontal plate in the inverted "T"-shaped plate, a voltage difference will be generated with the transmission signal RDL on the upper part of the insulation layer, thereby generating a parasitic capacitance C shied2 .

[0135]

[0136] GSSG-RDL modeling parameter extraction: GSSG on glass substrate and silicon substrate

[0137] (Ground-Signal-Signal-Ground) structure, such as Fig. 20 As shown in the figure, the analytical process of each parasitic parameter of RLGC (resistance, inductance, conductance and capacitance) is highly similar to that of GSGSG structure, so the solution formula of each parasitic parameter can be directly given. For this structure, the analytical models of the two substrates are consistent in most parameters, but due to the difference in substrate materials, the only significant difference is the presence or absence of parasitic capacitance and conductance between the redistribution layer (RDL) and the substrate of glass substrate and silicon substrate.

[0138] As an insulator, the dielectric constant and loss factor of the glass substrate are much lower than those of the silicon substrate, and there is no conductive path. Therefore, in the glass substrate, there is no need to consider the capacitance and conductivity between the RDL and the substrate. This simplification further reduces the signal loss of the glass substrate, making it more suitable for high-frequency signal transmission environments. The silicon substrate is different. Its semiconductor characteristics produce obvious parasitic capacitance and conductivity components, which directly affect the high-frequency characteristics of signal transmission and increase the signal loss during transmission.

[0139] Therefore, in parameter extraction, the complete RLGC model parameters can be given based on the silicon substrate first to fully consider the influence of its complex electrical characteristics. The glass substrate can be regarded as a simplified version of the model, and only the parasitic capacitance and conductance terms between the RDL and the substrate need to be removed during the extraction process. In this way, the electrical properties of the two substrate materials under the GSSG structure can be evaluated more efficiently and accurately, thereby providing reliable data support for substrate selection and design optimization in different application environments.

[0140]

[0141] Among them, R S is the resistance of the RDL signal line, R G is the resistance of the RDL ground line, R dc,S is the DC resistance of the RDL signal line, R ac,S is the AC resistance of the RDL signal line, R dc,G is the DC resistance of the RDL ground line, R ac,G is the AC resistance of the RDL ground line.

[0142] C RDL =C air +C SiO2 [F / m]

[0143]

[0144] Substitute the calculated RLGC parameters into the ADS (Advanced Design System) simulation environment for verification to further evaluate the electrical performance of the model. Construct the corresponding circuit model in ADS, establish an equivalent circuit according to the analytical parameters, and substitute the parasitic parameters. Figure 21-24 As shown in Figure 1, the simulation circuit topology of the GSSG structure in ADS is fully demonstrated. Fig.21 As shown, the GSGSG-Si circuit diagram is as follows Fig. 22 As shown, the GSSG-GLASS circuit is as follows Fig.23 As shown, the GSSG-Si circuit is as follows Fig.24 shown.

[0145] Next, the Origin drawing software will be used to perform fitting analysis on the ADS and HFSS simulation results to verify the accuracy of parameter extraction.

[0146] Specifically, the data of ADS simulation results and HFSS simulation results are first imported into Origin. By comparing and analyzing the key parameters such as insertion loss, return loss and near-end coupling of the two, fitting processing is performed to observe the degree of difference between the two. Here, the near-end coupling (S12) and insertion loss (S13) of RDL are performed on the two structures based on silicon substrate, and the return loss (S11) and insertion loss (S12) of RDL are performed on the two structures based on glass substrate. GSGSG-Si Fig.25 As shown, GSGSG-GLASS Fig.26 As shown, GSSG-Si Fig. 27 As shown, GSSG-GLASS Fig.28 shown.

[0147] Through ADS simulation verification, the fitting analysis of parasitic parameter extraction of four structures was successfully completed, and the results showed that the model has a high degree of accuracy. The parameters of the ADS simulation data and the theoretical analytical model show good consistency, which verifies the reliability and accuracy of the model in describing the electrical characteristics of GSGSG and GSSG structures. This verification process ensures the accuracy of the parameter extraction method, and further shows that the constructed RLGC model can effectively reflect the parasitic characteristics of the actual structure.

[0148] The above description is only by way of illustration of certain exemplary embodiments of the present invention. It is undoubted that those skilled in the art can modify the described embodiments in various ways without departing from the spirit and scope of the present invention. Therefore, the above drawings and descriptions are illustrative in nature and should not be construed as limiting the scope of protection of the claims of the present invention.

Claims

1. A three-dimensional packaging RDL layer signal integrity optimization structure, characterized in that: It comprises a substrate (4), on which an RDL signal line (1) and an RDL ground line (2) are respectively arranged; a shielding metal groove (5) is opened in the substrate (4); and the shielding metal groove (5) passes through the substrate (4) from front to back.

2. The three-dimensional packaging RDL layer signal integrity optimization structure according to claim 1, characterized in that: The shielding metal groove (5) consists of a transverse metal groove and a longitudinal metal groove, and its cross-sectional shape is an inverted "T" shape.

3. The three-dimensional packaging RDL layer signal integrity optimization structure according to claim 2, characterized in that: The substrate (4) is a silicon substrate (4).

4. The three-dimensional packaging RDL layer signal integrity optimization structure according to claim 3, characterized in that: An insulating layer (3) is provided between the silicon substrate (4) and the RDL signal line (1) and the RDL ground line (2).

5. The three-dimensional packaging RDL layer signal integrity optimization structure according to claim 2, characterized in that: The substrate (4) is a glass substrate (4).

6. The three-dimensional packaging RDL layer signal integrity optimization structure according to claim 4 or 5, characterized in that: There are three RDL signal lines (1) and two RDL ground lines (2), and the RDL signal lines (1) and the RDL ground lines (2) are arranged at intervals to form a GSGSG structure.

7. The three-dimensional packaging RDL layer signal integrity optimization structure according to claim 4 or 5, characterized in that: There are two RDL signal lines (1) and two RDL ground lines (2); the two RDL ground lines (2) are arranged between the two RDL signal lines (1) to form a GSSG structure.

8. The three-dimensional packaging RDL layer signal integrity optimization structure according to claim 3, characterized in that: The distances between the RDL signal lines (1) and the RDL ground lines (2) are equal.

9. A method for manufacturing a three-dimensional packaging RDL layer signal integrity optimization structure based on any one of claims 1 to 9, characterized in that: The steps include: S1: Select a substrate (4), clean the substrate (4), use ultrasonic cleaning, deionized water rinsing and drying to ensure that there is no contaminant on the surface of the substrate (4); S2: uniformly apply a layer of photoresist, using a spin coater to control the spin coating speed and time to obtain the desired thickness; The coated substrate is soft-baked to remove the solvent and enhance the adhesion of the photoresist; S3: using a mask to expose the photoresist, using an exposure machine to perform ultraviolet light exposure to form a pattern of lateral etching pits, developing with a developer to dissolve the photoresist in the exposed area, revealing the area to be etched, and performing hard baking; S4: Using a deep reactive ion etching (DRIE) method, placing the substrate in a DRIE device, and using plasma etching technology to form lateral etching pits on the substrate; controlling the etching depth and sidewall shape through a Bosch process (alternating cycles of etching and passivation) to obtain lateral etching pits with a high aspect ratio; S5: depositing metal copper in the etched pits using chemical vapor deposition (CVD), physical vapor deposition (PVD) or electroplating technology; ensuring that the metal copper completely fills the etched pits and forms a lateral metal groove, removing the photoresist on the surface of the substrate using a solvent or oxygen plasma, and cleaning the substrate again; S6: Selecting a bonding technique or an adhesive to stack a second substrate (4) on the surface of the original substrate (4), uniformly coating the second substrate (4) with photoresist, performing photolithography patterning to form a pattern of vertical etching pits, and repeating the exposure, development and baking steps in S3 to ensure the accuracy of the photolithography pattern; S7: using DRIE technology to etch vertical etching pits on the second substrate (4), controlling the etching depth and precision; similarly using CVD, PVD or electroplating technology to fill the vertical etching pits with metal copper to form vertical metal grooves; again using solvent or plasma etching to remove the photoresist, and thoroughly cleaning the substrate surface; S8: When the substrate (4) is a silicon substrate, an insulating layer is provided and RDL signal lines and ground lines are laid, a layer of insulating silicon oxide SiO2 is deposited on the surface of the vertical metal groove and the surface of the substrate (4), and a chemical vapor deposition or spin coating insulating polymer and other technologies are used to achieve insulating layer coverage; then, RDL signal lines (1) and RDL ground lines (2) are laid on the insulating layer using photolithography and metal sputtering processes; the signal line pattern is defined by photolithography, and then copper or aluminum metal is deposited to form the required signal transmission path and ground line; S9: When the substrate (4) is a glass substrate, a third substrate (4) is stacked to enhance structural stability; the third substrate (4) is firmly attached to the second substrate (4) by an adhesive or bonding technology; and the photolithography and metal deposition processes are repeated on the third substrate (4) to lay RDL signal lines (1) and RDL ground lines (2).

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