Semiconductor structure and forming method thereof

Abstract

The invention discloses a semiconductor structure and a forming method thereof. The semiconductor structure comprises a substrate and a word line. The substrate is provided with a plurality of active areas and a plurality of non-active areas, and the active areas and the non-active areas are alternately arranged in the first direction and extend in the second direction. The word lines are arranged on the active areas and the non-active areas in a crossing mode, and each word line comprises a plurality of first conductive parts located on the corresponding active areas, a plurality of isolation columns located on the corresponding non-active areas, a gate dielectric layer located on the first conductive parts and the isolation columns, and a second conductive part located on the gate dielectric layer and extending in the first direction. The first conductive parts and the isolation columns are alternately arranged in the first direction, the protruding pieces of the second conductive parts correspond to a plurality of non-active areas, and the isolation columns are located on the opposite sides of the corresponding protruding pieces along the section of the second direction on the non-active areas. Therefore, the word line prepared by the method has a good profile, so that the applied semiconductor structure has good electrical performance.

Description

Technical Field

[0001] The present invention relates to a semiconductor structure and a method for forming the same, and in particular to a semiconductor structure and a method for forming the same which can reduce parasitic capacitance and improve electrical performance. Background Art

[0002] Currently, semiconductor manufacturing technology is striving towards miniaturization of device size, which is accompanied by many challenges. For example, in the process of flash memory, a patterning process must be performed to separate the stacked structures from each other to form word lines. However, if the material layer to be etched has a height difference, over-etching is required to completely remove the material layer to be etched, which also leads to the occurrence of lateral etching effect and lateral etching of the sidewalls of the stacked structure, damaging the profile of the stacked structure. Summary of the invention

[0003] An embodiment of the present invention provides a semiconductor structure, including a substrate and a word line above the substrate. The substrate has a plurality of active areas and a plurality of inactive areas, the active areas and the inactive areas are alternately arranged in a first direction and extend along a second direction. The word line is arranged across the active areas and the inactive areas, and the word line includes a plurality of first conductive parts, which are located on the corresponding active areas; a plurality of isolation pillars, which are located on the corresponding inactive areas, and the plurality of first conductive parts and the plurality of isolation pillars are alternately arranged in the first direction; a gate dielectric layer, which is located on the plurality of first conductive parts and the plurality of isolation pillars; and a second conductive part, which is located on the gate dielectric layer and extends along the first direction, the protrusions of the second conductive part correspond to the plurality of inactive areas, wherein in the cross section along the second direction on the plurality of inactive areas, the isolation pillars are located on the opposite side of the corresponding protrusions.

[0004] Some embodiments of the present invention provide a method for forming a semiconductor structure, including providing a substrate having a plurality of active regions and a plurality of inactive regions, the plurality of active regions and the plurality of inactive regions being alternately arranged in a first direction and extending along a second direction; and forming a word line above the aforementioned substrate, and the word line is arranged across the aforementioned active regions and the aforementioned inactive regions. In some embodiments, the word line includes a plurality of first conductive portions, which are located on the corresponding plurality of active regions; a plurality of isolation pillars, which are located on the corresponding plurality of inactive regions, and the plurality of first conductive portions and the plurality of isolation pillars are alternately arranged in the aforementioned first direction; a gate dielectric layer, which is located on the aforementioned first conductive portions and on the aforementioned isolation pillars; and a second conductive portion, which is formed on the aforementioned gate dielectric layer and extends along the aforementioned first direction, and the protrusions of the second conductive portion correspond to the plurality of inactive regions, wherein in the cross section along the second direction on the plurality of inactive regions, the isolation pillars are located on the opposite side of the corresponding protrusions.

[0005] In the present invention, in each active area, the overall stack of the word line has a complete and good profile, and the first conductive part and the active area below and the second conductive part above all have a sufficient and complete overlapping area, so the semiconductor structure obtained later has good electrical performance. And the first conductive part of the word line and the active area below, as well as the first conductive part and the second conductive part above all have a sufficient and complete overlapping area, without the problem of sidewall concave. Therefore, the word line obtained according to the embodiment has a good profile, so that the applied semiconductor structure has good electrical performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 , Figure 2 , Figure 3 , Figure 4 , Figure 4A , Figure 4B , Figure 5 , Figure 5A , Figure 5B , Figure 6 , Fig. 6A and Figure 6B are cross-sectional schematic diagrams of semiconductor structures at various intermediate manufacturing stages according to some embodiments of the present invention;

[0007] Figure 2A and Figure 2B is a partial top view of a semiconductor structure in a memory cell according to some embodiments of the present invention;

[0008] Figure 7 shows a top view of a semiconductor structure at an intermediate manufacturing stage;

[0009] Fig. 8A A schematic diagram showing an intermediate manufacturing stage of forming a word line by a conventional method;

[0010] Figure 8B Shown corresponding to Fig. 8A A cross-sectional view of a conventional word line along line 8B-8B in FIG.

[0011] Fig. 9A A schematic diagram showing an intermediate manufacturing stage of a method for forming a word line according to some embodiments of the present invention;

[0012] Fig. 9B Shown corresponding to Fig. 9A A cross-sectional view of the word line along line 9B-9B in FIG.

[0013] Explanation of symbols

[0014] 10: Substrate

[0015] A1: Active area

[0016] A2: Non-active area

[0017] 10a, 12a, 120a, 14a, 142a, 143a, 143P-a, 181a, 180M-a: top surface

[0018] 11: Tunneling dielectric layer

[0019] 12, 32: first conductive material

[0020] 12s, 120s, 141s, 143P-s, 160s, 180s, 180P-s, 320s, 360s, 380s: Sidewall

[0021] 120, 120-1, 120-2, 320: first conductive part

[0022] 120-1i, 120-2i: inner wall

[0023] 143P-o: Outer wall

[0024] 14: Isolation material

[0025] 141: Depression

[0026] 142: Isolation Structure

[0027] 143: Isolation Island

[0028] 143P: Isolation column

[0029] 15: Mask

[0030] 151: Stripe pattern

[0031] 152: Gap between stripe patterns

[0032] 16,36: Gate dielectric material

[0033] 160, 360: gate dielectric layer

[0034] 161: First oxide layer

[0035] 162: Nitride layer

[0036] 163: Second oxide layer

[0037] 160A: The first part of the gate dielectric layer

[0038] 160B: The second part of the gate dielectric layer

[0039] 160C: The third part of the gate dielectric layer

[0040] 18: Second conductive layer

[0041] 180, 380: second conductive part

[0042] 181: Main layer

[0043] 180P, 182: protruding parts

[0044] 180M: Main body

[0045] 141b, 181b: bottom surface

[0046] 180P-b, 182b: bottom surface

[0047] 20: Word Line

[0048] AW: word line area

[0049] 21: Gap between word line areas

[0050] WM, WL, W1, W2: Width

[0051] DS: Dielectric Stack

[0052] DS1: First dielectric structure

[0053] DS2: Second dielectric structure

[0054] AA, BB, 1-1, 2-2, 8B-8B, 9B-9B: Line

[0055] D1: First direction

[0056] D2: Second direction

[0057] D3: Third direction DETAILED DESCRIPTION

[0058] The semiconductor structure and the method for forming the same provided in the embodiments of the present invention may be applied to a non-volatile memory structure, such as a flash memory, but the present invention is not limited thereto.

[0059] Reference Figure 1 , providing a substrate 10. The substrate 10 has a plurality of grooves recessed from a top surface 10a. Then, a tunnel dielectric layer 11 is conformally formed along the sidewalls and top surfaces of the grooves to cover the substrate 10. The substrate 10 has a plurality of active areas A1 and inactive areas A2, and the active areas A1 are separated by the grooves. The active areas A1 and the inactive areas A2 are alternately arranged along a first direction D1 (X direction) and extend along a second direction D2 (Y direction). The second direction D2 and the first direction D1 may be perpendicular to each other.

[0060] A plurality of first conductive materials 12 are formed on the tunnel dielectric layer 11 and correspond to the active area A1. A plurality of isolation materials 14 are located in the trench and correspond to the inactive area A2. The first conductive materials 12 and the isolation materials 14 extend along the second direction D2 and are alternately arranged in the first direction D1. The top surface 14a of the isolation material 14 may be coplanar with the top surface 12a of the first conductive material 12.

[0061] The material of the substrate 10 may include silicon, gallium arsenide, gallium nitride, silicon germanium, silicon on insulator (SOI), other suitable materials, or a combination of the above materials. The material of the tunnel dielectric layer 11 may include oxide or a high dielectric constant material, for example.

[0062] The first conductive material 12 may include polysilicon, other suitable conductive materials, or a combination thereof. In the application of the non-volatile memory structure, the first conductive material 12 may form the bottom gate of each functional bit, such as a floating gate, in a subsequent process. The first conductive material 12 may be formed by a deposition process and a patterning process.

[0063] Furthermore, a dielectric material is formed on the substrate 10 and fills the aforementioned trench. The dielectric material may include an oxide, such as silicon oxide. The isolation material 14 may be a single layer or a multi-layer structure. In one example, the isolation material 14 includes an oxide liner and a dielectric filling layer.

[0064] Reference Figure 2 A mask 15 is provided above the substrate 10. The mask 15 is, for example, a patterned photoresist. The mask 15 includes a plurality of strip patterns 151 separated by gaps 152 between the strip patterns. Specifically, the strip patterns 151 extend along the first direction D1 and cross and cover a portion of the isolation material 14 and the first conductive material 12. The gaps 152 between the strip patterns expose another portion of the isolation material 14 and the first conductive material 12.

[0065] Figure 2A and Figure 2B FIG. 1 is a partial top view of a semiconductor structure of a memory cell according to an embodiment of the present invention. The memory cell has a plurality of word line regions A extending in a first direction D1. W , and a plurality of active regions A1 extending in the second direction D2. The word lines (eg Figure 6 The word line 20 shown is located in the word line area A W and separated from each other.

[0066] In the second direction D2, the word line region A W The gap 21 between the word line regions, the stripe pattern 151, and the gap 152 of the stripe pattern have widths W1, W2, W3, W4, W5, W6, W7, W8, W9, W10, W11, W12, W13, W14, W15, W16, W17, W18, W19, W20, W21, W22, W23, W24, W25, W L , W MThe strip pattern 151 may be disposed corresponding to the gap 21 between two adjacent word line regions, and at least adjacent to the word line regions A on both sides. W Partial overlap.

[0067] According to this example, the width W of the stripe pattern 151 is M Greater than the width W of the gap 21 between the word line regions L And, word line region A W The width W1 of the stripe pattern is greater than the width W2 of the gap 152 of the stripe pattern.

[0068] According to some embodiments, after forming a mask 15 above the substrate 10, a portion of the isolation material 14 not covered by the stripe pattern 151 is removed, and the isolation material 14 is recessed to form a plurality of recesses 141 as shown in FIG. 3. In some embodiments, the bottom of the recess 141 is flush with the top surface 10a of the substrate 10 or slightly higher than the top surface 10a of the substrate 10.

[0069] The exposed isolation material 14 may be removed by an etching process according to an etching selectivity ratio between the isolation material 14 and the first conductive material 12 .

[0070] Thereafter, the mask 15 is removed by, for example, an ashing process.

[0071] The remaining portion of the isolation material 14 includes a recessed isolation structure 142 and an isolation island 143 protruding from the isolation structure 142. The isolation islands 143 are separated from each other by the recesses 141 in the second direction D2, and are separated from each other by the first conductive material 12 in the first direction D1. In other words, in the non-active area A2, the isolation islands 143 and the recesses 141 are alternately formed.

[0072] According to this example, the width W2 of the gaps 152 of the stripe pattern is also the width W2 of the recesses 141 (in the second direction D2 ).

[0073] It is worth noting that, unlike the conventional process in which the entire isolation material 14 is recessed, the process of the embodiment of the present invention is to recess part of the isolation material 14 to form a plurality of recesses 141 and isolation islands 143 .

[0074] Figure 4A and Figure 4B The Figure 4 14 is a schematic cross-sectional view taken along line AA and line BB, wherein line AA corresponds to the position of the isolation island 143, and line BB corresponds to the position of the recess 141. Figure 4 , Figure 4A and Figure 4BThe gate dielectric material 16 is formed to cover the top surface 143a of the isolation island 143 and the top surface 12a of the first conductive material 12, and is conformably formed on the sidewalls 141s and the bottom surface 141b of the recess 141. The bottom surface 141b of the recess 141 is also the top surface 142a of the recessed isolation structure 142.

[0075] Although the gate dielectric material 16 corresponding to the recess 141 is conformal with the recess 141 and presents an undulating surface with height differences, the gate dielectric material 16 corresponding to the isolation island 143 presents a flat surface because it is supported by the top surface 143a of the isolation island 143 and the top surface 12a of the first conductive material 12.

[0076] The gate dielectric material 16 may be a multi-layer structure and may include oxide, nitride, or a combination of the foregoing materials. In one embodiment, the gate dielectric material 16 includes a first oxide layer 161, a nitride layer 162, and a second oxide layer 163 from bottom to top, such as silicon oxide / silicon nitride / silicon oxide, but the present invention is not limited thereto, and the gate dielectric material 16 may also be a single-layer structure or a more complex multi-layer structure.

[0077] In some embodiments, the gate dielectric material 16 may be formed by physical vapor deposition, chemical vapor deposition, atomic layer deposition, other suitable processes, or a combination of the aforementioned processes.

[0078] Figure 5A and Figure 5B Shown along Figure 5 , wherein line AA corresponds to the position of the isolation island 143, and line BB corresponds to the position of the recess 141. Figure 5 , Figure 5A and Figure 5B , a second conductive layer 18 is formed on the gate dielectric material 16 to fill the remaining space outside the gate dielectric material 16 in the recess 141 .

[0079] Specifically, the second conductive layer 18 includes a main body layer 181 and a plurality of protrusions 182. The main body layer 181 is located above the isolation island 143 and the first conductive material 12, and has a top surface 181a and a bottom surface 181b opposite to each other. The protrusions 182 are located below the bottom surface 181b of the main body layer 181 and protrude from the bottom surface 181b toward the substrate 10, and the lower surface 182b of the protrusions 182 is away from the main body layer 181. Furthermore, the protrusions 182 are located in the remaining space outside the gate dielectric material 16 in the recess 141, so that the sidewalls and the lower surface 182b of the protrusions 182 are surrounded and covered by the gate dielectric material 16. In some examples, the protrusions 182 correspond to the non-active area A2, and the protrusions 182 are spaced apart from each other according to the position of the recess 141.

[0080] The second conductive layer 18 may be a single-layer structure or a multi-layer structure, for example, including polysilicon, metal, metal silicide or other conductive materials. In this embodiment, the second conductive layer 18 includes polysilicon.

[0081] The second conductive layer 18 may be formed by a deposition process, such as a physical vapor deposition process, a chemical vapor deposition process, an atomic layer deposition process, other suitable processes, or a combination of the foregoing processes.

[0082] Reference Figure 6 The second conductive layer 18, the gate dielectric material 16, the isolation island 143 and the first conductive material 12 are patterned to form a plurality of word lines 20 above the substrate 10. The word lines 20 are spaced apart in the second direction D2 and extend along the first direction D1, and are placed on alternating active areas A1 and inactive areas A2.

[0083] The word line 20 includes a plurality of first conductive portions 120 located on the corresponding active area A1, and a plurality of isolation pillars 143P located on the corresponding non-active area A2. The isolation pillars 143P are the remaining portions of the isolation islands 143 after the patterning process. In some embodiments, the word line 20 further includes a gate dielectric layer 160 and a second conductive portion 180. The gate dielectric layer 160 covers the top surface 120a of the first conductive portion 120 and the top surface 143P-a of the isolation pillars 143P. The second conductive portion 180 is located on the gate dielectric layer 160. It is worth noting that the first conductive portions 120 and the isolation pillars 143P are alternately arranged along the first direction D1.

[0084] In the application of flash memory, the first conductive portion 120 and the second conductive portion 180 can be used as a floating gate and a control gate, respectively.

[0085] According to some embodiments, a plurality of word lines 20 may be formed by a deposition process, a photolithography patterning process, and an etching process. For example, a hard mask material (not shown) may be formed on the second conductive layer 18. Then, a patterned photoresist corresponding to the position of the word line 20 is formed on the hard mask material, and the hard mask material is etched according to the patterned photoresist to form a hard mask. Thereafter, the patterned photoresist is removed, and the material layer and components below are etched according to the hard mask. In some embodiments, the etching process may include a dry etching process, a wet etching process, a plasma etching process, a reactive ion etching process, other suitable processes, or a combination of the foregoing processes.

[0086] Please also refer to Figure 6 , Fig. 6A and Figure 6B . Fig. 6A , Figure 6B Shown along Figure 6A three-dimensional schematic diagram of the line 1-1 corresponding to the active area A1 and the line 2-2 corresponding to the inactive area A2. Fig. 6A A cross section of the first conductive portion 120 , the gate dielectric layer 160 , and the second conductive portion 180 in the active area A1 is shown. Figure 6B A cross section of the second conductive portion 180 , the gate dielectric layer 160 , and the isolation pillar 143P in the non-active area A2 is shown.

[0087] When viewed from the second direction D2, the top surface 120a of the first conductive portion 120 and the top surface 143P-a of the isolation pillar 143P are coplanar. Therefore, the gate dielectric layer 160 extends at the same level.

[0088] Each isolation column 143P has two opposite side walls 143P-s, and the two side walls 143P-s respectively contact the inner side walls 120 - 1 i and 120 - 2 i of two adjacent first conductive portions.

[0089] Furthermore, the sidewall 120s of the first conductive portion 120 and the outer sidewall 143P-o of the isolation column 143P are coplanar.

[0090] like Figure 6 , Fig. 6A As shown, in each active area A1, the overall stack of the word line 20 has a complete and good profile, and the first conductive portion 120 has a sufficient and complete overlapping area with the active area A1 below and the second conductive portion 180 above, so that the subsequently manufactured semiconductor structure has good electrical performance, such as better word line coupling and a more stable erase operation threshold voltage.

[0091] like Figure 6 and Figure 6B As shown, the cross section of the word line 20 in the non-active area A2 shows a dielectric structure with a U-shaped cross section in the recess 141. The dielectric structure includes a gate dielectric layer 160 with a U-shaped cross section (which can be regarded as a first dielectric structure), and an isolation component with a U-shaped cross section (including an isolation column 143P and a recessed isolation structure 142, and can be regarded as a second dielectric structure). Details are described later.

[0092] Can refer to Figure 3 , Figure 4 , Figure 6B and Figure 7 . Figure 7 The top cross-sectional view after forming the gate dielectric layer 160 is shown, including a recess 141, two first conductive parts 120-1, 120-2 and two opposite isolation columns 143P, and the two opposite isolation columns 143P respectively connect the adjacent first conductive part 120-1 and the first conductive part 120-2. Figure 7The gate dielectric layer 160 on the first conductive portion 120 and the isolation column 143P is also deposited along the sidewalls of the recess 141 and covers the bottom of the recess 141 (not shown). The gate dielectric layer 160 on the recess 141 is annular, and the protrusion 180P subsequently filled into the recess 141 is surrounded by the gate dielectric layer 160.

[0093] According to some embodiments, the word line 20 has a recess 141 at the non-active area A2, and the gate dielectric layer 160 is conformally deposited at the recess 141 and retracted into the word line region, wherein the recess 141 is defined by the inner sidewalls 120-1i and 120-2i of the adjacent first conductive portion 120 and two opposing isolation pillars 143P. Therefore, the gate dielectric layer 160 covers the top surface 143P-a and the inner sidewall (not shown) of the isolation pillar 143P, and covers the top surface 12a and the inner sidewalls 120-1i and 120-2i of the first conductive portion 120.

[0094] like Figure 6 , Figure 6B and Figure 7 As shown, after forming the word line 20, the gate dielectric layer 160 includes a first portion 160A of the gate dielectric layer located on the top surface 12a of the first conductive portion 120, a second portion 160B of the gate dielectric layer located on the top surface 143P-a of the isolation column 143P, and a third portion 160C of the gate dielectric layer located in the recess 141.

[0095] Specifically, the first portion 160A of the gate dielectric layer and the second portion 160B of the gate dielectric layer are alternately arranged in the extending direction of the word line 20. Since the top surface 143P-a of the isolation column 143P and the top surface 12a of the first conductive portion 120 are substantially flush, the first portion 160A of the gate dielectric layer and the second portion 160B of the gate dielectric layer are substantially coplanar.

[0096] like Figure 6B As shown, the lower portion of the second conductive portion 180 in the non-active area A2 (i.e., the protrusion 180P described later) is surrounded by the dielectric stack DS. The dielectric stack DS has a U-shaped cross-section in the cross-section along the second direction D2. Specifically, the dielectric stack DS includes a first dielectric structure DS1 and a second dielectric structure DS2. The first dielectric structure DS1 is composed of the second portion 160B of the gate dielectric layer 160 and the third portion 160C of the gate dielectric layer. The first dielectric structure DS1 has a U-shaped cross-section in the cross-section along the second direction D2 ( Figure 6B ), and also has a U-shaped cross section along the first direction D1 ( Figure 5B). Furthermore, the third portion 160C of the gate dielectric layer at the recess in the non-active area A2 also has a U-shaped cross section in the cross section along the second direction D2. The second dielectric structure DS2 is composed of the connected isolation pillars 143P and the recessed isolation structure 142, and has a U-shaped cross section in the cross section along the second direction D2.

[0097] According to some embodiments, the isolation column 143P and the recessed isolation structure 142 are integrally formed. Figure 6B ,and Figure 7 It should be noted that, since the isolation column 143P does not cover the inner sidewall of the first conductive portion 120 that is perpendicular to the extension direction of the word line 20 , the second dielectric structure DS2 does not have a U-shaped cross-section in the cross-section along the extension direction of the word line 20 .

[0098] Reference Figure 6B The second conductive portion 180 of the word line 20 includes a main body 180M and a plurality of protrusions 180P. The main body 180M is located above the isolation column 143P and the first conductive material 12. The protrusions 180P are located below the bottom surface of the main body 180M and protrude from the bottom surface toward the substrate 10. The lower surface 180P-b of the protrusion 180P is away from the main body 180M.

[0099] The protrusion 180P is located in the remaining space outside the gate dielectric layer 160 in the recess 141, so that all sidewalls 180P-s and the bottom surface 180P-b of the protrusion 180P are surrounded and covered by the gate dielectric layer 160. The protrusions 180P are in the corresponding non-active area A2 and are spaced apart from each other along the extension direction of the word line 20.

[0100] Reference Fig. 6A and Figure 6B In the cross section along the second direction D2, the second conductive portion 180 corresponding to each active area A1 has a rectangular cross section, and the second conductive portion 180 corresponding to each non-active area A2 (including the main body 180M and the protruding member 180P) has a T-shaped cross section. Therefore, the second conductive portion 180 includes alternating rectangular structures and T-shaped structures in the first direction D1.

[0101] After forming the word lines, the semiconductor structure may further form additional features.

[0102] Fig. 8A A schematic diagram showing an intermediate manufacturing stage of a conventional method of forming a word line. Figure 8B is corresponding to Fig. 8A Cross-sectional view along line 8B-8B in FIG. Fig. 8A and Figure 8BThe same or similar components as those in the aforementioned embodiment are marked with the same or similar reference numbers, and reference may be made to the contents regarding the multiple components in the aforementioned embodiment, which will not be repeated here.

[0103] According to the traditional method, in a similar Figure 1 ,make Fig. 8A After the step of planarizing the first conductive material 32 and the isolation material (not shown), all the isolation materials are recessed to form a recessed isolation structure (not shown). Therefore, the gate dielectric material 36 deposited on the relatively protruding first conductive material 32 and the relatively recessed isolation structure will present an undulating surface along the first direction D1. Fig. 8A As shown, in the word line patterning process, after removing part of the second conductive layer to form the second conductive portion 380, the exposed gate dielectric material 36 has a surface with ups and downs. Since the subsequent process needs to remove the exposed gate dielectric material 36 and disconnect the bottom of the first conductive material 32 thereunder, in order to avoid the bottom of the formed word line (e.g. Figure 8B Here, for example, over-etching is used to completely disconnect the gate dielectric material 36 and the first conductive material 32. However, since the etched gate dielectric material 36 has a height difference, the sidewalls of the adjacent material stack (such as the sidewalls of the adjacent material stack) will be more laterally etched during over-etching. Fig. 8A ), thereby damaging the profile of the formed word line and affecting the electrical performance of the semiconductor structure.

[0104] according to Figure 8B As shown in the cross section, the sidewalls 380s of the second conductive portion 380, the sidewalls 360s of the gate dielectric layer 360 and the sidewalls 320s of the first conductive portion 320, which are originally ideally substantially perpendicular to the substrate 10, will be recessed inward due to the lateral etching effect caused by the height difference of the material layers during the over-etching process.

[0105] Fig. 9A A schematic diagram showing an intermediate manufacturing stage of a method for forming a word line according to an embodiment of the present invention. Fig. 9B is corresponding to Fig. 9A Cross-sectional view along line 9B-9B in FIG.

[0106] After the step of planarizing the first conductive material 12 and the isolation material 14, the isolation material 14 is partially recessed to form a plurality of separated recesses 141, and the remaining portion of the isolation material 14 forms separated isolation islands 143 ( Figure 3 ). The depression 141 is indented into the word line region. Therefore, Fig. 9AAs shown, after removing part of the second conductive layer 18 to form the second conductive portion 180, the exposed gate dielectric material 16 has a flat top surface 16a. In the subsequent step of etching the gate dielectric material 16 and the first conductive material 12 therebelow, since the material portion to be etched does not have a height difference, it is not necessary to use over-etching to disconnect the bottom of the first conductive material 12.

[0107] Therefore, after forming the word line 20, as shown in FIG. Fig. 9B As shown, the sidewall 180s of the second conductive portion 180, the sidewall 160s of the gate dielectric layer 160 and the sidewall 120s of the first conductive portion 120 are substantially perpendicular to the substrate 10 and coplanar. That is, the aforementioned sidewalls are not recessed inward. Furthermore, since there is no lateral etching effect, the second conductive portion 180 does not have a defect that the bottom width is smaller than the top width. The first conductive portion 120 of the word line 20 and the active area A1 below, as well as the first conductive portion 120 and the second conductive portion 180 above, all have sufficient and complete overlapping areas, and there is no problem of sidewall recessing. Therefore, the word line manufactured according to the embodiment has a good profile, so that the applied semiconductor structure has good electrical performance, such as better wordline coupling and more stable erase threshold voltage.

Claims

1. A semiconductor structure, characterized in that: include: A substrate having a plurality of active regions and a plurality of inactive regions, wherein the plurality of active regions and the plurality of inactive regions are alternately arranged in a first direction and extend along a second direction; and A word line is located above the substrate and straddles the plurality of active regions and the plurality of inactive regions, the word line comprising: A plurality of first conductive portions, located on the corresponding plurality of active regions; a plurality of isolation columns, located on the corresponding plurality of inactive regions, and the plurality of first conductive portions and the plurality of isolation columns are alternately arranged in the first direction; a gate dielectric layer, located on the plurality of first conductive portions and the plurality of isolation pillars; and A second conductive portion is located on the gate dielectric layer and extends along the first direction, a protrusion of the second conductive portion corresponds to the multiple inactive areas, wherein in the cross-section along the second direction on the multiple inactive areas, the multiple isolation columns are located on the opposite side of the corresponding protrusion.

2. The semiconductor structure according to claim 1, wherein: Top surfaces of the plurality of first conductive portions and top surfaces of the plurality of isolation pillars are coplanar.

3. The semiconductor structure according to claim 1, wherein: The gate dielectric layer covers a top surface and an inner sidewall of each of the isolation pillars, and covers a top surface and an inner sidewall of each of the plurality of first conductive portions.

4. The semiconductor structure according to claim 1, wherein: The gate dielectric layer comprises: A first portion located on a top surface of the plurality of first conductive portions; a second portion located on the top surface of the plurality of isolation pillars; The plurality of first parts and the plurality of second parts have a same horizontal height.

5. The semiconductor structure according to claim 4, characterized in that The word line has a recess at each of the plurality of inactive regions, and the gate dielectric layer further comprises: The third portion is located on the side walls and bottom surfaces of the corresponding recesses.

6. The semiconductor structure according to claim 1, wherein: The second conductive portion includes: a main body extending in the first direction; and The protrusion corresponds to the plurality of inactive regions, is connected to the bottom surface of the main body and protrudes toward the substrate, and a lower surface of the protrusion is away from the main body.

7. The semiconductor structure according to claim 6, wherein: It also includes a dielectric stack surrounding the side walls of the multiple protrusions and the multiple lower surfaces, the dielectric stack includes the multiple isolation columns and the gate dielectric layer, wherein the word line has a U-shaped cross-section in a cross-section along the second direction, corresponding to each of the multiple non-active areas.

8. The semiconductor structure according to claim 1, wherein: A portion of the second conductive portion corresponding to each of the plurality of inactive regions has a T-shaped cross section in a cross section along the second direction; The portion of the second conductive portion corresponding to each of the active regions has a rectangular cross-section in a cross-section along the second direction.

9. The semiconductor structure according to claim 1, wherein: The word line has a recess at each of the multiple non-active areas, the multiple recesses are separated in the first direction, the gate dielectric layer is conformally located in the multiple recesses, and part of the second conductive portion fills up the remaining space of the multiple recesses, wherein the width of the multiple recesses in the second direction is smaller than the width of the word line in the second direction.

10. A method for forming a semiconductor structure, characterized in that: include: A substrate is provided, wherein the substrate has a plurality of active regions and a plurality of inactive regions, wherein the plurality of active regions and the plurality of inactive regions are alternately arranged in a first direction and extend along a second direction; and A word line is formed above the substrate and straddles the plurality of active regions and the plurality of inactive regions, the word line comprising: A plurality of first conductive portions, located on the corresponding plurality of active regions; a plurality of isolation columns, located on the corresponding plurality of inactive regions, and the plurality of first conductive portions and the plurality of isolation columns are alternately arranged in the first direction; a gate dielectric layer, located on the plurality of first conductive portions and the plurality of isolation pillars; and A second conductive portion is formed on the gate dielectric layer and extends along the first direction, wherein the protrusions of the second conductive portion correspond to the multiple inactive areas, wherein in the cross-section along the second direction on the multiple inactive areas, the multiple isolation columns are located on the opposite side of the corresponding multiple protrusions.

11. The method for forming a semiconductor structure according to claim 10, wherein: After providing the substrate, the method further comprises: forming a plurality of isolation materials in the plurality of inactive regions and forming a plurality of first conductive materials in the plurality of active regions, wherein top surfaces of the plurality of isolation materials are coplanar with top surfaces of the plurality of first conductive materials; and Portions of the multiple isolation materials are removed to form a plurality of recesses, and the remaining portions of the multiple isolation materials include recessed isolation structures and isolation islands protruding from the multiple isolation structures, wherein the multiple isolation islands are separated from each other by the multiple recesses in the second direction, and the multiple isolation islands are separated by the multiple first conductive materials in the first direction.

12. The method for forming a semiconductor structure according to claim 11, wherein: Removing portions of the plurality of isolation materials includes: Providing a mask above the substrate, wherein strip patterns of the mask extend along the first direction and correspond to the gaps between two adjacent word line regions, wherein the widths of the plurality of strip patterns in the second direction are greater than the widths of the plurality of gaps in the second direction; removing portions of the plurality of isolation materials not covered by the plurality of strip patterns according to the mask to form the plurality of recesses; and The mask is removed.

13. The method for forming a semiconductor structure according to claim 11, wherein: After forming the plurality of isolation islands, the method further comprises: forming a gate dielectric material on the plurality of isolation islands and the plurality of first conductive materials, wherein the gate dielectric material is conformally formed on the sidewalls and bottom surfaces of the plurality of recesses; and A second conductive layer is formed on the gate dielectric material.

14. The method for forming a semiconductor structure according to claim 13, wherein: After forming the second conductive layer, the method further includes: Performing a patterning process to form the second conductive portion extending along the first direction in a word line region; removing a portion of the gate dielectric material to form the gate dielectric layer; and Part of the plurality of isolation islands and part of the plurality of first conductive materials are removed, so that the remaining parts of the plurality of isolation islands form the plurality of isolation pillars, and the remaining parts of the plurality of first conductive materials form the plurality of first conductive portions, so as to form the word lines.

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