A method for preparing a TBC battery with a polished isolation area without height difference

Abstract

The present invention relates to the field of solar cells, and discloses a method for preparing a polished TBC cell with no height difference isolation area. The present invention can protect the silicon wafer substrate from alkali corrosion during alkali cleaning or alkali cleaning and texturing by means of ultraviolet laser oxidation process and ingenious and reasonable step design, thereby ensuring that the p-zone, isolation zone and n-zone on the surface of the isolation zone are highly flush and have a polished surface structure, which is beneficial to improving the battery performance and product yield.

Description

Technical Field

[0001] The invention relates to the field of solar cells, and in particular to a method for preparing a polished TBC cell with a non-height difference isolation region. Background Art

[0002] Different from the passivation ideas of other crystalline silicon cells such as TOPCon and HJT, IBC cells mainly improve conversion efficiency by changing the structure. The electrodes of the emitter and base regions of IBC cells are on the back, and there is no grid line blocking the front, so it has higher conversion efficiency, simpler component packaging and higher aesthetics. In addition to optimizing the existing process, the current direction of improving the conversion efficiency of IBC cells is mainly to improve the surface passivation effect and open circuit voltage. TBC cells combine the excellent passivation contact characteristics of TOPCon and have a mature preparation process. It is currently the most cost-effective IBC process route, and the industrialization process is accelerating in recent years.

[0003] The isolation region structure between the p-region and the n-region of the current TBC battery is commonly a pyramid velvet surface (i.e., the surface of the silicon wafer substrate in the isolation region has a pyramid velvet structure). The pyramid velvet surface is usually formed by a wet process. Therefore, during the formation of the pyramid velvet surface, the surface of the silicon wafer substrate in the isolation region is often corroded deeply, resulting in a significant height difference between this part of the silicon wafer substrate and the surfaces of the silicon wafer substrate in the n-region and p-region on both sides thereof, which not only affects the carrier transport performance, but also leads to a reduction in the yield of the finished battery. In addition, the pyramid velvet structure on the back surface of the silicon wafer substrate will also lead to a weak internal reflection effect of the back side on light, which limits the improvement of the optical performance of the battery.

[0004] In view of this, it is necessary to develop a TBC battery with almost no height difference and polished p-region / isolation region / n-region on the back surface of the silicon wafer substrate, which can not only improve the carrier transport performance, but also significantly improve the optical performance of the battery. Summary of the invention

[0005] In order to solve the above technical problems, the present invention provides a method for preparing a TBC battery with a polished isolation area without height difference. The present invention can protect the silicon wafer substrate from alkali corrosion during alkali cleaning or alkali cleaning and texturing by means of ultraviolet laser oxidation process and ingenious and reasonable step design, thereby ensuring that the p-zone, isolation zone and n-zone on the surface of the isolation zone are highly flush and have a polished surface structure, which is beneficial to improving battery performance and product yield.

[0006] The specific technical solution of the present invention is: a method for preparing a polished TBC battery with no height difference isolation area, which specifically includes the following steps:

[0007] S1, double-sided polishing of silicon wafer.

[0008] S2. Ultraviolet laser once patterns the surface of the preset n-region and isolation region on the back of the silicon wafer to form an oxide layer.

[0009] Due to the tunneling SiO formed by S3 x The layer cannot effectively protect the surface of the n-region and isolation area of ​​the bottom silicon wafer substrate during the subsequent S6 alkaline cleaning process, causing the surface of the silicon wafer substrate in this area to be excessively corroded by alkali, resulting in a large height difference between the n-region, isolation region and p-region on the surface of the silicon wafer substrate, which not only affects the carrier transmission performance of the battery, but also leads to a reduction in the yield of the finished battery. To this end, the present invention adopts an ultraviolet laser oxidation method, which can selectively oxidize only the n-region and isolation region pre-designed on the back of the silicon wafer to form an oxide layer. The oxide layer can effectively resist the corrosion of the alkaline solution on the surface of the bottom silicon wafer substrate, thereby ensuring that there is almost no height difference between the various regions on the surface of the silicon wafer substrate.

[0010] S3, one-time deposition of tunnel SiO on the back of silicon wafer x The purpose of constructing the i-poly-Si layer in this step is to create conditions for the subsequent S4 boron diffusion to form a boron diffusion layer.

[0011] S4. Boron diffusion transforms the inner layer and the surface layer of the i-poly-Si layer into a boron diffusion layer and a BSG layer respectively.

[0012] S5: Laser patterning and grooving to remove the BSG layer in the preset n-region and isolation region. Laser patterning and grooving to remove the BSG layer in the above-mentioned region can pave the way for subsequent S6 alkaline cleaning and acid cleaning.

[0013] S6, alkaline cleaning to remove the boron diffusion layer of the preset n-region and isolation region, the tunneling SiO x layer; pickling to remove the oxide layer.

[0014] The boron diffusion layer and tunneling SiO x layer cleaning and removal (due to tunneling SiO x The thickness of the layer is usually thin, so it can be removed during the alkaline cleaning process); since there is a preset oxide layer on the surface of the silicon wafer substrate in this area, the thickness of the oxide layer is relatively large compared to the tunneling SiO x The oxide layer is thicker and reacts slowly in an alkaline environment, so that the alkaline solution cannot penetrate the oxide layer and corrode the bottom silicon wafer substrate; at the same time, since the surface of the boron diffusion layer in the non-laser patterned slotted area is protected by the BSG layer, the bottom boron diffusion layer can also be effectively protected from being damaged during the alkaline cleaning process. The oxide layer can then be completely removed through the low-concentration acid (HF) tank that comes with the alkaline cleaning tank (the oxide layer is resistant to alkali but not acid), while the BSG layer on the surface of the boron diffusion layer in the non-laser patterned slotted area is thicker, so only a slight portion will be removed, and most of it can still be retained.

[0015] S7. Ultraviolet laser secondary patterning oxidation is performed on the silicon surface of the preset isolation area to form an oxide layer.

[0016] The purpose of using ultraviolet laser to construct the oxide layer in this step is similar to that of S2, which is to ensure that the surface of the isolation area of ​​the silicon wafer substrate is protected from corrosion by the alkaline solution during the subsequent S12 alkaline washing and texturing process.

[0017] S8, secondary deposition of tunnel SiO on the back of silicon wafer x The purpose of constructing the i-poly-Si layer in this step is to create conditions for the subsequent S9 phosphorus diffusion to form a phosphorus diffusion layer.

[0018] S9. Phosphorus diffusion, so that the inner layer and the surface layer of the i-poly-Si layer are transformed into a phosphorus diffusion layer and a PSG layer respectively.

[0019] S10, laser patterning and grooving to remove the PSG layer in the preset p-region and isolation region. Laser patterning and grooving to remove the PSG layer in the above regions can pave the way for subsequent S12 alkali washing and acid washing.

[0020] S11, removing the wrap-around plating. The purpose of this step is to remove the wrap-around plating layer on the front and side surfaces of the silicon wafer substrate.

[0021] S12, alkali washing and texturing, acid washing to remove the residual PSG layer, BSG layer and oxide layer, forming an isolation area structure with no height difference in surface polishing.

[0022] The silicon wafer with the de-coated coating is placed in an alkaline texturing tank for wet cleaning and texturing. Since the de-coating on the front of the silicon wafer has been completed and there is no oxidation area, a pyramid texture surface can be formed during the texturing process. For the p-region on the back of the silicon wafer, the PSG layer on the surface, the phosphorus diffusion layer, the tunneling SiO x The PSG layer can be washed away during the wet texturing process, and the boron diffusion layer surface of the p-region is protected by the BSG layer and is not damaged by alkali corrosion. x The PSG layer can be washed away during the wet texturing process. Since there is an oxide layer on the surface of the silicon wafer substrate in this area, the bottom silicon wafer substrate can be protected from corrosion damage. For the n-region on the back of the silicon wafer, since no laser grooving is performed, the surface PSG layer can protect the bottom phosphorus diffusion layer from damage during the wet texturing process. After texturing, the subsequent acid (HF) washing tank of the texturing tank can further remove the PSG layer, BSG layer and oxide layer remaining on the surface of the silicon wafer, and finally realize that the p-region, isolation region and n-region on the surface of the silicon wafer substrate are polished planes and highly flush.

[0023] S13, double-sided coating: ALD deposition method is used to deposit AlO on both sides of the processed silicon wafer x film.

[0024] S14, screen printing, sintering, light injection, the double-sided coated silicon wafer is screen printed on the back to form a metal contact, and then sintered at high temperature to form an Ag-Si ohmic contact, and finally repaired by light injection to obtain a polished TBC battery with no height difference isolation area.

[0025] Preferably, in S6, the alkaline cleaning conditions are: KOH solution concentration 1.7-2.2 wt%, temperature 75-85°C.

[0026] Preferably, in S6, the pickling conditions are: the concentration of the HF solution in the pickling tank is 1-10 wt%, and the time is 30-60 s.

[0027] Under the above pickling conditions, not only can the oxide layer constructed by S2 be removed during the pickling process, but also the BSG layer on the surface of the boron diffusion layer in the non-laser patterned slotted area can be only slightly removed, while most of it can still be retained. If the pickling degree is too high, there is a risk of excessive removal of the BSG layer.

[0028] Preferably, in S12, the cleaning and texturing conditions are: KOH solution concentration 1.5-1.8 wt%, temperature 80-85°C, time 6-12 min.

[0029] Preferably, in S12, the pickling conditions are: the concentration of HF solution in the pickling tank is 20-40 wt%, and the time is 60-200 s.

[0030] Preferably, in S2 and S7, the conditions of the ultraviolet laser are: laser wavelength 300-400 nm, power 10-100 W, processing time 1-20 s, and oxide layer thickness 2-50 nm.

[0031] Preferably, in S3 and S8, the tunneling SiO x The deposition conditions of the layer are: O2 flow rate 10000~80000 sccm, temperature 400~800℃, time 200~1000 s, tunneling SiO x The layer thickness is 1~10 nm; the deposition conditions of the i-poly-Si layer are: SiH4 flow rate 300~2000 sccm, temperature 500~700℃, time 2~4 h, working gas pressure 100~500 mTorr, and the i-poly-Si layer thickness is 100~300 nm.

[0032] Preferably, in S4, the boron diffusion conditions are: boron diffusion temperature 800-950°C, diffusion time 5-50 min, BCl3 flow rate 50-500 sccm, O2 flow rate 500-2000 sccm; oxidation advancement temperature 900-1050°C, O2 flow rate 5000-30000 sccm, advancement time 30-80 min, and the thickness of the obtained BSG layer is 30-70 nm.

[0033] More preferably, in S4, the conditions for boron diffusion are: low-temperature and high-concentration boron diffusion: temperature 800-900°C, diffusion time 5-30 min, BCl3 flow rate 200-500 sccm, O2 flow rate 1000-2000 sccm; high-temperature and medium-concentration source + oxidation advancement: temperature 930-1050°C, BCl3 flow rate 100-200 sccm, O2 flow rate 10000-50000 sccm, advancement time 20-50 min; medium-temperature and low-concentration source + oxidation advancement: temperature 900-950°C, BCl3 flow rate 30-100 sccm, O2 flow rate 3000-8000 sccm, advancement time 10-50 min; the thickness of the resulting BSG layer is 30-70 nm.

[0034] Since the oxide layer formed in S2 needs to be removed in the subsequent S6, the BSG layer formed after the synchronous boron diffusion will inevitably be partially removed; in order to prevent the BSG layer from being significantly thinned during the process (the BSG layer is the key to preventing the phosphorus atoms from diffusing into the boron diffusion layer during the subsequent phosphorus diffusion process and preventing the layer from being inverted), the layer needs to be thicker and denser during the process. The conventional boron diffusion process generally consists of three parts: "low-temperature source deposition → high-temperature oxidation advancement → cooling and exiting the boat". First of all, in the conventional process of "high-temperature oxidation advancement", only oxygen is often introduced, and the process temperature is relatively high. The surface boron atoms will be further pushed into the silicon body, which will result in a smaller amount of boron atoms doped in the formed BSG layer. In the previous research, the present invention found that the acid resistance of the BSG layer is higher than that of the PSG layer. On the one hand, the process temperature for forming the BSG layer is higher (950~1050℃), while the process temperature for forming the PSG layer is lower (800~950℃). The higher process temperature will result in higher stability and compactness of the corresponding film layer; on the other hand, the doping type in the BSG layer is holes (while the doping type of the PSG layer is electrons). From the perspective of gaining and losing electrons, the PSG layer is easy to react chemically, while the BSG layer is difficult to react, and the BSG layer with a higher boron doping concentration within a certain range has stronger acid resistance. Secondly, the process time from the end of the conventional "high-temperature oxidation push" to "out of the boat" is short, which will cause the temperature to drop too fast, and the stress generated by the film is also large, which is not conducive to the formation of a stable film structure. In view of this, the present invention provides the above-mentioned "continuous gradual source" boron diffusion process. The main process is: low-temperature high-concentration source deposition → high-temperature medium-concentration source + oxidation push → medium-temperature low-concentration source + oxidation push → low-temperature out of the boat. Compared with the conventional boron diffusion process, the new process of the present invention is characterized in that: (1) during the oxidation process, source deposition is also carried out simultaneously, which can not only increase the surface doping concentration of the boron diffusion layer and reduce the subsequent gold / semi contact resistance, but also increase the doping amount of boron atoms in the formed BSG layer, which helps to enhance the subsequent acid resistance of the layer; (2) the oxidation advancement is divided into two process stages, in which the process temperature and the source concentration are gradually changed from high to low, which can not only improve the doping distribution of boron atoms in the BSG layer and improve the uniformity, but also reduce the film stress caused by temperature mutation, improve the stability and density of the film, and also improve the acid resistance of the layer; (3) the entire oxidation advancement process time is relatively long, and the oxygen flow rate is also relatively high, which can increase the thickness of the BSG layer and reduce the risk of the layer being completely corroded during the subsequent acid cleaning process; (4) during the subsequent high-temperature preparation process of the phosphorus diffusion layer, the higher concentration of boron doped BSG layer can further promote the boron atoms in the BSG layer into the boron diffusion layer, thereby maximizing the reduction of the subsequent gold / semi contact resistance of the layer.

[0035] Preferably, in S5 and S10, the conditions for the laser patterning grooving are: laser wavelength 400-600 nm, frequency 500-700 KHz, marking speed 40000-50000 mm / s, power 10-50 W, and processing time 1-5 s.

[0036] Preferably, in S9, the conditions for phosphorus diffusion are: first, a mixed gas of POCl3 and O2 is introduced at a temperature of 750~850°C, a diffusion time of 5~30 min, a POCl3 flow rate carried by N2 of 500~1200 sccm, and an O2 flow rate of 500~1000 sccm; then, O2 is introduced for oxidation advancement at a temperature of 850~950°C, a advancement time of 20~60 min, and an O2 flow rate of 1000~10000 sccm to generate a PSG layer with a thickness of 30~70 nm.

[0037] Compared with the prior art, the beneficial effects of the present invention are: the present invention, with the help of ultraviolet laser oxidation technology and through ingenious and reasonable step design, can protect the silicon wafer substrate from alkaline corrosion during alkaline cleaning or alkaline washing and texturing, thereby ensuring that the p-zone, isolation zone and n-zone on the surface of the isolation zone are highly flush and have a polished surface structure, which is beneficial to improving battery performance and increasing product yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 Schematic diagram of the structure of the silicon wafer after double-sided polishing.

[0039] Figure 2 Deposit tunnel SiO on the back of the silicon wafer x Schematic diagram of the structure after layer and i-poly-Si layer.

[0040] Figure 3 Schematic diagram of the structure after boron diffusion of silicon wafer.

[0041] Figure 4 Schematic diagram of the structure after laser patterning of the BSG layer of the silicon wafer + alkaline cleaning.

[0042] Figure 5 Secondary deposition of tunnel SiO on the back of the silicon wafer x Schematic diagram of the structure after layer and i-poly-Si layer.

[0043] Figure 6 Schematic diagram of the structure of the silicon wafer after phosphorus diffusion.

[0044] Figure 7 This is a schematic diagram of the structure after laser patterning of PSG layer on silicon wafer + alkali washing and acid washing.

[0045] Figure 8 It is a schematic diagram of the structure of the finished TBC battery of the present invention.

[0046] The reference numerals are: N-type single crystal silicon wafer 1; oxide layer 2; tunneling SiO x Layer 3; i-poly-Si layer 4; boron diffusion layer 5; BSG layer 6; phosphorus diffusion layer 7; PSG layer 8; pyramid velvet surface 9; passivation anti-reflection film 10; electrode 11. DETAILED DESCRIPTION

[0047] The present invention will be further described below in conjunction with the embodiments.

[0048] Overall embodiment

[0049] The specific technical solution of the present invention is: a method for preparing a polished TBC battery with no height difference isolation area, which specifically includes the following steps:

[0050] S1, double-sided polishing of silicon wafer.

[0051] In some preferred implementation cases, the double-sided polishing of the silicon wafer specifically includes: placing the N-type single crystal silicon wafer cut by diamond wire into an alkaline polishing tank for double-sided polishing, maintaining the temperature at 75~85°C, the time is 6~8 min, the polishing thickness is 3~7 μm, and the thinning amount is 0.35~0.45 g.

[0052] S2, ultraviolet laser once patterning oxide silicon wafer backside preset n area and isolation area surface, forming an oxide layer. x The layer cannot effectively protect the surface of the n-region and isolation area of ​​the bottom silicon wafer substrate during the subsequent S6 alkaline cleaning process, causing the surface of the silicon wafer substrate in this area to be excessively corroded by alkali, resulting in a large height difference between the n-region, isolation region and p-region on the surface of the silicon wafer substrate, which not only affects the carrier transmission performance of the battery, but also leads to a reduction in the yield of the finished battery. To this end, the present invention adopts an ultraviolet laser oxidation method, which can selectively oxidize only the n-region and isolation region pre-designed on the back of the silicon wafer to form an oxide layer. The oxide layer can effectively resist the corrosion of the alkaline solution on the surface of the bottom silicon wafer substrate, thereby ensuring that there is almost no height difference between the various regions on the surface of the silicon wafer substrate.

[0053] In some preferred implementation cases, the conditions of the ultraviolet laser are: laser wavelength 300~400 nm, power 10~100 W, processing time 1~20 s, and oxide layer thickness 2~50 nm.

[0054] S3, one-time deposition of tunnel SiO on the back of silicon wafer x The purpose of constructing the i-poly-Si layer in this step is to create conditions for the subsequent S4 boron diffusion to form a boron diffusion layer.

[0055] In some preferred implementation cases, the tunneling SiO xThe deposition conditions of the layer are: LPCVD method, O2 flow rate 10000~80000 sccm, temperature 400~800℃, time 200~1000 s, tunneling SiO x The layer thickness is 1~10 nm; the deposition conditions of the i-poly-Si layer are: LPCVD method, SiH4 flow rate 300~2000 sccm, temperature 500~700℃, time 2~4 h, working gas pressure 100~500 mTorr, i-poly-Si layer thickness 100~300 nm.

[0056] S4. Boron diffusion transforms the inner layer and the surface layer of the i-poly-Si layer into a boron diffusion layer and a BSG layer respectively.

[0057] In some preferred implementation cases, the conditions for boron diffusion are: boron diffusion temperature 800-950°C, diffusion time 5-50 min, BCl3 flow rate 50-500 sccm, O2 flow rate 500-2000 sccm; oxidation advancement temperature 900-1050°C, O2 flow rate 5000-30000 sccm, advancement time 30-80 min, and the thickness of the resulting BSG layer is 30-70 nm.

[0058] S5: Laser patterning and grooving to remove the BSG layer in the preset n-region and isolation region. Laser patterning and grooving to remove the BSG layer in the above-mentioned region can pave the way for subsequent S6 alkaline cleaning and acid cleaning.

[0059] In some preferred implementation cases, the conditions for the laser patterning grooving are: laser wavelength 400~600 nm, frequency 500~700 KHz, marking speed 40000~50000 mm / s, power 10~50 W, and processing time 1~5 s.

[0060] S6, alkaline cleaning to remove the boron diffusion layer of the preset n-region and isolation region, the tunneling SiO x The boron diffusion layer and the tunneling SiO2 layer in the S5 laser patterned slot area (n area and isolation area) can be removed by acid washing. x The oxide layer is removed by cleaning; since there is an oxide layer on the surface of the silicon wafer substrate in this area, the alkaline solution cannot penetrate the oxide layer to corrode the silicon wafer substrate at the bottom; at the same time, since the surface of the boron diffusion layer in the non-laser patterned slot area is protected by the BSG layer, the bottom boron diffusion layer can also be effectively protected from damage during the alkaline cleaning process. The oxide layer can then be removed by using the low-concentration acid (HF) tank that comes with the alkaline cleaning tank (the oxide layer is resistant to alkali but not acid), while the BSG layer on the surface of the boron diffusion layer in the non-laser patterned slot area is thicker, so only a slight portion will be removed, and most of it can still be retained.

[0061] In some preferred implementation cases, the alkaline cleaning conditions are: KOH solution concentration 1.7-2.2 wt%, temperature 75-85°C.

[0062] In some preferred implementation cases, the pickling conditions are: the concentration of HF solution in the pickling tank is 1-10 wt%, and the time is 30-60 s.

[0063] S7, ultraviolet laser secondary patterning oxidation of the silicon surface of the preset isolation area to form an oxide layer. The purpose of using ultraviolet laser to construct the oxide layer again in this step is similar to S2, which is to ensure that the isolation area surface of the silicon wafer substrate is protected from corrosion by the alkaline solution during the subsequent S12 alkaline washing and texturing process.

[0064] In some preferred implementation cases, the conditions of the ultraviolet laser are: laser wavelength 300~400 nm, power 10~100 W, processing time 1~20 s, and oxide layer thickness 2~50 nm.

[0065] S8, secondary deposition of tunnel SiO on the back of silicon wafer x The purpose of constructing the i-poly-Si layer in this step is to create conditions for the subsequent S9 phosphorus diffusion to form a phosphorus diffusion layer.

[0066] In some preferred implementation cases, the tunneling SiO x The deposition conditions of the layer are: LPCVD method, O2 flow rate 10000~80000 sccm, temperature 400~800℃, time 200~1000 s, tunneling SiO x The layer thickness is 1~10 nm; the deposition conditions of the i-poly-Si layer are: LPCVD method, SiH4 flow rate 300~2000 sccm, temperature 500~700℃, time 2~4 h, working gas pressure 100~500 mTorr, i-poly-Si layer thickness 100~300 nm.

[0067] S9. Phosphorus diffusion, so that the inner layer and the surface layer of the i-poly-Si layer are transformed into a phosphorus diffusion layer and a PSG layer respectively.

[0068] In some preferred implementation cases, the conditions for the phosphorus diffusion are: first, a mixed gas of POCl3 and O2 is introduced at a temperature of 750~850°C, a diffusion time of 5~30 min, a POCl3 flow rate carried by N2 of 500~1200 sccm, and an O2 flow rate of 500~1000 sccm; then, O2 is introduced for oxidation advancement at a temperature of 850~950°C, a advancement time of 20~60 min, and an O2 flow rate of 1000~10000 sccm to generate a PSG layer with a thickness of 30~70 nm.

[0069] S10, laser patterning and grooving to remove the PSG layer in the preset p-region and isolation region. Laser patterning and grooving to remove the PSG layer in the above-mentioned region can pave the way for subsequent S12 alkali washing and acid washing.

[0070] In some preferred implementation cases, the conditions for the laser patterning grooving are: laser wavelength 400~600 nm, frequency 500~700 KHz, marking speed 40000~50000 mm / s, power 10~50 W, and processing time 1~5 s.

[0071] S11, removing the wrap-around plating. The purpose of this step is to remove the wrap-around plating layer on the front and side surfaces of the silicon wafer substrate.

[0072] In some preferred implementation cases, a chain etcher is used to remove the coating on the front and side surfaces of the silicon wafer, the volume ratio of the hydrofluoric acid solution to the nitric acid solution in the acid tank is 1:2~1:8, the concentration of the hydrofluoric acid solution is 45~55 wt%, the concentration of the nitric acid solution is 65~75 wt%, and the belt speed is 1-10 m / min.

[0073] S12, alkali washing and texturing, acid washing to remove the residual PSG layer, BSG layer and oxide layer, forming an isolation area structure with no height difference in surface polishing. The silicon wafer with the de-plating layer is placed in the alkali texturing tank for wet cleaning and texturing integrated treatment. Since the de-plating layer on the front of the silicon wafer has been removed and there is no oxidation area, a pyramid velvet surface can be formed during the texturing process. For the p-region on the back of the silicon wafer, the PSG layer on the surface, the phosphorus diffusion layer, the tunneling SiO x The PSG layer can be washed away during the wet texturing process, and the boron diffusion layer surface of the p-region is protected by the BSG layer and is not damaged by alkali corrosion. x The PSG layer can be washed away during the wet texturing process. Since there is an oxide layer on the surface of the silicon wafer substrate in this area, the bottom silicon wafer substrate can be protected from corrosion damage. For the n-region on the back of the silicon wafer, since no laser grooving is performed, the surface PSG layer can protect the bottom phosphorus diffusion layer from damage during the wet texturing process. After texturing, the subsequent acid (HF) washing tank of the texturing tank can further remove the PSG layer, BSG layer and oxide layer remaining on the surface of the silicon wafer, and finally realize that the p-region, isolation region and n-region on the surface of the silicon wafer substrate are polished planes and highly flush.

[0074] In some preferred implementation cases, the cleaning and texturing conditions are: KOH solution concentration 1.5-1.8 wt%, temperature 80-85°C, time 6-12 min.

[0075] In some preferred implementation cases, the pickling conditions are: the concentration of the HF solution in the pickling tank is 20-40wt%, and the time is 60-200 s.

[0076] S13, double-sided coating: A passivation anti-reflection film is deposited on both sides of the processed silicon wafer using ALD deposition method.

[0077] In some preferred implementation cases, the anti-reflection film is passivated on both sides of the treated silicon wafer by ALD deposition, which is generated by the reaction of Al(CH3)3 and water vapor, with a thickness of 8-10 nm, and the process temperature is controlled at 220-280°C. Then, SiN is deposited on both sides of the silicon wafer by tubular PECVD equipment. x The film has a thickness of 80~120 nm and a refractive index of 1.9~2.1; the reaction gases in the tubular cavity are SiH4 and NH3, the working pressure is 1500~1700 mTorr, the power is 10000~15000 W, the temperature is 400~600℃, the SiH4 gas flow rate is 900~2000 sccm, the NH3 gas flow rate is 7000~12000 sccm, and the deposition time is 5~20 min.

[0078] S14, screen printing, sintering, light injection: The double-sided coated silicon wafer is screen printed on the back to form metal contact, and then sintered at high temperature to form Ag-Si ohmic contact, and finally repaired by light injection to obtain a polished TBC battery with no height difference isolation area.

[0079] In some preferred implementation cases, the coated silicon wafer is screen-printed on the back to form a metal contact, then sintered at 700-800°C to form an Ag-Si ohmic contact, and finally repaired by light injection to obtain a polished TBC battery with no height difference isolation area.

[0080] Specific examples and comparative examples.

[0081] Example 1

[0082] The specific technical solution of the present invention is: a method for preparing a polished TBC battery with no height difference isolation area, which specifically includes the following steps:

[0083] S1. Double-sided polishing of silicon wafer: Place the N-type single crystal silicon wafer 1 cut by diamond wire into an alkaline polishing tank for double-sided polishing (such as Figure 1 As shown in the figure), the temperature was maintained at 75°C, the polishing time was 6 min, the polishing thickness was about 4 μm, and the thinning amount was 0.42 g.

[0084] S2, using ultraviolet laser to pattern the preset n-region and isolation region surface on the back of the silicon wafer once, to form an oxide layer 2. The conditions of the ultraviolet laser are: laser wavelength 355 nm, power 15 W, processing time 3 s, and the oxide layer thickness is about 10 nm.

[0085] S3, using LPCVD to deposit tunneling SiO on the back of the silicon wafer x Layer 3, i-poly-Si layer 4 (such as Figure 2 As shown). Among them, the tunneling SiO x The deposition conditions of the layer are: the gas flow rate of O2 is 40000 sccm, the reaction temperature is 600℃, the time is 600 s, and the thickness of the tunnel oxide layer is about 3 nm. Then, an intrinsic polysilicon layer is deposited on the tunnel oxide layer, where the gas flow rate of SiH4 is 920 sccm, the reaction temperature is 550℃, the time is 3.3 h, the working pressure is 300 mTorr, and the thickness of the intrinsic polysilicon layer is about 290 nm.

[0086] S4, boron diffusion, so that the inner layer and the surface layer of the i-poly-Si layer are transformed into a boron diffusion layer 5 and a BSG layer 6 respectively (such as Figure 3 As shown). The conditions for boron diffusion are as follows: first, a mixed gas of BCl3 and O2 is introduced, the temperature is 850°C, the diffusion time is 10 min, the BCl3 gas flow rate is 200 sccm, and the O2 flow rate is 1200 sccm; then O2 is introduced for oxidation advancement, the oxidation advancement temperature is 950°C, the O2 gas flow rate is 7000 sccm, the advancement time is 30 min, and the thickness of the formed BSG is about 45 nm.

[0087] S5, laser patterning and grooving to remove the BSG layer of the preset n-region and isolation region. The conditions of laser patterning and grooving are as follows: the laser wavelength used is 532 nm, the frequency is 600 KHz, the marking speed is 45000 mm / s, the power is 50 W, and the processing time is 3 s.

[0088] S6, alkaline cleaning to remove the boron diffusion layer of the preset n-region and isolation region, the tunneling SiO x layer; pickling to remove the oxide layer (such as Figure 4 As shown). The conditions for alkaline cleaning are: KOH solution concentration 2.0 wt%, temperature 80°C. The conditions for acid cleaning are: HF solution concentration in the acid cleaning tank is 5 wt%, and the time is 40 s.

[0089] S7, using ultraviolet laser to perform secondary patterning oxidation on the silicon surface of the preset isolation region to form an oxide layer 2. The conditions of the ultraviolet laser are: laser wavelength 355 nm, power 15 W, processing time 3 s, and oxide layer thickness of about 10 nm.

[0090] S8, using LPCVD to deposit tunneling SiO on the back of the silicon wafer x Layer 3, i-poly-Si layer 4 (such as Figure 5 The purpose of constructing the i-poly-Si layer in this step is to create conditions for the subsequent S9 phosphorus diffusion to form a phosphorus diffusion layer. x The deposition conditions of the layer are: O2 gas flow rate of 40000 sccm, reaction temperature of 600℃, time of 600 s, tunneling SiO x The layer thickness is about 3 nm. x An i-poly-Si layer is deposited on the SiO2 layer, where the SiH4 gas flow rate is 920 sccm, the reaction temperature is 550°C, the reaction time is 3.3 h, the working gas pressure is 300 mTorr, and the thickness of the i-poly-Si layer is about 290 nm.

[0091] S9, phosphorus diffusion, so that the inner layer and the surface layer of the i-poly-Si layer are transformed into a phosphorus diffusion layer 7 and a PSG layer 8 respectively (such as Figure 6 As shown). The conditions for phosphorus diffusion are as follows: first, a mixed gas of POCl3 and O2 is introduced at a temperature of 790°C, a diffusion time of 20 min, a POCl3 flow rate carried by nitrogen of 1100 sccm, and an O2 flow rate of 700 sccm; then, O2 is introduced for oxidation advancement at a temperature of 890°C, a advancement time of 40 min, and an O2 flow rate of 3000 sccm, generating a PSG layer with a thickness of about 42 nm.

[0092] S10, laser patterning and grooving to remove the PSG layer of the preset p-region and isolation region. The conditions of laser patterning and grooving are: laser wavelength of 532 nm, frequency of 600 KHz, marking speed of 45000 mm / s, power of 25 W, and processing time of 2.7 s.

[0093] S11. De-coating: Use a chain etcher to remove the coating on the front and side of the silicon wafer. The volume ratio of the hydrofluoric acid solution and the nitric acid solution in the acid tank is 1:4, wherein the concentration of the hydrofluoric acid solution is 49 wt%, and the concentration of the nitric acid solution is 69 wt%. The belt speed is 1.3 m / min.

[0094] S12, alkali washing and texturing, acid washing to remove the residual PSG layer, BSG layer and oxide layer, forming an isolation area structure with no height difference in surface polishing (such as Figure 7 As shown). Specifically: put the silicon wafer after the coating is removed into the alkaline texturing tank for wet cleaning and texturing integrated treatment. Since the coating is removed from the front of the silicon wafer and there is no oxidation area, a pyramid velvet surface 9 can be formed during the texturing process. For the p-region on the back of the silicon wafer, the PSG layer on the surface, the phosphorus diffusion layer, the tunneling SiOx The PSG layer can be washed away during the wet texturing process, and the boron diffusion layer surface of the p-region is protected by the BSG layer and is not damaged by alkali corrosion. x The layer can be washed away during the wet texturing process. Since there is an oxide layer on the surface of the silicon wafer substrate in this area, the bottom silicon wafer substrate can be protected from corrosion damage. For the n-region on the back of the silicon wafer, since no laser grooving treatment is performed, the surface PSG layer can protect the bottom phosphorus diffusion layer from damage during the wet texturing process. After texturing, the subsequent acid (HF) cleaning tank of the texturing tank can further remove the PSG layer, BSG layer and oxide layer remaining on the surface of the silicon wafer, and finally realize that the p-region, isolation region and n-region on the surface of the silicon wafer substrate are polished planes and highly flush. Among them, the cleaning and texturing conditions are: KOH solution concentration 1.7 wt%, temperature 82℃, time 7 min; acid pickling conditions are: HF solution concentration in the pickling tank is 30 wt%, time 120 s.

[0095] S13, double-sided coating: ALD deposition method is used to deposit a passivation anti-reflection film 10 on both sides of the processed silicon wafer. The passivation anti-reflection film is generated by the reaction of Al(CH3)3 and water vapor, with a thickness of about 8 nm. The process temperature is controlled at 250°C. Then, SiN is deposited on both sides of the silicon wafer using a tubular PECVD device. x The film has a thickness of about 82 nm and a refractive index of 1.95; the reaction gases in the tubular cavity are SiH4 and NH3, the working pressure is 1600 mTorr, the power is 12000 W, the temperature is 450℃, the SiH4 gas flow rate is 1300 sccm, the NH3 gas flow rate is 11000 sccm, and the deposition time is 10 min.

[0096] S14, screen printing, sintering, light injection: The coated silicon wafer is screen printed on the back to form a metal contact, and then sintered at 770°C to form an Ag-Si ohmic contact (electrode 11), and finally repaired by light injection to obtain a polished TBC battery with no height difference isolation area (such as Figure 8 as shown).

[0097] Example 2

[0098] The difference between Example 2 and Example 1 is that S4 adopts a new boron diffusion process, which is as follows:

[0099] Low temperature and high concentration boron diffusion: deposition temperature 850°C, diffusion time 15 min, BCl3 flow rate 300 sccm, O2 flow rate 1500 sccm;

[0100] High temperature medium concentration source + oxidation push: temperature is 970℃, BCl3 flow rate is 120 sccm, O2 flow rate is 20000 sccm, and push time is 40 min;

[0101] Medium temperature and low concentration source + oxidation advancement: temperature 920℃, BCl3 flow rate 50 sccm, O2 flow rate 6000 sccm, advancement time 20 min; the thickness of the obtained BSG layer is about 56 nm.

[0102] Comparative Example 1 (Comparative Example Using Conventional Process, with Height Difference in Isolation Area)

[0103] S1. Select N-type single crystal silicon wafers cut by diamond wire, put the cut silicon wafers into alkaline polishing tank, maintain the temperature at 75℃, perform double-sided polishing for 6 min, the polishing thickness is 4 μm, and the thinning amount is 0.42 g.

[0104] S2, then the back surface of the polished silicon wafer is firstly grown by LPCVD tunneling SiO x layer, the gas flow rate of O2 is 40000 sccm, the temperature is 600℃, the time is 600 s, and the tunneling SiO x The layer thickness is about 3 nm; then tunneling SiO x An i-poly-Si layer is grown again on the layer, with a SiH4 gas flow rate of 920 sccm, a temperature of 550 °C, a time of 3.3 h, a working gas pressure of 300 mTorr, and a thickness of the i-poly-Si layer of about 290 nm.

[0105] S3, then use high temperature boron diffusion method to transform the i-poly-Si layer into p + -poly-Si layer, boron diffusion temperature 850℃, diffusion time 10 min, BCl3 gas flow rate 200 sccm, O2 gas flow rate 1200 sccm, oxidation push temperature 950℃, O2 flow rate 7000 sccm, push time 30 min, BSG layer thickness is about 45 nm.

[0106] S4. Use picosecond laser to perform a patterned grooving of the BSG layer. The laser wavelength used is 532 nm, the frequency is 600 KHZ, the marking speed is 45000 mm / s, the power is 50 W, and the processing time is 3 s.

[0107] S5. Place the laser patterned silicon wafer in an alkaline solution for cleaning at a temperature of 75°C for 360 seconds.

[0108] S6, then use LPCVD to grow tunnel SiO xlayer, the gas flow rate of O2 is 30000sccm, the temperature is 600℃, the time is 450s, and the tunneling SiO x The layer thickness is about 2.5 nm; then in the tunneling SiO x An i-poly-Si layer is grown again on the layer, with a SiH4 gas flow rate of 920 sccm, a temperature of 550 °C, a time of 1.5 h, a working gas pressure of 300 mTorr, and a thickness of the i-poly-Si layer of about 180 nm.

[0109] S7, using phosphorus diffusion method to form n + -poly-Si layer, phosphorus diffusion temperature 790℃, diffusion time 15 min, POCl3 is carried by nitrogen with a flow rate of 1000 sccm, O2 flow rate is 650 sccm, oxidation push temperature 890℃, O2 flow rate is 3000 sccm, push time is 20 min, PSG layer thickness is about 39 nm.

[0110] S8, then use picosecond laser to perform secondary patterning to open the PSG layer, so that p + -poly bottom corresponds to PSG layer and p + -poly and n + The PSG layer at the junction area of ​​-poly was loosened with a laser wavelength of 532 nm, a frequency of 600 KHz, a marking speed of 45000 mm / s, a power of 25 W, and a processing time of 2.7 s.

[0111] S9, using a chain machine to remove the n-plated silicon wafers on the front and side surfaces of the silicon wafers. + -poly-Si and p + -poly-Si layer, wherein the volume ratio of the hydrofluoric acid solution to the nitric acid solution in the acid tank is 1:4 (the concentration of the hydrofluoric acid solution is 49 wt %, and the concentration of the nitric acid solution is 69 wt %), and the belt speed is 1.3 m / min.

[0112] S10, put the silicon wafer that has been deplated into an alkaline texturing tank for wet cleaning of the laser slotted area on the back and integrated texturing of the front. The KOH solution concentration in the texturing tank is 1.7 wt%, the temperature is maintained at 82°C, and the time is 7 min for cleaning and texturing. Since the front of the silicon wafer has been deplated and there is no oxidation area, an effective light-trapping texture surface can be formed during the texturing process; and in the laser patterning area on the back, the alkaline solution can effectively corrode the bottom poly-Si to form an isolated insulating structure. The subsequent acid (HF / HCl) cleaning tank of the texturing tank can further remove the residual PSG layer and BSG layer of the silicon wafer.

[0113] S11, using ALD deposition method to deposit AlO on the front and back sides of the processed silicon wafer x The film is generated by the reaction of Al(CH3)3 and water vapor, with a thickness of about 8 nm and a process temperature of 250°C. Then, SiN is deposited on both sides of the silicon wafer using a tubular PECVD device. x The film has a thickness of about 82 nm and a refractive index of 1.95; the reaction gases in the tubular cavity are SiH4 and NH3, the working pressure is 1600mTorr, the power is 12000 W, the temperature is 450℃, the SiH4 gas flow rate is 1300 sccm, the NH3 gas flow rate is 11000 sccm, and the deposition time is 10 min.

[0114] S12. The coated sheet is screen-printed on the back to form a metal contact, and then sintered at 770°C to form an Ag-Si ohmic contact. Finally, the final TBC finished battery is obtained through light injection repair.

[0115] Comparative Example 2

[0116] The only difference between Comparative Example 2 and Example 1 is that the degree of S6 pickling is too high, resulting in excessive corrosion of the BSG layer, as follows:

[0117] S6, alkaline cleaning to remove the boron diffusion layer of the preset n-region and isolation region, the tunneling SiO x The conditions for alkaline cleaning are: KOH solution concentration 2.0 wt%, temperature 80°C. The oxide layer is removed by pickling, and the conditions for pickling are: HF solution concentration in the pickling tank is 20 wt%, and the time is 80 s.

[0118] Performance Testing

[0119] The electrical performance of the solar cells prepared in each embodiment and each comparative example was tested, and the data are shown in the following table:

[0120]

[0121] From the data in the above table, we can see that:

[0122] First, for Example 1, since there is no obvious height difference between the silicon wafer substrate surface of the isolation area on the back of the battery and the silicon wafer substrate surfaces of the n-region and p-region on both sides, it is not only beneficial to the carrier transmission performance in the body, but also increases the internal reflection of the back side to light, so that the optical performance of the battery can be further improved. In addition, compared with the isolation area structure of the pyramid velvet surface, the polished isolation area surface is more conducive to the uniform deposition of the passivation anti-reflection film, so that the surface passivation performance can be improved, and thus the corresponding battery performance is better.

[0123] Compared with Example 1, since Example 2 adopts the "continuous gradual through-source" boron diffusion process, the boron doping amount in the formed BSG layer is relatively large and the layer is relatively thick, which can slow down the thinning of the layer during the subsequent acid cleaning process and reduce the risk of phosphorus atoms diffusing into the boron diffusion layer during the subsequent phosphorus diffusion process. In addition, in the BSG layer with a higher boron doping concentration, some boron atoms can be further pushed into the body during the subsequent phosphorus diffusion process, so that the surface doping concentration of the boron diffusion layer is increased, which effectively reduces the subsequent gold / semi contact resistance, thereby having a higher FF , the corresponding battery performance is best.

[0124] For Comparative Example 1, since the battery isolation area structure is a conventional pyramid velvet surface and the height difference between the p-region / isolation region / n-region is obvious, the battery carrier transmission performance is limited. At the same time, the isolation area structure of the pyramid velvet surface is not conducive to the internal reflection of the incident light on the back side, and on the other hand, it will also cause unevenness in the subsequent deposition of the passivation anti-reflection film, making the battery performance lower than that of Example 1.

[0125] For Comparative Example 2, due to the high HF concentration in the subsequent acid cleaning tank during the alkaline cleaning process, the BSG layer on the surface of the boron diffusion layer is also excessively corroded while the oxide layer is pickled. As a result, during the phosphorus diffusion process, the phosphorus-doped atoms cannot be effectively blocked from diffusing into the boron diffusion layer, and there is a risk of boron diffusion being transformed into a phosphorus diffusion layer. Therefore, the corresponding battery performance is the lowest.

[0126] The raw materials and equipment used in the present invention, unless otherwise specified, are all commonly used raw materials and equipment in the art; the methods used in the present invention, unless otherwise specified, are all conventional methods in the art.

[0127] The above description is only a preferred embodiment of the present invention and does not limit the present invention in any way. Any simple modification, change and equivalent transformation made to the above embodiment based on the technical essence of the present invention still falls within the protection scope of the technical solution of the present invention.

Claims

1. A method for preparing a polished TBC battery with no height difference isolation area, characterized in that include: S1, double-sided polishing of silicon wafer; S2, ultraviolet laser oxidation of the preset n-region and isolation region on the back of the silicon wafer to form an oxide layer; S3, back-side one-time deposition tunneling SiO x layer, i-poly-Si layer; S4, boron diffusion, so that the inner layer and the surface layer of the i-poly-Si layer are converted into a boron diffusion layer and a BSG layer respectively; S5, laser removal of the BSG layer in the preset n-region and isolation region; S6, alkaline cleaning to remove the boron diffusion layer of the preset n-region and isolation region, the tunneling SiO x layer; pickling to remove the oxide layer; S7, ultraviolet laser oxidation of the silicon surface of the preset isolation area to form an oxide layer; S8, back secondary deposition tunneling SiO x layer, i-poly-Si layer; S9, phosphorus diffusion, so that the inner layer and the surface layer of the i-poly-Si layer are converted into a phosphorus diffusion layer and a PSG layer respectively; S10, laser removal of the PSG layer in the preset p-region and isolation region; S11, removing the coating on the front and side surfaces of the silicon wafer; S12, alkali washing and texturing to remove the phosphorus diffusion layer of the preset p-region and isolation region, the tunneling SiO x layer, and form a pyramid velvet surface on the front side of the silicon wafer, and pickle to remove the residual PSG layer, BSG layer and oxide layer; S13, double-sided deposition of passivation anti-reflection film; S14, screen printing, sintering, light injection.

2. The preparation method according to claim 1, characterized in that: In S6, the alkaline cleaning conditions are: KOH solution concentration 1.7-2.2 wt%, temperature 75-85°C.

3. The preparation method according to claim 1 or 2, characterized in that: In S6, the pickling conditions are: HF solution concentration 1-10 wt%, time 30-60 s.

4. The preparation method according to claim 1, characterized in that: In S12, the conditions for alkali washing and texturing are: KOH solution concentration 1.5-1.8 wt%, temperature 80-85°C, time 6-12 min.

5. The preparation method according to claim 1 or 4, characterized in that: In S12, the pickling conditions are: HF solution concentration 20-40 wt%, time 60-200 s.

6. The preparation method according to claim 1, characterized in that: In S2 and S7, the conditions of the ultraviolet laser are: laser wavelength 300-400 nm, power 10-100 W, processing time 1-20 s, and oxide layer thickness 2-50 nm.

7. The preparation method according to claim 1, characterized in that: In S4, the conditions for boron diffusion are: boron diffusion temperature 800-950°C, diffusion time 5-50 min, BCl3 flow rate 50-500 sccm, O2 flow rate 500-2000 sccm; oxidation advancement temperature 900-1050°C, O2 flow rate 5000-30000 sccm, advancement time 30-80 min, and the thickness of the resulting BSG layer is 30-70 nm.

8. The preparation method according to claim 1, characterized in that: In S4, the conditions for the boron diffusion are: Low temperature and high concentration boron diffusion: temperature 800-900°C, diffusion time 5-30 min, BCl3 flow rate 200-500 sccm, O2 flow rate 1000-2000 sccm; High temperature medium concentration source + oxidation advancement: temperature 930~1050℃, BCl3 flow rate 100~200 sccm, O2 flow rate 10000~50000 sccm, advancement time 20~50 min; Medium temperature and low concentration source + oxidation advancement: temperature 900~950℃, BCl3 flow rate 30~100 sccm, O2 flow rate 3000~8000sccm, advancement time 10~50 min; the thickness of the obtained BSG layer is 30~70 nm.

9. The preparation method according to claim 1, characterized in that: In S5 and S10, the laser conditions are: laser wavelength 400~600 nm, frequency 500~700 KHz, marking speed 40000~50000 mm / s, power 10~50 W, and processing time 1~5 s.

10. The preparation method according to claim 1, characterized in that: In S9, the conditions for phosphorus diffusion are as follows: first, a mixed gas of POCl3 and O2 is introduced at a temperature of 750~850°C, a diffusion time of 5~30 min, a POCl3 flow rate carried by N2 of 500~1200sccm, and an O2 flow rate of 500~1000sccm; then, O2 is introduced for oxidation advancement at a temperature of 850~950°C, an advancement time of 20~60 min, and an O2 flow rate of 1000~10000sccm to generate a PSG layer with a thickness of 30~70 nm.

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