Preparation method and system of high-efficiency heterojunction battery assembly

Abstract

The invention provides a preparation method and system of a high-efficiency heterojunction battery assembly, and the method comprises the steps: adjusting the reagent concentration, soaking time and reaction temperature in a texturing cleaning process according to the structural characteristics of an N-type silicon wafer of a heterojunction battery; a microcrystal process is introduced into an amorphous silicon thin film deposition process, and various types of microcrystalline silicon thin films are deposited in a batch mode; plating a transparent conductive film TCO after target optimization, and carrying out silk-screen printing on the coated silicon wafer through silver-coated copper slurry; and optimizing a component preparation process and a packaging material by taking reduction of battery standing attenuation, half cutting loss and thermal environment attenuation as targets, and packaging the heterojunction battery into the heterojunction battery component through the optimized component preparation process and packaging material. According to the method, a plurality of preparation processes are optimized, so that the power loss in the preparation process of the heterojunction battery assembly can be reduced, and the high-efficiency heterojunction battery assembly is prepared.

Description

Technical Field

[0001] The present application relates to the technical field of photovoltaic module preparation, and in particular to a method and system for preparing a high-efficiency heterojunction battery module. Background Art

[0002] In the field of solar cells, as P-type cells are gradually approaching the conversion efficiency limit, N-type cells will become the mainstream development direction of the next generation of solar cell technology. N-type cells include intrinsic thin-film heterojunction cells (Heterojunction Technology, referred to as HJT) and TOPCon cells, etc. Among them, HJT cells are increasingly attracting people's attention due to their advantages such as high photoelectric conversion efficiency.

[0003] However, although the theoretical efficiency of HJT cells is high, in actual applications, inappropriate manufacturing processes will reduce the efficiency of finished heterojunction battery components. For example, power loss may occur during component packaging. Therefore, how to optimize the manufacturing process of HJT battery components to prepare high-efficiency heterojunction battery components has become an urgent problem to be solved. Summary of the invention

[0004] The present application aims to solve one of the technical problems in the related art at least to some extent.

[0005] To this end, the first purpose of the present application is to propose a method for preparing a high-efficiency heterojunction battery module, which can reduce the power loss in the preparation process of the heterojunction battery module by optimizing multiple preparation processes, and prepare a high-efficiency heterojunction battery module.

[0006] The second objective of the present application is to provide a system for preparing a high-efficiency heterojunction battery assembly.

[0007] A third object of the present application is to provide a non-transitory computer-readable storage medium.

[0008] To achieve the above-mentioned object, the first aspect of the present application is to provide a method for preparing a high-efficiency heterojunction battery component, the method comprising the following steps:

[0009] According to the structural characteristics of the N-type silicon wafer of the heterojunction battery, the reagent concentration, immersion time and reaction temperature in the texturing and cleaning process are adjusted;

[0010] Introducing microcrystalline technology into the amorphous silicon thin film deposition process, depositing various types of microcrystalline silicon thin films on both sides of each silicon wafer after texturing and cleaning in batches;

[0011] After depositing the microcrystalline silicon thin film, a transparent conductive thin film TCO with optimized target material is plated on the silicon wafer, and the plated silicon wafer is screen-printed with silver-coated copper slurry;

[0012] The component preparation process and packaging materials are optimized with the goal of reducing the battery static attenuation, half-cut loss and thermal environment attenuation. Through the optimized component preparation process and packaging materials, the heterojunction batteries obtained by screen printing are packaged into heterojunction battery components.

[0013] Optionally, in one embodiment of the present application, the component preparation process and packaging materials are optimized with the goal of reducing the static attenuation of the battery, including: detecting the stability parameters of various materials of the heterojunction battery, and controlling the temperature, humidity and light conditions in the packaging environment according to the stability parameters; adding light-converting substances to the anti-reflection film on the photovoltaic glass surface of the heterojunction battery, and using a highly reflective black film as the photovoltaic film in the packaging material; adding a water-blocking material generated by mixing butyl rubber and silica gel to the packaging material.

[0014] Optionally, in one embodiment of the present application, the component preparation process and packaging materials are optimized with the goal of reducing the half-cut loss, including: combining the shingling technology and the strategy of cutting from the back field side to perform cell cutting and slicing; and passivating the edge cut defect area after the heterojunction cell string is cut through the liquid phase edge passivation strategy LEPS.

[0015] Optionally, in one embodiment of the present application, before the adjustment of the texturing and cleaning process, it also includes: preparing an ultra-thin N-type silicon wafer with a thickness less than a preset thickness threshold through an optimized slicing process, optimizing the component preparation process and packaging materials with the goal of reducing the thermal environment attenuation, including: performing light injection treatment on the heterojunction battery through light injection technology; using a low-melting point brazing alloy as a welding material, adjusting the welding temperature based on the melting point of the low-melting point brazing alloy and the thickness of the ultra-thin N-type silicon wafer, and performing low-temperature welding at the adjusted welding temperature.

[0016] Optionally, in one embodiment of the present application, the adjustment of the reagent concentration, immersion time and reaction temperature in the texturing and cleaning process includes: adjusting the reagent concentration, immersion time and reaction temperature of the etching solution according to the corrosion rate of the ultra-thin N-type silicon wafer to the chemical reagent, with the goal of generating a uniform pyramid structure of a preset size.

[0017] Optionally, in one embodiment of the present application, the screen printing of the coated silicon wafer by silver-coated copper slurry includes: selecting a plurality of constituent materials of the polymer resin carrier according to the low-temperature process requirements of the ultra-thin N-type silicon wafer, so that the generated polymer resin carrier can be cured at the temperature required by the low-temperature process; adjusting the ratio of silver powder, copper powder and the polymer resin carrier to generate silver-coated copper slurry.

[0018] To achieve the above-mentioned purpose, the second aspect of the present application also proposes a low-cost heterojunction battery assembly preparation system, comprising the following modules:

[0019] An adjustment module is used to adjust the reagent concentration, immersion time and reaction temperature in the texturing and cleaning process according to the structural characteristics of the N-type silicon wafer of the heterojunction battery;

[0020] The deposition module is used to introduce the microcrystalline process into the amorphous silicon thin film deposition process, and deposit various types of microcrystalline silicon thin films on both sides of each silicon wafer after texturing and cleaning in a batch manner;

[0021] The plating and printing module is used to plate the transparent conductive film TCO after the target material is optimized on the silicon wafer after the microcrystalline silicon film is deposited, and screen print the coated silicon wafer with silver-coated copper paste;

[0022] The packaging module is used to optimize the component preparation process and packaging materials with the goal of reducing the static attenuation, half-cut loss and thermal environment attenuation of the battery. Through the optimized component preparation process and packaging materials, the heterojunction battery obtained by screen printing is packaged into a heterojunction battery component.

[0023] In order to implement the above-mentioned embodiments, the third aspect of the present application also proposes a non-temporary computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, the method for preparing a high-efficiency heterojunction battery component in the above-mentioned first aspect is implemented.

[0024] The technical solution provided by the embodiments of the present application brings at least the following beneficial effects: the present application first adjusts the reagent concentration, immersion time and reaction temperature in the texturing and cleaning process according to the structural characteristics of the N-type silicon wafer of the heterojunction battery; then introduces the microcrystalline process in the amorphous silicon thin film deposition process, and deposits various types of microcrystalline silicon films on both sides of each silicon wafer after texturing and cleaning in a batch manner; then, the transparent conductive film TCO after the target material is optimized is plated, and the plated silicon wafer is screen-printed with silver-coated copper slurry; finally, the component preparation process and packaging materials are optimized with the goal of reducing the static attenuation, half-cutting loss and thermal environment attenuation of the battery, and the heterojunction battery obtained by screen printing is packaged into a heterojunction battery component through the optimized component preparation process and packaging materials. Therefore, this application introduces new technologies and adjusts process parameters according to the characteristics of heterojunction battery modules by optimizing multiple preparation processes such as texturing and cleaning, coating process, screen printing and component packaging. It can reduce power loss in the preparation process of heterojunction battery modules, prepare high-efficiency heterojunction battery modules, improve the photoelectric conversion efficiency of heterojunction battery modules, ensure the quality of heterojunction battery modules, and facilitate the mass production of heterojunction battery modules.

[0025] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0027] Figure 1 A flow chart of a method for preparing a high-efficiency heterojunction battery assembly proposed in an embodiment of the present application;

[0028] Figure 2 A flow chart of a method for optimizing a heterojunction battery assembly packaging process proposed in an embodiment of the present application;

[0029] Figure 3 A flow chart of a method for reducing thermal environment attenuation proposed in an embodiment of the present application;

[0030] Figure 4 A schematic diagram of the structure of a high-efficiency heterojunction battery assembly preparation system proposed in an embodiment of the present application. DETAILED DESCRIPTION

[0031] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present invention, and should not be construed as limiting the present invention.

[0032] A method and system for preparing a high-efficiency heterojunction battery assembly according to an embodiment of the present invention will be described below with reference to the accompanying drawings.

[0033] Figure 1 A flow chart of a method for preparing a high-efficiency heterojunction battery assembly proposed in an embodiment of the present application, such as Figure 1 As shown, the method comprises the following steps:

[0034] Step S101, adjusting the reagent concentration, immersion time and reaction temperature in the texturing and cleaning process according to the structural characteristics of the N-type silicon wafer of the heterojunction battery.

[0035] Specifically, this step first performs a texturing and cleaning process. Since the surface of the silicon wafer may be contaminated by organic impurities, particles, metal ions, etc. after the previous processing steps, the present application first cleans the silicon wafer when making the battery. At the same time, in order to increase the absorption of light energy and enhance the passivation effect, a pyramid morphology is etched on the surface of the silicon wafer as a light trapping structure.

[0036] Among them, when performing texturing cleaning, the present application, based on the current texturing cleaning process, adjusts multiple parameters such as the reagent concentration and type of the etching solution in the texturing cleaning process, the immersion time of the silicon wafer in the etching solution, and the corrosion reaction temperature according to the structural characteristics of the N-type silicon wafer of the heterojunction battery currently obtained and the requirements of subsequent processes, thereby optimizing and improving the texturing cleaning process to generate a pyramid structure that better meets the needs of heterojunction batteries.

[0037] Among them, the structural characteristics of N-type silicon wafers include parameters such as the size and thickness of the silicon wafer, and can also include the anisotropy of N-type silicon wafers. The anisotropy of N-type silicon wafers is mainly manifested in their crystal structure and electrical properties. Since N-type silicon wafers are made by doping pentavalent elements (such as phosphorus) into pure silicon, this makes N-type silicon wafers have more free electrons and a small number of holes, thus forming a semiconductor structure dominated by electrons. This difference in material properties leads to the anisotropic performance of N-type silicon wafers in the texturing and cleaning process, including anisotropy in various aspects such as physical properties, optical properties and electrical properties.

[0038] The present application adjusts the reagent concentration, immersion time and reaction temperature in the texturing and cleaning process according to the structural characteristics and anisotropy of the currently obtained N-type silicon wafers, so as to adapt to the structural characteristics and anisotropy of the current crystalline silicon materials.

[0039] For example, it is assumed that before adjusting the texturing and cleaning process, that is, in the early processing steps of the silicon wafer, an ultra-thin N-type silicon wafer with a thickness less than a preset thickness threshold is first prepared through an optimized slicing process. It should be noted that since the substrate of the heterojunction battery is an N-type silicon wafer, this type of silicon wafer has a higher thinning potential, and the structure of the heterojunction battery cell has a strong compatibility with thin silicon wafers. Therefore, the present application first optimizes the slicing process to prepare a large-size ultra-thin N-type silicon wafer with a thickness less than a preset thickness threshold. Among them, when the thickness of the silicon wafer is less than the preset thickness threshold, it indicates that the silicon wafer is an ultra-thin N-type silicon wafer that meets the requirements. For example, the thickness threshold can be set to 130μm, or the thickness of the heterojunction battery cell can be set to less than 100μm based on the analysis of the structural characteristics of the silicon wafer and the development of slicing technology.

[0040] In specific implementation, as a possible implementation method, the diamond wire cutting technology can be optimized to enable silicon wafers to be thinned while maintaining a low fracture and breakage rate. The thinning of silicon wafers is achieved by continuously optimizing cutting wire management, tension control, clamping feed, multi-spindle dynamic balancing and crystal line detection technologies.

[0041] Furthermore, in this embodiment, the reagent concentration, immersion time, and reaction temperature in the texturing cleaning process are adjusted, including: adjusting the reagent concentration, immersion time, and reaction temperature of the etching solution according to the corrosion rate of the ultra-thin N-type silicon wafer to the chemical reagent, with the goal of generating a uniform pyramid structure of a preset size. That is, in this example, when adjusting the reagent concentration, immersion time, and reaction temperature in the texturing cleaning process for the currently obtained ultra-thin N-type silicon wafer, the parameters are mainly adjusted according to the different corrosion rates of the ultra-thin silicon wafer to the chemical reagent on different crystal surfaces.

[0042] Specifically, when adjusting the reagent concentration in this example, the concentration of the alkali solution in the etching solution has a significant effect on the etching rate. Increasing the concentration of the alkali solution, the etching rate first increases and then decreases. The etching rate can be controlled by adjusting the concentration of alkali solutions such as NaOH or KOH to adapt to the characteristics of the crystal surface of the current ultra-thin N-type silicon wafer. For example, currently, a 30-40% KOH solution is commonly used for etching conventional N-type silicon wafers, maintaining a temperature of 70-80°C. Under this condition, the silicon wafer is at a high etching rate, while in this example, the concentration of the alkali solution can be reduced to adapt to the thinner silicon wafer thickness.

[0043] When controlling the immersion time in this example, since the immersion time affects the corrosion depth of the silicon wafer surface, the appropriate immersion time can ensure that the damaged layer on the silicon wafer surface is effectively removed while avoiding excessive corrosion. For the pre-cleaning process of the diamond wire cut single crystal silicon wafer in this example, a 10% NaOH solution can be used at 78°C for 50 seconds to achieve single-sided thinning of the silicon wafer.

[0044] When adjusting the reaction temperature in this example, the reaction temperature has a significant effect on the corrosion rate. Increasing the temperature usually increases the corrosion rate, but too high a temperature may cause uneven corrosion on the surface of the silicon wafer. Therefore, it is necessary to select an appropriate reaction temperature while ensuring effective removal of the damaged layer and impurities, but without excessively corroding the normal area of ​​the ultra-thin N-type silicon wafer.

[0045] Therefore, this embodiment reasonably and effectively adjusts the parameters of the texturing and cleaning process to adapt to the structural characteristics and anisotropy of the current N-type silicon wafer. After continuous process optimization, a pyramid structure of uniform size (such as 1-2μm) can be stably generated on the surface of the silicon wafer, further enhancing the light trapping effect and reducing surface reflection, which is beneficial to improving the efficiency of the battery.

[0046] Step S102, introducing a microcrystalline process into the amorphous silicon thin film deposition process, and depositing various types of microcrystalline silicon thin films on both sides of each silicon wafer after texturing and cleaning in a batch manner.

[0047] Specifically, this step is the process of depositing an amorphous silicon thin film. This process uses chemical vapor deposition to deposit an intrinsic amorphous silicon thin film and an impurity-doped amorphous silicon thin film of the opposite conductivity type on both sides of the silicon wafer. Amorphous silicon thin film deposition determines the effectiveness of heterojunction battery passivation, and the passivation effect is the guarantee of improved conversion efficiency. By continuously adjusting and optimizing the coating process, the present application can introduce a microcrystalline process in the mass production of heterojunction batteries, that is, when preparing heterojunction batteries in a batch manner, the above-mentioned types of microcrystalline silicon films are deposited on both sides of each silicon wafer after the previous step of texturing and cleaning.

[0048] Among them, after the microcrystal process is introduced in the heterojunction battery, a microcrystalline silicon film is formed on the surface of the battery through chemical vapor deposition (CVD) technology. Compared with the traditional amorphous silicon film, the microcrystalline silicon film has a higher electron mobility, which helps to improve the conductivity and transmittance of the battery, thereby improving the photoelectric conversion efficiency of the battery. This application further increases the light transmittance of the battery cell while increasing the doping concentration through the microcrystal process, while reducing the resistance of the doping layer. The crystallization rate of the mass-produced battery cell reaches 65%, and the efficiency reaches more than 25.5%.

[0049] Step S103 , coating a transparent conductive film TCO after target material optimization on the silicon wafer after the microcrystalline silicon film is deposited, and screen printing the coated silicon wafer with silver-coated copper slurry.

[0050] Specifically, this step first deposits a metal oxide conductive layer (TCO), which uses physical vapor deposition to bombard the cathode target with argon ions generated by glow discharge. The target is sputtered and deposited on the surface of the silicon wafer to form a transparent conductive oxide layer film, which is used as an anti-reflection layer and a conductive layer for lateral carrier transport to the electrode. In order to improve the performance of heterojunction cells, this application optimizes the target material of the TCO film and continuously adjusts the coating process. After coating the TCO film with optimized target material, the efficiency can be effectively improved compared with the benchmark cell.

[0051] For example, the target material of the transparent conductive film TCO is optimized, including adding a metal nanowire structure to the target material of the transparent conductive film TCO; according to the added metal nanowire structure, the amount of the target material of the transparent conductive film TCO is reduced. Another example is coating a graphene film on a composite TCO film with a metal nanowire structure added; according to the amount of graphene film used, the amount of the target material of the composite TCO film is reduced.

[0052] Furthermore, this step also performs the last process in the preparation of the battery terminal, namely the screen printing process. Since the process temperature of the heterojunction battery is limited to a low temperature environment within 200 degrees Celsius, the traditional high-temperature sintering production process is not suitable for the production of heterojunction batteries. Therefore, in the preparation process of the heterojunction battery, the conductive paste is mainly applied to the solar cell through screen printing technology to form electrodes and wires. This application uses silver-coated copper slurry to screen print the coated silicon wafer to reduce costs.

[0053] In one embodiment of the present application, screen printing is performed on a coated silicon wafer using a silver-coated copper slurry, including: selecting a plurality of constituent materials of a polymer resin carrier according to the low-temperature process requirements of an ultra-thin N-type silicon wafer, so that the generated polymer resin carrier can be cured at a temperature required by the low-temperature process; and adjusting the ratio of silver powder, copper powder and the polymer resin carrier to generate the silver-coated copper slurry.

[0054] Specifically, in this embodiment, the production of silver-coated copper paste involves the selection of a key material, resin. As part of the organic carrier, the resin has an important influence on the printing performance of the paste and the bonding strength after sintering. The resin usually selected needs to be cured at low temperature to meet the low temperature process requirements of the HJT battery. However, due to the low temperature process of the ultra-thin N-type silicon wafer of this application, there are more special requirements for temperature, such as lower temperatures. Therefore, when selecting a variety of constituent materials of the polymer resin carrier, this application needs to meet the requirement that the resin can be cured at the low temperature required by the large-size ultra-thin N-type silicon wafer.

[0055] For example, the polymer resin carrier is composed of the following materials: polyester, polyacrylate, ethylene glycol ether ester, silicone resin and other polymers. Among them, the embodiments of the present application can use other polymers of the corresponding type as carriers according to specific low-temperature curing application requirements to meet the performance requirements of curing under specific low-temperature conditions.

[0056] Further, according to the prepared polymer resin carrier, the silver-coated copper slurry is prepared. In one embodiment of the present application, it may include: adjusting the ratio of silver powder, copper powder and polymer resin carrier in the silver-coated copper slurry to maintain the conversion efficiency of the heterojunction battery as a constraint. Specifically, the silver-coated copper slurry needs to meet certain performance requirements, including good printability, suitable sintering temperature, low resistivity and high heat resistance, and these performance indicators can be changed by adjusting the ratio of various materials in the slurry. In this embodiment, the ratio of silver powder, copper powder and polymer resin carrier in the silver-coated copper slurry can be adjusted to maintain the conversion efficiency of the heterojunction battery as a constraint. Then, according to first preparing the polymer resin carrier and then preparing the organic carrier mixture, the silver powder, silver-coated copper powder, resin, diluent, curing agent and rust inhibitor are finally mixed in a determined ratio to form a silver-coated copper slurry. Then, the obtained silver-coated copper slurry is used to screen print the coated silicon wafer.

[0057] Step S104, optimizing the component preparation process and packaging materials with the goal of reducing the static attenuation, half-cut loss and thermal environment attenuation of the battery, and packaging the heterojunction battery obtained by screen printing into a heterojunction battery component through the optimized component preparation process and packaging materials.

[0058] Specifically, this step is to package the heterojunction battery components, and the heterojunction batteries obtained in the above steps are packaged into components. While HJT batteries continue to achieve higher efficiency, this step improves the component power from the component end. This can be achieved by matching advanced packaging materials with large-size ultra-thin batteries and designing new component formats.

[0059] It should be noted that HJT batteries usually have some power loss in the process of packaging into components. This application optimizes the relevant preparation process at the battery end in the above step and the component packaging end in this step to achieve the three goals of battery static attenuation, half-cut loss and thermal environment attenuation. Through the optimized component preparation process and packaging materials, heterojunction batteries are prepared, and the heterojunction batteries obtained by screen printing are packaged into heterojunction battery components, thereby greatly reducing the power loss in the component manufacturing process and improving the efficiency of the battery components finally prepared. The specific implementation process of achieving the above three goals is described in detail below.

[0060] In order to more clearly describe the specific implementation process of reducing battery static attenuation in the present application, an optimization method proposed in an embodiment of the present application is exemplified below. Figure 2 This is a flow chart of a method for optimizing a heterojunction battery assembly packaging process proposed in an embodiment of the present application, such as Figure 2 As shown, the method comprises the following steps:

[0061] Step S201, detecting the stability parameters of various materials of the heterojunction battery, and controlling the temperature, humidity and light conditions in the packaging environment according to the stability parameters.

[0062] Specifically, static attenuation in solar cell packaging refers to the power drop phenomenon caused by chemical reactions and physical changes in the materials during or after the packaging process, which is usually related to the stability of the battery materials, the selection of packaging materials, and environmental factors. This step first detects the stability parameters of various materials of the battery, including the materials used in the positive and negative electrodes of the battery, to determine the chemical stability and structural stability of the relevant materials. Then, various parameters in the production environment are controlled according to the test results, including controlling the temperature, humidity, and light conditions during the battery production and packaging process to reduce the impact of environmental factors on battery performance.

[0063] Step S202, adding a light-converting substance to the anti-reflection film on the photovoltaic glass surface of the heterojunction cell, and using a highly reflective black adhesive film as the photovoltaic adhesive film in the packaging material.

[0064] It should be noted that the main packaging materials of HJT include photovoltaic film, photovoltaic glass and backplane. In the related technology, in order to improve the transmittance of photovoltaic glass, a layer of anti-reflection film is generally coated on the surface of the photovoltaic glass substrate through the anti-reflection coating process of photovoltaic glass. The anti-reflection film is mainly a porous film layer composed of nano-SiO2 particles, which has good anti-reflection and increased light transmittance effects. Then it is tempered and sintered at high temperature to enhance the bonding force between the film layer and the glass and enhance the strength of the glass. In addition, since the transparent conductive film layer and the amorphous / microcrystalline silicon film layer on the surface of the HJT battery are more sensitive to ultraviolet light, the current of the battery is lower than that of ordinary batteries. To solve this problem, the related technology usually adds light-converting substances to the photovoltaic film to convert ultraviolet light into blue light, reduce the battery's absorption of short-wave light (ultraviolet light), and effectively increase the power generation of the component.

[0065] This step is to transfer the light conversion function from the photovoltaic film to the anti-reflection film on the surface of the photovoltaic glass. Since the thickness of the anti-reflection film coated on the photovoltaic glass is much smaller than the thickness of the photovoltaic film, the application adds light conversion substances to the anti-reflection film on the surface of the photovoltaic glass, which can reduce the amount of light conversion substances and reduce the cost of light conversion. In addition, after the light conversion on the photovoltaic glass, the absorbed ultraviolet light is converted into blue light, thereby solving the problem that the TCO film layer and the amorphous silicon film layer absorb ultraviolet light and reduce the battery current, which can not only improve the power generation and reliability of the HJT photovoltaic module, but also improve the ultraviolet (UV) aging resistance of the module.

[0066] Furthermore, this step also uses a highly reflective black film, which has a high reflectivity in the long-wave band and can effectively reduce packaging losses. When used in combination with the above-mentioned UV-resistant photovoltaic glass, it can reduce the power generation temperature of the component and improve the power generation efficiency.

[0067] Step S203, adding a water-blocking material produced by mixing butyl rubber and silica gel to the packaging material.

[0068] Specifically, selecting packaging materials with high weather resistance, such as packaging materials with high light transmittance and low water vapor permeability, can reduce the battery performance degradation caused by environmental factors. Therefore, this step is based on the water vapor sensitivity of heterojunction batteries. By mixing butyl rubber and silica gel to generate a water-blocking material, the cost of the water-blocking material can be reduced while effectively blocking water vapor penetration and alleviating the static attenuation of the battery.

[0069] In this embodiment, other methods can also be combined to reduce the static attenuation of the battery, including: adopting a main-grid-free component packaging solution, through 0BB (main-grid-free) technology, the consumption of silver paste can be reduced, the effective illumination area can be increased, and the power generation efficiency of the photovoltaic module can be improved. And the use of a carrier-encapsulated integrated film can reduce the amount of UV glue used, cooperate with the light-conversion synergistic optimization formula system, shield ultraviolet rays, and improve the power generation power and UV aging resistance of the HJT component. Strict quality control can also be carried out at each stage of battery production and packaging to ensure the quality of batteries and components, thereby reducing the risk of static attenuation. For example, the battery material and structure can also be optimized: by improving the material and structure of the HJT battery, such as using high-quality silicon wafers and optimized amorphous silicon layers, the sensitivity of the battery to environmental changes can be reduced, thereby reducing attenuation.

[0070] Therefore, through the optimization method of this embodiment, the relevant processes in the component packaging process are optimized, thereby reducing the static attenuation of the battery.

[0071] In one embodiment of the present application, the component preparation process and packaging materials are optimized with the goal of reducing the half-cut loss, including: combining the shingling technology and the strategy of cutting from the back field side to perform cell cutting and slicing; and passivating the edge cut defect area after the heterojunction cell string is cut through the liquid phase edge passivation strategy LEPS.

[0072] Specifically, in this embodiment, in order to reduce the loss of cutting in half, the shingling technology is first used. The shingling technology can optimize the connection method of the battery cells and the structure of the component. The laser slicing technology is used to cut the entire battery into several small battery strips, and these small strips are flexibly connected by stacking with conductive glue. By performing this operation, the component structure can be optimized, thereby reducing the efficiency loss caused by battery cutting and slicing. And through high-precision laser cutting and special connection methods, the shingled battery cells can reduce internal losses, improve power generation efficiency, and have better flexibility and anti-shadow shading performance. Then, the cutting strategy is optimized. By analyzing the changes in the photovoltaic performance of the HJT battery when cutting from the emitter side and the back field side, this embodiment chooses the strategy of cutting from the back field side to reduce cutting losses.

[0073] Furthermore, in this embodiment, a liquid phase edge passivation strategy (LEPS) is applied, through which the edge cut defect area of ​​the above-mentioned shingled technology cutting string can be excellently passivated, reducing the performance loss caused by cutting. Thus, the open circuit voltage, fill factor and conversion efficiency of the component can be improved, thereby reducing power loss.

[0074] In this embodiment, other methods may be combined to reduce the half-cut loss, including adopting the main-grid-free component packaging solution, light-conversion packaging glass, and high-reflection black film in the above embodiment.

[0075] In order to more clearly describe the specific implementation process of reducing thermal environment attenuation in the present application, another optimization method proposed in an embodiment of the present application is exemplified below. Figure 3 This is a flow chart of a method for reducing thermal environment attenuation proposed in an embodiment of the present application, such as Figure 3 As shown, the method comprises the following steps:

[0076] Step S301 , performing light injection processing on the heterojunction cell by using light injection technology.

[0077] Specifically, in order to reduce the thermal environment attenuation of HJT cells during the packaging process, this step can perform light injection treatment on the cell through light injection technology. Among them, the light injection process is a process of irradiating semiconductor materials with light to excite electron-hole pairs, thereby generating current. The light injection process helps to reduce light-induced attenuation and improve the conversion efficiency of HJT cells. In addition, light injection can improve battery performance. The light injection annealing process can improve the electrical performance parameters of the battery and enhance the stability of the battery. By controlling the valence and distribution of atoms, the recombination of electrons and holes is reduced, and the stability of the battery is improved. After the stability of the HJT battery is improved, the thermal environment attenuation can be reduced.

[0078] Step S302, using a low melting point brazing alloy as a welding material, adjusting the welding temperature based on the melting point of the low melting point brazing alloy and the thickness of the ultra-thin N-type silicon wafer, and performing low temperature welding at the adjusted welding temperature.

[0079] It should be noted that this step uses low-temperature welding technology under low-temperature process to reduce thermal environment attenuation, and this process can be carried out in the process of preparing the battery end. The use of low-temperature process can reduce the thermal damage and deformation of the silicon wafer, so that the thin silicon wafer in the above embodiment can be used as the substrate. The use of low-temperature welding technology can reduce the amount of silver paste used, and the use of a carrier-encapsulation integrated film can reduce the amount of UV glue used. In conjunction with the light-conversion synergistic optimization formula system, it can shield ultraviolet rays and improve the power generation power and UV aging resistance of the HJT component.

[0080] During specific implementation, in order to further lower the temperature on the basis of the low-temperature welding process in the prior art to reduce thermal environment attenuation, this embodiment uses a low-melting-point brazing alloy as the welding material, and determines the specific welding temperature value used in the low-temperature process based on the melting point of the low-melting-point brazing alloy and the thickness of the ultra-thin N-type silicon wafer. This temperature value is lower than the value of the prior art, and low-temperature welding is then performed at the adjusted welding temperature.

[0081] Specifically, in order to reduce the temperature in low-temperature welding, the present embodiment adopts a new welding technology, that is, a brazing alloy with high cost performance, which can achieve low-temperature welding and reduce thermal stress. Among them, the brazing alloy is usually used for welding strips that connect battery cells and transmit current, and its melting point directly affects the welding temperature. In specific implementation, a new low-melting point brazing alloy can be designed. By alloying, low-melting point elements (such as In and Bi) are added to traditional brazing alloys to prepare a new low-melting point brazing alloy for photovoltaic welding strips, so that welding can be performed at a lower temperature. In addition, the brazing process can be optimized, and the welding time and temperature can be adjusted to reduce the thermal impact during the welding process, thereby reducing the welding temperature.

[0082] In other embodiments of the present application, the welding temperature may be reduced by various methods such as using low-temperature silver paste, using high-mobility target materials, and designing without a main grid.

[0083] On the other hand, as described in the above embodiments, the present application also prepares ultra-thin HJT cells, and thinning can reduce mechanical stress in cell manufacturing, reduce fragmentation rate, and reduce thermal damage to silicon wafers. Therefore, when the N-type silicon wafer is the ultra-thin N-type silicon wafer prepared in the above embodiments, this embodiment determines the welding temperature that the cell can adapt to based on the melting point of the brazing alloy after reducing the melting point in the above various ways and the thickness of the ultra-thin N-type silicon wafer, and then adjusts the welding temperature according to the determined temperature, and performs low-temperature welding at the adjusted welding temperature to achieve the purpose of reducing thermal environment attenuation.

[0084] Therefore, the relevant processes involved are improved in the manner shown in the above-mentioned embodiments. Through the optimized component preparation process and packaging materials, the static attenuation, half-cut loss and thermal environment attenuation of the battery component can be reduced, so that the power loss in the component manufacturing process can be greatly reduced.

[0085] In practical applications, the post-processing process at the component end is also studied to further improve the efficiency of the component. After testing and evaluation, after optimizing the preparation process by the method in the above embodiment, the average power of mass production can reach 711W, the average efficiency can reach 23.85%, and the maximum power of the high-efficiency heterojunction component can reach 750.54W, and the component efficiency can reach 24.13%.

[0086] In summary, the preparation method of the high-efficiency heterojunction battery assembly of the embodiment of the present application first adjusts the reagent concentration, immersion time and reaction temperature in the texturing and cleaning process according to the structural characteristics of the N-type silicon wafer of the heterojunction battery; then introduces the microcrystalline process in the amorphous silicon thin film deposition process, and deposits various types of microcrystalline silicon thin films in a batch manner; then the transparent conductive film TCO after the target material is optimized is plated, and the plated silicon wafer is screen-printed with a silver-coated copper slurry; finally, the assembly preparation process and packaging materials are optimized with the goal of reducing the static attenuation, half-cut loss and thermal environment attenuation of the battery, and the heterojunction battery is packaged into a heterojunction battery assembly through the optimized assembly preparation process and packaging materials. Thus, the method optimizes multiple preparation processes such as texturing and cleaning, coating process, screen printing and assembly packaging, introduces new technologies and adjusts process parameters according to the characteristics of heterojunction battery assemblies, can reduce the power loss in the preparation process of heterojunction battery assemblies, prepare high-efficiency heterojunction battery assemblies, improve the photoelectric conversion efficiency of heterojunction battery assemblies, ensure the quality of heterojunction battery assemblies, and is conducive to the mass production of heterojunction battery assemblies.

[0087] In order to realize the above-mentioned embodiment, the present application also proposes a preparation system of a high-efficiency heterojunction battery assembly. Figure 4 A schematic diagram of the structure of a high-efficiency heterojunction battery assembly preparation system proposed in an embodiment of the present application is shown in FIG. Figure 4 As shown, the system includes: an adjustment module 100 , a deposition module 200 , a plating and printing module 300 and a packaging module 400 .

[0088] The adjustment module 100 is used to adjust the reagent concentration, immersion time and reaction temperature in the texturing and cleaning process according to the structural characteristics of the N-type silicon wafer of the heterojunction battery.

[0089] The deposition module 200 is used to introduce a microcrystalline process into the amorphous silicon thin film deposition process, and deposit various types of microcrystalline silicon thin films on both sides of each silicon wafer after texturing and cleaning in a batch manner.

[0090] The plating and printing module 300 is used to plate a transparent conductive film TCO after target material optimization on the silicon wafer after the microcrystalline silicon film is deposited, and to screen print the plated silicon wafer with silver-coated copper slurry.

[0091] The packaging module 400 is used to optimize the component preparation process and packaging materials with the goal of reducing the static attenuation, half-cut loss and thermal environment attenuation of the battery. Through the optimized component preparation process and packaging materials, the heterojunction battery obtained by screen printing is packaged into a heterojunction battery component.

[0092] Optionally, in one embodiment of the present application, the packaging module 400 is specifically used to: detect stability parameters of various materials of the heterojunction battery, and control the temperature, humidity and lighting conditions in the packaging environment according to the stability parameters; add light-converting substances to the anti-reflection film on the photovoltaic glass surface of the heterojunction battery, and use a highly reflective black film as the photovoltaic film in the packaging material; add a water-blocking material generated by mixing butyl rubber and silica gel to the packaging material.

[0093] Optionally, in one embodiment of the present application, the packaging module 400 is specifically used to: combine the shingling technology and the strategy of cutting from the back field side to perform cell cutting and slicing; and passivate the edge cut defect area after the heterojunction cell string is cut through the liquid phase edge passivation strategy LEPS.

[0094] Optionally, in one embodiment of the present application, the packaging module 400 is specifically used to: perform light injection processing on the heterojunction battery through light injection technology; use a low-melting point brazing alloy as a welding material, adjust the welding temperature based on the melting point of the low-melting point brazing alloy and the thickness of the ultra-thin N-type silicon wafer, and perform low-temperature welding at the adjusted welding temperature.

[0095] Optionally, in one embodiment of the present application, the adjustment module 100 is specifically used to: adjust the reagent concentration, immersion time and reaction temperature of the etching solution according to the corrosion rate of the ultra-thin N-type silicon wafer to the chemical reagent, with the goal of generating a uniform pyramid structure of a preset size.

[0096] Optionally, in one embodiment of the present application, the plating and printing module 300 is specifically used to: select a variety of constituent materials of the polymer resin carrier according to the low-temperature process requirements of the ultra-thin N-type silicon wafer, so that the generated polymer resin carrier can be cured at the temperature required by the low-temperature process; adjust the ratio of silver powder, copper powder and polymer resin carrier to generate silver-coated copper slurry.

[0097] It should be noted that the above explanation of the embodiment of the method for preparing a high-efficiency heterojunction battery assembly is also applicable to the system of this embodiment and will not be repeated here.

[0098] In summary, the preparation system of the high-efficiency heterojunction battery module of the embodiment of the present application, by optimizing multiple preparation processes such as texturing and cleaning, coating process, screen printing and module packaging, introduces new technologies and adjusts process parameters according to the characteristics of heterojunction battery modules, can reduce power losses in the preparation process of heterojunction battery modules, prepare high-efficiency heterojunction battery modules, improve the photoelectric conversion efficiency of heterojunction battery modules, ensure the quality of heterojunction battery modules, and facilitate the mass production of heterojunction battery modules.

[0099] In order to implement the above embodiments, the present application also proposes a non-temporary computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, it implements the method for preparing a high-efficiency heterojunction battery component as described in any one of the above-mentioned first aspect embodiments.

[0100] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.

[0101] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of this application, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0102] Any process or method description in a flowchart or otherwise described herein may be understood to represent a module, fragment or portion of code comprising one or more executable instructions for implementing the steps of a custom logical function or process, and the scope of the preferred embodiments of the present application includes alternative implementations in which functions may not be performed in the order shown or discussed, including performing functions in a substantially simultaneous manner or in the reverse order depending on the functions involved, which should be understood by technicians in the technical field to which the embodiments of the present application belong.

[0103] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as an ordered list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by an instruction execution system, device or apparatus (such as a computer-based system, a system including a processor, or other system that can fetch instructions from an instruction execution system, device or apparatus and execute the instructions), or in combination with these instruction execution systems, devices or apparatuses. For the purpose of this specification, "computer-readable medium" can be any device that can contain, store, communicate, propagate or transmit a program for use by an instruction execution system, device or apparatus, or in combination with these instruction execution systems, devices or apparatuses. More specific examples of computer-readable media (a non-exhaustive list) include the following: an electrical connection with one or more wires (electronic device), a portable computer disk box (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable and programmable read-only memory (EPROM or flash memory), a fiber optic device, and a portable compact disk read-only memory (CDROM). In addition, the computer-readable medium may even be paper or other suitable medium on which the program is printed, since the program may be obtained electronically, for example, by optically scanning the paper or other medium and then editing, interpreting or processing in other suitable ways if necessary, and then stored in a computer memory.

[0104] It should be understood that the various parts of the present application can be implemented by hardware, software, firmware or a combination thereof. In the above-mentioned embodiments, multiple steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented by hardware, as in another embodiment, it can be implemented by any one of the following technologies known in the art or their combination: a discrete logic circuit having a logic gate circuit for implementing a logic function for a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0105] A person skilled in the art may understand that all or part of the steps in the method for implementing the above-mentioned embodiment may be completed by instructing related hardware through a program, and the program may be stored in a computer-readable storage medium, which, when executed, includes one or a combination of the steps of the method embodiment.

[0106] In addition, each functional unit in each embodiment of the present application may be integrated into a processing module, or each unit may exist physically separately, or two or more units may be integrated into one module. The above-mentioned integrated module may be implemented in the form of hardware or in the form of a software functional module. If the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it may also be stored in a computer-readable storage medium.

[0107] The storage medium mentioned above may be a read-only memory, a magnetic disk or an optical disk, etc. Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limiting the present application. A person of ordinary skill in the art may change, modify, replace and modify the above embodiments within the scope of the present application.

Claims

1. A method for preparing a high-efficiency heterojunction battery assembly, characterized in that: The following steps are involved: According to the structural characteristics of the N-type silicon wafer of the heterojunction battery, the reagent concentration, immersion time and reaction temperature in the texturing and cleaning process are adjusted; Introducing microcrystalline technology into the amorphous silicon thin film deposition process, depositing various types of microcrystalline silicon thin films on both sides of each silicon wafer after texturing and cleaning in batches; A transparent conductive film TCO with optimized target material is plated on the silicon wafer after depositing the microcrystalline silicon film, and the plated silicon wafer is screen-printed with silver-coated copper slurry; The component preparation process and packaging materials are optimized with the goal of reducing the battery static attenuation, half-cut loss and thermal environment attenuation. Through the optimized component preparation process and packaging materials, the heterojunction batteries obtained by screen printing are packaged into heterojunction battery components.

2. The preparation method according to claim 1, characterized in that: The component preparation process and packaging materials are optimized with the goal of reducing the static attenuation of the battery, including: Detecting stability parameters of various materials of the heterojunction battery, and controlling temperature, humidity and light conditions in the packaging environment according to the stability parameters; Adding a light-converting substance to the anti-reflection film on the photovoltaic glass surface of the heterojunction cell, and using a highly reflective black adhesive film as the photovoltaic adhesive film in the packaging material; A water-blocking material produced by mixing butyl rubber and silicone rubber is added to the potting material.

3. The preparation method according to claim 1, characterized in that: The component preparation process and packaging materials are optimized with the goal of reducing the halving loss, including: Combining shingling technology with cutting from the back side to slice cells; The edge cut defect area after cutting the heterojunction battery string is passivated through the liquid phase edge passivation strategy LEPS.

4. The preparation method according to claim 1, characterized in that: Before adjusting the texturing and cleaning process, the method further includes: preparing an ultra-thin N-type silicon wafer having a thickness less than a preset thickness threshold by an optimized slicing process, optimizing the component preparation process and packaging materials with the goal of reducing the thermal environment attenuation, including: Light injection treatment is performed on heterojunction cells through light injection technology; A low melting point brazing alloy is used as a welding material, the welding temperature is adjusted based on the melting point of the low melting point brazing alloy and the thickness of the ultra-thin N-type silicon wafer, and low temperature welding is performed at the adjusted welding temperature.

5. The preparation method according to claim 4, characterized in that: The adjusting of the reagent concentration, immersion time and reaction temperature in the texturing and cleaning process comprises: According to the corrosion rate of the ultra-thin N-type silicon wafer to the chemical reagent, the reagent concentration, immersion time and reaction temperature of the etching solution are adjusted with the goal of generating a uniform pyramid structure of a preset size.

6. The preparation method according to claim 4, characterized in that: The method of screen printing the coated silicon wafer by using the silver-coated copper slurry comprises: According to the low temperature process requirements of the ultra-thin N-type silicon wafer, multiple constituent materials of the polymer resin carrier are selected so that the generated polymer resin carrier can be cured at the temperature required by the low temperature process; The ratio of silver powder, copper powder and the polymer resin carrier is adjusted to generate silver-coated copper slurry.

7. A system for preparing a high-efficiency heterojunction battery assembly, characterized in that: include: An adjustment module is used to adjust the reagent concentration, immersion time and reaction temperature in the texturing and cleaning process according to the structural characteristics of the N-type silicon wafer of the heterojunction battery; The deposition module is used to introduce the microcrystalline process into the amorphous silicon thin film deposition process, and deposit various types of microcrystalline silicon thin films on both sides of each silicon wafer after texturing and cleaning in a batch manner; The plating and printing module is used to plate the transparent conductive film TCO after the target material is optimized on the silicon wafer after the microcrystalline silicon film is deposited, and screen print the coated silicon wafer with silver-coated copper paste; The packaging module is used to optimize the component preparation process and packaging materials with the goal of reducing the static attenuation, half-cut loss and thermal environment attenuation of the battery. Through the optimized component preparation process and packaging materials, the heterojunction battery obtained by screen printing is packaged into a heterojunction battery component.

8. The preparation system according to claim 7, characterized in that: The encapsulation module is specifically used for: Detecting stability parameters of various materials of the heterojunction battery, and controlling temperature, humidity and light conditions in the packaging environment according to the stability parameters; Adding a light-converting substance to the anti-reflection film on the photovoltaic glass surface of the heterojunction cell, and using a highly reflective black adhesive film as the photovoltaic adhesive film in the packaging material; A water-blocking material produced by mixing butyl rubber and silicone rubber is added to the potting material.

9. The preparation system according to claim 7, characterized in that: The encapsulation module is specifically used for: Combining shingling technology with cutting from the back side to slice cells; The edge cut defect area after cutting the heterojunction battery string is passivated through the liquid phase edge passivation strategy LEPS.

10. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the method for preparing a high-efficiency heterojunction battery assembly as described in any one of claims 1 to 6 is implemented.

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