Display device and method of manufacturing same

Abstract

A display device and a method of manufacturing the same are provided. The display device includes a substrate, a light emitting element layer on the substrate and including a light emitting element in a display area, and an encapsulation layer including a first inorganic encapsulation layer on the light emitting element layer, an organic encapsulation layer on the first inorganic encapsulation layer, and a second inorganic encapsulation layer on the organic encapsulation layer, at least one of the first inorganic encapsulation layer and the second inorganic encapsulation layer includes a first inorganic layer, a second inorganic layer on the first inorganic layer, and a third inorganic layer on the second inorganic layer, each of the first inorganic layer and the third inorganic layer having a thickness less than a thickness of the second inorganic layer and being about # imgabs0 # or less, and a ratio of a thickness of the first inorganic layer to a thickness of the second inorganic layer is about 0.03 or less.

Description

[0001] This application claims priority to and all benefits derived from Korean Patent Application No. 10-2023-0119590, filed on September 8, 2023, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0002] The present disclosure relates to a display device and a method of manufacturing the display device. Background Art

[0003] With the development of information society, the demand for display devices for displaying images in various fields is increasing. For example, display devices are applied to various electronic devices, such as smart phones, digital cameras, notebook computers, navigation devices, and smart TVs. The display device may be a flat panel display device, such as a liquid crystal display device, a field emission display device, and an organic light emitting display device. Among these flat panel display devices, the light emitting display device includes a light emitting element that enables each pixel of the display panel to emit light itself. Therefore, the light emitting display device can display an image without using a backlight unit that provides light to the display panel.

[0004] The display device may further include pixels emitting predetermined light, scan lines, data lines, and power lines for driving the pixels, a scan driver outputting scan signals to the scan lines, and a display driver outputting data voltages to the data lines. Summary of the invention

[0005] Embodiments of the present disclosure provide a display device including a thin encapsulation layer and a method of manufacturing the display device.

[0006] Embodiments of the present disclosure also provide a display device including an encapsulation layer having specifications required as the display device becomes smaller and thinner and has flexible characteristics, and a method of manufacturing the display device.

[0007] However, the features of the embodiments of the present disclosure are not limited to the features described herein. The above and other features of the embodiments of the present disclosure will become more apparent to those skilled in the art to which the present disclosure belongs by referring to the detailed description of the present disclosure given below.

[0008] According to an embodiment of the present disclosure, a display device includes a substrate, a light-emitting element layer, and an encapsulation layer, wherein a display area and a non-display area surrounding the display area are defined on the substrate, the light-emitting element layer is arranged on the substrate and includes a plurality of light-emitting elements arranged in the display area, and the encapsulation layer includes a first inorganic encapsulation layer arranged on the light-emitting element layer, an organic encapsulation layer arranged on the first inorganic encapsulation layer, and a second inorganic encapsulation layer arranged on the organic encapsulation layer, wherein at least one selected from the first inorganic encapsulation layer and the second inorganic encapsulation layer includes a first inorganic layer, a second inorganic layer arranged on the first inorganic layer, and a third inorganic layer arranged on the second inorganic layer, the thickness of each of the first inorganic layer and the third inorganic layer is less than the thickness of the second inorganic layer, and the thickness of each of the first inorganic layer and the third inorganic layer is about or less, and a ratio of a thickness of the first inorganic layer to a thickness of the second inorganic layer is about 0.03 or less.

[0009] In an embodiment, the sum of the thicknesses of the first inorganic layer, the second inorganic layer, and the third inorganic layer may be about 0.4 micrometers (μm) or less.

[0010] In an embodiment, the layer density of the second inorganic layer may be about 1.7 g / cm3. 3 ) to about 2.10 g / cm 3 In the range of , the layer density of each of the first inorganic layer and the third inorganic layer may be about 2.05 g / cm 3 or greater, and a layer density of each of the first inorganic layer and the third inorganic layer may be greater than a layer density of the second inorganic layer.

[0011] In an embodiment, the refractive index of the second inorganic layer may be in the range of about 1.75 to about 1.90, the refractive index of each of the first inorganic layer and the third inorganic layer may be about 1.85 or greater, and the refractive index of each of the first inorganic layer and the third inorganic layer may be greater than the refractive index of the second inorganic layer.

[0012] In an embodiment, each of the first inorganic layer, the second inorganic layer, and the third inorganic layer may include silicon nitride (SiN x ).

[0013] In an embodiment, each of the first inorganic encapsulating layer and the second inorganic encapsulating layer may include a first inorganic layer, a second inorganic layer, and a third inorganic layer.

[0014] In an embodiment, the first inorganic encapsulation layer and the second inorganic encapsulation layer including the first inorganic layer, the second inorganic layer, and the third inorganic layer may have a thickness of about 5×10 -5 g / m 2 Water vapor transmission rate (WVTR) of day or less.

[0015] In an embodiment, the second inorganic layer may have a thickness of about 3×10 -4 g / m 2 day or less WVTR.

[0016] In an embodiment, the display device may further include a first dam arranged in the non-display area and surrounding the display area, and a second dam surrounding the first dam, wherein the organic encapsulating layer may be arranged in the display area and the non-display area inside the second dam.

[0017] In an embodiment, the first inorganic encapsulating layer and the second inorganic encapsulating layer may directly contact each other in the non-display area outside the second dam.

[0018] In an embodiment, a side surface of the second inorganic layer may be exposed in the non-display area.

[0019] In an embodiment, the display device may further include a circuit layer arranged between the substrate and the light emitting element layer, wherein the circuit layer may include a first semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, a second semiconductor layer, a fourth insulating layer, a third conductive layer, a fifth insulating layer and a fourth conductive layer sequentially arranged on the substrate.

[0020] According to an embodiment of the present disclosure, a method for manufacturing a display device includes: forming a light-emitting element layer including a plurality of light-emitting elements on a substrate; forming a first inorganic encapsulation layer on the light-emitting element layer and forming an organic encapsulation layer on the first inorganic encapsulation layer; and forming a second inorganic encapsulation layer on the organic encapsulation layer, wherein forming the second inorganic encapsulation layer includes: forming a first inorganic layer having a high density on the organic encapsulation layer; forming a second inorganic layer having a low density on the first inorganic layer; and forming a third inorganic layer having a high density on the second inorganic layer, wherein a deposition rate when forming the second inorganic layer is higher than deposition rates when forming the first inorganic layer and forming the third inorganic layer.

[0021] In an embodiment, the deposition rate when forming the second inorganic layer may be about or greater, and the deposition rate when forming the first inorganic layer and the deposition rate when forming the third inorganic layer may each be about or smaller.

[0022] In an embodiment, the thickness of each of the first inorganic layer and the third inorganic layer may be less than the thickness of the second inorganic layer, and the thickness of each of the first inorganic layer and the third inorganic layer may be about 100 Å. or less, and a ratio of a thickness of the first inorganic layer to a thickness of the second inorganic layer may be about 0.03 or less.

[0023] In an embodiment, the layer density of the second inorganic layer may be about 1.7 g / cm 3To about 2.10g / cm 3 In the range of , the layer density of each of the first inorganic layer and the third inorganic layer may be about 2.05 g / cm 3 or greater and the layer density of each of the first inorganic layer and the third inorganic layer may be greater than the layer density of the second inorganic layer, the refractive index of the second inorganic layer may be in the range of about 1.75 to about 1.90, the refractive index of each of the first inorganic layer and the third inorganic layer may be about 1.85 or greater, and the refractive index of each of the first inorganic layer and the third inorganic layer may be greater than the refractive index of the second inorganic layer.

[0024] In embodiments, forming the first inorganic layer and forming the third inorganic layer may each be performed by a plasma enhanced atomic layer deposition (PEALD) process or a plasma enhanced chemical vapor deposition (PECVD) process, and forming the second inorganic layer may be performed by a PECVD process.

[0025] In an embodiment, forming the first inorganic layer and forming the third inorganic layer may be performed using a liquid precursor containing Si—N bonds.

[0026] In an embodiment, the liquid precursor may include at least one selected from cyclosilazane, trisilyamine, bis(diethylamino)silane, bis(t-butylamino)silane, tris(dimethylamino)silane, tris(isopropylamino)silane, tetrakis(dimethylamino)silane, tri(isopropyl)cyclotrisilazane and tetramethyldisilazane.

[0027] In an embodiment, the second inorganic encapsulation layer including the first inorganic layer, the second inorganic layer, and the third inorganic layer may have a thickness of 5×10 -5 g / m 2 day or less, and the second inorganic layer may have a WVTR of 3×10 -4 g / m 2 day or less WVTR. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The above and other features of the present invention will become more apparent by describing in further detail embodiments of the present invention with reference to the accompanying drawings, in which:

[0029] Figure 1 is a perspective view of a display device according to an embodiment;

[0030] Figure 2 yes Figure 1 A plan view of a display device;

[0031] Figure 3 is along Figure 2 A cross-sectional view taken along line AA';

[0032] Figure 4 is a plan view of a display panel according to an embodiment;

[0033] Figure 5 is a pixel circuit diagram of a sub-pixel according to an embodiment;

[0034] Figure 6 is a pixel circuit diagram of a sub-pixel according to an embodiment;

[0035] Figure 7 is a cross-sectional view of a sub-pixel of a display device according to an embodiment;

[0036] Figure 8 is a cross-sectional view of an outer portion of a display panel according to an embodiment;

[0037] Fig. 9 is a schematic view of an encapsulation layer of a display device according to an embodiment;

[0038] Fig.10 yes Fig. 9 an enlarged view of a portion C of;

[0039] Fig.11 is an enlarged view of an inorganic encapsulation region in an outer portion of a display panel according to an embodiment;

[0040] Fig.12 is a flowchart showing a method of manufacturing a display device according to an embodiment;

[0041] Fig.13 It is shown in detail Fig.12 A flow chart of a process for forming a second inorganic encapsulation layer;

[0042] Figures 14 to 19 are views sequentially showing a process of manufacturing a display device according to an embodiment;

[0043] Fig. 20 shows an encapsulation layer of a display device according to an embodiment;

[0044] Fig.21 yes Fig. 20 an enlarged view of an inorganic encapsulation region in an outer portion of a display device;

[0045] Fig. 22 is a perspective view of a head mounted display device according to an embodiment;

[0046] Fig.23 yes Fig. 22 An exploded perspective view of an example of a head mounted display device; and

[0047] Fig.24 is a perspective view of a head mounted display device according to an embodiment. DETAILED DESCRIPTION

[0048] Now the present invention will be described more fully below with reference to the accompanying drawings showing various embodiments of the present invention. However, the present invention can be implemented in different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art.

[0049] It will also be understood that when a layer is referred to as being 'on' another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. Like reference numerals refer to like components throughout the specification.

[0050] It will be understood that, although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, the first element discussed below can be referred to as the second element without departing from the teachings of the present invention. Similarly, the second element can also be referred to as the first element.

[0051] The terms used herein are only for the purpose of describing a specific embodiment, and are not intended to be limited. Unless the context clearly indicates otherwise, "a", "an", "the" and "at least one" as used herein do not represent the limitation of quantity, and are intended to include both the singular and the plural. Therefore, the "a" element mentioned in a claim of the "said" element mentioned later includes one element and multiple elements. For example, unless the context clearly indicates otherwise, "element" has the same meaning as "at least one element". "At least one (at least one)" should not be interpreted as limiting "a" or "an". "Or (or)" means "and / or (and / or)". As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. It will also be understood that when the terms “comprise” and / or “comprising” or “include” and / or “including” are used in the present specification, it specifies the presence of stated features, regions, integers, steps, operations, elements and / or components, but does not preclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components and / or clusters thereof.

[0052] In addition, relative terms such as "lower" or "bottom" and "upper" or "top" may be used herein to describe the relationship of one element to another element as shown in the figure. It will be understood that, in addition to the orientation depicted in the figure, relative terms are intended to include different orientations of the device. For example, if the device in one of the multiple figures is turned over, the element described as being on the "lower" side of the other elements will then be oriented on the "upper" side of the other elements. Therefore, the term "lower" can include both the orientation of "lower" and "upper" according to the specific orientation of the figure. Similarly, if the device in one of the multiple figures is turned over, the element described as being "below" or "under" the other elements will then be oriented to be "above" the other elements. Therefore, the term "below" or "beneath" can include both the orientation of the upper and lower sides.

[0053] As used herein, "about" or "approximately" includes the stated value and means within an acceptable range of deviation for a particular value as determined by one of ordinary skill in the art, taking into account the errors associated with the measurements and with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, or ±5% of the stated value.

[0054] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It will also be understood that, unless explicitly defined as such herein, terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology and the present disclosure, and will not be interpreted in an idealized or overly formal sense.

[0055] Embodiments are described herein with reference to schematically illustrated cross-sectional illustrations of idealized embodiments. Thus, variations in the shapes of the illustrations due to, for example, manufacturing techniques and / or tolerances will be expected. Therefore, the embodiments described herein should not be construed as being limited to the shapes of the specific zones as shown herein, but will include deviations in shape due to, for example, manufacturing. For example, a zone shown or described as flat may typically have rough and / or nonlinear features. In addition, the sharp corners shown may be rounded. Therefore, the zones shown in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shapes of the zones, and are not intended to limit the scope of the claims.

[0056] Hereinafter, embodiments will be described with reference to the accompanying drawings.

[0057] Figure 1 is a perspective view of a display device 10 according to the embodiment.

[0058] Reference Figure 1 The display device 10 is a device for displaying moving images or still images. The display device 10 can be used as a display screen in portable electronic devices such as mobile phones, smart phones, tablet personal computers (PCs), smart watches, watch phones, mobile communication terminals, electronic notebooks, electronic books, portable multimedia players (PMPs), navigation devices, and ultra mobile PCs (UMPCs) and various products such as televisions, notebook computers, monitors, billboards, and Internet of Things (IoT) devices.

[0059] The display device 10 may be a light-emitting display device, such as an organic light-emitting display device including an organic light-emitting diode, a quantum dot light-emitting display device including a quantum dot light-emitting layer, an inorganic light-emitting display device including an inorganic semiconductor, or a micro- or nano-light-emitting display device using a micro- or nano-light-emitting diode. Hereinafter, for the convenience of description, an embodiment in which the display device 10 is an organic light-emitting display device will be described, but the type of the display device is not limited thereto.

[0060] In an embodiment, the display device 10 may be formed to be flat. In an embodiment, for example, the display device 10 may be formed substantially flat on a plane defined by the first direction DR1 and the second direction DR2, and may have a predetermined thickness (or height) in the third direction DR3. In an embodiment, the display device 10 may include a curved surface portion in at least one portion (e.g., an edge region). In addition, the display device 10 may be formed to be flexible so that the display device 10 can be bent, curved, folded, or rolled.

[0061] In an embodiment, the first direction DR1 may be a length direction, a column direction, or a longitudinal direction of an image display surface of the display device 10, and the second direction DR2 may be a direction crossing the first direction DR1, for example, a width direction, a row direction, or a transverse direction. The third direction DR3 may be a thickness direction or a height direction of the display device 10.

[0062] In an embodiment, the display device 10 may include a display panel 100 , a driver 200 , and a circuit board 300 .

[0063] The display panel 100 may include a main area MA including a display area DA displaying an image, and a sub area SBA positioned at one side of the main area MA.

[0064] The main area MA may include a display area DA and a non-display area NA around the display area DA. The display area DA may be located at the center of the main area MA and may occupy most of the main area MA. The non-display area NA may be located at an edge of the main area MA and may contact the sub-area SBA.

[0065] The display area DA may be a region where pixels (eg, Figure 4 In an embodiment, a sensing pattern (e.g., a touch electrode) for detecting a touch input or similar event may be further provided in the display area DA, and the display area DA may include a sensing area for detecting a touch input through the sensing pattern.

[0066] In an embodiment, the display area DA may have a substantially rectangular plane shape having long sides in the first direction DR1 and short sides in the second direction DR2. Each corner where the long side and the short side intersect may be rounded or right angled. The plane shape of the display area DA may vary according to the embodiment. In an embodiment, for example, the display area DA may also have a polygonal shape, a circular shape, or an elliptical shape in addition to the quadrilateral shape.

[0067] The non-display area NA may be positioned adjacent to the periphery of the display area DA. The non-display area NA may surround the display area DA. An embedded circuit may be arranged in the non-display area NA. In an embodiment, for example, an embedded circuit such as a scan drive circuit may be arranged in the non-display area NA on one side (e.g., the left side or the right side) or both sides of the display area DA.

[0068] The sub-region SBA may be positioned on one side of the main region MA. In an embodiment, for example, the sub-region SBA may be a region protruding from one side of the main region MA in the first direction DR1. In an embodiment, for example, the sub-region SBA may protrude from the lower end of the main region MA in the first direction DR1. In an embodiment, the sub-region SBA may be narrower than the main region MA. In an embodiment, for example, the sub-region SBA may be narrower than the main region MA in the second direction DR2.

[0069] Lines and pads may be arranged in the sub-area SBA. In an embodiment, for example, lines and pads connected to pixels and / or embedded circuits positioned in the main area MA and a driver 200 and / or a circuit board 300 positioned in the sub-area SBA may be arranged in the sub-area SBA. In the description of the embodiment, the term "connection" may mean physical connection and / or electrical connection.

[0070] In an embodiment, the driver 200 (eg, a display driving circuit) may be mounted in the sub-area SBA. The circuit board 300 may be disposed on a portion of the sub-area SBA.

[0071] The driver 200 may include a data driving circuit for driving pixels. In an embodiment, the driver 200 may be formed as an integrated circuit (IC) chip and arranged in the sub-area SBA. In an embodiment, the driver 200 may be arranged on the circuit board 300 in the sub-area SBA, or may be arranged on another circuit board connected to the display panel 100 through the circuit board 300.

[0072] The circuit board 300 may be arranged on a portion of the sub-area SBA. For example, the circuit board 300 may be bonded to a pad positioned in a portion (e.g., a lower edge) of the sub-area SBA, and may supply or transmit a power voltage and a driving signal for driving the display panel 100 to the display panel 100. In an embodiment, for example, the circuit board 300 may supply input image data (e.g., digital image data), a driving signal including a timing signal, and a driving voltage to the display panel 100. The circuit board 300 may be, but is not limited to, a flexible printed circuit board (FPCB), a printed circuit board (PCB), or a flexible film such as a chip on film (COF).

[0073] Figure 2 yes Figure 1 FIG. 1 is a plan view of the display device 10 . Figure 3is along Figure 2 A cross-sectional view taken along line AA'.

[0074] Figure 1 The display device 10 is shown in a state where the display device 10 is unfolded without being bent, and Figure 2 and Figure 3 The display device 10 is shown in a state where the display device 10 is bent in the sub-area SBA. Figure 1 The display device 10 is shown in a state where the sub-area SBA is expanded to be spread side by side with the main area MA, and Figure 2 and Figure 3 The display device 10 is shown in a state where a portion of the sub-area SBA is bent.

[0075] Reference Figure 2 and Figure 3 In an embodiment, the display panel 100 may include a substrate 110 including a main area MA and a sub-area SBA, and a circuit layer 120, a light emitting element layer 130, and an encapsulation layer 140 sequentially stacked on the substrate 110. The circuit layer 120 may be positioned on the substrate 110 in the main area MA and the sub-area SBA. The light emitting element layer 130 and the encapsulation layer 140 may be positioned on portions of the substrate 110 and the circuit layer 120. In an embodiment, for example, the light emitting element layer 130 and the encapsulation layer 140 may be positioned in the main area MA.

[0076] In an embodiment, the display device 10 may further include additional elements disposed on the display panel 100. In an embodiment, for example, the display device 10 may further include at least one of a sensor layer (e.g., a touch sensor layer), a polarizing layer, a color filter layer, and a protective layer (e.g., a window) disposed on the encapsulation layer 140. Each of the sensor layer, the polarizing layer, the color filter layer, and the protective layer may be manufactured integrally with the display panel 100, or may be manufactured separately from the display panel 100 and then attached to the display panel 100 by an adhesive layer or the like.

[0077] The substrate 110 may include an insulating material such as a polymer resin. For example, the substrate 110 may include or be made of polyimide or another insulating material. The substrate 110 may be a flexible substrate that can be bent, folded, or curled. Alternatively, the substrate 110 may include an insulating material such as glass.

[0078] The circuit layer 120 may include pixel circuits and lines. In an embodiment, for example, the circuit layer 120 may include circuit elements (e.g., pixel transistors and capacitors) constituting the pixel circuit of each pixel and lines connected to the pixels. In an embodiment, the circuit layer 120 may also include circuit elements constituting embedded circuits (such as scan drive circuits) and lines connected to the embedded circuits.

[0079] The light emitting element layer 130 may include a light emitting element arranged in an emission region of a pixel. In an embodiment, for example, each of the pixels may include at least one light emitting element and a pixel circuit connected to the light emitting element. Each of the pixels may be positioned in a pixel region including an emission region in which a light emitting element is arranged and a pixel circuit region in which a pixel circuit is arranged. The emission region and the pixel circuit region of each pixel may overlap each other, but the present disclosure is not limited thereto.

[0080] In an embodiment, the circuit layer 120 and the light emitting element layer 130 may be separated from each other. However, the embodiment is not limited thereto. In an embodiment, for example, the circuit layer 120 and the light emitting element layer 130 may also be integrated.

[0081] The encapsulation layer 140 may cover the light emitting element layer 130 and extend to the non-display area NA to contact the circuit layer 120. In an embodiment, the encapsulation layer 140 may have a multilayer structure including at least two inorganic encapsulation layers overlapping each other and at least one organic encapsulation layer interposed therebetween.

[0082] In an embodiment, the display panel 100 may be bent in the bending area BA. The bending area BA may be part of the sub area SBA and may be spaced apart from the main area MA.

[0083] The substrate 110 and the circuit layer 120 may be bent in the bending area BA corresponding to a portion of the sub-area SBA. Accordingly, a bezel area perceived as the non-display area NA by a user can be reduced or minimized.

[0084] Figure 4 is a plan view of a display panel 100 according to an embodiment. Figure 4 The display panel 100 is shown in an unbent, unfolded state.

[0085] Reference Figure 4 , an embodiment of the display panel 100 may include a main area MA and a sub-area SBA. The main area MA may include a display area DA and a non-display area NA, and the sub-area SBA may include a dam area BNKA, a driving circuit mounting area ICA, and a pad area PA.

[0086] The display area DA may be an area where a plurality of pixels PX are arranged. The pixels PX and lines (or parts of the lines) connected to the pixels PX may be arranged in the display area DA.

[0087] The pixels PX may be provided in the circuit layer 120 and the light emitting element layer 130 of the display panel 100. In an embodiment, for example, each of the pixels PX may include a circuit element arranged in the circuit layer 120 and a light emitting element (e.g., Figure 5 or Figure 6A pixel circuit (e.g., a light emitting element EL) Figure 5 or Figure 6 Pixel circuit PCA).

[0088] The pixel PX may include at least two color sub-pixels SPX that respectively emit light of different colors. In an embodiment, for example, the pixel PX may include a first color sub-pixel SPX1 that emits light of a first color (e.g., red light), a second color sub-pixel SPX2 that emits light of a second color (e.g., green light), and a third color sub-pixel SPX3 that emits light of a third color (e.g., blue light).

[0089] At least one first color sub-pixel SPX1, at least one second color sub-pixel SPX2, and at least one third color sub-pixel SPX3 adjacent to each other may form a unit pixel PX (may be referred to as pixel PX in this article). In an embodiment, for example, one first color sub-pixel SPX1, two second color sub-pixels SPX2, and one third color sub-pixel SPX3 adjacent to each other may form a unit pixel PX. Each unit pixel PX may emit light of various colors including white light by mixing the colors of light emitted from the sub-pixels SPX1 to SPX3 forming the unit pixel PX. In an embodiment, the first color sub-pixel SPX1 and the third color sub-pixel SPX3 may be arranged alternately in the first direction DR1 and / or the second direction DR2, and the second color sub-pixel SPX2 may be arranged continuously and / or sequentially in the first direction DR1. The type, shape, and / or arrangement structure of the sub-pixels SPX1 to SPX3 may vary according to the embodiment. In addition, the type, number, ratio, and / or arrangement structure of the sub-pixels SPX1 to SPX3 forming each unit pixel PX may vary according to the embodiment.

[0090] The encapsulation layer 140 may be disposed on the pixel PX. In an embodiment, for example, the encapsulation layer 140 may be provided to cover the pixel PX at least in the display area DA, and a portion of the encapsulation layer 140 may extend to the non-display area NA.

[0091] The wire may be provided in the circuit layer 120 and positioned in the display area DA and the non-display area NA. In addition, the wire may be positioned in the sub-area SBA. In an embodiment, for example, the wire may extend from the sub-area SBA to the display area DA via the non-display area NA.

[0092] The non-display area NA may be positioned around the display area DA. In an embodiment, for example, the non-display area NA may be an edge area of ​​the main area MA positioned outside the display area DA.

[0093] The non-display area NA may include a dam area DAMA spaced apart from the display area DA, a first non-display area NA1 between the display area DA and the dam area DAMA, and a second non-display area NA2 outside the dam area DAMA. The dam area DAMA may be an area where a dam surrounding the display area DA is arranged. The second non-display area NA2 may include an inorganic encapsulation area IEA (also referred to as a "joining area") where the inorganic encapsulation layers of the encapsulation layer 140 are joined to each other.

[0094] The sub-area SBA may include a dam area BNKA, a driving circuit mounting area ICA, and a pad area PA sequentially defined or arranged on one side of the main area MA. Lines (or portions of lines), dams, and pads PD may be arranged in the sub-area SBA. At least some of the lines may extend to the main area MA and may be connected to the pixels PX.

[0095] The dam area BNKA may be an area where a dam including at least one organic layer is arranged. In an embodiment, the dam area BNKA may include a curved area BA. In an embodiment, for example, the dam area BNKA may include a curved area BA spaced apart from the main area MA and a first edge area BEA1 and a second edge area BEA2 positioned on both sides of the curved area BA in the first direction DR1. The dam may be provided in the curved area BA and an area around the curved area BA (e.g., the first edge area BEA1 and the second edge area BEA2 of the dam area BNKA) to cover a line passing through the curved area BA. The display panel 100 may be bent in the curved area BA so that a portion of the sub-area SBA is positioned on the rear surface of the main area MA.

[0096] The driving circuit mounting area ICA may be an area where the driver 200 is arranged. Pads for connecting at least some lines to the driver 200 may be arranged in the driving circuit mounting area ICA. In an embodiment, for example, input pads for connecting the driver 200 to specific pads (e.g., data input pads) of the pad area PA and output pads for connecting the driver 200 to the pixels PX may be arranged in the driving circuit mounting area ICA.

[0097] In some embodiments, the driver 200 may not be disposed on the display panel 100. In such embodiments, the display panel 100 may not include the driving circuit mounting area ICA, and only the wires may be disposed in the area between the dam area BNKA and the pad area PA.

[0098] The pad area PA may be a region where a display panel 100 and / or a driver 200 is connected to a circuit board 300 (eg, referring to FIG. 1 ). Figure 3 ) of a pad area PA or the like. The circuit board 300 may be arranged or bonded on the pad area PA.

[0099] A plurality of pads PD including power pads and signal pads connected to the pixel PX, the driver 200, and / or the embedded circuit may be arranged in the pad area PA. A power voltage for driving the pixel PX, the driver 200, and / or the embedded circuit may be supplied to the power pad. A driving signal and / or image data for driving the pixel PX, the driver 200, and / or the embedded circuit may be supplied to the signal pad. The type, position, arrangement order, and / or number of the pads PD may vary according to the embodiment.

[0100] Figure 5 is a pixel circuit diagram of a sub-pixel SPX according to an embodiment. Figure 6 is a pixel circuit diagram of a sub-pixel SPX according to an embodiment.

[0101] Figure 5 and Figure 6 Various embodiments of the pixel circuit PCA and the lines connected to the pixel circuit PCA are shown. The configuration of the pixel circuit PCA and the type and number of lines connected to the pixel circuit PCA may vary according to the embodiment.

[0102] Figure 5 1 shows an embodiment in which each pixel circuit PCA includes a first transistor T1 to a seventh transistor T7. In the embodiment, the Figure 5 The scan lines SL of the sub-pixel SPX may include a first scan line SL1, a second scan line SL2, a third scan line SL3, and a fourth scan line SL4, and are connected to Figure 5 The power line PL of the sub-pixel SPX may include a first pixel power line VDL, a second pixel power line VSL, a first initialization power line VIL, and a second initialization power line VAIL. Figure 5 The sub-pixel SPX may also be connected to an emission control line ECL.

[0103] Figure 6 1 shows an embodiment in which each pixel circuit PCA includes a first transistor T1 to an eighth transistor T8. In the embodiment, the transistors connected to Figure 6 The scan lines SL of the sub-pixel SPX may include a first scan line SL1, a second scan line SL2, a third scan line SL3, and a fifth scan line SL5, and are connected to Figure 6 The power lines PL of the sub-pixel SPX may include a first pixel power line VDL, a second pixel power line VSL, a first initialization power line VIL, a second initialization power line VAIL, and a bias power line VOBL. Figure 6 The sub-pixel SPX may also be connected to an emission control line ECL.

[0104] Reference Figure 5, the sub-pixel SPX may include a light emitting unit EMU including at least one light emitting element EL and a pixel circuit PCA (also referred to as a “pixel driver”) connected to the light emitting unit EMU.

[0105] The light emitting element EL may be connected between the second pixel power line VSL to which the second pixel power voltage ELVSS is applied and the pixel circuit PCA. In an embodiment, the second pixel power voltage ELVSS may be a low potential pixel driving voltage. The light emitting element EL may be a light source of the pixel PX and may emit light in response to a driving current supplied from the pixel circuit PCA.

[0106] The light emitting element EL may be an organic light emitting diode. However, the present disclosure is not limited thereto. In an embodiment, for example, the light emitting element EL may also be an inorganic light emitting element, a quantum dot light emitting element, or another type of light emitting element.

[0107] The pixel circuit PCA can control the light emission timing and brightness of the light emitting element EL by controlling the driving current supplied to the light emitting element EL. The pixel circuit PCA may include at least one pixel transistor T and a capacitor Cst. In an embodiment, the pixel circuit PCA may include a plurality of pixel transistors T including a first transistor T1 to a seventh transistor T7.

[0108] The first transistor T1 may include a gate electrode connected to the first node N1, a first electrode electrically connected to the first pixel power line VDL through a fifth transistor T5, and a second electrode electrically connected to the light emitting unit EMU through a sixth transistor T6. One of the first electrode and the second electrode may be a source electrode, and the other of the first electrode and the second electrode may be a drain electrode. The first transistor T1 may control a source-drain current (referred to herein as a "driving current") flowing between the first electrode and the second electrode according to a voltage applied to the gate electrode (e.g., a voltage of the first node N1 corresponding to a voltage of a data signal). In such an embodiment, the first transistor T1 may be referred to as a driving transistor of the sub-pixel SPX.

[0109] The second transistor T2 may include a gate electrode connected to the first scan line SL1, a first electrode connected to the data line DL, and a second electrode connected to the first electrode of the first transistor T1. The second transistor T2 may be turned on by a first scan signal supplied to the first scan line SL1 to electrically connect the first electrode of the first transistor T1 to the data line DL. When the second transistor T2 is turned on, a voltage of a data signal supplied to the data line DL may be applied to the first electrode of the first transistor T1.

[0110] The third transistor T3 may include a gate electrode connected to the second scan line SL2, a first electrode connected to the second electrode of the first transistor T1, and a second electrode connected to the gate electrode (or the first node N1) of the first transistor T1. The third transistor T3 may be turned on by the second scan signal supplied to the second scan line SL2 to electrically connect the gate electrode and the second electrode of the first transistor T1. When the third transistor T3 is turned on, the first transistor T1 may operate as a diode.

[0111] The fourth transistor T4 may include a gate electrode connected to the third scan line SL3, a first electrode connected to the gate electrode of the first transistor T1, and a second electrode connected to the first initialization power line VIL. The fourth transistor T4 may be turned on by the third scan signal supplied to the third scan line SL3 to electrically connect the gate electrode of the first transistor T1 to the first initialization power line VIL. When the fourth transistor T4 is turned on, a first initialization voltage VINT (e.g., a gate initialization voltage) of the first initialization power line VIL may be applied to the gate electrode of the first transistor T1.

[0112] The fifth transistor T5 may include a gate electrode connected to an emission control line ECL, a first electrode connected to a first pixel power line VDL, and a second electrode connected to a first electrode of the first transistor T1. The fifth transistor T5 may be turned on by an emission control signal supplied to the emission control line ECL to electrically connect the first electrode of the first transistor T1 to the first pixel power line VDL to which the first pixel power voltage ELVDD is applied. When the fifth transistor T5 is turned on, the first pixel power voltage ELVDD may be applied to the first electrode of the first transistor T1. In such an embodiment, the first pixel power voltage ELVDD may be referred to as a high potential pixel driving voltage.

[0113] The sixth transistor T6 may include a gate electrode connected to an emission control line ECL, a first electrode connected to a second electrode of the first transistor T1, and a second electrode connected to the light emitting element EL. The sixth transistor T6 may be turned on by an emission control signal supplied to the emission control line ECL to electrically connect the first transistor T1 to the light emitting element EL. When both the fifth transistor T5 and the sixth transistor T6 are turned on, a driving current of a magnitude corresponding to a voltage of the gate electrode of the first transistor T1 may flow to the light emitting element EL.

[0114] The seventh transistor T7 may include a gate electrode connected to the fourth scan line SL4, a first electrode connected to the anode of the light emitting element EL, and a second electrode connected to the second initialization power line VAIL. The seventh transistor T7 may be turned on by the fourth scan signal supplied to the fourth scan line SL4 to electrically connect the anode of the light emitting element EL to the second initialization power line VAIL. The fourth scan signal may be the same signal as the first scan signal or a different signal. When the seventh transistor T7 is turned on, a second initialization voltage VAINT (e.g., an anode initialization voltage) of the second initialization power line VAIL may be applied to the anode of the light emitting element EL.

[0115] The capacitor Cst may be connected between the gate electrode of the first transistor T1 and the first pixel power line VDL. The capacitor Cst may be charged with a voltage corresponding to a voltage of a data signal applied to the gate electrode of the first transistor T1.

[0116] The active layer (e.g., a semiconductor pattern including a channel region) of each of the plurality of pixel transistors T (e.g., the first transistor T1 to the seventh transistor T7) may include a semiconductor material selected from polysilicon, amorphous silicon, and an oxide semiconductor. In an embodiment, some of the plurality of pixel transistors T and other pixel transistors T may be formed as transistors of different conductivity types. In addition, some of the plurality of pixel transistors T and other pixel transistors T may include different types of semiconductor materials.

[0117] In an embodiment, for example, the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be formed as P-type transistors (e.g., P-type metal oxide semiconductor field effect transistors (MOSFETs)) each including an active layer including polysilicon or made of polysilicon, and the third transistor T3 and the fourth transistor T4 may be formed as N-type transistors (e.g., N-type MOSFETs) each including an active layer including an oxide semiconductor or made of an oxide semiconductor. In an embodiment, transistors each including an active layer including polysilicon or made of polysilicon and transistors each including an active layer including an oxide semiconductor or made of an oxide semiconductor may be arranged in different layers within the circuit layer 120.

[0118] Apart from Figure 5 In addition, refer to Figure 6, the pixel circuit PCA may further include an eighth transistor T8. The eighth transistor T8 may include a gate electrode connected to the fifth scan line SL5, a first electrode connected to the bias power line VOBL, and a second electrode connected to the first electrode of the first transistor T1. The eighth transistor T8 may be turned on by the fifth scan signal supplied to the fifth scan line SL5 to electrically connect the first electrode of the first transistor T1 to the bias power line VOBL. When the eighth transistor T8 is turned on, the bias voltage VOBS supplied to the bias power line VOBL may be applied to the first electrode of the first transistor T1. In an embodiment, the bias voltage VOBS may have a voltage level suitable for compensating for the hysteresis characteristic of the first transistor T1. When the eighth transistor T8 is turned on, the first electrode of the first transistor T1 may be initialized to the bias voltage VOBS.

[0119] exist Figure 6 In the embodiment of the present invention, the gate electrode of the seventh transistor T7 may be connected to the fifth scan line SL5. Accordingly, the seventh transistor T7 may be turned on by the fifth scan signal supplied to the fifth scan line SL5 to connect the anode of the light emitting element EL to the second initialization power line VAIL.

[0120] Figure 7 is a display device 10 according to an embodiment (for example, referring to Figure 3 ) of the sub-pixel SPX (for example, refer to Figure 4 ) cross-sectional view. Figure 7 is related to the display area DA (for example, refer to Figure 4 ) is a partial cross-sectional view of the area corresponding to the sub-pixel SPX.

[0121] Reference Figure 7 The display panel 100 may include a substrate 110 and a circuit layer 120, a light emitting element layer 130, and an encapsulation layer 140 arranged on the substrate 110. The circuit layer 120, the light emitting element layer 130, and the encapsulation layer 140 may be arranged along a third direction DR3 (eg, referring to Figure 4 ) are sequentially arranged or stacked on the substrate 110.

[0122] The substrate 110 may include or be made of a flexible material that can be bent, folded, or curled. The substrate 110 may include or be made of an insulating material such as a polymer resin. In an embodiment, for example, the substrate 110 may include or be made of polyimide.

[0123] The circuit layer 120 may include a pixel circuit PXC (eg, corresponding to Figure 5 or Figure 6In an embodiment, for example, the circuit layer 120 may include circuit elements (e.g., pixel transistor T and capacitor Cst) constituting the pixel circuit PXC of each sub-pixel SPX and lines (e.g., including power lines PL (e.g., referring to Figure 5 or Figure 6 ), scanning line SL (for example, refer to Figure 5 or Figure 6 ), emission control line ECL (for example, refer to Figure 5 or Figure 6 ) and the data line DL (for example, refer to Figure 5 or Figure 6 ) various power lines and signal lines).

[0124] Figure 7 The first thin film transistor TFT1 (also referred to as "first pixel transistor"), the second thin film transistor TFT2 (also referred to as "second pixel transistor"), and the capacitor Cst included in the pixel circuit PXC of each sub-pixel SPX are shown among the elements that can be provided in the circuit layer 120. The first thin film transistor TFT1 may be a first type transistor (for example, a P-type transistor) including a first semiconductor material (for example, polysilicon) among the pixel transistors T constituting each pixel circuit PXC. In an embodiment, for example, the first thin film transistor TFT1 may be a first transistor T1 (for example, refer to Figure 5 or Figure 6 ), the second transistor T2 (for example, refer to Figure 5 or Figure 6 ), the fifth transistor T5 (for example, refer to Figure 5 or Figure 6 ), the sixth transistor T6 (for example, refer to Figure 5 or Figure 6 ), the seventh transistor T7 (for example, refer to Figure 5 or Figure 6 ) and the eighth transistor T8 (eg, referring to Figure 6 ). Figure 7 In the embodiment, one transistor (eg, a first connection electrode CNE1 and a second connection electrode CNE2) among the first type transistors is connected to the light emitting element EL through at least one connection electrode (eg, a first connection electrode CNE1 and a second connection electrode CNE2). Figure 5 or Figure 6 1) is shown as an example of the first thin film transistor TFT1. The second thin film transistor TFT2 may be a second type transistor (e.g., an N-type transistor) including a second semiconductor material (e.g., an oxide semiconductor) among the pixel transistors T. In an embodiment, for example, the second thin film transistor TFT2 may be one of the third transistor T3 and the fourth transistor T4.

[0125] The cross-section of the subpixel SPX may vary according to the type and / or structure of each subpixel SPX and the display panel 100 including the subpixel SPX. In embodiments, for example, the positions and formation order of the first thin film transistor TFT1, the second thin film transistor TFT2, and the capacitor Cst may vary according to embodiments.

[0126] The circuit layer 120 may include semiconductor layers and conductive layers for forming circuit elements and lines, and insulating layers arranged between and / or around the conductive layers and semiconductor layers. In an embodiment, for example, the circuit layer 120 may include a first semiconductor layer SCL1 (e.g., a polysilicon semiconductor layer), a first insulating layer 123 (e.g., a first gate insulating layer), a first conductive layer CDL1 (e.g., a first gate conductive layer), a second insulating layer 124 (e.g., a second gate insulating layer), a second conductive layer CDL2 (e.g., a second gate conductive layer), a third insulating layer 125 (e.g., a first interlayer insulating layer), a second semiconductor layer SCL2 (e.g., an oxide semiconductor layer), a fourth insulating layer 126 (e.g., a third gate insulating layer), a third conductive layer CDL3 (e.g., a third gate conductive layer), a fifth insulating layer 127 (e.g., a second interlayer insulating layer), a fourth conductive layer CDL4 (e.g., a first source-drain conductive layer), and a sixth insulating layer 128 (e.g., a first through-hole layer or a first planarization layer) sequentially arranged on the substrate 110 in the third direction DR3. In an embodiment, the circuit layer 120 may further include a fifth conductive layer CDL5 (e.g., a second source-drain conductive layer) and a seventh insulating layer 129 (e.g., a second via layer or a second planarization layer) sequentially disposed on the sixth insulating layer 128. In an embodiment, the circuit layer 120 may further include a bottom conductive layer BCDL disposed between the substrate 110 and the first semiconductor layer SCL1, a barrier layer 121 disposed between the substrate 110 and the bottom conductive layer BCDL, and a buffer layer 122 disposed between the bottom conductive layer BCDL and the first semiconductor layer SCL1.

[0127] The barrier layer 121 may be disposed on the substrate 110. The barrier layer 121 may protect the elements disposed in the circuit layer 120 and the light emitting element layer 130 from moisture introduced through the substrate 110 susceptible to moisture penetration. The barrier layer 121 may include at least one inorganic layer including an inorganic insulating material (e.g., silicon nitride, silicon oxide, silicon oxynitride, titanium oxide, aluminum oxide, or other inorganic insulating material). The material of the barrier layer 121 may vary according to the embodiment.

[0128] The bottom conductive layer BCDL may be disposed on the barrier layer 121. The bottom conductive layer BCDL may include a bottom metal layer BML overlapping an active layer (eg, the first active layer ACT1 and / or the second active layer ACT2) of at least one pixel transistor T, and / or may include at least one line (or a portion of at least one line). Figure 7 As shown in FIG, the bottom metal layer BML overlaps only the first active layer ACT1 of the first thin film transistor TFT1 and the capacitor electrodes CAE1 and CAE2 of the capacitor Cst, but the present disclosure is not limited thereto. In an embodiment, for example, the bottom metal layer BML may be patterned into an appropriate size and / or shape as required and thus arranged in a portion of the pixel circuit PXC, or may be arranged in the entire pixel circuit PXC. In an embodiment, for example, the bottom metal layer BML may be arranged in only a portion of the pixel area to overlap with the capacitor electrodes CAE1 and CAE2 of the capacitor Cst. Figure 5 and Figure 6 In an embodiment, the bottom metal layer BML may be used as a light blocking pattern and / or a back gate electrode of at least one pixel transistor T.

[0129] The buffer layer 122 may be disposed on the bottom conductive layer BCDL to cover the bottom conductive layer BCDL. The buffer layer 122 may include at least one inorganic layer including an inorganic insulating material.

[0130] The first thin film transistor TFT1, the second thin film transistor TFT2, and the capacitor Cst may be arranged on the surface of the substrate 110 including the buffer layer 122. The first thin film transistor TFT1 may include a first active layer ACT1 and a first gate electrode G1. The second thin film transistor TFT2 may include a second active layer ACT2 and a second gate electrode G2. In an embodiment, the second thin film transistor TFT2 may include a back gate electrode BG. The capacitor Cst may include a first capacitor electrode CAE1 and a second capacitor electrode CAE2.

[0131] The first semiconductor layer SCL1 may be disposed on the buffer layer 122. The first semiconductor layer SCL1 may include a first active layer ACT1 of the first thin film transistor TFT1. In an embodiment, for example, the first semiconductor layer SCL1 may include a first active layer ACT1 of each of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8.

[0132] The first active layer ACT1 may be provided in the first semiconductor layer SCL1 and may include a first semiconductor material (e.g., polysilicon). The first active layer ACT1 may include a first channel region CH1, a first source region S1, and a first drain region D1. The first channel region CH1 may overlap with the first gate electrode G1 in the third direction DR3. The first source region S1 may be arranged on one side of the first channel region CH1, and the first drain region D1 may be arranged on the other side of the first channel region CH1. The first source region S1 and the first drain region D1 may be regions formed to have conductivity by doping a semiconductor used to form the first active layer ACT1 with ions or impurities. In an embodiment, the first source region S1 may be a source electrode of the first thin film transistor TFT1. In an embodiment, the first thin film transistor TFT1 may include a separate source electrode connected to the first source region S1. In an embodiment, the first drain region D1 may be a drain electrode of the first thin film transistor TFT1. In an embodiment, the first thin film transistor TFT1 may include a separate drain electrode connected to the first drain region D1.

[0133] The first insulating layer 123 may be disposed on the first semiconductor layer SCL1. The first insulating layer 123 may cover the first semiconductor layer SCL1.

[0134] The first conductive layer CDL1 may be disposed on the first insulating layer 123. The first conductive layer CDL1 may include a first gate electrode G1 of the first thin film transistor TFT1. The first gate electrode G1 may overlap a portion of the first active layer ACT1 (e.g., the first channel region CH1). In an embodiment, the first conductive layer CDL1 may further include at least one line (or a portion of at least one line), a metal pattern (e.g., a bridge pattern), and / or a capacitor electrode. For example, the first conductive layer CDL1 may further include a first capacitor electrode CAE1 of a capacitor Cst.

[0135] In an embodiment, the first capacitor electrode CAE1 may be integrally formed with the gate electrode of at least one first thin film transistor TFT1 as a single body and undivided portion. In an embodiment, for example, the first capacitor electrode CAE1 may be integrally formed with the gate electrode of at least one first thin film transistor TFT1 as a single body and undivided portion. Figure 5 and Figure 6 In an embodiment, for example, the first capacitor electrode CAE1 and the gate electrode of the first transistor T1 may be formed as one conductive pattern, and the second capacitor electrode CAE2 may be arranged to overlap the conductive pattern.

[0136] The second insulating layer 124 may be disposed on the first conductive layer CDL1. The second insulating layer 124 may cover the first conductive layer CDL1.

[0137] The second conductive layer CDL2 may be disposed on the second insulating layer 124. The second conductive layer CDL2 may include one electrode of the capacitor Cst (e.g., the second capacitor electrode CAE2). In an embodiment, the second conductive layer CDL2 may further include at least one electrode, at least one line (or at least one line portion) and / or a metal pattern (e.g., a bridge pattern). In an embodiment, for example, the second conductive layer CDL2 may further include a back gate electrode BG connected to the second gate electrode G2 of the second thin film transistor TFT2.

[0138] The third insulating layer 125 may be disposed on the second conductive layer CDL2. The third insulating layer 125 may cover the second conductive layer CDL2.

[0139] The second semiconductor layer SCL2 may be disposed on the third insulating layer 125. The second semiconductor layer SCL2 may include a second active layer ACT2 of the second thin film transistor TFT2. In an embodiment, for example, the second semiconductor layer SCL2 may include a second active layer ACT2 of each of the third transistor T3 and the fourth transistor T4.

[0140] The second active layer ACT2 may be provided in the second semiconductor layer SCL2 and may include a second semiconductor material (e.g., an oxide semiconductor) different from the first semiconductor material. In an embodiment, for example, the second active layer ACT2 may include at least one selected from indium gallium zinc oxide (IGZO), indium gallium zinc tin oxide (IGZTO), and indium gallium tin oxide (IGTO).

[0141] The second active layer ACT2 may include a second channel region CH2, a second source region S2, and a second drain region D2. The second channel region CH2 may overlap with the second gate electrode G2 in the third direction DR3. The second source region S2 may be arranged at one side of the second channel region CH2, and the second drain region D2 may be arranged at an opposite side of the second channel region CH2. The second source region S2 and the second drain region D2 may be regions formed to have conductivity by doping a semiconductor used to form the second active layer ACT2 with ions or impurities. In an embodiment, the second source region S2 may be a source electrode of the second thin film transistor TFT2. In an embodiment, the second thin film transistor TFT2 may include a separate source electrode connected to the second source region S2. In an embodiment, the second drain region D2 may be a drain electrode of the second thin film transistor TFT2. In an embodiment, the second thin film transistor TFT2 may include a separate drain electrode connected to the second drain region D2.

[0142] The fourth insulating layer 126 may be disposed on the second semiconductor layer SCL2. The fourth insulating layer 126 may cover the second semiconductor layer SCL2.

[0143] The third conductive layer CDL3 may be disposed on the fourth insulating layer 126. The third conductive layer CDL3 may include a second gate electrode G2 of the second thin film transistor TFT2. The second gate electrode G2 may overlap a portion of the second active layer ACT2 (e.g., the second channel region CH2). In embodiments, the third conductive layer CDL3 may further include at least one line (or a portion of at least one line), a metal pattern (e.g., a bridge pattern), and / or a capacitor electrode.

[0144] In an embodiment, each of the electrodes, conductive patterns and wires provided in the bottom conductive layer BCDL, the first conductive layer CDL1, the second conductive layer CDL2 and the third conductive layer CDL3 may include a conductive material (for example, at least one selected from molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu) and other metals, alloys thereof, or other conductive materials), and may have a single-layer or multi-layer structure. In an embodiment, for example, the electrodes, conductive patterns and / or wires provided in the bottom conductive layer BCDL, the first conductive layer CDL1, the second conductive layer CDL2 and the third conductive layer CDL3 may include molybdenum (Mo) or other metal materials. At least two selected from the bottom conductive layer BCDL, the first conductive layer CDL1, the second conductive layer CDL2 and the third conductive layer CDL3 may include the same material as each other or different materials from each other. The material of each of the bottom conductive layer BCDL, the first conductive layer CDL1, the second conductive layer CDL2 and the third conductive layer CDL3 is not limited and may vary according to the embodiment.

[0145] The fifth insulating layer 127 may be disposed on the third conductive layer CDL3. The fifth insulating layer 127 may cover the third conductive layer CDL3.

[0146] In an embodiment, each of the first insulating layer 123, the second insulating layer 124, the third insulating layer 125, the fourth insulating layer 126, and the fifth insulating layer 127 may be an inorganic insulating layer including an inorganic insulating material (e.g., silicon nitride, silicon oxide, silicon oxynitride, titanium oxide, aluminum oxide, or other inorganic insulating materials), and may have a single-layer or multi-layer structure. At least two selected from the first insulating layer 123, the second insulating layer 124, the third insulating layer 125, the fourth insulating layer 126, and the fifth insulating layer 127 may include the same material as each other or different materials from each other. The material of each of the first insulating layer 123, the second insulating layer 124, the third insulating layer 125, the fourth insulating layer 126, and the fifth insulating layer 127 may vary according to the embodiment.

[0147] The fourth conductive layer CDL4 may be disposed on the fifth insulating layer 127. The fourth conductive layer CDL4 may include a first connection electrode CNE1 (or a drain electrode of the first thin film transistor TFT1), a first bridge electrode BE1 (or a source electrode of the second thin film transistor TFT2), and a second bridge electrode BE2 (or a drain electrode of the second thin film transistor TFT2). The first connection electrode CNE1 may be provided in the fourth conductive layer CDL4 and connected to the first drain region D1 of the first active layer ACT1 through a first contact hole CT1 defined through the first insulating layer 123, the second insulating layer 124, the third insulating layer 125, the fourth insulating layer 126, and the fifth insulating layer 127. The first bridge electrode BE1 may be disposed in the fourth conductive layer CDL4 and connected to the second source region S2 of the second active layer ACT2 through a second contact hole CT2 defined through the fourth insulating layer 126 and the fifth insulating layer 127. The second bridge electrode BE2 may be connected to the second drain region D2 of the second active layer ACT2 through a third contact hole CT3 defined through the fourth insulating layer 126 and the fifth insulating layer 127. In an embodiment, the fourth conductive layer CDL4 may further include at least one line (or at least a portion of a line) and / or a metal pattern (e.g., a bridge pattern). In an embodiment, for example, the fourth conductive layer CDL4 may include a portion of the power line PL provided inside and / or outside the display area DA (e.g., the first pixel power line VDL (e.g., refer to Figure 5 or Figure 6 ) and / or the second pixel power line VSL (eg, referring to Figure 5 or Figure 6 )).

[0148] The sixth insulating layer 128 may be disposed on the fourth conductive layer CDL4. The sixth insulating layer 128 may cover the fourth conductive layer CDL4.

[0149] The fifth conductive layer CDL5 may be disposed on the sixth insulating layer 128. The fifth conductive layer CDL5 may include a second connection electrode CNE2. The second connection electrode CNE2 may be disposed in the fifth conductive layer CDL5 and connected to the first connection electrode CNE1 through a fourth contact hole CT4 (or a first through hole) defined through the sixth insulating layer 128. In an embodiment, the fifth conductive layer CDL5 may further include at least one line (or a portion of at least one line) and / or a metal pattern (e.g., a bridge pattern). In an embodiment, for example, the fifth conductive layer CDL5 may include a portion of a power line PL provided inside and / or outside the display area DA (e.g., a first pixel power line VDL and / or a second pixel power line VSL).

[0150] In an embodiment, each of the electrodes, conductive patterns and wires provided in the fourth conductive layer CDL4 and the fifth conductive layer CDL5 may include a conductive material (e.g., at least one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu) and other metals, alloys thereof, or other conductive materials), and may have a single-layer or multi-layer structure. For example, each of the electrodes, conductive patterns and wires provided in the fourth conductive layer CDL4 and the fifth conductive layer CDL5 may have a three-layer structure of titanium / aluminum / titanium (Ti / Al / Ti). The fourth conductive layer CDL4 and the fifth conductive layer CDL5 may include the same material or different materials. The material of each of the fourth conductive layer CDL4 and the fifth conductive layer CDL5 may vary according to the embodiment.

[0151] The seventh insulating layer 129 may be disposed on the fifth conductive layer CDL5. The seventh insulating layer 129 may cover the fifth conductive layer CDL5.

[0152] In an embodiment, each of the sixth insulating layer 128 and the seventh insulating layer 129 may be an organic insulating layer including an organic insulating material (e.g., acryl resin, epoxy resin, phenol resin, polyamide resin, polyimide resin or other organic insulating material) of the planarization circuit layer 120, and may have a single layer or multilayer structure. The sixth insulating layer 128 and the seventh insulating layer 129 may include the same material or different materials. The material of each of the sixth insulating layer 128 and the seventh insulating layer 129 may vary according to the embodiment.

[0153] The light emitting element layer 130 may include a pixel defining layer 131 separating emission areas EA of the sub-pixels SPX and light emitting elements EL respectively positioned in the emission areas EA. In an embodiment, the light emitting element layer 130 may further include a spacer 132 disposed on a portion of the pixel defining layer 131 .

[0154] Each light emitting element EL may include a first electrode ET1 (e.g., an anode) connected to at least one pixel transistor T (e.g., a first thin film transistor TFT1) included in a corresponding sub-pixel SPX through a first connection electrode CNE1 and / or a second connection electrode CNE2, and a light emitting layer EML and a second electrode ET2 (e.g., a cathode) sequentially arranged on the first electrode ET1. In an embodiment, each light emitting element EL may further include a first intermediate layer (e.g., a hole layer including a hole transport layer) interposed between the first electrode ET1 and the light emitting layer EML, and a second intermediate layer (e.g., an electron layer including an electron transport layer) interposed between the light emitting layer EML and the second electrode ET2.

[0155] The first electrode ET1 of each light emitting element EL may include a conductive material and may be disposed on the circuit layer 120. In an embodiment, for example, the first electrode ET1 may be disposed on the seventh insulating layer 129 in each emission area EA. The first electrode ET1 may be connected to the second connection electrode CNE2 through a fifth contact hole CT5 (or a second through hole) defined through the seventh insulating layer 129. In an embodiment, the first electrode ET1 may include a metal material having a high reflectivity. In an embodiment, for example, the first electrode ET1 may have a single-layer structure of molybdenum (Mo), titanium (Ti), copper (Cu), or aluminum (Al), or may have a structure including indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In 2 O 3 ), silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), lead (Pb), gold (Au), or nickel (Ni) (e.g., ITO / Mg, ITO / MgF 2 , ITO / Ag or ITO / Ag / ITO).

[0156] The light emitting layer EML of each light emitting element EL may include a polymer material or a low molecular material. In an embodiment, a light emitting layer EML may be provided for each sub-pixel SPX, and the light emitting layer EML of each sub-pixel SPX may emit visible light of a color corresponding to the sub-pixel SPX. In an embodiment, the light emitting layer EML may be a common layer shared by sub-pixels SPX of different colors, and a wavelength conversion layer and / or a color filter corresponding to the color (or wavelength band) of light emitted from each sub-pixel SPX may be arranged in the emission area EA of at least some of the plurality of sub-pixels SPX.

[0157] The second electrode ET2 of each light emitting element EL may include a conductive material and may be connected to the second pixel power line VSL. In an embodiment, the second electrode ET2 may be a common layer formed throughout the entire display area DA to cover the light emitting layer EML and the pixel defining layer 131. In an embodiment, the second electrode ET2 may include a transparent conductive material (TCO) (such as ITO or IZO) capable of transmitting light or a semi-transmissive conductive material (such as magnesium (Mg), silver (Ag), or an alloy of Mg and Ag), or be made of a transparent conductive material (TCO) (such as ITO or IZO) capable of transmitting light or a semi-transmissive conductive material (such as magnesium (Mg), silver (Ag), or an alloy of Mg and Ag). In an embodiment in which the second electrode ET2 includes a semi-transmissive conductive material or is made of a semi-transmissive conductive material, an improvement in light output efficiency through a microcavity effect can be expected.

[0158] The pixel defining layer 131 may define a plurality of openings corresponding to the plurality of emission regions EA, respectively, and may surround the emission regions EA. In an embodiment, for example, the pixel defining layer 131 may be formed to cover the edge of the first electrode ET1 of each light emitting element EL, and may define an opening exposing the other portion of the first electrode ET1. The region where the exposed first electrode ET1 overlaps the light emitting layer EML (or the region including the exposed first electrode ET1 and the light emitting layer EML) may be defined as the emission region EA of each sub-pixel SPX.

[0159] In an embodiment, the pixel defining layer 131 may include at least one organic layer including an organic insulating material. In an embodiment, for example, the pixel defining layer 131 may include polyacrylate resin, epoxy resin, phenol resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, or benzocyclobutene (BCB), or may include other organic insulating materials.

[0160] The spacer 132 may be arranged on a portion of the pixel defining layer 131. The spacer 132 may include at least one organic layer including an organic insulating material. The spacer 132 may include the same material as the pixel defining layer 131, or may include a material different from the pixel defining layer 131. In an embodiment, the pixel defining layer 131 and the spacer 132 may be sequentially formed by corresponding mask processes. In an embodiment, the pixel defining layer 131 and the spacer 132 may be formed simultaneously using a halftone mask. In this case, the pixel defining layer 131 and the spacer 132 may be regarded as an integrated insulating layer. The organic insulating material forming the spacer 132 is not particularly limited and may vary according to the embodiment.

[0161] The encapsulation layer 140 may be formed in the main area MA (eg, Figure 4 ) is arranged on the light emitting element layer 130. In an embodiment, for example, the encapsulation layer 140 may be disposed in the display area DA and the non-display area NA (eg, referring to Figure 4 ) is arranged to cover the light emitting element layer 130. The encapsulation layer 140 can block oxygen or moisture from penetrating into the light emitting element layer 130, and reduce electrical or physical impact on the circuit layer 120 and the light emitting element layer 130.

[0162] In an embodiment, the encapsulation layer 140 may include a first inorganic encapsulation layer 141, an organic encapsulation layer 142, and a second inorganic encapsulation layer 143 sequentially disposed on the light emitting element layer 130. The first and second inorganic encapsulation layers 141 and 143 may include inorganic materials, and the organic encapsulation layer 142 may include organic materials.

[0163] Figure 8 is a display panel 100 according to an embodiment (for example, referring to Figure 3 ) is a cross-sectional view of the outer part. Figure 8 A portion of a display area DA and a portion of a non-display area NA of the display panel 100 are shown.

[0164] Reference Figure 8 , the display panel 100 may include a plurality of dam structures DAM1 and DAM2 arranged in the dam area DAMA of the non-display area NA. The dam structures DAM1 and DAM2 may surround the display area DA of the display panel 100 in a plan view. In an embodiment, for example, the dam structures DAM1 and DAM2 may include a first dam DAM1 surrounding the display area DA and a second dam DAM2 surrounding the first dam DAM1. The second dam DAM2 may be arranged closer to the edge of the display panel 100 than the first dam DAM1. The display panel 100 including the dam structures DAM1 and DAM2 may effectively prevent the organic material of the organic encapsulation layer 142 of the encapsulation layer 140 from overflowing.

[0165] In an embodiment, each of the first dam DAM1 and the second dam DAM2 may include a plurality of sub-dams SDAM1 to SDAM3. In an embodiment, the sub-dams SDAM1 to SDAM3 may include the same material as the plurality of organic material layers arranged in the display area DA, respectively, and may be formed by the same process as the plurality of organic material layers. In an embodiment, the sub-dams SDAM1 to SDAM3 may be respectively arranged in the same layer as the plurality of organic material layers arranged in the display area DA (or respectively arranged directly on the same layer as the plurality of organic material layers arranged in the display area DA).

[0166] In an embodiment, for example, each of the first dam DAM1 and the second dam DAM2 may include a first sub-dam SDAM1 and a second sub-dam SDAM2 arranged on the first sub-dam SDAM1. The second dam DAM2 may further include a third sub-dam SDAM3 arranged on the second sub-dam SDAM2. The first sub-dam SDAM1 may include the same material as the sixth insulating layer 128, and may be formed in substantially the same layer as the sixth insulating layer 128 (or directly formed on substantially the same layer as the sixth insulating layer 128). The second sub-dam SDAM2 may include the same material as the seventh insulating layer 129, and may be formed in substantially the same layer as the seventh insulating layer 129 (or directly formed on substantially the same layer as the seventh insulating layer 129). The third sub-dam SDAM3 may include the same material as the pixel defining layer 131 and / or the spacer 132, and may be formed in substantially the same layer as the pixel defining layer 131 and / or the spacer 132 (or directly formed on substantially the same layer as the pixel defining layer 131 and / or the spacer 132). The first sub-dam SDAM1 , the second sub-dam SDAM2 , and the third sub-dam SDAM3 may be respectively regarded as parts of the sixth insulating layer 128 , the seventh insulating layer 129 , and the pixel defining layer 131 and / or the spacer 132 disposed in the display area DA.

[0167] Since the first dam DAM1 and the second dam DAM2 are spaced apart from the display area DA, a valley may be formed between the dam area DAMA and the display area DA and / or between the adjacent first dam DAM1 and second dam DAM2. The valley may effectively prevent the organic encapsulation layer 142 from overflowing to the edge of the display panel 100. The organic encapsulation layer 142 may fill the valley between the first dam DAM1 and the display area DA.

[0168] The first inorganic encapsulation layer 141, the organic encapsulation layer 142, and the second inorganic encapsulation layer 143 of the encapsulation layer 140 may be arranged in the first non-display area NA1 between the first dam DAM1 and the display area DA and in the dam area DAMA of the non-display area NA. Since the organic encapsulation layer 142 does not extend at least beyond the second dam DAM2, the organic encapsulation layer 142 may not be arranged in the second non-display area NA2 between the second dam DAM2 and the edge in the non-display area NA, and the first inorganic encapsulation layer 141 and the second inorganic encapsulation layer 143 of the encapsulation layer 140 may contact each other in the second non-display area NA2. The second non-display area NA2 in which the first inorganic encapsulation layer 141 and the second inorganic encapsulation layer 143 contact each other may be the inorganic encapsulation area IEA. The inorganic encapsulation area IEA in which the first inorganic encapsulation layer 141 and the second inorganic encapsulation layer 143 contact each other may be formed outside the second dam DAM2, thereby blocking a path in which moisture penetration from the outside may occur.

[0169] In an embodiment, the encapsulation layer 140 may include an organic encapsulation layer 142 between two different inorganic encapsulation layers 141 and 143 as described above, but the present disclosure is not limited thereto. In some embodiments, the organic encapsulation layer 142 may be omitted, and the encapsulation layer 140 may have a structure in which one or more inorganic encapsulation layers are stacked.

[0170] The display panel 100 may include a second pixel power line VSL arranged in the non-display area NA. The second pixel power line VSL may overlap the first dam DAM1 and may surround the display area DA. A portion of the second pixel power line VSL may not overlap the first dam DAM1 and may contact the second electrode ET2 of the light emitting element EL arranged in the valley between the first dam DAM1 and the display area DA. The second electrode ET2 of the light emitting element EL may receive a second power voltage (e.g., Figure 5 or Figure 6 The second pixel power voltage ELVSS shown in FIG.

[0171] In an embodiment, Figure 8As shown in , the first dam DAM1 and the second dam DAM2 are arranged on the second pixel power line VSL, but the present disclosure is not limited thereto. In an embodiment, for example, either of the first dam DAM1 and the second dam DAM2 may not be arranged on the second pixel power line VSL. Alternatively, neither the first dam DAM1 nor the second dam DAM2 may be arranged on the second pixel power line VSL. In such an embodiment, the first dam DAM1 and the second dam DAM2 may be arranged outside the second pixel power line VSL.

[0172] Fig. 9 is a display device 10 according to an embodiment (for example, referring to Figure 3 ) is a schematic view of the encapsulation layer 140. Fig.10 yes Fig. 9 An enlarged view of portion C.

[0173] Reference Fig. 9 and Fig.10 In an embodiment of the display device 10, the first inorganic encapsulation layer 141 and / or the second inorganic encapsulation layer 143 of the encapsulation layer 140 may have a structure in which one or more inorganic insulating layers are stacked. The multiple inorganic insulating layers of the first inorganic encapsulation layer 141 and the second inorganic encapsulation layer 143 may be formed by different processes. Even if the first inorganic encapsulation layer 141 and / or the second inorganic encapsulation layer 143 have a structure in which a plurality of layers are stacked, the first inorganic encapsulation layer 141 and / or the second inorganic encapsulation layer 143 may be relatively thin. In an embodiment of the display device 10, the first inorganic encapsulation layer 141 and / or the second inorganic encapsulation layer 143 including a plurality of inorganic insulating layers may have a thin thickness and be used to encapsulate the display panel 100 (for example, refer to Figure 3 ).

[0174] The first inorganic encapsulation layer 141 and / or the second inorganic encapsulation layer 143 may include a first inorganic layer IL1, a second inorganic layer IL2, and a third inorganic layer IL3. The first inorganic encapsulation layer 141 and / or the second inorganic encapsulation layer 143 may have a structure in which the first inorganic layer IL1, the second inorganic layer IL2, and the third inorganic layer IL3 are sequentially stacked on each other. In an embodiment in which the first inorganic layer IL1, the second inorganic layer IL2, and the third inorganic layer IL3 have different materials or physical properties from each other, the first inorganic encapsulation layer 141 and / or the second inorganic encapsulation layer 143 may have a structure in which inorganic insulating layers having different properties are stacked on each other. However, the present disclosure is not limited thereto. In an embodiment in which the first inorganic layer IL1 and the third inorganic layer IL3 have the same materials and physical properties as each other, the first inorganic encapsulation layer 141 and / or the second inorganic encapsulation layer 143 may have a structure in which inorganic insulating layers having different properties are alternately and repeatedly stacked.

[0175] According to an embodiment, the first inorganic layer IL1, the second inorganic layer IL2, and the third inorganic layer IL3 may include the same material as each other, but the second inorganic layer IL2 may be formed by a manufacturing process different from that of the first inorganic layer IL1 and the third inorganic layer IL3. Accordingly, the second inorganic layer IL2 may have physical properties different from those of the first inorganic layer IL1 and the third inorganic layer IL3, and the first inorganic layer IL1 and the third inorganic layer IL3 may have physical properties the same as each other.

[0176] In an embodiment, for example, each of the first inorganic layer IL1, the second inorganic layer IL2, and the third inorganic layer IL3 may include silicon nitride (SiN x ). The first inorganic layer IL1 and the third inorganic layer IL3 may be formed by a plasma enhanced chemical vapor deposition (PECVD) process or a plasma enhanced atomic layer deposition (PEALD) process, and the second inorganic layer IL2 may be formed by a PECVD process. The deposition rate may be faster or higher in the formation process of the second inorganic layer IL2 than in the formation process of the first inorganic layer IL1 and the third inorganic layer IL3. Depending on the process conditions of the deposition process, the second inorganic layer IL2 may have different physical properties from the first inorganic layer IL1 and the third inorganic layer IL3.

[0177] In an embodiment, for example, the thickness t2 of the second inorganic layer IL2 may be greater than the thickness t1 of the first inorganic layer IL1 and the thickness t3 of the third inorganic layer IL3. In an embodiment, the thickness t1 of the first inorganic layer IL1 and the thickness t3 of the third inorganic layer IL3 may each be about 100 Å. In such an embodiment, the thickness t2 of the second inorganic layer IL2 may be about or greater, and the ratio (t1 / t2) of the thickness t1 of the first inorganic layer IL1 to the thickness t2 of the second inorganic layer IL2 may be 0.03 or less. In addition, the total thickness (t1+t2+t3) of the first inorganic encapsulation layer 141 and / or the second inorganic encapsulation layer 143 may be about 0.4 micrometers (μm) or less. Since the first inorganic layer IL1 and the third inorganic layer IL3 are formed thinner than the second inorganic layer IL2, the total thickness of the first inorganic encapsulation layer 141 and / or the second inorganic encapsulation layer 143 and the total thickness of the encapsulation layer 140 may be reduced. In addition, the total thickness of the first inorganic layer IL1, the second inorganic layer IL2 and the third inorganic layer IL3 and the thickness ratio of each layer with different thicknesses may be adjusted within the above range. Therefore, even if the first inorganic encapsulation layer 141 and / or the second inorganic encapsulation layer 143 have a thin thickness, the first inorganic encapsulation layer 141 and / or the second inorganic encapsulation layer 143 can have sufficient encapsulation properties.

[0178] The first inorganic layer IL1 and the third inorganic layer IL3 may be formed by a deposition process slower than that of the second inorganic layer IL2. Accordingly, the first inorganic layer IL1 and the third inorganic layer IL3 may have a layer density greater than that of the second inorganic layer IL2. In an embodiment, for example, the layer density of the second inorganic layer IL2 may be about 1.7 g / cm3. 3 ) to about 2.10 g / cm 3 , and the layer density of each of the first inorganic layer IL1 and the third inorganic layer IL3 may be about 2.05 g / cm 3 or greater and may be greater than the layer density of the second inorganic layer IL2. The refractive index of the second inorganic layer IL2 may be in the range of about 1.75 to about 1.90, and the refractive index of each of the first inorganic layer IL1 and the third inorganic layer IL3 may be about 1.85 or greater and may be greater than the refractive index of the second inorganic layer IL2. Since the first inorganic layer IL1 and the third inorganic layer IL3 formed by the slow deposition process may have dense layer properties, the first inorganic layer IL1 and the third inorganic layer IL3 may have high encapsulation properties. However, considering the manufacturing process yield, the first inorganic layer IL1 and the third inorganic layer IL3 may be formed to be thinner than the second inorganic layer IL2.

[0179] In addition, the second inorganic layer IL2 may have a relatively low layer density, but at least about 1.7 g / cm 3 layer density. In addition, since the ratio of the thickness t1 of the high-density first inorganic layer IL1 to the thickness t2 of the low-density second inorganic layer IL2 is adjusted to 0.03 or less, the second inorganic layer IL2 may have a high encapsulation property like the first inorganic layer IL1 and the third inorganic layer IL3. Specifically, the side surface of the second inorganic layer IL2 may be exposed in the inorganic encapsulation area IEA of the outer portion of the display panel 100. However, since the second inorganic layer IL2 has a sufficient layer density, the second inorganic layer IL2 can effectively prevent moisture from penetrating from the outside.

[0180] In an embodiment, the layer density of the first inorganic layer IL1 to the third inorganic layer IL3 can be measured using an X-ray reflectometer (XRR) (D8 ADVANCE Plus of Bruker). In some embodiments, the layer density of the first inorganic layer IL1 and the third inorganic layer IL3 measured using the XRR device can be about 2.14 g / cm 3 To about 2.70g / cm 3 , and the layer density of the second inorganic layer IL2 measured using an XRR device may be about 1.90 g / cm 3 to about 2.04g / cm 3 However, the present disclosure is not limited thereto.

[0181] Fig.11is a display panel 100 according to an embodiment (for example, referring to Figure 3 ) in an enlarged view of the inorganic encapsulation area IEA in the outer part.

[0182] Reference Fig.11 In an embodiment of the display panel 100, the first inorganic encapsulation layer 141 and the second inorganic encapsulation layer 143 may contact each other in the inorganic encapsulation area IEA. In an embodiment in which the second inorganic encapsulation layer 143 includes a plurality of inorganic layers IL1 to IL3, the first inorganic layer IL1 of the second inorganic encapsulation layer 143 may directly contact the upper surface of the first inorganic encapsulation layer 141. A side surface of each of the first inorganic encapsulation layer 141 and the second inorganic encapsulation layer 143 may be exposed in an outer portion of the display panel 100. A side surface of the second inorganic layer IL2 having a relatively low layer density among the inorganic layers IL1 to IL3 of the second inorganic encapsulation layer 143 may also be exposed.

[0183] In an embodiment, the water vapor transmission rate (WVTR) of the second inorganic layer IL2 may be about 3×10 -4 g / m2 / day 2 day) or less, and the total WVTR of the inorganic encapsulation layer 141 or 143 including the first inorganic layer IL1, the second inorganic layer IL2, and the third inorganic layer IL3 may be about 5×10 -5 g / m 2 day or less. Since the first inorganic encapsulation layer 141 and / or the second inorganic encapsulation layer 143 has a structure in which a plurality of inorganic layers IL1 to IL3 are stacked, the first inorganic encapsulation layer 141 and / or the second inorganic encapsulation layer 143 can have high encapsulation properties while their total thickness is reduced or substantially thin. Specifically, even if its side surface is exposed in the outer portion of the display panel 100, the relatively thick second inorganic layer IL2 can have a thickness of about 3×10 -4 g / m 2 day or less and may also have adequate packaging properties.

[0184] According to an embodiment, in the display device 10 (for example, referring to Figure 3 ), the encapsulation layer 140 (eg, referring to Figure 3 ) may include a plurality of inorganic layers IL1 to IL3. Therefore, the first inorganic encapsulation layer 141 and / or the second inorganic encapsulation layer 143 may have a thin thickness but sufficient encapsulation properties. Accordingly, even if the display device 10 is reduced in size, damage caused by moisture penetration from the outside can be effectively prevented. In an embodiment, in the case where the display device 10 has a foldable characteristic, since the thickness of the encapsulation layer 140 is reduced, its folding and bending characteristics can be improved.

[0185] An embodiment of a method of manufacturing the display device 10 will now be described with reference to other drawings.

[0186] Fig.12 is a flowchart illustrating a method of manufacturing a display device according to an embodiment. Fig.13 It is shown in detail Fig.12 Flow chart of a process for forming a second inorganic encapsulation layer in FIG.

[0187] Reference Fig.12 and Fig.13 (See also, for example, Figure 8 , Fig. 9 and Fig.10 ), according to the manufacturing display device 10 of the embodiment (for example, referring to Figure 3 ) may include: forming a plurality of light emitting elements EL on a substrate (operation S10); forming a first inorganic encapsulation layer 141 on the light emitting element EL (operation S20); forming an organic encapsulation layer 142 on the first inorganic encapsulation layer 141 (operation S30); and forming a second inorganic encapsulation layer 143 on the organic encapsulation layer 142 (operation S40). Forming the second inorganic encapsulation layer 143 (operation S40) may include: forming a high-density first inorganic layer IL1 (operation S41); forming a low-density second inorganic layer IL2 on the first inorganic layer IL1 (operation S42); and forming a high-density third inorganic layer IL3 on the second inorganic layer IL2 (operation S43). In an embodiment of the method of manufacturing the display device 10, the first inorganic encapsulation layer 141 and / or the second inorganic encapsulation layer 143 may include inorganic layers IL1 to IL3 formed by different deposition processes.

[0188] although Fig.12 and Fig.13 The subsequent figures show an embodiment in which the second inorganic encapsulation layer 143 includes a plurality of inorganic layers IL1 to IL3, but the present disclosure is not limited thereto. The first inorganic encapsulation layer 141 may also include a plurality of inorganic layers IL1 to IL3. In this case, forming the first inorganic encapsulation layer 141 on the light emitting element EL (operation S20) may be performed by a plurality of deposition processes.

[0189] Figures 14 to 19 are views sequentially illustrating a process of manufacturing a display device according to an embodiment.

[0190] Reference Fig.14 (See also, for example, Fig.12 and Fig.13 ), in manufacturing the display device 10 (for example, referring to Figure 3), a plurality of light emitting elements EL are formed on a substrate BSUB (operation S10) to form a light emitting element layer 130. A pixel defining layer 131 may be formed on the substrate BSUB, and the light emitting element EL may be formed in an opening of the pixel defining layer 131. The structures of the pixel defining layer 131 and the light emitting element EL are the same as those described above. Each of the pixel defining layer 131 and the light emitting element EL may be formed by a typical patterning process or a deposition process.

[0191] Reference Fig.15 , a first inorganic encapsulation layer 141 is formed on the light emitting element EL (operation S20). The first inorganic encapsulation layer 141 may be composed of one inorganic insulating layer, but the present disclosure is not limited thereto. Like the second inorganic encapsulation layer 143 to be described later, the first inorganic encapsulation layer 141 may also be composed of a plurality of inorganic layers IL1 to IL3, or defined by a plurality of inorganic layers IL1 to IL3.

[0192] Like the inorganic layers IL1 to IL3, the first inorganic encapsulating layer 141 may include silicon nitride (SiN x ), and may have a thickness similar to that of the second inorganic encapsulation layer 143. In an embodiment, the first inorganic encapsulation layer 141 may be formed by a PECVD process using a gas precursor or a liquid precursor. However, the present disclosure is not limited thereto. In an embodiment where the first inorganic encapsulation layer 141 includes a plurality of inorganic layers IL1 to IL3, each of the inorganic layers IL1 to IL3 may be formed by a process to be described later.

[0193] Reference Fig.16 , an organic encapsulation layer 142 is formed on the first inorganic encapsulation layer 141 (operation S30). The organic encapsulation layer 142 may include an organic insulating material. The process of forming the organic encapsulation layer 142 is not particularly limited. In an embodiment, for example, the organic encapsulation layer 142 may be formed by a chemical vapor deposition (CVD) method or an inkjet printing process.

[0194] Reference Figures 17 to 19 , forming a second inorganic encapsulation layer 143 on the organic encapsulation layer 142 (operation S40). Forming the second inorganic encapsulation layer 143 may include: Fig.17 As shown in , a high-density first inorganic layer IL1 is formed (operation S41) (this may be referred to as a first deposition); Fig.18 forming a low-density second inorganic layer IL2 on the first inorganic layer IL1 as shown in (operation S42 ) (this may be referred to as a second deposition); and Fig.19 As shown in FIG. 4 , a high-density third inorganic layer IL3 is formed on the second inorganic layer IL2 (operation S43 ) (this may be referred to as a third deposition).

[0195] In an embodiment, the forming of the first inorganic layer IL1 (operation S41) and the forming of the third inorganic layer IL3 (operation S43) may be performed by a PEALD or PECVD process using a liquid precursor, and the forming of the second inorganic layer IL2 (operation S42) may be performed by a PECVD process using a gas precursor or a liquid precursor. The forming of the first inorganic layer IL1 (operation S41) and the forming of the third inorganic layer IL3 (operation S43) may be a slow deposition process and may have a deposition rate of about 100 %. The formation of the second inorganic layer IL2 (operation S42) may be a fast deposition process and may have a deposition rate of about The first inorganic layer IL1 and the third inorganic layer IL3 may have a high layer density due to their slow deposition rate, and the second inorganic layer IL2 may have a low layer density due to its fast deposition rate. However, considering the manufacturing process yield, since the first inorganic layer IL1 and the third inorganic layer IL3 are formed in a short time, the first inorganic layer IL1 and the third inorganic layer IL3 may be thin, and the second inorganic layer IL2 may be relatively thick.

[0196] In an embodiment of the manufacturing process of the display device 10, forming a high-density first inorganic layer IL1 (operation S41) and forming a high-density third inorganic layer IL3 (operation S43) may use a liquid precursor for the PEALD process. In an embodiment in which the first inorganic layer IL1 and the third inorganic layer IL3 are formed by a PEALD process using a liquid precursor, a higher refractive index than when a gas precursor is used and a lower WVTR than when a gas precursor is used can be achieved. In addition, the second inorganic encapsulation layer 143 including the second inorganic layer IL2 formed by the PECVD process in addition to the first inorganic layer IL1 and the third inorganic layer IL3 may also have high encapsulation properties.

[0197] In an embodiment, the inorganic layers IL1 to IL3 may include silicon nitride (SiN x), and the liquid precursor used in the deposition process of forming the inorganic layers IL1 to IL3 may be an aminosilane compound having a Si-N bond as a core structure. In an embodiment, for example, the liquid precursor used in the process of forming the inorganic layers IL1 to IL3 may include, but is not limited to, cyclosilazane, trisilyamine, bis(diethylamino)silane, bis(t-butylamino)silane, tris(dimethylamino)silane, tris(isopropylamino)silane, tetrakis(dimethylamino)silane, tri(isopropyl)cyclotrisilazane, and tetramethyldisilazane. The invention may be composed of at least one of cyclosilazane, trisilyamine, bis(diethylamino)silane, bis(t-butylamino)silane, tris(dimethylamino)silane, tris(isopropylamino)silane, tetrakis(dimethylamino)silane, tri(isopropyl)cyclotrisilazane and tetramethyldisilazane.

[0198] In an embodiment of the manufacturing process of the display device 10, the first inorganic encapsulation layer 141 and / or the second inorganic encapsulation layer 143 of the encapsulation layer 140 may include a plurality of inorganic layers IL1 to IL3 formed by different deposition processes. Therefore, the first inorganic encapsulation layer 141 and / or the second inorganic encapsulation layer 143 may have a thin thickness and excellent encapsulation properties. An embodiment in which the second inorganic encapsulation layer 143 of the encapsulation layer 140 includes a plurality of inorganic layers IL1 to IL3 has been described above. However, the present disclosure is not limited thereto, and the first inorganic encapsulation layer 141 may also include a plurality of inorganic layers IL1 to IL3.

[0199] Fig. 20A display device 10 according to an embodiment is shown (for example, referring to Figure 1 )'s encapsulation layer 140_1. Fig.21 yes Fig. 20 FIG. 1 is an enlarged view of the inorganic encapsulation area IEA in the outer portion of the display device 10 .

[0200] Reference Fig. 20 and Fig.21 , in the display device 10 according to the embodiment, the first inorganic encapsulation layer 141_1 and the second inorganic encapsulation layer 143_1 of the encapsulation layer 140_1 may each have a structure in which a plurality of inorganic insulating layers are stacked on each other. Each of the first inorganic encapsulation layer 141_1 and the second inorganic encapsulation layer 143_1 may include a first inorganic layer IL1, a second inorganic layer IL2, and a third inorganic layer IL3. The inorganic layers IL1 to IL3 of each of the first inorganic encapsulation layer 141_1 and the second inorganic encapsulation layer 143_1 are the same as described above. In an embodiment, for example, the inorganic layers IL1 to IL3 of each of the first inorganic encapsulation layer 141_1 and the second inorganic encapsulation layer 143_1 may have different thicknesses and different layer densities from each other.

[0201] In addition, the formation process of the inorganic layers IL1 to IL3 of the first inorganic encapsulation layer 141_1 can be the same as that described above. Figures 17 to 19 The formation process of the second inorganic encapsulation layer 143 is the same as described.

[0202] In the embodiment of the display device 10, since each of the first inorganic encapsulation layer 141_1 and the second inorganic encapsulation layer 143_1 of the encapsulation layer 140_1 includes inorganic layers IL1 to IL3 having different physical properties from each other, the encapsulation layer 140_1 can have high encapsulation properties while its total thickness is reduced or substantially thinned. Accordingly, in an embodiment in which the display device 10 has a foldable characteristic or is reduced in size, the encapsulation layer 140_1 can have characteristics suitable for the display device 10.

[0203] Fig. 22 is a perspective view of a head mounted display device 1000 according to an embodiment. Fig.23 yes Fig. 22 1 is an exploded perspective view of an example of a head mounted display device 1000.

[0204] Reference Fig. 22 and Fig.23 According to an embodiment, the head-mounted display device 1000 includes a first display device 11, a second display device 12, a display device housing 1100, a housing cover 1200, a first eyepiece 1210, a second eyepiece 1220, a head strap 1300, an intermediate frame 1400, a first optical member 1510, a second optical member 1520, a control circuit board 1600 and a connector.

[0205] The first display device 11 provides an image to the left eye of the user, and the second display device 12 provides an image to the right eye of the user. Each of the first display device 11 and the second display device 12 is connected to the reference Figure 1 The display devices 10 described are substantially the same. Therefore, any repeated detailed description of the first display device 11 and the second display device 12 will be omitted.

[0206] The first optical member 1510 may be disposed between the first display device 11 and the first eyepiece 1210. The second optical member 1520 may be disposed between the second display device 12 and the second eyepiece 1220. Each of the first optical member 1510 and the second optical member 1520 may include at least one convex lens.

[0207] The middle frame 1400 may be disposed between the first display device 11 and the control circuit board 1600, and may be disposed between the second display device 12 and the control circuit board 1600. The middle frame 1400 supports and fixes the first display device 11, the second display device 12, and the control circuit board 1600.

[0208] The control circuit board 1600 may be disposed between the middle frame 1400 and the display device housing 1100. The control circuit board 1600 may be connected to the first display device 11 and the second display device 12 through a connector. The control circuit board 1600 may convert an image source received from the outside into digital video data and transmit the digital video data to the first display device 11 and the second display device 12 through the connector.

[0209] The control circuit board 1600 may transmit digital video data corresponding to a left-eye image optimized for the user's left eye to the first display device 11, and may transmit digital video data corresponding to a right-eye image optimized for the user's right eye to the second display device 12. Alternatively, the control circuit board 1600 may transmit the same digital video data to the first display device 11 and the second display device 12.

[0210] The display device housing 1100 accommodates the first display device 11, the second display device 12, the middle frame 1400, the first optical member 1510, the second optical member 1520, the control circuit board 1600, and the connector. The housing cover 1200 is placed to cover the open surface of the display device housing 1100. The housing cover 1200 may include a first eyepiece 1210 on which the user's left eye is placed and a second eyepiece 1220 on which the user's right eye is placed. In an embodiment, as shown in FIG. Fig. 22 and Fig.23 As shown in , the first eyepiece 1210 and the second eyepiece 1220 may be arranged separately (for example, in the X-axis direction), but the present disclosure is not limited thereto. In an embodiment, the first eyepiece 1210 and the second eyepiece 1220 may also be combined into one.

[0211] The first eyepiece 1210 may be aligned with the first display device 11 and the first optical member 1510 (for example, in the Z-axis direction), and the second eyepiece 1220 may be aligned with the second display device 12 and the second optical member 1520 (for example, in the Z-axis direction). Therefore, the user can view the image of the first display device 11 magnified as a virtual image by the first optical member 1510 through the first eyepiece 1210, and can view the image of the second display device 12 magnified as a virtual image by the second optical member 1520 through the second eyepiece 1220.

[0212] The headband 1300 fixes the display device housing 1100 to the user's head in such a manner that the first eyepiece 1210 and the second eyepiece 1220 of the housing cover 1200 remain placed on the user's left eye and right eye, respectively. In an embodiment where it is desired to implement the display device housing 1100 as being lightweight and small, the head mounted display device 1000 may include a Fig.24 The eyeglass frame shown in FIG. 1 is used to replace the headband 1300.

[0213] In addition, the head mounted display device 1000 may further include a battery for supplying power, an external memory slot for accommodating an external memory, and an external connection port and a wireless communication module for receiving an image source. The external connection port may be a universal serial bus (USB) terminal, a display port, or a high definition multimedia interface (HDMI) terminal, and the wireless communication module may be a 5G communication module, a 4G communication module, a Wi-Fi module, or a Bluetooth module. In addition, the unmentioned Y-axis direction may be a direction perpendicular to the surface defined by the X-axis direction and the Z-axis direction.

[0214] Fig.24 is a perspective view of a head mounted display device 1000_1 according to an embodiment.

[0215] Reference Fig.24 The head mounted display device 1000_1 according to the embodiment may be a display device in which the display device housing 1200_1 is implemented as a lightweight and small glasses form. The head mounted display device 1000_1 according to the embodiment may include a display device 13, a left eyeglass 1010, a right eyeglass 1020, a support frame 1030, eyeglass frame legs 1040 and 1050, an optical member 1060, an optical path conversion member 1070, and a display device housing 1200_1.

[0216] The display device housing 1200_1 may include (e.g., accommodate) the display device 13, the optical member 1060, and the optical path conversion member 1070. The image displayed on the display device 13 may be enlarged by the optical member 1060, may have its optical path converted by the optical path conversion member 1070, and may then be provided to the user's right eye through the right eye lens 1020. Accordingly, the user is able to view an augmented reality image composed of a virtual image displayed on the display device 13 and a real image viewed through the right eye lens 1020 through the right eye.

[0217] In an embodiment, Fig.24 As shown in , the display device housing 1200_1 may be arranged at the right end of the support frame 1030, but the present disclosure is not limited thereto. In an embodiment, for example, the display device housing 1200_1 may also be arranged at the left end of the support frame 1030. In such an embodiment, the image of the display device 13 may be provided to the user's left eye. Alternatively, the display device housing 1200_1 may be arranged at both the left and right ends of the support frame 1030. In such an embodiment, the user can view the image displayed on the display device 13 through both the left and right eyes.

[0218] In the display device according to the embodiment, the inorganic encapsulation layer of the encapsulation layer includes a plurality of inorganic layers respectively formed by different deposition processes. Therefore, the inorganic encapsulation layer can have a high encapsulation property while having a thin thickness.

[0219] In an embodiment, in the case where the display device has a flexible characteristic, since the thickness of the encapsulation layer is reduced or substantially thinned, damage to the encapsulation layer during folding or bending can be effectively prevented.

[0220] The present invention should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the present invention to those skilled in the art.

[0221] While the invention has been particularly shown and described with reference to embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the scope or spirit of the invention as defined in the following claims.

Claims

1. A display device, comprising: A substrate, wherein a display area and a non-display area surrounding the display area are defined on the substrate; a light emitting element layer disposed on the substrate and including a plurality of light emitting elements disposed in the display area; as well as an encapsulation layer, the encapsulation layer comprising a first inorganic encapsulation layer arranged on the light emitting element layer, an organic encapsulation layer arranged on the first inorganic encapsulation layer, and a second inorganic encapsulation layer arranged on the organic encapsulation layer, wherein at least one selected from the first inorganic encapsulation layer and the second inorganic encapsulation layer includes a first inorganic layer, a second inorganic layer disposed on the first inorganic layer, and a third inorganic layer disposed on the second inorganic layer, The thickness of each of the first inorganic layer and the third inorganic layer is smaller than the thickness of the second inorganic layer, The thickness of each of the first inorganic layer and the third inorganic layer is or smaller, and A ratio of the thickness of the first inorganic layer to the thickness of the second inorganic layer is 0.03 or less.

2. The display device according to claim 1, wherein: The sum of the thicknesses of the first inorganic layer, the second inorganic layer, and the third inorganic layer is 0.4 μm or less.

3. The display device according to claim 1, wherein: The layer density of the second inorganic layer is 1.7 g / cm 3 Up to 2.10g / cm 3 within the range of The layer density of each of the first inorganic layer and the third inorganic layer is 2.05 g / cm 3 or greater, and The layer density of each of the first inorganic layer and the third inorganic layer is greater than the layer density of the second inorganic layer.

4. The display device according to claim 1, wherein: The refractive index of the second inorganic layer is in the range of 1.75 to 1.90, The refractive index of each of the first inorganic layer and the third inorganic layer is 1.85 or more, and The refractive index of each of the first inorganic layer and the third inorganic layer is greater than the refractive index of the second inorganic layer.

5. The display device according to claim 1, wherein: Each of the first inorganic layer, the second inorganic layer, and the third inorganic layer includes silicon nitride (SiN x ).

6. The display device according to claim 1, wherein: Each of the first inorganic encapsulating layer and the second inorganic encapsulating layer includes the first inorganic layer, the second inorganic layer, and the third inorganic layer.

7. The display device according to claim 1, wherein: The first inorganic encapsulation layer and the second inorganic encapsulation layer including the first inorganic layer, the second inorganic layer and the third inorganic layer have a thickness of 5×10 -5 g / m 2 Water vapor transmission rate of day or less.

8. The display device according to claim 7, wherein: The second inorganic layer has 3×10 -4 g / m 2 Water vapor transmission rate of day or less.

9. The display device according to claim 1, further comprising: a first dam arranged in the non-display area and surrounding the display area; as well as a second dam, the second dam surrounding the first dam, The organic encapsulation layer is arranged inside the second dam in the display area and the non-display area.

10. The display device according to claim 9, wherein: The first inorganic encapsulating layer and the second inorganic encapsulating layer directly contact each other in the non-display area outside the second dam.

11. The display device according to claim 10, wherein: A side surface of the second inorganic layer is exposed in the non-display area.

12. The display device according to claim 1, further comprising: a circuit layer, the circuit layer being arranged between the substrate and the light emitting element layer, The circuit layer includes a first semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, a second semiconductor layer, a fourth insulating layer, a third conductive layer, a fifth insulating layer and a fourth conductive layer sequentially arranged on the substrate.

13. A method for manufacturing a display device, the method comprising: forming a light emitting element layer including a plurality of light emitting elements on a substrate; forming a first inorganic encapsulation layer on the light emitting element layer and forming an organic encapsulation layer on the first inorganic encapsulation layer; as well as forming a second inorganic encapsulation layer on the organic encapsulation layer, Wherein, forming the second inorganic encapsulation layer comprises: forming a first inorganic layer having a high density on the organic encapsulation layer; forming a second inorganic layer having a low density on the first inorganic layer; and forming a third inorganic layer having a high density on the second inorganic layer, The deposition rate when forming the second inorganic layer is higher than the deposition rates when forming the first inorganic layer and the third inorganic layer.

14. The method of claim 13, wherein: The deposition rate when forming the second inorganic layer is or greater, and The deposition rate when forming the first inorganic layer and the deposition rate when forming the third inorganic layer are each or smaller.

15. The method of claim 13, wherein: The thickness of each of the first inorganic layer and the third inorganic layer is smaller than the thickness of the second inorganic layer, The thickness of each of the first inorganic layer and the third inorganic layer is or smaller, and A ratio of the thickness of the first inorganic layer to the thickness of the second inorganic layer is 0.03 or less.

16. The method of claim 13, wherein: The layer density of the second inorganic layer is 1.7 g / cm 3 Up to 2.10g / cm 3 within the range of The layer density of each of the first inorganic layer and the third inorganic layer is 2.05 g / cm 3 or greater, and the layer density of each of the first inorganic layer and the third inorganic layer is greater than the layer density of the second inorganic layer, The refractive index of the second inorganic layer is in the range of 1.75 to 1.90, The refractive index of each of the first inorganic layer and the third inorganic layer is 1.85 or more, and The refractive index of each of the first inorganic layer and the third inorganic layer is greater than the refractive index of the second inorganic layer.

17. The method of claim 13, wherein: The forming of the first inorganic layer and the forming of the third inorganic layer are each performed by a plasma enhanced atomic layer deposition process or a plasma enhanced chemical vapor deposition process, and The forming of the second inorganic layer is performed by a plasma enhanced chemical vapor deposition process.

18. The method of claim 17, wherein: The forming of the first inorganic layer and the forming of the third inorganic layer are performed using a liquid precursor containing Si—N bonds.

19. The method of claim 18, wherein: The liquid precursor includes at least one selected from cyclosilamine, trisilamine, bis(diethylamino)silane, bis(tert-butylamino)silane, tri(dimethylamino)silane, tri(isopropylamino)silane, tetra(dimethylamino)silane, tri(isopropyl)cyclotrisilazane and tetramethyldisilazane.

20. The method of claim 13, wherein: The second inorganic encapsulation layer including the first inorganic layer, the second inorganic layer and the third inorganic layer has a thickness of 5×10 -5 g / m 2 day or less water vapor transmission rate, and The second inorganic layer has 3×10 -4 g / m 2 Water vapor transmission rate of day or less.

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