Method for manufacturing display device

Abstract

Provided is a method for manufacturing a display device, including: preparing a substrate including a display area, a pad area, a peripheral area, a first electrode, and an intermediate layer, the first electrode and the intermediate layer being in the display area; forming a primary first stripping layer on the substrate; forming a first photoresist pattern having an optical opening overlapping the display region on the preliminary first release layer; etching the preliminary first stripping layer to form a first stripping layer exposing the display area; forming a second electrode on the intermediate layer through the optical opening; and removing the first release layer and the first photoresist pattern.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0120517 filed in the Korean Intellectual Property Office on September 11, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to a method for manufacturing a display device, and more particularly, to a method for manufacturing a display device in which a manufacturing process is simplified. Background Art

[0004] The display device includes a light emitting element located on a substrate and a pad electrically connected thereto. Various electrical signals can be applied to the light emitting element through the pad. The light emitting element may include a common electrode positioned on a plurality of emission layers. The common electrode is a layer provided in common on a plurality of emission layers and may be provided continuously on the plurality of emission layers.

[0005] When manufacturing the common electrode, it is desirable that the pad to which the external electrical signal is applied is not covered by the common electrode. Therefore, when manufacturing the common electrode, the common electrode is formed in a preset area of ​​the substrate, and thus a mask is used. However, due to repeated use, the mask may be damaged, and thus may need to be replaced regularly. Therefore, the manufacturing cost of the display device increases, and there is a defect in the process of precisely aligning the substrate and the mask during the manufacturing process. Summary of the invention

[0006] Aspects of some embodiments of the present disclosure are directed to a simplified method for manufacturing a display device.

[0007] According to some embodiments of the present disclosure, a method for manufacturing a display device is provided, comprising: preparing a substrate comprising a display area, a pad area, a peripheral area, a first electrode and an intermediate layer, the first electrode and the intermediate layer being in the display area; forming a preliminary first peeling layer on the substrate; forming a first photoresist pattern having a light opening portion overlapping the display area on the preliminary first peeling layer; etching the preliminary first peeling layer to form a first peeling layer exposing the display area; forming a second electrode on the intermediate layer through the light opening portion; and removing the first peeling layer and the first photoresist pattern.

[0008] In one or more embodiments, the method may further include: after forming the second electrode, forming an optical layer on the second electrode through the light opening portion.

[0009] In one or more embodiments, the first peeling layer may overlap the pad region in plane.

[0010] In one or more embodiments, the first release layer may include polytetrafluoroethylene (PTFE).

[0011] In one or more embodiments, forming the first lift-off layer may include etching the preliminary first lift-off layer with a first solvent including fluorine by using the first photoresist pattern as a mask.

[0012] In one or more embodiments, the first solvent may include a hydrofluoroether (HFE).

[0013] In one or more embodiments, removing the first lift-off layer and the first photoresist pattern may include treating the first lift-off layer and the first photoresist pattern with a second solvent including fluorine.

[0014] In one or more embodiments, preparing a substrate may include: preparing a base substrate in which a display area and a pad area are defined; forming a first electrode on the base substrate to overlap with the display area; forming a pixel defining layer that defines a pixel opening portion that exposes a portion of the first electrode and includes a liquid-repellent portion that includes a liquid-repellent material; and forming an intermediate layer on the first electrode.

[0015] In one or more embodiments, during the formation of the first peeling layer, at least a portion of the liquid-repellent portion may be removed by an etching process.

[0016] In one or more embodiments, forming the intermediate layer may include: forming a hole transport region on the first electrode; forming an emission layer on the hole transport region; and forming an electron transport region on the emission layer.

[0017] In one or more embodiments, forming the intermediate layer may be performed by an inkjet process.

[0018] In one or more embodiments, forming the second electrode may be performed by a deposition process.

[0019] In one or more embodiments, the method may further include: forming a preliminary second stripping layer on the substrate; forming a second photoresist pattern overlapping the pad area on the preliminary second stripping layer; etching the preliminary second stripping layer to form a second stripping layer exposing the display area; forming an encapsulation layer on the second electrode using the second photoresist pattern as a mask; and removing the second stripping layer and the second photoresist pattern.

[0020] In one or more embodiments, the second peeling layer may not overlap the display area in plane, and may not overlap the peripheral area in plane.

[0021] In one or more embodiments, forming the second lift-off layer may include etching the preliminary second lift-off layer with a third solvent including fluorine by using the second photoresist pattern as a mask.

[0022] In one or more embodiments, removing the second lift-off layer and the second photoresist layer may include treating the second lift-off layer and the second photoresist pattern with a fourth solvent including fluorine.

[0023] According to some embodiments of the present disclosure, a method for manufacturing a display device according to the present disclosure is provided, including: preparing a base substrate in which a display area including a plurality of pixel areas and a pad area are defined; forming a first electrode and a pixel defining layer on the base substrate, the pixel defining layer defining a plurality of pixel openings, each of the plurality of pixel openings overlapping the pixel area; providing an intermediate layer in the pixel opening by an inkjet printing method; forming a first stripping layer exposing the display area and containing fluorine and a first photoresist pattern in which a light opening exposing the display area is defined; forming a second electrode on the intermediate layer through the light opening portion; and removing the first stripping layer and the first photoresist pattern.

[0024] In one or more embodiments, the method may further include: forming an optical layer on the second electrode through the light opening portion.

[0025] In one or more embodiments, forming a first stripping layer and a first photoresist pattern may include: forming a preliminary first stripping layer on a display area and a pad area; forming a first photoresist pattern on the preliminary first stripping layer; and etching the preliminary first stripping layer using the first photoresist pattern as a mask to form a first stripping layer.

[0026] In one or more embodiments, the pixel defining layer may include: a first pixel defining portion arranged on a base substrate; and a second pixel defining portion arranged on the first pixel defining portion and including a liquid-repellent material, wherein at least a portion of the second pixel defining portion may be removed during etching of the preliminary first peeling layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The accompanying drawings are included to provide a further understanding of the present disclosure and are incorporated into and constitute a part of this specification. The accompanying drawings illustrate embodiments of the present disclosure and together with the description serve to explain the principles of the present disclosure. In the drawings:

[0028] Figure 1A illustrates a perspective view of a display device according to one or more embodiments of the present disclosure;

[0029] Figure 1B illustrates a cross-sectional view of a display device according to one or more embodiments of the present disclosure;

[0030] Figure 2A and Figure 2Billustrates a cross-sectional view of a display panel according to one or more embodiments of the present disclosure;

[0031] Figure 3 illustrates a plan view of a display panel according to one or more embodiments of the present disclosure;

[0032] Figure 4 An enlarged plan view illustrating a portion of a display device according to one or more embodiments of the present disclosure;

[0033] Figure 5 illustrates a cross-sectional view of a display device according to one or more embodiments of the present disclosure;

[0034] Fig. 6A and Figure 6B An enlarged view of a portion of a cross section of a display device according to one or more embodiments of the present disclosure is illustrated;

[0035] Figure 7 A flow chart illustrating a method for manufacturing a display device according to one or more embodiments of the present disclosure is illustrated;

[0036] FIG. 8A to FIG. 8Q illustrates a diagram schematically showing some steps of a method for manufacturing a display device according to one or more embodiments of the present disclosure;

[0037] Fig. 9 A flowchart illustrating some steps of a method for manufacturing a display device according to one or more embodiments of the present disclosure;

[0038] FIG. 10A to FIG. 10K illustrates a diagram schematically showing some steps of a method for manufacturing a display device according to one or more embodiments of the present disclosure; and

[0039] FIG. 11A to FIG. 11H A diagram schematically showing some steps of a method for manufacturing a display device according to one or more embodiments of the present disclosure is illustrated. DETAILED DESCRIPTION

[0040] Hereinafter, embodiments of the present disclosure will be explained with reference to the accompanying drawings.

[0041] In the description, it will be understood that when an element (or region, layer, component and / or the like) is referred to as being "on," "connected to" or "coupled to" another element, it can be directly on, directly connected to or directly coupled to the other element, or intervening elements may be present.

[0042] Throughout the specification, similar reference numerals refer to similar elements. In addition, in the drawings, for the effective explanation of the technical content, the thickness, proportion and size of the constituent elements are exaggerated. The term "and / or" includes one or more combinations that can be defined by the relevant elements.

[0043] It will be understood that although the terms first, second and / or the like may be used to describe various elements in this article, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, without departing from the scope of the rights of the present disclosure, the first element may be referred to as the second element. Similarly, the second element may be referred to as the first element. Unless otherwise clearly indicated in the context, the singular form is intended to also include the plural form.

[0044] In addition, the terms "below", "beneath", "on", and "above" are used to explain the relationship between elements shown in the drawings. The terms are relative concepts and are explained based on the directions shown in the drawings.

[0045] It will also be understood that the terms “comprises” or “comprising”, when used in this specification, specify the presence of stated features, numbers, steps, operations, elements, components, or combinations thereof, but do not preclude the presence or addition of one or more other features, numbers, steps, operations, elements, components, or combinations thereof.

[0046] In the description, "directly arranged" may mean that there is no additional layer, film, region, or plate between one component (such as a layer, film, region, or plate) and another component. For example, "directly arranged" may mean that two layers or two components are arranged without using an additional component (such as an adhesive component) therebetween.

[0047] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. In addition, it will also be understood that, unless explicitly defined as such herein, terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and will not be interpreted in an idealized or overly formal sense.

[0048] Hereinafter, a display panel according to one or more embodiments of the present disclosure will be explained with reference to the accompanying drawings.

[0049] Figure 1A A perspective view of a display device according to one or more embodiments of the present disclosure is illustrated. Figure 1B A cross-sectional view of a display device according to one or more embodiments of the present disclosure is illustrated.

[0050] like Figure 1A As shown in , the display device DD may display an image through a display surface DD-IS. The display surface DD-IS may be parallel to a plane defined by a first direction DR1 and a second direction DR2. The display surface DD-IS may include a display area DA and a non-display area NDA. The pixel PX may be in the display area DA, and the pixel PX may not be in the non-display area NDA. The non-display area NDA may be defined along a boundary of the display surface DD-IS. The non-display area NDA may surround the display area DA. However, the present disclosure is not limited thereto. In one or more embodiments of the present disclosure, the non-display area NDA may be omitted or positioned only at one side of the display area DA.

[0051] The normal direction of the display surface DD-IS (i.e., the thickness direction of the display panel DP) may be indicated by a third direction DR3. The front surface (or top surface) and the rear surface (or bottom surface) of each layer or unit explained below may be distinguished by the third direction DR3. However, the first direction DR1, the second direction DR2, and the third direction DR3 shown in one or more embodiments are only examples.

[0052] In one or more embodiments of the present disclosure, a display device DD provided with a flat display surface DD-IS is shown, but is not limited thereto. The display device DD may include a curved display surface or a three-dimensional display surface. The three-dimensional display surface may include a plurality of display areas indicating different directions from each other.

[0053] like Figure 1B As shown in , the display device DD includes a display panel DP and an optical structure layer OSL positioned on the display panel DP. The display panel DP may include a base substrate BS, a circuit element layer DP-CL, a display element layer DP-LED, and an encapsulation layer TFE. The base substrate BS may include a synthetic resin substrate or a glass substrate. The circuit element layer DP-CL may include at least one insulating layer and a circuit element. The circuit element includes a signal line, a driving circuit of a pixel PX, and / or the like. The circuit element layer DP-CL may be formed by a formation process of an insulating layer, a semiconductor layer, and a conductive layer according to coating, deposition, and / or similar processes, and a patterning process of an insulating layer, a semiconductor layer, and a conductive layer according to a photolithography process. The display element layer DP-LED may include at least one display element. The optical structure layer OSL may convert the color of light provided from the display element. The optical structure layer OSL may include a light control pattern and a structure for improving (e.g., increasing) the conversion efficiency of light.

[0054] Figure 2A and Figure 2B is a cross-sectional view illustrating a display panel according to one or more embodiments of the present disclosure.

[0055] like Figure 2A As shown in FIG. 1 , the display panel DP includes a base substrate BS, a circuit element layer DP-CL positioned on the base substrate BS, a display element layer DP-LED, and an encapsulation layer TFE. Figure 1A . In the display panel DP, the display area DA may be defined as an area in which the pixels PX are located. In the display panel DP, the non-display area NDA may be defined as an area in which the pixels PX are not located and signal lines supporting the operation of the pixels PX are located. In the detailed description, "one area corresponds to another area" means "a plurality of areas overlap each other", but is not limited to having the same area.

[0056] The base substrate BS may include at least one plastic film. The base substrate BS may include a plastic substrate, a glass substrate, a metal substrate, or an organic / inorganic composite material substrate. In one or more embodiments, the base substrate BS may be a thin film glass substrate having a thickness of tens to hundreds of microns.

[0057] The circuit element layer DP-CL may include at least one insulating layer and a circuit element. The insulating layer may include at least one inorganic layer and at least one organic layer. The circuit element may include a signal line, a driving circuit of a pixel PX, and / or the like. Details thereof will be further described below.

[0058] The display element layer DP-LED may include at least one organic light emitting diode.The display element layer DP-LED may further include an organic layer, such as a pixel defining layer.

[0059] The encapsulation layer TFE may include a plurality of thin films, a portion of which may be used to improve (eg, increase) optical efficiency, and a portion of which may be used to protect the organic light emitting diode.

[0060] refer to Figure 2B ,and Figure 1B and Figure 2A Differently, the display panel DP may not include the encapsulation layer TFE, but may include the encapsulation substrate ES. Figure 2BAs shown in , the display panel DP may include a base substrate BS, a circuit element layer DP-CL positioned on the base substrate BS, a display element layer DP-LED, an encapsulation substrate ES, and a sealant SM combining the base substrate BS and the encapsulation substrate ES. The encapsulation substrate ES may be separated from the display element layer DP-LED by a specific gap GP. The gap GP may be formed in a vacuum state. However, the present disclosure is not limited thereto, and the gap GP may be filled with air or an inert gas (hereinafter referred to as external gas). The base substrate BS and the encapsulation substrate ES may include a plastic substrate, a glass substrate, a metal substrate, or an organic / inorganic composite material substrate.

[0061] The base substrate BS may be combined with the encapsulation substrate ES by the sealant SM. For example, the sealant SM may be positioned along an edge defined by the encapsulation substrate ES in the first direction DR1 and the second direction DR2. In one or more embodiments, the edge refers to a portion of the encapsulation substrate ES that is adjacent to the display panel DP (eg, see FIG. Figure 3 ) of the non-display area NDA (see, for example, Figure 3 ) overlaps the periphery of the encapsulation substrate ES. Therefore, the sealant SM may overlap the display panel DP (eg, see Figure 3 ) of the non-display area NDA (see, for example, Figure 3 The sealant SM together with the encapsulation substrate ES can block the light emitting element ED (for example, see Figure 5 ) is exposed to external moisture and air. The sealant SM may include an organic binder or a melt.

[0062] Figure 3 illustrates a plan view of a display panel according to one or more embodiments of the present disclosure, Figure 3 The diagram illustrates a layout relationship on a plane between the wirings SGL and the pixels PX included in the display panel DP.

[0063] like Figure 3 As shown in , the display panel DP may include a display area DA and a non-display area NDA. The display area DA may be an area in which pixels PX are formed, which will be explained later. The non-display area NDA may include a first non-display area NDA1 surrounding at least a portion of the display area DA and a second non-display area NDA2 overlapping the pad area PA. In one or more embodiments, the first non-display area NDA1 may be defined along a boundary of the display area DA. The display area DA and the first non-display area NDA1 may define an active area AA. The second non-display area NDA2 may define the pad area PA.

[0064] The display panel DP may include a driving circuit GDC, a plurality of wirings SGL, a plurality of pads PD, and a plurality of pixels PX. The pixels PX may be positioned in the display area DA. Each of the plurality of pixels PX may include an organic light emitting diode and a pixel driving circuit connected thereto. The driving circuit GDC, the wirings SGL, and the pixel driving circuit may be included in the circuit element layer DP-CL, which will be explained later.

[0065] The driving circuit GDC may include a scan driving circuit. The scan driving circuit may generate a plurality of scan signals and may output the plurality of scan signals to a plurality of scan lines GL in sequence. The scan driving circuit may also output another control signal to the pixel driving circuit of the pixel PX.

[0066] The scan driving circuit may include a plurality of thin film transistors (hereinafter referred to as transistors) formed by a process identical or substantially identical to that of a pixel driving circuit of the pixel PX (eg, a low temperature polycrystalline silicon (LTPS) process or a low temperature polycrystalline oxide (LTPO) process).

[0067] The wiring SGL may include a scan line GL, a data line DL, a source line SL, and a control signal line CSL. Each of the plurality of scan lines GL may be connected to a respective corresponding pixel PX among a plurality of pixels PX, and each of the plurality of data lines DL may be connected to a respective corresponding pixel PX among a plurality of pixels PX. The control signal line CSL may provide a control signal to the scan driving circuit.

[0068] The wiring SGL may overlap the display area DA, the first non-display area NDA1, and the second non-display area NDA2. The pad PD may be connected to a corresponding wiring among the plurality of wirings SGL.

[0069] The line portion may constitute most of the wiring SGL and be connected to the pixel PX. The line portion may be connected to the transistor of the pixel PX. The line portion may have a single layer / multilayer structure, and the line portion may have a monomer (e.g., a single integral / monolithic body) or may include two or more portions. The two or more portions may be located at different layers and may be connected to each other by one or more contact holes penetrating an insulating layer located between the two or more portions.

[0070] Figure 4 An enlarged plan view of a portion of a display device according to one or more embodiments of the present disclosure is illustrated. Figure 4 In the display device DD according to one or more embodiments (for example, see Figure 1A ), a plane including the first pixel region PXA-R, the second pixel region PXA-B and the third pixel region PXA-G and the adjacent dam well region BWA is shown as an example. In one or more embodiments of the present disclosure, Figure 4The first pixel region PXA-R, the second pixel region PXA-B, and the third pixel region PXA-G shown in FIG. 1 may be repeatedly arranged in the entire display area DA (eg, see Figure 1A )middle.

[0071] The non-luminous region NPXA may be positioned around the first pixel region PXA-R, the second pixel region PXA-B, and the third pixel region PXA-G (e.g., may surround the first pixel region PXA-R, the second pixel region PXA-B, and the third pixel region PXA-G). The non-luminous region NPXA may determine the boundaries of the first pixel region PXA-R, the second pixel region PXA-B, and the third pixel region PXA-G. In the non-luminous region NPXA, a structure that prevents or substantially reduces color mixing among the first pixel region PXA-R, the second pixel region PXA-B, and the third pixel region PXA-G may be positioned, such as a pixel defining layer PDL (e.g., see Figure 5 ) or dam BMP (see, for example, Figure 5 ).

[0072] exist Figure 4 , the first pixel region PXA-R, the second pixel region PXA-B, and the third pixel region PXA-G having the same or substantially the same shape on a plane and having different areas on a plane are shown as examples, but are not limited thereto. At least two or more regions among the first pixel region PXA-R, the second pixel region PXA-B, and the third pixel region PXA-G may be the same or substantially the same. The areas of the first pixel region PXA-R, the second pixel region PXA-B, and the third pixel region PXA-G may be determined according to the color of the emitted light. The area of ​​the pixel region emitting red light among the primary color lights may be the largest, and the area of ​​the pixel region emitting blue light may be the smallest.

[0073] exist Figure 4 , the first pixel region PXA-R, the second pixel region PXA-B, and the third pixel region PXA-G are shown as having a square shape, but the present disclosure is not limited thereto. For example, the first pixel region PXA-R, the second pixel region PXA-B, and the third pixel region PXA-G may have different polygonal shapes (substantially including polygonal shapes) on a plane, such as a rhombus and a pentagon. In one or more embodiments, the first pixel region PXA-R, the second pixel region PXA-B, and the third pixel region PXA-G may have a rectangular shape (e.g., a substantially rectangular shape) with rounded corners on a plane.

[0074] exist Figure 4, as an example, the third pixel region PXA-G is positioned at the first row, and the first pixel region PXA-R and the second pixel region PXA-B are positioned at the second row. However, the present disclosure is not limited thereto, and the arrangement of the first pixel region PXA-R, the second pixel region PXA-B, and the third pixel region PXA-G may be changed in various ways. For example, the first pixel region PXA-R, the second pixel region PXA-B, and the third pixel region PXA-G may be arranged at the same row.

[0075] Any one of the first pixel region PXA-R, the second pixel region PXA-B, and the third pixel region PXA-G may provide a second light corresponding to the source light, another may provide a first light different from the second light, and the remaining one may provide a third light different from the first light and the second light. In one or more embodiments, the second pixel region PXA-B may provide a second light corresponding to the source light. In one or more embodiments, the first pixel region PXA-R may provide red light, the second pixel region PXA-B may provide blue light, and the third pixel region PXA-G may provide green light.

[0076] In the display area DA (see, for example, Figure 1A ), a dam well area BWA may be defined. The dam well area BWA may be a region in which a dam well is formed for preventing or reducing the Fig. 6A ) in the first light control pattern CCP-R, the second light control pattern CCP-B and the third light control pattern CCP-G (see Fig. 6A The dam well may be an area of ​​defects caused by mis-landing during the patterning process of the first light-controlling pattern CCP-R, the second light-controlling pattern CCP-B and the third light-controlling pattern CCP-G (see Fig. 6A ) during the patterning process of receiving the first light-controlling pattern CCP-R, the second light-controlling pattern CCP-B and the third light-controlling pattern CCP-G (see Fig. 6A ) of the forming material. By means of the dam well, the first light-controlling pattern CCP-R, the second light-controlling pattern CCP-B and the third light-controlling pattern CCP-G (see Fig. 6A ) forming material remains on the dam BMP. The dam well may be formed by removing a portion of the dam BMP. The dam well may have the first light-controlling pattern CCP-R, the second light-controlling pattern CCP-B, and the third light-controlling pattern CCP-G positioned therein (see Fig. 6A ) plane and the dam opening BW-OH (see Fig. 6A ) is separately defined. Figure 4In the embodiment of the present invention, as an example, two dam well areas BWA are defined to be adjacent to the third pixel area PXA-G. However, the present disclosure is not limited thereto, and the shape and arrangement of the dam well area BWA may be changed in any appropriate manner.

[0077] Figure 5 A cross-sectional view of a display device according to one or more embodiments of the present disclosure is illustrated. Fig. 6A An enlarged view of a portion of a cross section of a display device according to one or more embodiments of the present disclosure is illustrated. Figure 5 A cross-sectional view of a light emitting element ED included in a display panel DP according to one or more embodiments of the present disclosure is illustrated. Figure 5 The diagram shows the Figure 4 The cross-sectional view of the display device DD corresponds to the line II' cut in FIG. Fig. 6A shows that along with Figure 4 The cross-sectional view of the display device DD corresponds to the line II-II' cut in FIG.

[0078] refer to Figure 5 According to one or more embodiments, the display panel DP may include a base substrate BS, a circuit element layer DP-CL positioned on the base substrate BS, and a display element layer DP-LED positioned on the circuit element layer DP-CL. In the description, the base substrate BS, the circuit element layer DP-CL, and the display element layer DP-LED may be collectively referred to as a lower panel.

[0079] The base substrate BS may be a layer providing a base surface on which the elements included in the circuit element layer DP-CL are positioned. In one or more embodiments, the base substrate BS may be a glass substrate, a metal substrate, a polymer substrate, or the like. However, the present disclosure is not limited thereto, and the base substrate BS may be an inorganic layer, a functional layer, or a composite material layer.

[0080] The base substrate BS may have a multilayer structure. For example, the base substrate BS may have a three-layer structure of a polymer resin layer, an adhesive layer and a polymer resin layer. In particular, the polymer resin layer may include a polyimide-based resin. In addition, the polymer resin layer may include at least one of an acrylic-based resin, a methacrylic-based resin, a polyisoprene-based resin, a vinyl resin, an epoxy-based resin, a urethane-based resin, a cellulose-based resin, a siloxane-based resin, a polyamide-based resin and a perylene-based resin. In the description, a "*-based" resin refers to a resin containing a functional group of "*".

[0081] The circuit element layer DP-CL may be positioned on the base substrate BS. The circuit element layer DP-CL may include a transistor TD as a circuit element. Figure 3 ) of the pixel driving circuit, the configuration of the circuit element layer DP-CL can be changed, and Figure 5 , one transistor TD is shown as an example. The layout relationship of the active region AD, source region SD, drain region DD, and gate region GD constituting the transistor TD is shown as an example. The active region AD, source region SD, and drain region DD may be regions divided according to the doping concentration or conductivity of the semiconductor pattern.

[0082] The circuit element layer DP-CL may include a lower buffer layer BRL positioned on the base substrate BS, a first insulating layer 10, a second insulating layer 20, and a third insulating layer 30. For example, the lower buffer layer BRL, the first insulating layer 10, and the second insulating layer 20 may be inorganic layers, and the third insulating layer 30 may be an organic layer.

[0083] The display element layer DP-LED may include a light emitting element ED as a display element. The light emitting element ED may generate the above-mentioned source light. The light emitting element ED may include a first electrode EL1, a second electrode EL2, and an emission layer EML positioned between the first electrode EL1 and the second electrode EL2. In one or more embodiments, the display element layer DP-LED may include an organic light emitting diode as the light emitting element ED. In one or more embodiments of the present disclosure, the light emitting element ED may include a quantum dot light emitting diode. For example, the emission layer EML included in the light emitting element ED may include an organic light emitting material as a light emitting material, or the emission layer EML may include one or more quantum dots as a light emitting material. In addition, in one or more embodiments, the display element layer DP-LED may include an ultra-small light emitting element to be explained later as the light emitting element ED. For example, the ultra-small light emitting element may include a micro LED element and / or a nano LED element. The ultra-small light emitting element may have a micrometer or nanometer size, and may be a light emitting element ED including an active layer positioned among a plurality of semiconductor layers.

[0084] The first electrode EL1 may be positioned on the third insulating layer 30. The first electrode EL1 may be an anode or a cathode. In addition, the first electrode EL1 may be a pixel electrode. The first electrode EL1 may be a transmissive electrode, a transflective electrode, or a reflective electrode. The first electrode EL1 may be directly or indirectly connected to the transistor TD.

[0085] The display element layer DP-LED may include a pixel defining layer PDL. For example, the pixel defining layer PDL may be an organic layer. At the pixel defining layer PDL, a pixel opening OH may be defined. The pixel opening OH of the pixel defining layer PDL may expose at least a portion of the first electrode EL1. In the present embodiment, the first light emitting area EA1 may be defined by the pixel opening OH.

[0086] On the first electrode EL1, an intermediate layer may be positioned. The intermediate layer may be positioned between the first electrode EL1 and the second electrode EL2. The intermediate layer may include at least one of a hole transport region HTR, an emission layer EML, and an electron transport region ETR. For example, Figure 5 As shown in , the intermediate layer may include a hole transport region HTR, an emission layer EML, and an electron transport region ETR. The hole transport region HTR, the emission layer EML, and the electron transport region ETR may be stacked in sequence in the third direction DR3 as the thickness direction. For example, the intermediate layer may include a hole transport region HTR positioned on the first electrode EL1, an emission layer EML positioned on the hole transport region HTR, and an electron transport region ETR positioned on the emission layer EML.

[0087] The hole transport region HTR, the emission layer EML, and the electron transport region ETR included in the intermediate layer may overlap at least the first pixel region PXA-R. At least one of the hole transport region HTR, the emission layer EML, and the electron transport region ETR may be detachably formed in the first pixel region PXA-R, the second pixel region PXA-B, and the third pixel region PXA-G (see Fig. 6A ). For example, Figure 5 As shown in FIG. 1 , each of the hole transport region HTR, the emission layer EML, and the electron transport region ETR may be patterned in the pixel opening portion OH and separately formed in the first pixel region PXA-R, the second pixel region PXA-B, and the third pixel region PXA-G (see FIG. 1 ). Fig. 6A ). In one or more embodiments, at least one of the hole transport region HTR, the emission layer EML, and the electron transport region ETR may be patterned and provided by an inkjet printing method. However, the present disclosure is not limited thereto, and each of the hole transport region HTR, the emission layer EML, and the electron transport region ETR may be commonly arranged in the first pixel region PXA-R, the second pixel region PXA-B, and the third pixel region PXA-G (for example, see Fig. 6A ) (i.e., located or positioned in the first pixel region PXA-R, the second pixel region PXA-B, and the third pixel region PXA-G). Fig. 6A ) Each of the overlapped hole transport region HTR, emission layer EML, and electron transport region ETR may have a single body (eg, a single integral / monolithic body).

[0088] The hole transport region HTR may include at least one of a hole injection layer, a hole transport layer, and an electron blocking layer.

[0089] The emission layer EML may generate a second light as a source light. The emission layer EML may generate blue light. The blue light may include light having a wavelength of about 410 nm to about 480 nm. The emission spectrum of the blue light may have a maximum peak in a wavelength region of about 440 nm to about 460 nm.

[0090] The electron transport region ETR may include at least one of an electron injection layer, an electron transport layer, and a hole blocking layer.

[0091] The second electrode EL2 may be positioned on the intermediate layer. Figure 5 As shown in , the second electrode EL2 may be positioned on the electron transport region ETR. The second electrode EL2 may be a cathode or an anode, but the present disclosure is not limited thereto. For example, if the first electrode EL1 is an anode, the second electrode EL2 may be a cathode, and if the first electrode EL1 is a cathode, the second electrode EL2 may be an anode. The second electrode EL2 may be a transmissive electrode, a transflective electrode, or a reflective electrode.

[0092] In one or more embodiments, the second electrode EL2 may be commonly positioned in the first pixel region PXA-R, the second pixel region PXA-B, and the third pixel region PXA-G (eg, see Fig. 6A The second electrode EL2 may be connected to the first pixel region PXA-R, the second pixel region PXA-B, and the third pixel region PXA-G (for example, see Fig. 6A ) and the adjacent non-light emitting region NPXA. The second electrode EL2 overlapping the first pixel region PXA-R, the second pixel region PXA-B, and the third pixel region PXA-G may have a single body (eg, a single integral / monolithic body).

[0093] The display element layer DP-LED may further include an optical layer OPL. The optical layer OPL may be positioned on the light emitting element ED. The optical layer OPL may be positioned on the second electrode EL2. The optical layer OPL may be positioned directly on the second electrode EL2. The optical layer OPL may be a layer for preventing or reducing reflection of external light by the second electrode EL2 of the light emitting element ED. The optical layer OPL may include a plurality of layers or a single layer. In one or more embodiments, the optical layer OPL may be an organic layer or an inorganic layer. In one or more embodiments, the optical layer OPL may have a refractive index of about 1.6 or greater. The refractive index of the optical layer OPL relative to light in a wavelength region of about 550 nm to 660 nm may be about 1.6 or greater.

[0094] In one or more embodiments, the optical layer OPL may be commonly positioned in the first pixel area PXA-R, the second pixel area PXA-B, and the third pixel area PXA-G (eg, see Fig. 6AThe optical layer OPL may be connected to the first pixel region PXA-R, the second pixel region PXA-B, and the third pixel region PXA-G (for example, see Fig. 6A ) and the adjacent non-light emitting area NPXA. Overlapping with the first pixel area PXA-R, the second pixel area PXA-B and the third pixel area PXA-G (for example, see Fig. 6A )The overlapping optical layers OPL may have a single body (eg, a single integral / monolithic body).

[0095] The display panel DP may include an encapsulation layer TFE protecting the second electrode EL2. The encapsulation layer TFE may be positioned on the pixel defining layer PDL to cover the light emitting element ED. The encapsulation layer TFE may be positioned on the second electrode EL2 while filling a portion of the pixel opening OH. Figure 5 As shown in , if the display element layer DP-LED includes an optical layer OPL, the encapsulation layer TFE may be positioned on the optical layer OPL. The encapsulation layer TFE may protect the light emitting element ED from moisture and / or oxygen and from foreign matter such as dust particles.

[0096] The encapsulation layer TFE may include an organic material or an inorganic material. The encapsulation layer TFE may have a multilayer structure in which an inorganic layer and an organic layer are repeated. In one or more embodiments, the encapsulation layer TFE may include a first inorganic layer IOL1, an organic layer OL and / or a second inorganic layer IOL2. The first inorganic layer IOL1 and the second inorganic layer IOL2 may protect the light emitting element ED from external moisture, and the organic layer OL may prevent poor embossing defects of the light emitting element ED caused by foreign matter injected during the manufacturing process. The display panel DP may also include a refractive index control layer on the encapsulation layer TFE for improving (e.g., increasing) luminous efficiency.

[0097] For example, the inorganic layer included in the encapsulation layer TFE may include a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer, and the present disclosure is not limited thereto. The organic layer included in the encapsulation layer TFE may include an acrylate-based organic film, but the present disclosure is not limited thereto.

[0098] like Figure 5 As shown in , the optical structure layer OSL may be positioned on the encapsulation layer TFE. The optical structure layer OSL may include a light control layer CCL, a low refractive layer LR, a color filter layer CFL, and a base layer BL. The optical structure layer OSL may be referred to as an upper panel.

[0099] The light-controlling layer CCL may be positioned on the display element layer DP-LED including the light-emitting element ED. The light-controlling layer CCL may include a dam BMP, a first light-controlling pattern CCP-R, a second light-controlling pattern CCP-B, and a blocking layer CAP1.

[0100] The dam BMP may include a base resin and additives. The base resin may be composed of a variety of resin compositions that may be generally referred to as binders. The additives may include coupling agents and / or photoinitiators. The additives may also include dispersants.

[0101] The dam BMP may include a black colorant for blocking light. The dam BMP may include a black dye or a black pigment mixed with a base resin. In one or more embodiments, the black colorant may include carbon black, or a metal such as chromium or an oxide thereof.

[0102] The dam BMP may include a dam opening portion BW-OH corresponding to the pixel opening portion OH. In a plane, the dam opening portion BW-OH may overlap with the pixel opening portion OH and have an area larger than that of the pixel opening portion OH. For example, the dam opening portion BW-OH may have an area larger than that of the first light emitting area EA1 defined by the pixel opening portion OH. The term "corresponding" refers to the idea that two elements overlap when viewed from the thickness direction of the display panel DP (i.e., the third direction DR3), and is not limited to the same area.

[0103] In the dam opening BW-OH, the first light-controlling pattern CCP-R and the second light-controlling pattern CCP-B may be positioned. At least a portion of the first light-controlling pattern CCP-R and the second light-controlling pattern CCP-B may change the optical properties of the source light. In one or more embodiments, the first light-controlling pattern CCP-R may change the optical properties of the source light.

[0104] The first light-controlling pattern CCP-R may include one or more quantum dots for changing the optical properties of the source light. The first light-controlling pattern CCP-R may include one or more quantum dots for converting the source light into light having a different wavelength. In the first light-controlling pattern CCP-R overlapping the first pixel area PXA-R, the quantum dots may convert the blue light as the source light into red light.

[0105] "Quantum dot" refers to a crystal of a semiconductor compound. Quantum dots can emit light of various wavelengths depending on the size of the quantum dot crystal. Quantum dots can emit light of various wavelengths by controlling the ratio of elements in the quantum dot compound.

[0106] The diameter of the quantum dot may be, for example, about 1 nm to about 10 nm.

[0107] Quantum dots can be synthesized by chemical bath deposition, metal organic chemical vapor deposition, molecular beam epitaxy or similar processes.

[0108] Chemical bath deposition is a method of growing quantum dot particle crystals after mixing an organic solvent and a precursor material. During the growth of the crystal, the organic solvent naturally acts as a dispersant coordinated at the surface of the quantum dot crystal, and the growth of the crystal can be controlled. Therefore, chemical bath deposition can be more advantageous than vapor deposition methods such as metal organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE), and the growth of quantum dot particles can be controlled by a low-cost (e.g., lower-cost) process.

[0109] The core of the quantum dot may be selected from a group consisting of a II-VI compound, a III-V compound, a III-VI compound, a I-III-VI compound, a IV-VI compound, a Group IV element, a Group IV compound, and combinations thereof.

[0110] The II-VI compounds may be selected from binary compounds such as CdSe, CdTe, CdS, ZnS, ZnSe, ZnTe, ZnO, HgS, HgSe, HgTe, MgSe, MgS and mixtures thereof, binary compounds such as CdSeS, CdSeTe, CdSTe, ZnSeS, ZnSeTe, ZnSTe, HgSeS, HgSeTe, HgSTe, CdZnS, CdZnSe, CdZnTe, CdH The group consisting of ternary compounds such as HgZnTeS, CdZnSeS, CdZnSeTe, CdZnSTe, CdHgSeS, CdHgSeTe, CdHgSTe, HgZnSeS, HgZnSeTe, HgZnSTe and mixtures thereof. The II-VI semiconductor compounds may also include Group I metals and / or Group IV elements. The I-II-V compounds may be selected from CuSnS and / or CuZnS, and the II-IV-VI compounds may be selected from ZnSnS and / or the like. The I-II-IV-VI compounds may be selected from CuSnS and / or CuZnS. 2 ZnSnS 2 , Cu 2 ZnSnS 4 , Cu 2 ZnSnSe 4 、Ag 2 ZnSnS 2 and mixtures thereof constitute a group of selected quaternary compounds.

[0111] The III-VI compounds may include compounds such as In 2 S 3 or In 2 Se 3Binary compounds such as InGaS 3 or InGaSe 3 or any combination thereof.

[0112] The I-III-VI group compound can be selected from AgInS, AgInS 2 、CuInS、CuInS 2 、AgGaS 2 、CuGaS 2 、CuGaO 2 、AgGaO 2 、AgAlO 2 and their mixtures or ternary compounds such as AgInGaS 2 and CuInGaS 2 of quaternary compounds.

[0113] The III-V compound may be selected from the group consisting of binary compounds such as GaN, GaP, GaAs, GaSb, AlN, AlP, AlAs, AlSb, InN, InP, InAs, InSb and mixtures thereof, ternary compounds such as GaNP, GaNAs, GaNSb, GaPAs, GaPSb, AlNP, AlNAs, AlNSb, AlPAs, AlPSb, InGaP, InAlP, InNP, InNAs, InNSb, InPAs, InPSb and mixtures thereof, and quaternary compounds such as GaAlNP, GaAlNAs, GaAlNSb, GaAlPAs, GaAlPSb, GaInNP, GaInNAs, GaInNSb, GaInPAs, GaInPSb, InAlNP, InAlNAs, InAlNSb, InAlPAs, InAlPSb and mixtures thereof. The III-V compound may also include a Group II metal. For example, InZnP and / or the like may be selected as the III-II-V compound.

[0114] The IV-VI group compounds may be selected from the group consisting of binary compounds such as SnS, SnSe, SnTe, PbS, PbSe, PbTe and mixtures thereof, ternary compounds such as SnSeS, SnSeTe, SnSTe, PbSeS, PbSeTe, PbSTe, SnPbS, SnPbSe, SnPbTe and mixtures thereof, and quaternary compounds such as SnPbSSe, SnPbSeTe, SnPbSTe and mixtures thereof.

[0115] The II-IV-V semiconductor compound may be selected from ZnSnP, ZnSnP 2、ZnSnAs 2 、ZnGeP 2 、ZnGeAs 2 、CdSnP 2 、CdGeP 2 and their mixtures constitute a group of ternary compounds.

[0116] The Group IV element may be selected from the group consisting of Si, Ge, and mixtures thereof. The Group IV compound may be a binary compound selected from the group consisting of SiC, SiGe, and mixtures thereof.

[0117] Each element contained in a multi-element compound such as a binary compound, a ternary compound, and a quaternary compound may be present in a particle at a uniform concentration or a non-uniform concentration. The chemical formula refers to the type of element contained in the compound, and the ratio of elements in the compound may be different. For example, AgInGaS may mean AgIn x Ga 1-x S 2 (x is a real number from 0 to 1).

[0118] For example, a binary compound, a ternary compound, or a quaternary compound may be present in a particle at a uniform concentration, or may be present in the same particle at partially different concentration distributions. In addition, quantum dots may have a core / shell structure in which one quantum dot surrounds another quantum dot. The core / shell structure may have a concentration gradient in which the concentration of the element present in the shell decreases toward the core.

[0119] In one or more embodiments, the quantum dot may have a core-shell structure including a core containing the above-mentioned nanocrystals and a shell surrounding the core. The shell of the quantum dot may be a protective layer for preventing or reducing chemical deformation of the core to maintain semiconductor properties. The shell of the quantum dot may be a charging layer for imparting electrophoretic properties to the quantum dot. The shell may be a single layer or multiple layers. The shell of the quantum dot may include a metal or non-metal oxide, a semiconductor compound, or a combination thereof.

[0120] For example, metal or non-metal oxides may include SiO 2 、Al 2 O 3 、TiO 2 、ZnO、MnO、Mn 2 O 3 , Mn 3 O 4 , CuO, FeO, Fe 2 O 3 , Fe 3 O 4 , CoO, Co 3 O 4 and / or binary compounds of NiO or such as MgAl2 O 4 、CoFe 2 O 4 、NiFe 2 O 4 and / or CoMn 2 O 4 However, the present disclosure is not limited thereto.

[0121] In addition, the semiconductor compound may include CdS, CdSe, CdTe, ZnS, ZnSe, ZnTe, ZnSeS, ZnTeS, GaAs, GaP, GaS, GaSe, AgGaS, AgGaS 2 , GaSb, HgS, HgSe, HgTe, InAs, InP, InGaP, InSb, AlAs, AlP, AlSb, etc. However, the present disclosure is not limited thereto.

[0122] The quantum dots may have a full width at half maximum (FWHM) of an emission wavelength spectrum of about 45 nm or less, about 40 nm or less, or about 30 nm or less. Within these ranges, color purity or color reproducibility may be improved (e.g., increased). Light emitted from the quantum dots is emitted in all directions, thus expanding the light viewing angle.

[0123] In addition, the shape of the quantum dot can be a shape commonly used in the art without being specifically limited. For example, the shape of the quantum dot can be a spherical, pyramidal, multi-armed or cubic nanoparticle, nanotube, nanowire, nanofiber, nanoplate particle, etc.

[0124] By controlling the size of one or more quantum dots and / or controlling the ratio of elements in the quantum dot compound, light of various wavelength bands can be obtained from the quantum dot emission layer. Therefore, by using quantum dots with different sizes or by changing the ratio of elements in the quantum dot compound, the light emitting element ED can emit light of different wavelengths. For example, by controlling the size of the quantum dots and / or by changing the ratio of elements in the quantum dots, the quantum dot compound can be designed to emit red light, green light and / or blue light. For example, quantum dots can be used to emit white light by a combination of various appropriate colors of light.

[0125] In one or more embodiments, the quantum dots included in the first light control pattern CCP-R overlapping the first pixel region PXA-R may have a red light color. If the particle size of the quantum dots is reduced, light in the short wavelength region may be emitted. For example, for quantum dots having the same core, the particle size of quantum dots emitting green light may be smaller than the particle size of quantum dots emitting red light. For example, for quantum dots having the same core, the particle size of quantum dots emitting blue light may be smaller than the particle size of quantum dots emitting green light. However, the present disclosure is not limited thereto, and for quantum dots having the same core, the particle size may be controlled according to the material forming the shell and the thickness of the shell.

[0126] If the quantum dots have various appropriate colors of light (such as blue, red, and green), then quantum dots with different emission colors can have different core materials.

[0127] The first light-controlling pattern CCP-R may further include a scatterer. The first light-controlling pattern CCP-R may include one or more quantum dots for converting blue light into red light and a scatterer that scatters the light.

[0128] The scatterer may include inorganic particles. For example, the scatterer may include TiO 2 、ZnO、Al 2 O 3 、SiO 2 and hollow silicon dioxide. The scatterer may include TiO 2 、ZnO、Al 2 O 3 、SiO 2 and hollow silica, or may be a TiO 2 、ZnO、Al 2 O 3 、SiO 2 and a mixture of two or more materials selected from hollow silica.

[0129] The first light control pattern CCP-R may include a base resin in which quantum dots and scatterers are dispersed. The base resin is a medium in which quantum dots and scatterers are dispersed. The base resin may be composed of various suitable resin compositions that may be referred to as universal binders. For example, the base resin may be an acrylate-based resin, a urethane-based resin, a silicon-based resin, an epoxy-based resin, etc. The base resin may be a transparent resin.

[0130] In one or more embodiments, the first light-controlling pattern CCP-R may be formed by an inkjet process. The liquid composition may be applied to the dam opening BW-OH. The volume of the composition polymerized by a thermal curing process or a photocuring process may be reduced after curing.

[0131] A step may be formed between the bottom of the dam BMP and the bottom of the first light-controlling pattern CCP-R. For example, the bottom of the dam BMP may be defined to be lower than the bottom of the first light-controlling pattern CCP-R. The height difference between the bottom of the dam BMP and the bottom of the first light-controlling pattern CCP-R may be, for example, about 2 μm to about 3 μm.

[0132] The light control layer CCL may include a barrier layer CAP1 positioned on one surface of the first light control pattern CCP-R. The barrier layer CAP1 may prevent or reduce the penetration of moisture and / or oxygen (hereinafter referred to as "moisture / oxygen"). The barrier layer CAP1 may control the refractive index of the optical structure layer OSL. The barrier layer CAP1 may be positioned on one surface of the top or one surface of the bottom of the first light control pattern CCP-R to block or reduce the first light control pattern CCP-R from being exposed to moisture / oxygen. For example, the barrier layer CAP1 may block or reduce the quantum dots included in the first light control pattern CCP-R from being exposed to moisture / oxygen. The barrier layer CAP1 may protect the first light control pattern CCP-R from external impact.

[0133] In one or more embodiments, the barrier layer CAP1 may be separated from the display element layer DP-LED with the first light control pattern CCP-R therebetween. For example, the barrier layer CAP1 may be positioned on top of the first light control pattern CCP-R. In one or more embodiments, the light control layer CCL may include an additional barrier layer CAP2 positioned between the first light control pattern CCP-R and the display element layer DP-LED. The barrier layer CAP1 may cover the top of the first light control pattern CCP-R adjacent to the low-refractive layer LR. The additional barrier layer CAP2 may cover the bottom of the first light control pattern CCP-R adjacent to the display element layer DP-LED. The "top" may be a surface positioned on the upper portion relative to the third direction DR3, and the "bottom" may be a surface positioned on the lower portion relative to the third direction DR3.

[0134] In addition, the barrier layer CAP1 and the additional barrier layer CAP2 may cover one surface of the dam BMP and cover the first light-controlling pattern CCP-R.

[0135] The barrier layer CAP1 may cover one surface of the dam BMP and the first light-controlling pattern CCP-R adjacent to the low-refractive layer LR. The barrier layer CAP1 may be positioned directly below the low-refractive layer LR. The additional barrier layer CAP2 may be positioned under the step of the dam BMP and the first light-controlling pattern CCP-R. The additional barrier layer CAP2 may be positioned directly on the filling layer FML.

[0136] The barrier layer CAP1 and the additional barrier layer CAP2 may include an inorganic material. In the display panel DP according to one or more embodiments, the barrier layer CAP1 may include silicon oxynitride SiON. Both the barrier layer CAP1 and the additional barrier layer CAP2 may include silicon oxynitride. However, the present disclosure is not limited thereto. For example, the barrier layer CAP1 positioned on the first light-controlling pattern CCP-R may include silicon oxynitride, and the additional barrier layer CAP2 positioned below the first light-controlling pattern CCP-R may include silicon oxide (SiO x ). However, the present disclosure is not limited thereto.

[0137] The color filter layer CFL may be positioned on the light control layer CCL. The color filter layer CFL may include at least one color filter. The color filter may transmit (e.g., pass) light of a wavelength region and block light not in the wavelength region. The first color filter CF1 of the first pixel region PXA-R may transmit (e.g., pass) red light and may block green light and blue light.

[0138] The first color filter CF1 may include a base resin and a dye and / or pigment dispersed in the base resin. The base resin may be a medium for dispersing the dye and / or pigment. The base resin may be composed of various suitable resin compositions that may be generally referred to as a binder.

[0139] The first color filter CF1 may have a uniform thickness in the first pixel region PXA-R. Light converted from source light of blue light to red light by the first light-controlling pattern CCP-R may be provided to the outside with uniform brightness in the first pixel region PXA-R.

[0140] The optical structure layer OSL may include a low refractive layer LR. The low refractive layer LR may be positioned between the light control layer CCL and the color filter layer CFL. The low refractive layer LR may be positioned on the light control layer CCL and may block or reduce the exposure of the first light control pattern CCP-R to moisture / oxygen. The low refractive layer LR may be positioned between the first light control pattern CCP-R and the first color filter CF1, and the low refractive layer LR may be an optical functional layer that improves (e.g., increases) light extraction efficiency or prevents or substantially reduces reflected light from being incident on the light control layer CCL. The low refractive layer LR may be a layer having a low refractive index compared to adjacent layers.

[0141] The low refractive layer LR may include at least one inorganic layer. For example, the low refractive layer LR may be formed by including silicon nitride, aluminum nitride, zirconium nitride, titanium nitride, hafnium nitride, tantalum nitride, silicon oxide, aluminum oxide, titanium oxide, tin oxide, cerium oxide, silicon oxynitride or a metal film that ensures light transmittance. However, the present disclosure is not limited thereto, and the low refractive layer LR may include an organic layer. For example, the low refractive layer LR may have a structure in which a plurality of hollow particles are dispersed in an organic polymer resin. The low refractive layer LR may be composed of a single layer or a plurality of layers.

[0142] In one or more embodiments, the display panel DP may further include a base layer BL positioned on the color filter layer CFL. The base layer BL may be a member providing a base surface on which the color filter layer CFL, the low refractive layer LR, and the light control layer CCL are positioned. The base layer BL may be a glass substrate, a metal substrate, a plastic substrate, etc. However, the present disclosure is not limited thereto, and the base layer BL may be an inorganic layer, an organic layer, or a composite material layer. In one or more embodiments, the base layer BL may be omitted.

[0143] The anti-reflection layer may be positioned on the base layer BL. The anti-reflection layer may be a layer that reduces reflection of external light incident from the outside. The anti-reflection layer may be a layer that selectively passes light emitted from the display panel DP. In one or more embodiments, the anti-reflection layer may be a single layer including a dye and / or a pigment dispersed in a base resin. The anti-reflection layer may be provided to be aligned with the first pixel region PXA-R, the second pixel region PXA-B, and the third pixel region PXA-G (see Figure 4 ) of all completely overlapping consecutive layers.

[0144] The polarizing layer may be omitted from the anti-reflection layer. Therefore, the light passing through the anti-reflection layer and incident on the display element layer DP-LED may be non-polarized light. The display element layer DP-LED may receive non-polarized light from the upper portion of the anti-reflection layer.

[0145] The display panel DP may include a lower panel including a display element layer DP-LED and an upper panel (optical structure layer OSL) including a light control layer CCL and a color filter layer CFL. In one or more embodiments, the filling layer FML may be positioned between the lower panel and the upper panel (optical structure layer OSL). In one or more embodiments, the filling layer FML may fill the space between the display element layer DP-LED and the light control layer CCL. The filling layer FML may be positioned directly on the encapsulation layer TFE, and the additional barrier layer CAP2 may be positioned directly on the filling layer FML. The bottom of the filling layer FML may be in contact with the top of the encapsulation layer TFE, and the top of the filling layer FML may be in contact with the bottom of the additional barrier layer CAP2.

[0146] The filling layer FML may be a buffer between the display element layer DP-LED and the light control layer CCL. In one or more embodiments, the filling layer FML may play a role in absorbing impact and increasing the strength of the display panel DP. The filling layer FML may be formed of a filling resin including a polymer resin. For example, the filling layer FML may be formed of a filling layer resin including an acrylate-based resin or an epoxy resin.

[0147] The filling layer FML may be a separate element from the encapsulation layer TFE positioned thereunder and the additional barrier layer CAP2 positioned thereover and may be formed by separate process steps.The filling layer FML may be formed using a different material than the encapsulation layer TFE and the additional barrier layer CAP2.

[0148] refer to Fig. 6A , the display panel DP may include a base substrate BS and a circuit element layer DP-CL positioned on the base substrate BS. The circuit element layer DP-CL may be positioned on the base substrate BS. The circuit element layer DP-CL may include an insulating layer, a semiconductor pattern, a conductive pattern, and a signal line. The circuit element layer DP-CL may be obtained by forming an insulating layer, a semiconductor layer, and a conductive layer on the base substrate BS by a method such as coating and deposition, and then selectively patterning the insulating layer, the semiconductor layer, and the conductive layer by a plurality of photolithography processes. Then, a semiconductor pattern, a conductive pattern, and a signal line included in the circuit element layer DP-CL may be formed. In one or more embodiments, the circuit element layer DP-CL may include a transistor, a buffer layer, and a plurality of insulating layers.

[0149] The display element layer DP-LED may be positioned on the circuit element layer DP-CL. The display element layer DP-LED may include a pixel defining layer PDL and a light emitting element ED.

[0150] The light emitting element ED may include a first light emitting element ED1, a second light emitting element ED2, and a third light emitting element ED3. Each of the first light emitting element ED1, the second light emitting element ED2, and the third light emitting element ED3 may include a first electrode EL1, an intermediate layer, and a second electrode EL2 sequentially stacked in a third direction DR3. The intermediate layer may include at least one of a hole transport region HTR, an emission layer EML, and an electron transport region ETR. The first light emitting element ED1 may include a first emission layer EML1 overlapping the first pixel region PXA-R. The second light emitting element ED2 may include a second emission layer EML2 overlapping the third pixel region PXA-G. The third light emitting element ED3 may include a third emission layer EML3 overlapping the second pixel region PXA-B. The emission layer EML may include a first emission layer EML1, a second emission layer EML2, and a third emission layer EML3. The first electrode EL1 may include a first sub-electrode EL1-1, a second sub-electrode EL1-2, and a third sub-electrode EL1-3. The hole transport region HTR may include a first hole transport region HTR1, a second hole transport region HTR2, and a third hole transport region HTR3. The electron transport region ETR may include a first electron transport region ETR1, a second electron transport region ETR2, and a third electron transport region ETR3.

[0151] The pixel defining layer PDL may be positioned on the circuit element layer DP-CL. A preset pixel opening OH may be defined at the pixel defining layer PDL (see Figure 5 The pixel opening OH defined in the pixel defining layer PDL (see Figure 5 ) may correspond to the first pixel region PXA-R, the second pixel region PXA-B, and the third pixel region PXA-G, respectively. The non-light emitting region NPXA may be a region corresponding to the pixel defining layer PDL and adjacent to the first pixel region PXA-R, the second pixel region PXA-B, and the third pixel region PXA-G.

[0152] The pixel defining layer PDL may include an organic resin and an inorganic material. For example, the pixel defining layer PDL may include a polyacrylate-based resin, a polyimide-based resin, a silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO x N y ) etc. to form.

[0153] like Figure 6B As shown in , the first hole transport region HTR1, the second hole transport region HTR2, and the third hole transport region HTR3 of the first light-emitting element ED1, the second light-emitting element ED2, and the third light-emitting element ED3, the first emission layer EML1, the second emission layer EML2, and the third emission layer EML3, and the first electron transport region ETR1, the second electron transport region ETR2, and the third electron transport region ETR3 may be patterned and provided in the pixel opening portion OH defined in the pixel defining layer PDL. In one or more embodiments, at least one of the first hole transport region HTR1, the second hole transport region HTR2, and the third hole transport region HTR3 of the first light-emitting element ED1, the second light-emitting element ED2, and the third light-emitting element ED3, the first emission layer EML1, the second emission layer EML2, and the third emission layer EML3, and the first electron transport region ETR1, the second electron transport region ETR2, and the third electron transport region ETR3 may be patterned and provided by an inkjet printing method. However, the present disclosure is not limited thereto, and at least one of the first hole transport region HTR1, the second hole transport region HTR2, and the third hole transport region HTR3, the first emission layer EML1, the second emission layer EML2, and the third emission layer EML3 of the first light-emitting element ED1, the second light-emitting element ED2, and the third light-emitting element ED3, and the first electron transport region ETR1, the second electron transport region ETR2, and the third electron transport region ETR3 may be provided as a common layer in the entire first pixel region PXA-R, the second pixel region PXA-B, and the third pixel region PXA-G.

[0154] The pixel defining layer PDL may be positioned on the circuit element layer DP-CL and may cover a portion of the first electrode EL1. In the pixel defining layer PDL, a pixel opening portion OH may be defined. The pixel opening portion OH of the pixel defining layer PDL may expose at least a portion of the first electrode EL1. In one or more embodiments, the first light emitting area EA1, the second light emitting area EA2, and the third light emitting area EA3 are defined corresponding to a portion of the area of ​​the first electrode EL1 exposed by the pixel opening portion OH.

[0155] The display element layer DP-LED may include a first light emitting area EA1, a second light emitting area EA2, and a third light emitting area EA3. The first light emitting area EA1, the second light emitting area EA2, and the third light emitting area EA3 may be areas divided by a pixel defining layer PDL. The first light emitting area EA1, the second light emitting area EA2, and the third light emitting area EA3 may correspond to the first pixel area PXA-R, the third pixel area PXA-G, and the second pixel area PXA-B, respectively.

[0156] The first light emitting area EA1, the second light emitting area EA2, and the third light emitting area EA3 may overlap with the first pixel area PXA-R, the third pixel area PXA-G, and the second pixel area PXA-B, respectively, and may not overlap with the dam well area BWA. When viewed from a plane, the areas of the first pixel area PXA-R, the third pixel area PXA-G, and the second pixel area PXA-B divided by the dam BMP may be larger than the areas of the first light emitting area EA1, the second light emitting area EA2, and the third light emitting area EA3 divided by the pixel defining layer PDL.

[0157] In the light emitting element ED, the first electrode EL1 may be positioned on the circuit element layer DP-CL. The first electrode EL1 may be an anode or a cathode. In addition, the first electrode EL1 may be a pixel electrode. The first electrode EL1 may be a transmissive electrode, a transflective electrode, or a reflective electrode.

[0158] The first hole transport region HTR1, the second hole transport region HTR2, and the third hole transport region HTR3 may be positioned between the first sub-electrode EL1-1, the second sub-electrode EL1-2, and the third sub-electrode EL1-3 and the first emission layer EML1, the second emission layer EML2, and the third emission layer EML3, respectively. The hole transport region HTR may include at least one of a hole injection layer, a hole transport layer, and an electron blocking layer. The first hole transport region HTR1, the second hole transport region HTR2, and the third hole transport region HTR3 may be patterned and provided to be separately positioned corresponding to the first light emitting region EA1, the second light emitting region EA2, and the third light emitting region EA3, respectively. However, the present disclosure is not limited thereto, and the hole transport region HTR may be positioned as a common layer to overlap with the first light emitting region EA1, the second light emitting region EA2, and the third light emitting region EA3 and the pixel defining layer PDL that divides the first light emitting region EA1, the second light emitting region EA2, and the third light emitting region EA3.

[0159] The first emission layer EML1, the second emission layer EML2, and the third emission layer EML3 may be positioned on the first hole transport region HTR1, the second hole transport region HTR2, and the third hole transport region HTR3, respectively. In one or more embodiments, the first emission layer EML1, the second emission layer EML2, and the third emission layer EML3 may be patterned and provided to be separately positioned corresponding to the first light emitting area EA1, the second light emitting area EA2, and the third light emitting area EA3, respectively. In one or more embodiments, each of the first emission layer EML1, the second emission layer EML2, and the third emission layer EML3 may be positioned in the pixel opening portion OH. For example, the first emission layer EML1, the second emission layer EML2, and the third emission layer EML3 may be separately formed to correspond to the first light emitting area EA1, the second light emitting area EA2, and the third light emitting area EA3 divided by the pixel defining layer PDL. All of the first, second, and third emission layers EML1, EML2, and EML3 separately formed to correspond to the first, second, and third light emitting regions EA1, EA2, and EA3 may emit blue light or light in different wavelength regions.

[0160] However, the present disclosure is not limited thereto, and the first emission layer EML1, the second emission layer EML2, and the third emission layer EML3 may be provided as a common layer overlapping the entire pixel defining layer PDL that divides the first light emitting area EA1, the second light emitting area EA2, and the third light emitting area EA3. In one or more embodiments, the emission layer provided as a common layer in the first light emitting area EA1, the second light emitting area EA2, and the third light emitting area EA3 may emit blue light.

[0161] The first emission layer EML1, the second emission layer EML2, and the third emission layer EML3 may have a single layer formed using a single material, a single layer formed using a plurality of different materials, or a multilayer structure having a plurality of layers formed using a plurality of different materials. The first emission layer EML1, the second emission layer EML2, and the third emission layer EML3 may include a fluorescent or phosphorescent material. In the light-emitting element ED according to one or more embodiments, the first emission layer EML1, the second emission layer EML2, and the third emission layer EML3 may include an organic light-emitting material, a metal organic composite, or one or more quantum dots as the light-emitting material. Figure 5 and Fig. 6A In the embodiment, the first light emitting element ED1, the second light emitting element ED2 and the third light emitting element ED3 including one emission layer are shown as examples. Figure 5 ) may include a plurality of emission stacks each including at least one emission layer. For example, a light emitting element ED according to one or more embodiments may include a first electrode EL1, a second electrode EL2 positioned opposite to the first electrode EL1, and a plurality of emission stacks positioned between the first electrode EL1 and the second electrode EL2. Between the plurality of emission stacks, a charge generation layer may be positioned.

[0162] The first emission layer EML1, the second emission layer EML2, and the third emission layer EML3 respectively included in the first light-emitting element ED1, the second light-emitting element ED2, and the third light-emitting element ED3 may include an organic light-emitting material as a light-emitting material, or one or more quantum dots. The first light-emitting element ED1, the second light-emitting element ED2, and the third light-emitting element ED3 may also include a first hole transport region HTR1, a second hole transport region HTR2, and a third hole transport region HTR3, and a first electron transport region ETR1, a second electron transport region ETR2, and a third electron transport region ETR3, respectively. The first light-emitting element ED1, the second light-emitting element ED2, and the third light-emitting element ED3 may also include a capping layer positioned on the second electrode EL2.

[0163] In one or more embodiments, the first light-emitting element ED1, the second light-emitting element ED2, and the third light-emitting element ED3 may emit light in a direction from the first sub-electrode EL1-1, the second sub-electrode EL1-2, and the third sub-electrode EL1-3 to the second electrode EL2, and based on the emission direction of the light, the first hole transport region HTR1, the second hole transport region HTR2, and the third hole transport region HTR3 may be positioned below the first emission layer EML1, the second emission layer EML2, and the third emission layer EML3, respectively, and the first electron transport region ETR1, the second electron transport region ETR2, and the third electron transport region ETR3 may be positioned on the first emission layer EML1, the second emission layer EML2, and the third emission layer EML3, respectively. However, the present disclosure is not limited thereto, and the first light-emitting element ED1, the second light-emitting element ED2, and the third light-emitting element ED3 may have an inverted element structure in which the first electron transport region ETR1, the second electron transport region ETR2, and the third electron transport region ETR3 may be positioned under the first emission layer EML1, the second emission layer EML2, and the third emission layer EML3, and the hole transport region HTR may be positioned on the first emission layer EML1, the second emission layer EML2, and the third emission layer EML3 based on the emission direction of light.

[0164] Reference again Fig. 6A , the first electron transport region ETR1, the second electron transport region ETR2, and the third electron transport region ETR3 may be positioned between the first emission layer EML1, the second emission layer EML2, and the third emission layer EML3 and the second electrode EL2, respectively. The electron transport region ETR may include at least one of an electron injection layer, an electron transport layer, and a hole blocking layer. Fig. 6A , the first electron transport region ETR1, the second electron transport region ETR2, and the third electron transport region ETR3 may be patterned and provided to be separately positioned corresponding to the first light emitting region EA1, the second light emitting region EA2, and the third light emitting region EA3, respectively. However, the present disclosure is not limited thereto, and the electron transport region ETR may be a common layer overlapping the entirety of the first light emitting region EA1, the second light emitting region EA2, and the third light emitting region EA3 and the pixel defining layer PDL that divides the first light emitting region EA1, the second light emitting region EA2, and the third light emitting region EA3.

[0165] The second electrode EL2 may be provided on the electron transport region ETR. The second electrode EL2 may be a common electrode. The second electrode EL2 may be a cathode or an anode, but the present disclosure is not limited thereto. For example, if the first electrode EL1 is an anode, the second electrode EL2 may be a cathode. For example, if the first electrode EL1 is a cathode, the second electrode EL2 may be an anode. The second electrode EL2 may be a transmissive electrode, a transflective electrode, or a reflective electrode.

[0166] The encapsulation layer TFE may be positioned on the light emitting element ED. For example, in one or more embodiments, the encapsulation layer TFE may be positioned on the second electrode EL2. In addition, if the display element layer DP-LED includes an optical layer OPL, the encapsulation layer TFE may be positioned on the optical layer OPL. As described above, the encapsulation layer TFE may include at least one organic layer and at least one inorganic layer, and the inorganic layer and the organic layer may be positioned alternately.

[0167] The display device DD according to one or more embodiments may include an optical structure layer OSL positioned on the display element layer DP-LED. The optical structure layer OSL may include a light control layer CCL, a color filter layer CFL, and a base layer BL.

[0168] The light control layer CCL may include a light converter. The light converter may be one or more quantum dots or a phosphor. The light converter may convert the wavelength of the provided light and emit the converted light. For example, the light control layer CCL may be a layer including one or more quantum dots in a local portion or a layer including a phosphor in a local portion.

[0169] The light control layer CCL may include a first light control pattern CCP-R, a second light control pattern CCP-B, and a third light control pattern CCP-G. The first light control pattern CCP-R, the second light control pattern CCP-B, and the third light control pattern CCP-G may be separated from each other. The first light control pattern CCP-R, the second light control pattern CCP-B, and the third light control pattern CCP-G may be separated by a dam BMP. The first light control pattern CCP-R, the second light control pattern CCP-B, and the third light control pattern CCP-G may be positioned in a dam opening BW-OH defined in the dam BMP. However, the present disclosure is not limited thereto. Figure 4 In the embodiment, the dam BMP has a rectangular shape in a cross-sectional view and does not overlap with the first light-controlling pattern CCP-R, the second light-controlling pattern CCP-B, and the third light-controlling pattern CCP-G, but the edges of the first light-controlling pattern CCP-R, the second light-controlling pattern CCP-B, and the third light-controlling pattern CCP-G may overlap with at least a portion of the dam BMP. In a cross-sectional view, the dam BMP may have a trapezoidal shape. If the dam BMP is closer to the display element layer DP-LED, the dam BMP may have an increased width in a cross-sectional view.

[0170] The first light control pattern CCP-R, the second light control pattern CCP-B, and the third light control pattern CCP-G can convert the wavelength of light provided from the display element layer DP-LED or transmit the light provided. The first light control pattern CCP-R, the second light control pattern CCP-B, and the third light control pattern CCP-G can be formed by an inkjet process. The liquid ink composition can be applied to the dam opening BW-OH. The applied ink composition can be polymerized by a thermal curing process or a photocuring process to form the first light control pattern CCP-R, the second light control pattern CCP-B, and the third light control pattern CCP-G.

[0171] The light control layer CCL may include a first light control pattern CCP-R including first quantum dots converting source light provided from the light emitting element ED into first light, a second light control pattern CCP-B transmitting the source light, and a third light control pattern CCP-G including second quantum dots converting the source light into second light.

[0172] In one or more embodiments, the first light-controlling pattern CCP-R may provide red light as the first light, and the second light-controlling pattern CCP-B may transmit and provide blue light as the source light provided from the light-emitting element ED. The third light-controlling pattern CCP-G may provide green light as the second light. For example, the first quantum dot may be a red quantum dot, and the second quantum dot may be a green quantum dot.

[0173] In addition, the light control layer CCL may further include a scatterer. The first light control pattern CCP-R may include first quantum dots and a scatterer, the third light control pattern CCP-G may include second quantum dots and a scatterer, and the second light control pattern CCP-B may not include quantum dots and may include a scatterer.

[0174] Each of the first light-control pattern CCP-R, the second light-control pattern CCP-B, and the third light-control pattern CCP-G may include a base resin for dispersing quantum dots and scatterers. In one or more embodiments, the first light-control pattern CCP-R may include first quantum dots and scatterers dispersed in the base resin. In one or more embodiments, the third light-control pattern CCP-G may include second quantum dots and scatterers dispersed in the base resin. In one or more embodiments, the second light-control pattern CCP-B may include scatterers dispersed in the base resin.

[0175] The light control layer CCL may include a barrier layer CAP1 positioned on one surface of the light control pattern. The light control layer CCL may include a barrier layer CAP1 separated from the display element layer DP-LED with the first light control pattern CCP-R therebetween and an additional barrier layer CAP2 adjacent to the display element layer DP-LED.

[0176] In the display panel DP, the optical structure layer OSL may include a color filter layer CFL positioned on the light control layer CCL. The color filter layer CFL may include a first color filter CF1, a second color filter CF2, and a third color filter CF3. The color filter layer CFL may include a first color filter CF1 that transmits a first light, a second color filter CF2 that transmits a source light, and a third color filter CF3 that transmits a second light. In one or more embodiments, the first color filter CF1 may be a red color filter, the second color filter CF2 may be a blue color filter, and the third color filter CF3 may be a green color filter.

[0177] Each of the first color filter CF1, the second color filter CF2, and the third color filter CF3 may include a polymer photosensitive resin and a colorant. The first color filter CF1 may include a red colorant, the second color filter CF2 may include a blue colorant, and the third color filter CF3 may include a green colorant. The first color filter CF1 may include a red pigment or a red dye, the second color filter CF2 may include a blue pigment or a blue dye, and the third color filter CF3 may include a green pigment or a green dye.

[0178] The first color filter CF1, the second color filter CF2, and the third color filter CF3 may be positioned in the first pixel region PXA-R, the second pixel region PXA-B, and the third pixel region PXA-G, respectively. In addition, the first color filter CF1, the second color filter CF2, and the third color filter CF3 may be arranged corresponding to the first light-controlling pattern CCP-R, the second light-controlling pattern CCP-B, and the third light-controlling pattern CCP-G, respectively.

[0179] In addition, corresponding to the non-luminous area NPXA positioned among the first pixel area PXA-R, the second pixel area PXA-B, and the third pixel area PXA-G, the first color filter CF1, the second color filter CF2, and the third color filter CF3 that transmit different light may be overlapped and positioned. The first color filter CF1, the second color filter CF2, and the third color filter CF3 may overlap and be positioned in the third direction DR3 as the thickness direction to divide the boundary between the adjacent first pixel area PXA-R, the second pixel area PXA-B, and the third pixel area PXA-G. The color filter layer CFL may include a light blocking portion for dividing the boundary between the adjacent first color filter CF1, the second color filter CF2, and the third color filter CF3. The light blocking portion may be formed as a blue color filter or may be formed by including an organic light blocking material or an inorganic light blocking material containing a black pigment or a black dye.

[0180] The optical structure layer OSL may include a low refractive layer LR positioned between the light control layer CCL and the color filter layer CFL. The low refractive layer LR may be positioned on the light control layer CCL to block the first light control pattern CCP-R, the second light control pattern CCP-B, and the third light control pattern CCP-G from being exposed to moisture / oxygen. In addition, the low refractive layer LR may be positioned between the first light control pattern CCP-R, the second light control pattern CCP-B, and the third light control pattern CCP-G and the first color filter CF1, the second color filter CF2, and the third color filter CF3 to serve as an optical functional layer that improves (e.g., increases) light extraction efficiency or prevents or substantially reduces reflected light from being incident on the light control layer CCL. The low refractive layer LR may be a layer having a low refractive index compared to other adjacent layers.

[0181] The low refractive layer LR may include at least one inorganic layer. For example, the low refractive layer LR may be formed by including silicon nitride, aluminum nitride, zirconium nitride, titanium nitride, hafnium nitride, tantalum nitride, silicon oxide, aluminum oxide, titanium oxide, tin oxide, cerium oxide, silicon oxynitride or a metal film that ensures light transmittance. However, the present disclosure is not limited thereto, and the low refractive layer LR may include an organic film. For example, the low refractive layer LR may have a structure in which a plurality of hollow particles are dispersed in an organic polymer resin. The low refractive layer LR may be composed of a single layer or a plurality of layers.

[0182] In one or more embodiments, the optical structure layer OSL may further include a base layer BL positioned on the color filter layer CFL. The base layer BL may be a member that provides a base surface on which the color filter layer CFL and the light control layer CCL are positioned. The base layer BL may be a glass substrate, a metal substrate, a plastic substrate, or the like. However, the present disclosure is not limited thereto, and the base layer BL may be an inorganic layer, an organic layer, or a composite material layer. In one or more embodiments, the base layer BL may be omitted.

[0183] Figure 6B An enlarged view of a portion of a cross section of a display device according to one or more embodiments of the present disclosure is illustrated. Figure 6B Shown with Figure 4 The cross-sectional view of the display device DD-1 corresponding to the cutting line II-II' in FIG. Figure 6B Shown with Fig. 6A The display device DD shown in FIG. 1 is different from the display device DD-1 according to one or more other embodiments.

[0184] refer to Figure 6B, a display device DD-1 according to one or more embodiments may include: a lower panel including a base substrate BS, a circuit element layer DP-CL positioned on the base substrate BS, and a display element layer DP-LED positioned on the circuit element layer DP-CL; and an optical structure layer OSL-1 positioned on the lower panel. In the display device DD-1 according to one or more embodiments, the optical structure layer OSL-1 may include a light control layer CCL-1, a low refractive layer LR-1, a color filter layer CFL, and a base layer BL-1 stacked in sequence on the encapsulation layer TFE. The optical structure layer OSL-1 may include a blocking layer CAP1 and an additional blocking layer CAP2 positioned on and below the light control layer CCL-1.

[0185] The light control layer CCL-1 may be positioned on the display element layer DP-LED and the encapsulation layer TFE with an additional barrier layer CAP2 therebetween. The light control layer CCL-1 may include a plurality of dams BMP and a first light control pattern CCP-R, a second light control pattern CCP-B, and a third light control pattern CCP-G positioned between the plurality of dams BMP. On the light control layer CCL-1, a low refractive layer LR may be positioned.

[0186] The color filter layer CFL may include first, second, and third color filters CF1, CF2, and CF3, and a light blocking part BM.

[0187] and Fig. 6A Compared with the display device DD shown in Figure 6B The display device DD-1 according to one or more embodiments shown in the figure is a display device in which the light control layer CCL-1, the low refractive layer LR and the color filter layer CFL are positioned with the top of the encapsulation layer TFE as the base surface. For example, the first light control pattern CCP-R, the second light control pattern CCP-B and the third light control pattern CCP-G of the light control layer CCL-1 may be formed on the encapsulation layer TFE by a continuous process. The first color filter CF1, the second color filter CF2 and the third color filter CF3 of the color filter layer CFL may be formed in sequence on the light control layer CCL-1 by a continuous process. The light control layer CCL-1 may be formed on the top of the additional barrier layer CAP2 positioned on the encapsulation layer TFE as the base surface, and may have the same Fig. 6A The shape of the light control layer CCL shown in FIG. 1 is an upside-down shape. The plurality of dams BMP and the first light control pattern CCP-R, the second light control pattern CCP-B, and the third light control pattern CCP-G may have the same Fig. 6A The color filter layer CFL may be formed with the light control layer CCL-1 as a base surface and may have the same Fig. 6A The shapes shown are different shapes.

[0188] In the color filter layer CFL according to one or more embodiments, the light blocking part BM may be a black matrix. The light blocking part BM may be formed by including an organic light blocking material or an inorganic light blocking material including a black pigment or a black dye. The light blocking part BM may prevent light leakage and divide the boundaries between the adjacent first color filter CF1, the second color filter CF2, and the third color filter CF3.

[0189] Figure 7 A flow chart of a method for manufacturing a display device according to one or more embodiments of the present disclosure is illustrated. Figure 7 According to one or more embodiments of the present disclosure, a method for manufacturing a display device may include: a step of preparing a substrate including a first electrode and an intermediate layer (S101); a step of forming a preliminary first peeling layer on the substrate (S102); a step of forming a first photoresist pattern having a light opening portion overlapping a display area on the preliminary first peeling layer (S103); a step of etching the preliminary first peeling layer to form a first peeling layer exposing the display area (S104); a step of forming a second electrode on the intermediate layer through the light opening portion (S105); and a step of removing the first peeling layer and the first photoresist pattern (S106).

[0190] FIG. 8A to FIG. 8Q A diagram schematically showing some steps of a method for manufacturing a display device according to one or more embodiments of the present disclosure is illustrated. Fig. 8A , Fig.8D , Figure 8F , Figure 8H , Figure 8J , Figure 8M and Figure 8P A perspective view illustrating a method for manufacturing a display device according to one or more embodiments of the present disclosure is illustrated. Figure 8B , Figure 8C , Fig. 8E , Figure 8G , Fig.8I , Figure 8K , Figure 8L , Figure 8N , Fig.8O and Figure 8Q A cross-sectional view illustrating a method for manufacturing a display device according to one or more embodiments of the present disclosure is illustrated. Figure 8B , Fig. 8E , Figure 8G , Fig.8I , Figure 8K , Figure 8N and Figure 8Q About Yan Fig. 8A A cross section taken along line III-III′ in FIG. 1 illustrates cross-sectional views sequentially showing a method for manufacturing a display device. Figure 8C , Figure 8L and Fig.8O About Yan Fig. 8A A cross section taken along line IV-IV′ in FIG. 1 illustrates a cross-sectional view showing some steps of a method for manufacturing a display device.

[0191] By reference FIG. 8A to FIG. 8Q The display device manufactured by the method for manufacturing a display device according to one or more embodiments explained may have reference Figures 1A to 6B The structure of the display device according to one or more embodiments explained in the above description. FIG. 8A to FIG. 8Q In the explanation of the method for manufacturing a display device according to one or more embodiments of the present disclosure, Figures 1A to 6B The same elements of the display device (ie, display device DD or DD-1) will be designated by the same reference numerals, and explanation of overlapping parts will be omitted.

[0192] refer to FIG. 8A to FIG. 8C , the method for manufacturing a display device according to one or more embodiments of the present disclosure may include a step of preparing a substrate WP.

[0193] Fig. 8A A diagram showing the steps of providing a substrate WP according to one or more embodiments of the present disclosure is illustrated. Fig. 8A As shown in , the substrate WP may be a mother glass substrate having a large area. For example, the substrate WP may be a mother substrate for manufacturing a plurality of display devices simultaneously or substantially simultaneously. Fig. 8A , a plurality of first preliminary display panels P-DP may be formed in the substrate WP. The substrate WP may be a mother substrate having a size on which a plurality of first preliminary display panels P-DP may be formed. The first preliminary display panels P-DP may be detachably arranged on a plane.

[0194] The substrate WP may include a display unit area DPA in which a plurality of first preliminary display panels P-DP are formed, and a peripheral area SA other than the display unit area DPA. The display unit area DPA of the substrate WP may be an area on which the first preliminary display panels P-DP are formed. The display unit area DPA of the substrate WP may be an area on which a plurality of display panels are formed by deposition, patterning, thin film formation, and etching processes. A plurality of display panels may be provided simultaneously or substantially simultaneously by the same or substantially the same process.

[0195] The display unit area DPA of the substrate WP may include an active area AA and a pad area PA adjacent to the active area AA. Figure 3 The active area AA shown in FIG. 1 corresponds to the active area AA shown in FIG. 1 , and the pad area PA of the substrate WP may correspond to the active area AA shown in FIG. 1 . Figure 3 The pad area PA shown in FIG. Figure 3 , Fig. 8A and Figure 8B , the first preliminary display panel P-DP may include pads PD formed correspondingly in the pad area PA. Figure 3 and Figure 8B The active area AA may include a display area DA and a first non-display area NDA1 surrounding the display area DA. The display area DA may be an area corresponding to an area on which the light emitting element ED is formed. The display area DA, the first non-display area NDA1, and the second non-display area NDA2 of the substrate WP may be respectively Figure 3 The display area DA, the first non-display area NDA1, and the second non-display area NDA2 of the display panel DP shown in FIG.

[0196] refer to Fig. 8A and Figure 8C The first preliminary display panel P-DP may be defined as a panel formed by forming the second electrode EL2, the optical layer OPL (see Figure 8M ) and encapsulation layer TFE (see Figure 6B ) in a step before, wherein the element comprises Fig. 6A and Figure 6B In the display panel DP explained in the above, in addition to the second electrode EL2, the optical layer OPL (see Figure 8M ) and encapsulation layer TFE (see Figure 6B ), the first preliminary display panel P-DP may include elements that are the same or substantially the same as those of the display panel DP described above. The first preliminary display panel P-DP may include a base substrate BS, a circuit element layer DP-CL, a first sub-electrode EL1-1, a second sub-electrode EL1-2, and a third sub-electrode EL1-3, and an intermediate layer. The intermediate layer may include a first hole transport region HTR1, a second hole transport region HTR2, and a third hole transport region HTR3, a first emission layer EML1, a second emission layer EML2, and a third emission layer EML3, and at least one of a first electron transport region ETR1, a second electron transport region ETR2, and a third electron transport region ETR3. For example, as Figure 8C As shown in , the intermediate layer may include first, second, and third hole transport regions HTR1, HTR2, and HTR3, first, second, and third emission layers EML1, EML2, and EML3, and first, second, and third electron transport regions ETR1, ETR2, and ETR3.

[0197] refer to Figure 8C, the first preliminary display panel P-DP may include a base substrate BS, a circuit element layer DP-CL positioned on the base substrate BS, and a preliminary display element layer PL positioned on the circuit element layer DP-CL. The preliminary display element layer PL may include a pixel defining layer PDL positioned on the circuit element layer DP-CL and a first preliminary light-emitting element ED-1I, a second preliminary light-emitting element ED-2I, and a third preliminary light-emitting element ED-3I. Figure 4 and Fig. 6A As shown in FIG. 1 , a first pixel opening OH-1, a second pixel opening OH-2, and a third pixel opening OH-3 corresponding to the first pixel region PXA-R, the second pixel region PXA-B, and the third pixel region PXA-G, respectively, may be defined at the pixel defining layer PDL. The first pixel opening OH-1 may be aligned with the first pixel region PXA-R (see FIG. 1 ). Fig. 6A and Figure 6B ) is defined correspondingly, the second pixel opening OH-2 may be adjacent to the third pixel region PXA-G (see Fig. 6A and Figure 6B ) is defined correspondingly, and the third pixel opening portion OH-3 may be aligned with the second pixel region PXA-B (see Fig. 6A and Figure 6B ) are defined accordingly.

[0198] The first preliminary light emitting element ED-1I, the second preliminary light emitting element ED-2I, and the third preliminary light emitting element ED-3I may be positioned in the first pixel opening OH-1, the second pixel opening OH-2, and the third pixel opening OH-3, respectively. The preliminary display element layer PL may include the first preliminary light emitting element ED-1I positioned in the first pixel opening OH-1, the second preliminary light emitting element ED-2I positioned in the second pixel opening OH-2, and the third preliminary light emitting element ED-3I positioned in the third pixel opening OH-3. The first preliminary light emitting element ED-1I may include a first sub-electrode EL1-1, a first hole transport region HTR1, a first emission layer EML1, and a first electron transport region ETR1 stacked in sequence along the third direction DR3. The second preliminary light emitting element ED-2I may include a second sub-electrode EL1-2, a second hole transport region HTR2, a second emission layer EML2, and a second electron transport region ETR2 stacked in sequence along the third direction DR3. The third preliminary light emitting element ED-3I may include a third sub-electrode EL1-3, a third hole transport region HTR3, a third emission layer EML3, and a third electron transport region ETR3 sequentially stacked along the third direction DR3.

[0199] exist FIG. 8A to FIG. 8QIn the embodiment, the first hole transport region HTR1, the second hole transport region HTR2 and the third hole transport region HTR3, the first emission layer EML1, the second emission layer EML2 and the third emission layer EML3 and the first electron transport region ETR1, the second electron transport region ETR2 and the third electron transport region ETR3 in the first preliminary light-emitting element ED-1I, the second preliminary light-emitting element ED-2I and the third preliminary light-emitting element ED-3I are separately formed to correspond to the first pixel opening portion OH-1, the second pixel opening portion OH-2 and the third pixel opening portion OH-3, but one or more embodiments of the present disclosure are not limited thereto. For example, at least one of the first hole transport region HTR1, the second hole transport region HTR2 and the third hole transport region HTR3, the first emission layer EML1, the second emission layer EML2 and the third emission layer EML3, and the first electron transport region ETR1, the second electron transport region ETR2 and the third electron transport region ETR3 may be positioned in the first pixel opening portion OH-1, the second pixel opening portion OH-2 and the third pixel opening portion OH-3, and may be provided on the pixel defining layer PDL as a common layer having a monomer (e.g., a single integral / monolithic body).

[0200] refer to Fig.8D and Fig. 8E , the method for manufacturing a display device according to one or more embodiments of the present disclosure may include a step of forming a preliminary first peeling layer P-LOL1 on the substrate WP.

[0201] A preliminary first peeling layer P-LOL1 may be provided on the first preliminary display panel P-DP. The preliminary first peeling layer P-LOL1 may completely overlap the first preliminary display panel P-DP. Fig.8D and Fig. 8E As shown in FIG. 1 , the preliminary first peeling layer P-LOL1 may provide an overlap with the active area AA, the pad area PA, and the peripheral area SA of the substrate WP. Figure 3 , Fig.8D and Fig. 8E , the preliminary first peeling layer P-LOL1 may cover the pad PD positioned in the pad area PA. The preliminary first peeling layer P-LOL1 may be positioned on the first preliminary display panel P-DP to completely cover the pad PD.

[0202] exist Fig.8D , the area of ​​the preliminary first peeling layer P-LOL1 on the plane is shown to be the same as the area of ​​the substrate WP on the plane, but the present disclosure is not limited thereto. For example, the preliminary first peeling layer P-LOL1 may overlap with the display unit area DPA of the substrate WP. For example, the area of ​​the preliminary first peeling layer P-LOL1 on the plane may be smaller than or larger than the area of ​​the substrate WP on the plane.

[0203] Also refer to Figure 8C and Fig. 8E , a preliminary first peeling layer P-LOL1 may be formed on the substrate WP on which the first electrode EL1 and the intermediate layer are formed. In particular, the preliminary first peeling layer P-LOL1 may be formed on the substrate WP on which the first electrode EL1, the first hole transport region HTR1, the second hole transport region HTR2, and the third hole transport region HTR3, the first emission layer EML1, the second emission layer EML2, and the third emission layer EML3, and the first electron transport region ETR1, the second electron transport region ETR2, and the third electron transport region ETR3 are formed. The preliminary first peeling layer P-LOL1 may include a material having low reactivity with the intermediate layer. For example, the preliminary first peeling layer P-LOL1 may include a material having low chemical reactivity with a material constituting the intermediate layer.

[0204] In one or more embodiments, the preliminary first peeling layer P-LOL1 may include a polymer material. For example, the preliminary first peeling layer P-LOL1 may include a polymer material containing fluorine. For example, the preliminary first peeling layer P-LOL1 may include at least one of polytetrafluoroethylene, polytrifluorochloroethylene, polydichlorodifluoroethylene, a copolymer of trifluorochloroethylene and dichlorodifluoroethylene, a copolymer of tetrafluoroethylene and perfluoroalkyl vinyl ether, a copolymer of trifluorochloroethylene and perfluoroalkyl vinyl ether, a copolymer of tetrafluoroethylene and perfluoroalkyl vinyl ether, and a copolymer of trifluorochloroethylene and perfluoroalkyl vinyl ether. In one or more embodiments, the preliminary first peeling layer P-LOL1 may include polytetrafluoroethylene.

[0205] The preliminary first peeling layer P-LOL1 may be formed using various suitable methods such as a coating method, a printing method, or a deposition method. In addition, during the formation of the preliminary first peeling layer P-LOL1, a curing and polymerization process may be performed as desired.

[0206] refer to Figure 8F and Figure 8G , the method for manufacturing a display device according to one or more embodiments of the present disclosure may include a step of forming a first photoresist pattern PR1 on the preliminary first lift-off layer P-LOL1.

[0207] A first photoresist pattern PR1 may be formed on the preliminary first peeling layer P-LOL1 by forming a preliminary first photoresist layer and then patterning the preliminary first photoresist layer using a photomask. For example, in the patterning process, a photomask in which a mask opening portion corresponding to the display area DA is formed may be provided on the preliminary first photoresist layer, and light may be provided on the preliminary first photoresist layer through the mask opening portion. Then, by a development process of the preliminary first photoresist layer exposed to light, a portion corresponding to the display area DA in the preliminary first photoresist layer may be removed. By the patterning process, a light opening portion OP-PR overlapping the display area DA may be formed in the first photoresist pattern PR1. A positive method of removing a portion provided with light in the preliminary first photoresist layer by a patterning method of the preliminary first photoresist layer has been explained, but the present disclosure is not limited thereto. For example, the preliminary first photoresist layer may be patterned by a negative method for removing a portion of the preliminary first photoresist layer to which light is not provided.

[0208] The first photoresist pattern PR1 may overlap the pad area PA in a plane. The first photoresist pattern PR1 may be formed to overlap the pad PD in a plane. Figure 8G As shown in , the first photoresist pattern PR1 may overlap the first non-display area NDA1. In one or more embodiments, the first photoresist pattern PR1 may not overlap the display area DA on a plane.

[0209] refer to Figure 8H and Fig.8I The method for manufacturing a display device according to one or more embodiments of the present disclosure may include etching the preliminary first peeling layer P-LOL1 (see Figure 8G ) to form a first peeling layer LOL1.

[0210] The preliminary first lift-off layer P-LOL1 may be etched by using the first photoresist pattern PR1 as a mask (see Figure 8G ) to form the first peeling layer LOL1. The preliminary first peeling layer P-LOL1 is etched (see Figure 8G ) may include providing a preliminary first peeling layer P-LOL1 (see Figure 8G ) provides a first solvent step. The first peeling layer P-LOL1 (see Figure 8G ) removes the portion overlapping with the optical opening OP-PR. Figure 8G), a first peeling layer LOL1 having a peeling opening OP-LOL for exposing at least a portion of the display area DA defined therein may be formed. On a plane, the peeling opening OP-LOL defined in the first peeling layer LOL1 may completely overlap the display area DA.

[0211] In one or more embodiments, the first solvent may contain fluorine. By using the first solvent containing fluorine as an etching solution, the etching of the preliminary first peeling layer P-LOL1 including a polymer containing fluorine can be smooth. Any first solvent can be used as long as it can dissolve the preliminary first peeling layer P-LOL1 without limitation, and the first solvent may include hydrofluoroether (HFE), hydrofluorocarbon, perfluorocarbon, trifluorotoluene, octafluorotoluene, perfluorobenzene and / or the like. In one or more embodiments, the first solvent may include hydrofluoroether (HFE). Hydrofluoroether (HFE) has little interaction with other materials and is an electrochemically stable material. Therefore, if the preliminary first peeling layer P-LOL1 is etched (see Figure 8G ) step, using hydrofluoroether (HFE) as the first solvent can prevent or reduce the positioning of the preliminary first peeling layer P-LOL1 (see Figure 8G ) damage to the functional layer of the first preliminary display panel P-DP below.

[0212] exist Figure 8H and Fig.8I , the area of ​​the stripping opening portion OP-LOL defined in the first stripping layer LOL1 on a plane is shown to be approximately equal to the area of ​​the light opening portion OP-PR defined in the first photoresist pattern PR1 on a plane, but the present disclosure is not limited to this. The area of ​​the stripping opening portion OP-LOL defined in the first stripping layer LOL1 on a plane may be greater than the area of ​​the light opening portion OP-PR defined in the first photoresist pattern PR1 on a plane. The first stripping layer LOL1 may have an undercut shape that is recessed from the inner side surface of the first photoresist pattern PR1 that defines the light opening portion OP-PR.

[0213] The first peeling layer LOL1 may expose the display area DA. The first peeling layer LOL1 may overlap the pad area PA. The first peeling layer LOL1 may completely cover the pad PD positioned in the pad area PA. The first peeling layer LOL1 may prevent or reduce the second electrode EL2 (eg, see Figure 8J ) is provided to the element positioned in the pad area PA to form the second electrode EL2 (for example, see Figure 8J ) material, which will be explained later. Since the first peeling layer LOL1 covers the pad PD, it can effectively prevent or reduce the second electrode EL2 (for example, see Figure 8J) is formed in the step of forming the second electrode EL2 (for example, see Figure 8J ) and can prevent or reduce the possibility of short circuit due to electrode material deposited in the pad area PA.

[0214] refer to Figures 8J to 8L , the method for manufacturing a display device according to one or more embodiments of the present disclosure may include the step of forming the second electrode EL2.

[0215] The optical opening portion OP-PR (see FIG. 1 ) of the first photoresist pattern PR1 may be formed. Figure 8H ) A second electrode EL2 is formed on the intermediate layer. The second electrode EL2 may be formed on the first preliminary light-emitting element ED-1I, the second preliminary light-emitting element ED-2I, and the third preliminary light-emitting element ED-3I using the first peeling layer LOL1 and the first photoresist pattern PR1 as a mask. Figure 8L As shown in FIG. 1 , the second electrode EL2 may be formed on the first electron transport region ETR1, the second electron transport region ETR2, and the third electron transport region ETR3 in the first preliminary light emitting element ED-1I, the second preliminary light emitting element ED-2I, and the third preliminary light emitting element ED-3I.

[0216] refer to Figure 8K and Figure 8L In the step of forming the second electrode EL2 , the second electrode EL2 may be formed on the preliminary display element layer PL, and a portion of the second electrode EL2 may be formed on the first photoresist pattern PR1 .

[0217] The step of forming the second electrode EL2 may be performed by a deposition process of a conductive material. The conductive material used to form the second electrode EL2 may include a metal material. For example, the conductive material forming the second electrode EL2 may include a transparent metal oxide. For example, the conductive material forming the second electrode EL2 may include at least one of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO) and indium tin zinc oxide (ITZO). The conductive material forming the second electrode EL2 may include a metal material, for example, Ag, Mg, Cu, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, LiF / Ca, LiF / Al, Mo, Ti, Yb, W or a compound or mixture thereof (for example, AgMg, AgYb or MgAg).

[0218] refer to Figure 8K, the material forming the second electrode EL2 may be formed on the first photoresist pattern PR1 and on the display area DA. The second electrode EL2 may be formed to overlap the display area DA and the pad area PA. Since the first peeling layer LOL1 is positioned to overlap the pad area PA, the material forming the second electrode EL2 may be prevented or reduced from being deposited on the pad PD. The second electrode EL2 may contact the intermediate layer. For example, Figure 8L As shown in , the second electrode EL2 may contact the first electron transport region ETR1, the second electron transport region ETR2, and the third electron transport region ETR3. By forming the second electrode EL2, the first light emitting element ED1, the second light emitting element ED2, and the third light emitting element ED3 may be formed. Fig. 6A The same contents explained in can be applied to the first light emitting element ED1, the second light emitting element ED2, and the third light emitting element ED3.

[0219] refer to FIG. 8M to FIG. 8O , the method for manufacturing a display device according to one or more embodiments of the present disclosure may further include a step of forming an optical layer OPL on the second electrode EL2.

[0220] After the step of forming the second electrode EL2, the optical opening portion OP-PR (eg, see Figure 8H ) forms an optical layer OPL. In one or more embodiments, the step of forming the optical layer OPL may be performed by a deposition process. Figure 8N and Fig.8O , an optical layer OPL may be formed on the second electrode EL2. The optical layer OPL may be in contact with the second electrode EL2. Figure 8N , a material for forming the optical layer OPL may be provided on the first photoresist pattern PR1.

[0221] refer to Figure 8P and Figure 8Q The method for manufacturing a display device according to one or more embodiments of the present disclosure may include removing the first peeling layer LOL1 (see Figure 8M ) and the first photoresist pattern PR1 (see Figure 8M ) steps.

[0222] Remove the first peeling layer LOL1 (see Figure 8M ) and the first photoresist pattern PR1 (see Figure 8M ) may include treating the first peeling layer LOL1 with a second solvent (see Figure 8M ) and the first photoresist pattern PR1 (see Figure 8M ) steps.

[0223] In one or more embodiments, the second solvent may include fluorine. Figure 8M ) includes a fluoropolymer, a solvent including fluorine can be used to remove the fluorine from the substrate WP (see Figure 8M ) Remove the first peeling layer LOL1 (see Figure 8M The second solvent can dissolve the first peeling layer LOL1 (see Figure 8M ), and may include, for example, hydrofluoroether (HFE), hydrofluorocarbon, perfluorocarbon, trifluorotoluene, octafluorotoluene, perfluorobenzene, or the like. In one or more embodiments, the second solvent may include hydrofluoroether (HFE). Hydrofluoroether (HFE) has little interaction with other materials and is an electrochemically stable material. Therefore, if hydrofluoroether (HFE) is used as the second solvent, when removing the first peeling layer LOL1 (see Figure 8M ) and the first photoresist pattern PR1 (see Figure 8M ), damage to the functional layers included in the display element layer DP-LED can be prevented or reduced.

[0224] Also refer to Figure 8N and Figure 8Q In the step of removing the first peeling layer LOL1 and the first photoresist pattern PR1, the second electrode EL2 and the optical layer OPL formed on the first photoresist pattern PR1 may be removed, and the second electrode EL2 and the optical layer OPL formed on the preliminary display element layer PL may be retained. The first peeling layer LOL1 may protect the pad PD arranged in the pad area PA during the formation of the second electrode EL2 and the optical layer OPL. The first peeling layer LOL1 may prevent or reduce defects such as a short circuit phenomenon generated during the formation of the second electrode EL2 due to the deposition of the material forming the second electrode EL2 on the pad PD positioned in the pad area PA. By removing the first peeling layer LOL1 and the first photoresist pattern PR1, a display element layer DP-LED may be formed on the circuit element layer DP-CL.

[0225] The method for manufacturing a display device according to one or more embodiments of the present disclosure may further include: after removing the first peeling layer LOL1 and the first photoresist pattern PR1, providing a package substrate ES (see Figure 2B ) step. The packaging substrate ES (see Figure 2B ) is formed on one surface of the sealant SM (see Figure 2B ), and a base substrate BS can be attached (see Figure 2B ) and package substrate ES (see Figure 2B ). By providing a packaging substrate ES (see Figure 2B ) steps, which may include reference Figure 2BA display device DD of a display panel DP according to one or more embodiments is explained.

[0226] According to the present disclosure, the steps of forming the second electrode EL2 and the optical layer OPL may be performed through a lift-off process, and a misalignment problem of the substrate WP and the metal mask may be prevented or reduced.

[0227] Fig. 9 A flowchart illustrating some steps of a method for manufacturing a display device according to one or more embodiments of the present disclosure. Fig. 9 FIG. 1 is a flowchart showing steps of forming an encapsulation layer TFE in a display device DD or DD-1 according to one or more embodiments of the present disclosure. Fig. 9 According to one or more embodiments of the present disclosure, the method for manufacturing a display device may include: a step of forming a preliminary second peeling layer on a substrate (S201); a step of forming a second photoresist pattern on the preliminary second peeling layer (S202); a step of etching the preliminary second peeling layer to form a second peeling layer (S203); a step of forming an encapsulation layer on a second electrode using the second photoresist pattern as a mask (S204); and a step of removing the second peeling layer and the second photoresist pattern (S205).

[0228] FIG. 10A to FIG. 10K A diagram schematically showing some steps of a method for manufacturing a display device according to one or more embodiments of the present disclosure is illustrated. Fig. 10A , Fig. 10C , Fig. 10E , Figure 10G and Fig.10I A perspective view illustrating a method for manufacturing a display device according to one or more embodiments of the present disclosure is illustrated. Fig. 10B , Fig. 10D , Fig.10F , Fig. 10H , Fig.10J and Figure 10K A cross-sectional view illustrating a method for manufacturing a display device according to one or more embodiments of the present disclosure is illustrated. Fig. 10B , Fig. 10D , Fig.10F , Fig. 10H and Fig.10J About Yan Fig. 10A A cross section taken along line VV′ in FIG. 1 illustrates cross-sectional views sequentially showing a method for manufacturing a display device. Figure 10K About Yan Fig.10I A cross section taken along line VI-VI′ in FIG. 1 illustrates a cross-sectional view showing some steps of a method for manufacturing a display device.

[0229] By reference FIG. 10A to FIG. 10KThe display device manufactured by the method for manufacturing a display device according to one or more embodiments explained may have a reference Figures 1A to 2A and Figures 3 to 6B The structure of the display device (ie, display device DD or DD-1) according to one or more embodiments explained in the above description. FIG. 10A to FIG. 10K In the explanation of the method for manufacturing a display device according to one or more embodiments, Figures 1A to 2A and Figures 3 to 6B The same elements as those of the display device are given the same reference numerals, and repeated descriptions thereof will be omitted.

[0230] refer to Fig. 10A and Fig. 10B The method for manufacturing a display device according to one or more embodiments of the present disclosure may include the step of forming a preliminary second peeling layer P-LOL2 on the substrate WP-M. In addition, the method for manufacturing a display device according to one or more embodiments of the present disclosure may further include the step of providing a substrate WP-M.

[0231] refer to Fig. 10A The substrate WP-M may be a large-sized mother glass substrate. For example, a plurality of second preliminary display panels P-Dpa may be formed on the substrate WP-M. The plurality of second preliminary display panels P-Dpa may be detachably arranged on a plane.

[0232] Also refer to Figure 8P , Figure 8Q , Fig. 10A and Fig. 10B The substrate WP-M may be a substrate on which the second electrode EL2 is formed, such as by FIG. 8A to FIG. 8Q The substrate WP-M may be a substrate in which the second electrode EL2 and the optical layer OPL are formed, such as by FIG. 8A to FIG. 8Q Explain. Fig. 8A The same contents explained in or similar figures may be applied to the active area AA, the pad area PA, and the peripheral area SA included in the substrate WP-M.

[0233] The second preliminary display panel P-Dpa may be defined as including Fig. 6A and Figure 6B The components in the display panel DP explained in Figure 10G The second preliminary display panel P-Dpa may include the display panel DP described above (see Fig. 6A ) components, except that the encapsulation layer TFE (see Figure 10G). The second preliminary display panel P-Dpa may include a base substrate BS, a circuit element layer DP-CL, a first sub-electrode EL1-1, a second sub-electrode EL1-2, and a third sub-electrode EL1-3, an intermediate layer, and a second electrode EL2. In addition, the second preliminary display panel P-Dpa may further include an optical layer OPL positioned on the second electrode EL2. The same contents explained for the first preliminary display panel P-DP may be applied to the intermediate layer.

[0234] Reference again Fig. 10A and Fig. 10B , a preliminary second peeling layer P-LOL2 may be formed on the substrate WP-M. The preliminary second peeling layer P-LOL2 may completely overlap with the second preliminary display panel P-Dpa. The preliminary second peeling layer P-LOL2 may be provided to overlap with the active area AA, the pad area PA, and the peripheral area SA of the substrate WP-M.

[0235] Although in Fig. 10A The area of ​​the preliminary second peeling layer P-LOL2 on the plane is shown to be substantially equal to the area of ​​the substrate WP-M on the plane, but the present disclosure is not limited thereto. For example, it is sufficient that only the preliminary second peeling layer P-LOL2 overlaps the display unit area DPA of the substrate WP-M. For example, the area of ​​the preliminary second peeling layer P-LOL2 on the plane may be smaller than or larger than the area of ​​the substrate WP-M on the plane.

[0236] Also refer to Figure 8P , Figure 8Q , Fig. 10A and Fig. 10B A preliminary second peeling layer P-LOL2 may be formed on the substrate WP-M in which the second electrode EL2 and the optical layer OPL are formed. Fig. 6A ), the first hole transport region HTR1, the second hole transport region HTR2 and the third hole transport region HTR3 (see Fig. 6A ), a first emission layer EML1, a second emission layer EML2 and a third emission layer EML3 (see Fig. 6A ), a first electron transport region ETR1, a second electron transport region ETR2 and a third electron transport region ETR3 (see Fig. 6A ), the second electrode EL2 (see Fig. 6A ) and the optical layer OPL (see Fig. 6A ) is formed on the substrate WP-M of the second preliminary display panel P-Dpa. The preliminary second peeling layer P-LOL2 may include a material having low reactivity with the functional layer included in the second preliminary display panel P-Dpa.

[0237] In one or more embodiments, the preliminary second peeling layer P-LOL2 may include a polymer material. For example, the preliminary second peeling layer P-LOL2 may include a polymer material containing fluorine. For example, the preliminary second peeling layer P-LOL2 may include at least one of polytetrafluoroethylene, polytrifluorochloroethylene, polydichlorodifluoroethylene, a copolymer of trifluorochloroethylene and dichlorodifluoroethylene, a copolymer of tetrafluoroethylene and perfluoroalkyl vinyl ether, a copolymer of trifluorochloroethylene and perfluoroalkyl vinyl ether, a copolymer of tetrafluoroethylene and perfluoroalkyl vinyl ether, and a copolymer of trifluorochloroethylene and perfluoroalkyl vinyl ether. In one or more embodiments, the preliminary second peeling layer P-LOL2 may include polytetrafluoroethylene.

[0238] The preliminary second peeling layer P-LOL2 may be formed using various suitable methods such as a coating method, a printing method, and a deposition method. In addition, during the formation of the preliminary second peeling layer P-LOL2, a curing and polymerization process may be performed as desired.

[0239] refer to Fig. 10C and Fig. 10D , the method for manufacturing a display device according to one or more embodiments of the present disclosure may include a step of forming a second photoresist pattern PR2 on the preliminary second lift-off layer P-LOL2.

[0240] A second photoresist pattern PR2 may be formed on the preliminary second peeling layer P-LOL2 by forming a preliminary second photoresist layer and then patterning the preliminary second photoresist layer using a photomask. For example, in the patterning process, the second photoresist pattern PR2 may be formed by exposing a portion of the preliminary second photoresist layer other than a portion overlapping with the pad area PA and removing the exposed portion by development. A positive method of removing a portion provided with light in the preliminary second photoresist layer by a patterning method of the preliminary second photoresist layer has been explained, but the present disclosure is not limited thereto. For example, the preliminary second photoresist layer may be patterned by a negative method of removing a portion not provided with light in the preliminary second photoresist layer.

[0241] The second photoresist pattern PR2 may overlap the pad area PA on a plane. The second photoresist pattern PR2 may be formed to overlap the pad PD on a plane. The second photoresist pattern PR2 may not overlap the display area DA on a plane. In addition, the second photoresist pattern PR2 may not overlap the first non-display area NDA1. However, the present disclosure is not limited thereto. The second photoresist pattern PR2 may partially overlap the first non-display area NDA1 on a plane.

[0242] refer to Fig. 10E and Fig.10FThe method for manufacturing a display device according to one or more embodiments of the present disclosure may include etching the preliminary second peeling layer P-LOL2 (see Fig. 10D ) to form a second peeling layer LOL2.

[0243] The second lift-off layer LOL2 may be formed by etching the preliminary second lift-off layer P-LOL2 using the second photoresist pattern PR2 as a mask. The step of etching the preliminary second lift-off layer P-LOL2 may include etching the preliminary second lift-off layer P-LOL2 (see Fig. 10D ) step of providing a third solvent. The first step of removing the second peeling layer P-LOL2 (see Fig. 10D ) overlaps with the display area DA. Fig.10F As shown in FIG. 1 , the second peeling layer P-LOL2 (see FIG. 1 ) can be removed. Fig. 10D ) overlaps with the first non-display area NDA1.

[0244] After etching the preliminary second peeling layer P-LOL2 (see Fig. 10D ) step, a second peeling layer LOL2 exposing the display area DA may be formed. Fig. 10D ) step, the preliminary second peeling layer P-LOL2 (see Fig. 10D ) to form a second peeling layer LOL2.

[0245] In one or more embodiments, the third solvent may contain fluorine. By using the third solvent containing fluorine as an etching solution, the preliminary second peeling layer P-LOL2 including the polymer containing fluorine (see Fig. 10D ) is etched. The third solvent can dissolve the preliminary second peeling layer P-LOL2 (see Fig. 10D ). The third solvent may include, for example, hydrofluoroether (HFE), hydrofluorocarbon, perfluorocarbon, trifluorotoluene, octafluorotoluene, perfluorobenzene, or the like. In one or more embodiments, the third solvent may include hydrofluoroether (HFE). Hydrofluoroether (HFE) has little interaction with other materials and is an electrochemically stable material. Therefore, if hydrofluoroether (HFE) is used as the third solvent, when etching the preliminary second peeling layer P-LOL2 (see Fig. 10D ) step, the second peeling layer P-LOL2 (see Fig. 10D ) damage to the functional layer below.

[0246] The second peeling layer LOL2 may overlap the pad area PA. The second peeling layer LOL2 may completely cover the pad PD positioned in the pad area PA. The second peeling layer LOL2 may not overlap the display area DA. The second peeling layer LOL2 may not overlap the first non-display area NDA1. The second peeling layer LOL2 may be formed in the encapsulation layer TFE (see Fig. 10H ) in the step of preventing or reducing the need to provide the element positioned in the pad area PA with a packaging layer TFE (see Fig. 10H )'s role, which will be explained later.

[0247] exist Fig. 10E and Fig.10F , the second peeling layer LOL2 and the second photoresist pattern PR2 are shown as not overlapping the peripheral area SA, but the present disclosure is not limited thereto. The second peeling layer LOL2 may overlap the pad area PA and the peripheral area SA of the substrate WP-M. In this case, a peeling opening portion overlapping the display area DA may be defined in the second peeling layer LOL2. By changing the shape of the second photoresist pattern PR2, the planar layout of the second peeling layer LOL2 may be modified.

[0248] refer to Figure 10G and Fig. 10H The method for manufacturing a display device according to one or more embodiments of the present disclosure may include forming an encapsulation layer TFE on the second electrode EL2 using the second photoresist pattern PR2 as a mask.

[0249] Also refer to FIG. 10E to FIG. 10H , an encapsulation layer TFE may be formed on the display element layer DP-LED using the second peeling layer LOL2 and the second photoresist pattern PR2 as a mask. The encapsulation layer TFE may be formed on the second electrode EL2. If the display element layer DP-LED includes an optical layer OPL, the encapsulation layer TFE may be formed on the optical layer OPL. In the step of forming the encapsulation layer TFE, the encapsulation layer TFE may be formed on the display element layer DP-LED and may be partially formed on the second photoresist pattern PR2.

[0250] The material forming the encapsulation layer TFE may be provided in the display area DA. The material forming the encapsulation layer TFE may be provided in the display area DA and the first non-display area NDA1 surrounding the display area DA. Therefore, the encapsulation layer TFE may be formed to completely cover the display element layer DP-LED. Since the second peeling layer LOL2 is positioned to overlap the pad area PA, the deposition of the material forming the encapsulation layer TFE on the pad PD may be prevented or reduced.

[0251] The encapsulation layer TFE may be formed to have a single layer structure or a multi-layer structure. For example, forming the first inorganic layer IOL1 on the second electrode EL2 (see Figure 5 ) step, in the first inorganic layer IOL1 (see Figure 5 ) is formed on an organic layer OL (see Figure 5 ) and in the organic layer OL (see Figure 5 ) is formed on the second inorganic layer IOL2 (see Figure 5 The first inorganic layer IOL1 may be sequentially formed on the second electrode EL2 using the second lift-off layer LOL2 and the second photoresist pattern PR2 as masks (see Figure 5 ), organic layer OL (see Figure 5 ) and a second inorganic layer IOL2 (see Figure 5 ).

[0252] refer to FIG. 10I to FIG. 10K The method for manufacturing a display device according to one or more embodiments of the present disclosure may include removing the second peeling layer LOL2 (see Fig. 10E ) and the second photoresist pattern PR2 (see Fig. 10E ) steps.

[0253] Remove the second peeling layer LOL2 (see Fig. 10E ) and the second photoresist pattern PR2 (see Fig. 10E ) may include treating the second peeling layer LOL2 with a fourth solvent (see Fig. 10E ) and the second photoresist pattern PR2 (see Fig. 10E ) steps.

[0254] In one or more embodiments, the fourth solvent may include fluorine. Fig. 10E ) includes a fluoropolymer, the second peeling layer LOL2 can be removed using a fluorine-containing solvent (see Fig. 10E ). The fourth solvent can dissolve the second peeling layer LOL2 (see Fig. 10E ), and may include, for example, hydrofluoroether (HFE), hydrofluorocarbon, perfluorocarbon, trifluorotoluene, octafluorotoluene, perfluorobenzene, or the like. In one or more embodiments, the fourth solvent may include hydrofluoroether (HFE). Hydrofluoroether (HFE) has little interaction with other materials and is an electrochemically stable material. If hydrofluoroether (HFE) is used as the second solvent, the second peeling layer LOL2 and the second photoresist pattern PR2 (see Fig. 10E ), damage to the functional layers included in the display element layer DP-LED can be prevented or reduced.

[0255] After removing the second lift-off layer LOL2 and the second photoresist pattern PR2 (see Fig. 10E ) step, the second photoresist pattern PR2 (see Fig. 10E ) and the encapsulation layer TFE formed on the display element layer DP-LED can be retained. The second peeling layer LOL2 (see Fig. 10E ) can protect the pads PD located in the pad area PA during the formation of the encapsulation layer TFE. By removing the second peeling layer LOL2 (see Fig. 10E ) and a second photoresist pattern PR2 can form an encapsulation layer TFE on the display element layer DP-LED.

[0256] After removing the second peeling layer LOL2 (see Fig. 10E ) and the second photoresist pattern PR2 (see Fig. 10E ) step, the substrate WP-M may be cut to separate a plurality of display panels DP (see Fig. 6A ) steps. Figure 10K As shown in FIG. , a plurality of separated display panels DP (see Fig. 6A ) may include a base substrate BS, a circuit element layer DP-CL and a display element layer DP-LED.

[0257] FIG. 11A to FIG. 11H FIG. 1 schematically illustrates some steps of a method for manufacturing a display device according to one or more embodiments of the present disclosure. FIG. 11A to FIG. 11H In the explanation of the method for manufacturing a display device according to one or more embodiments of the present disclosure, Figures 1A to 6B The same elements as those of the display device in FIG. 1 (ie, display device DD or DD-1) are designated by the same reference numerals, and repeated explanation thereof will be omitted.

[0258] refer to Fig.11A In the method for manufacturing a display device according to one or more embodiments, a circuit element layer DP-CL may be formed on a base substrate BS, and a pixel defining layer PDL may be formed on the circuit element layer DP-CL. For example, a first pixel opening portion OH-1, a second pixel opening portion OH-2, and a third pixel opening portion OH-3 may be defined in the pixel defining layer PDL.

[0259] Before forming the pixel defining layer PDL, the first sub-electrode EL1-1, the second sub-electrode EL1-2, and the third sub-electrode EL1-3 may be formed on the circuit element layer DP-CL. The first sub-electrode EL1-1, the second sub-electrode EL1-2, and the third sub-electrode EL1-3 may be patterned on the circuit element layer DP-CL. The first sub-electrode EL1-1, the second sub-electrode EL1-2, and the third sub-electrode EL1-3 may be separated from each other on a plane. The tops of the first sub-electrode EL1-1, the second sub-electrode EL1-2, and the third sub-electrode EL1-3 may be exposed through the first pixel opening OH-1, the second pixel opening OH-2, and the third pixel opening OH-3, respectively. The edge portions of the first sub-electrode EL1-1, the second sub-electrode EL1-2, and the third sub-electrode EL1-3 may partially overlap with the pixel defining layer PDL.

[0260] The first pixel opening OH-1, the second pixel opening OH-2, and the third pixel opening OH-3 may be the same as in Figure 3 The portions corresponding to the first pixel area PXA-R, the third pixel area PXA-G, and the second pixel area PXA-B explained in FIG.

[0261] The pixel defining layer PDL may include a first pixel defining portion PDL1 and a second pixel defining portion PDL2. The first pixel defining portion PDL1 may be positioned on the circuit element layer DP-CL, and the second pixel defining portion PDL2 may be positioned on the first pixel defining portion PDL1. The second pixel defining portion PDL2 may be positioned directly on the first pixel defining portion PDL1. The second pixel defining portion PDL2 may cover the top of the first pixel defining portion PDL1. The second pixel defining portion PDL2 may be referred to as a liquid repelling portion.

[0262] The first pixel defining portion PDL1 may include an inorganic material. For example, the first pixel defining portion PDL1 may include silicon nitride (SiN x ), silicon oxide (SiO x ) and silicon oxynitride (SiO x N y ). The first pixel defining portion PDL1 may include silicon nitride (SiN x ).

[0263] The second pixel defining portion PDL2 may include a liquid-repellent additive. The second pixel defining portion PDL2 may be formed by including a liquid-repellent additive. For example, the second pixel defining portion PDL2 may be formed by including a polymer resin and a liquid-repellent additive. In one or more embodiments, the liquid-repellent additive may include fluorine. For example, the liquid-repellent additive may include a fluorine compound. The second pixel defining portion PDL2 may be formed by including a liquid-repellent additive including a fluorine compound. Since the pixel defining layer PDL includes a liquid-repellent portion including a liquid-repellent additive, the ink may contact the surface of the liquid-repellent portion during the inkjet process, which will be explained later, and thus an overflow phenomenon of the ink may be prevented or reduced.

[0264] FIG. 11A to FIG. 11F The step of forming the intermediate layer on the first sub-electrode EL1-1, the second sub-electrode EL1-2, and the third sub-electrode EL1-3 is illustrated. In one or more embodiments, the step of forming the intermediate layer may be performed by an inkjet process.

[0265] refer to Fig.11A and Fig. 11B , a first hole transport region HTR1, a second hole transport region HTR2, and a third hole transport region HTR3 may be formed on the first sub-electrode EL1-1, the second sub-electrode EL1-2, and the third sub-electrode EL1-3. In one or more embodiments, the step of forming the first hole transport region HTR1, the second hole transport region HTR2, and the third hole transport region HTR3 may be performed by an inkjet process. The hole transport region ink IK-HT may be applied on the first sub-electrode EL1-1, the second sub-electrode EL1-2, and the third sub-electrode EL1-3 to form the first hole transport region HTR1, the second hole transport region HTR2, and the third hole transport region HTR3. The hole transport region ink IK-HT may be applied by the first nozzle NZ-A. The first hole transport region HTR1, the second hole transport region HTR2, and the third hole transport region HTR3 may be formed in the first pixel opening OH-1, the second pixel opening OH-2, and the third pixel opening OH-3.

[0266] refer to Fig. 11C and Fig.11D, a first emission layer EML1, a second emission layer EML2, and a third emission layer EML3 may be formed on the first hole transport region HTR1, the second hole transport region HTR2, and the third hole transport region HTR3. In one or more embodiments, the steps of forming the first hole transport region HTR1, the second hole transport region HTR2, and the third hole transport region HTR3 may be performed by an inkjet process. The first emission layer ink IK-Q1, the second emission layer ink IK-Q2, and the third emission layer ink IK-Q3 may be applied to the first hole transport region HTR1, the second hole transport region HTR2, and the third hole transport region HTR3 to form the first emission layer EML1, the second emission layer EML2, and the third emission layer EML3. The first emission layer ink IK-Q1 may be applied to the first pixel opening portion OH-1 to form the first emission layer EML1. The second emission layer ink IK-Q2 may be applied to the second pixel opening portion OH-2 to form the second emission layer EML2. The third emission layer ink IK-Q3 may be applied to the third pixel opening OH-3 to form the third emission layer EML3. The first emission layer ink IK-Q1, the second emission layer ink IK-Q2, and the third emission layer ink IK-Q3 may be applied through the second nozzle, respectively. The second nozzle may include a first sub-nozzle NZ-E1 for applying the first emission layer ink IK-Q1, a second sub-nozzle NZ-E2 for applying the second emission layer ink IK-Q2, and a third sub-nozzle NZ-E3 for applying the third emission layer ink IK-Q3.

[0267] The first emission layer ink IK-Q1, the second emission layer ink IK-Q2, and the third emission layer ink IK-Q3 can be applied to the first pixel opening OH-1, the second pixel opening OH-2, and the third pixel opening OH-3 by an inkjet printing method to form the first emission layer EML1, the second emission layer EML2, and the third emission layer EML3. The first emission layer ink IK-Q1, the second emission layer ink IK-Q2, and the third emission layer ink IK-Q3 can each independently include an organic light emitting body or an inorganic light emitting body.

[0268] refer to Fig.11E and Fig.11F, a first electron transport region ETR1, a second electron transport region ETR2, and a third electron transport region ETR3 may be formed on the first emission layer EML1, the second emission layer EML2, and the third emission layer EML3. In one or more embodiments, the steps of forming the first electron transport region ETR1, the second electron transport region ETR2, and the third electron transport region ETR3 may be performed by an inkjet process. The electron transport region ink IK-ET may be applied on the first emission layer EML1, the second emission layer EML2, and the third emission layer EML3 to form the first electron transport region ETR1, the second electron transport region ETR2, and the third electron transport region ETR3. The electron transport region ink IK-ET may be applied by a third nozzle NZ-B. The first electron transport region ETR1, the second electron transport region ETR2, and the third electron transport region ETR3 may be formed in the first pixel opening OH-1, the second pixel opening OH-2, and the third pixel opening OH-3.

[0269] pass FIG. 11A to FIG. 11F Then, an intermediate layer may be formed on the first sub-electrode EL1-1, the second sub-electrode EL1-2 and the third sub-electrode EL1-3 by a process. FIG. 8D to FIG. 8Q , FIG. 10A to FIG. 10K The second electrode EL2, the optical layer OPL, and the encapsulation layer TFE are formed by the same method or substantially the same method as described in to form the display panel DP.

[0270] Fig.11G and Fig.11H 1 is a diagram illustrating a step of providing a preliminary first peeling layer P-LOL1 and a step of etching in a method for manufacturing a display device according to one or more embodiments of the present disclosure. Fig.11G and Fig.11H The step of etching the preliminary first peeling layer P-LOL1 shown in Figure 8H and Fig.8I The etching of the preliminary first peeling layer P-LOL1 corresponds to the above-mentioned step.

[0271] refer to Fig.11G In the step of providing the preliminary first peeling layer P-LOL1, the preliminary first peeling layer P-LOL1 may be formed on the intermediate layer and the pixel defining layer PDL.

[0272] refer to Fig.11G and Fig.11H, in the step of etching the preliminary first peeling layer P-LOL1, the first solvent SV1 may be applied on the preliminary first peeling layer P-LOL1. As described above, the first solvent SV1 including fluorine may be used to etch the preliminary first peeling layer P-LOL1 including a fluoropolymer. By processing using the first solvent SV1, the preliminary first peeling layer P-LOL1 corresponding to the display area DA may be removed. In this case, a portion of the second pixel defining portion PDL2 of the pixel defining layer PDL may be dissolved in the first solvent SV1 and removed. Therefore, the top of the second pixel defining portion PDL2 may have an irregular surface roughness.

[0273] According to one or more embodiments of the present disclosure, a method for manufacturing a display device in which a manufacturing process is simplified may be provided.

[0274] Although the embodiments of the present disclosure have been described, it should be understood that the present disclosure should not be limited to these embodiments, but a person skilled in the art will be able to make various suitable changes and modifications within the spirit and scope of the present disclosure as defined by the appended claims and their equivalents.

Claims

1. A method for manufacturing a display device, the method for manufacturing a display device comprising: Prepare a substrate including a display region, a pad region, a peripheral region, a first electrode and an intermediate layer, wherein the first electrode and the intermediate layer are in the display region; forming a preliminary first peeling layer on the substrate; forming a first photoresist pattern on the preliminary first peeling layer and defining a light opening portion overlapping the display area; etching the preliminary first peeling layer to form a first peeling layer exposing the display area; forming a second electrode on the intermediate layer through the optical opening; as well as The first lift-off layer and the first photoresist pattern are removed.

2. The method for manufacturing a display device according to claim 1, further comprising: After the second electrode is formed, an optical layer is formed on the second electrode through the light opening.

3. The method for manufacturing a display device according to claim 1, wherein: The first peeling layer overlaps the pad region in a plane.

4. The method for manufacturing a display device according to claim 1, wherein: The first release layer includes polytetrafluoroethylene.

5. The method for manufacturing a display device according to claim 1, wherein: Forming the first peeling layer includes: The preliminary first lift-off layer is etched by a first solvent containing fluorine by using the first photoresist pattern as a mask.

6. The method for manufacturing a display device according to claim 5, wherein: The first solvent includes a hydrofluoroether.

7. The method for manufacturing a display device according to claim 1, wherein: Removing the first lift-off layer and the first photoresist pattern includes: The first lift-off layer and the first photoresist pattern are treated with a second solvent including fluorine.

8. The method for manufacturing a display device according to claim 1, wherein: Preparing the substrate comprises: Prepare a base substrate defining the display area and the pad area; forming the first electrode on the base substrate to overlap the display area; forming a pixel defining layer defining a pixel opening portion exposing a portion of the first electrode and including a liquid repellent portion including a liquid repellent material; and The intermediate layer is formed on the first electrode.

9. The method for manufacturing a display device according to claim 8, wherein: During the formation of the first peeling layer, at least a portion of the liquid-repellent portion is removed by an etching process.

10. The method for manufacturing a display device according to claim 8, wherein: Forming the intermediate layer comprises: forming a hole transport region on the first electrode; forming an emission layer on the hole transport region; and An electron transport region is formed on the emission layer.

11. The method for manufacturing a display device according to claim 8, wherein: The forming of the intermediate layer is performed by an inkjet process.

12. The method for manufacturing a display device according to claim 1, wherein: Forming the second electrode is performed by a deposition process.

13. The method for manufacturing a display device according to claim 1, further comprising: forming a preliminary second peeling layer on the substrate; forming a second photoresist pattern overlapping the pad region on the preliminary second peeling layer; etching the preliminary second peeling layer to form a second peeling layer exposing the display area; forming an encapsulation layer on the second electrode using the second photoresist pattern as a mask; as well as The second lift-off layer and the second photoresist pattern are removed.

14. The method for manufacturing a display device according to claim 13, wherein: The second peeling layer does not overlap the display area on a plane, and does not overlap the peripheral area on the plane.

15. The method for manufacturing a display device according to claim 13, wherein: Forming the second peeling layer includes: The preliminary second lift-off layer is etched by a third solvent containing fluorine by using the second photoresist pattern as a mask.

16. The method for manufacturing a display device according to claim 13, wherein: Removing the second lift-off layer and the second photoresist pattern comprises: The second lift-off layer and the second photoresist pattern are treated with a fourth solvent including fluorine.

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