Array substrate and touch display device

Abstract

An array substrate and a touch display device are provided. The array substrate comprises: a substrate including a plurality of pixels; a pixel electrode; a touch sensing block including a plurality of touch electrodes; a touch signal line, each touch sensing block being connected with at least one touch signal line; a first connection line, two adjacent rows of touch electrodes in each touch sensing block being connected by the first connection line; a second connection line not overlapping with the touch signal line, the pixel electrode being connected with a TFT by the second connection line. The pixel structure is a Z-architecture pixel. Each adjacent four pixels are a repeating unit, each repeating unit including four adjacent sub-pixels arranged in two rows and two columns, pixel electrodes of two diagonally opposite sub-pixels being connected with a TFT by the second connection line respectively, and touch electrodes of the other two diagonally opposite sub-pixels being connected by the first connection line.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and more particularly to an array substrate and a touch display device including the array substrate. Background Technology

[0002] Touch display panels, as an important tool for human-computer interaction, are widely used in display products such as smartphones, tablets, laptops, and monitors. Among various types of touch display panels, capacitive touch display panels are widely used due to their advantages such as higher sensitivity and multi-touch capability. Summary of the Invention

[0003] According to one aspect of this disclosure, an array substrate is provided, comprising: a substrate including a plurality of pixels arranged in an array, the plurality of pixels including a plurality of sub-pixels arranged in an array, each of the plurality of sub-pixels including a pixel electrode, a touch electrode, and a thin-film transistor; a plurality of touch sensing blocks located on the substrate and electrically insulated from each other, each touch sensing block including a plurality of the touch electrodes, the plurality of touch electrodes of each touch sensing block being electrically connected to each other and arranged in an array; a plurality of gate lines extending along a first direction, each row of sub-pixels being associated with two of the plurality of gate lines; and a plurality of gate lines extending along a second direction. The device includes a touch signal line and multiple data lines, the touch signal line and the data lines being located on the same layer, each touch sensing block being electrically connected to at least one of the multiple touch signal lines, and the first direction and the second direction being intersected; a first connecting line, through which two adjacent rows of touch electrodes in each touch sensing block are electrically connected; and a second connecting line, through which at least a portion of the multiple pixel electrodes are electrically connected to the drain of a corresponding thin-film transistor, the orthographic projection of the second connecting line on the substrate not overlapping the orthographic projection of the touch signal line on the substrate. The gate of the thin-film transistor (TFT) of each sub-pixel is electrically connected to the gate line, the drain of the TFT of each sub-pixel is electrically connected to the pixel electrode of that sub-pixel, and the source of the TFT of each sub-pixel is electrically connected to the data line. Each pair of adjacent sub-pixels in the same row forms a unit group, and the sources of the TFTs in each unit group are electrically connected to the same data line. The gates of the TFTs in each unit group are electrically connected to different gate lines. Furthermore, the sources of the TFTs of adjacent sub-pixels in the same column are electrically connected to different data lines. Each set of four adjacent pixels forms a repeating unit, and each repeating unit includes four adjacent sub-pixels arranged in two rows and two columns. The pixel electrodes of two sub-pixels located in different rows and diagonally opposite each other are electrically connected to the drain of a corresponding TFT via the second connecting line. The touch electrodes of the other two sub-pixels located in different rows and diagonally opposite each other are electrically connected via the first connecting line.

[0004] In some embodiments, the array substrate further includes a third connection line, wherein each of a portion of the plurality of pixel electrodes is electrically connected to the drain of a corresponding thin-film transistor via the second connection line, and each of the remaining portions of the plurality of pixel electrodes is electrically connected to the drain of a corresponding thin-film transistor via the third connection line, wherein the orthographic projection of the third connection line on the substrate partially overlaps with the orthographic projection of the touch signal line on the substrate.

[0005] In some embodiments, the orthographic projection of the third connecting line on the substrate does not overlap with the orthographic projection of the first connecting line on the substrate.

[0006] In some embodiments, the portion where the orthographic projection of the third connecting line on the substrate overlaps with the orthographic projection of the touch signal line on the substrate constitutes a first overlapping region, and the areas of all first overlapping regions are equal to each other.

[0007] In some embodiments, the array substrate further includes a plurality of common connection lines extending along the first direction. Each of the plurality of common connection lines is arranged between two adjacent rows of sub-pixels, and each touch electrode in the same row within each touch sensing block is electrically connected to each other via the common connection line, and each common connection line is disconnected at the interval between two adjacent touch sensing blocks.

[0008] In some embodiments, a data line is provided at the interval region between any two adjacent touch sensing blocks along the first direction. The disconnected portion of the common connection line at the interval region is located on the first side of the data line. The continuous portion of the common connection line includes a first sub-part, a second sub-part, and a third sub-part connected in sequence. The first sub-part is located on the second side of the data line, the third sub-part is located on the first side of the data line, the second sub-part is located between the first sub-part and the third sub-part, and the orthographic projection of the second sub-part on the substrate falls within the orthographic projection of the data line on the substrate.

[0009] In some embodiments, the length of the third sub-part along the first direction is greater than or equal to a first threshold.

[0010] In some embodiments, the array substrate further includes a fourth connection line. A first end of the fourth connection line is electrically connected to a touch electrode of one of two adjacent touch sensing blocks along the second direction, and a second end of the fourth connection line is disconnected from the touch electrode of the other of the two adjacent touch sensing blocks along the second direction, such that the two adjacent touch sensing blocks along the second direction are electrically insulated from each other.

[0011] In some embodiments, the orthographic projection of the fourth connection line on the substrate spans the orthographic projections of two gate lines located between any two adjacent touch sensing blocks along the second direction on the substrate, and the second end of the fourth connection line extends beyond the gate line closest to the second end of the two gate lines by a distance greater than or equal to a second threshold.

[0012] In some embodiments, the orthographic projection of the first connecting line on the substrate partially overlaps with the orthographic projection of the touch signal line on the substrate, and the extension direction of the first connecting line at the overlap is perpendicular to the extension direction of the touch signal line at the overlap.

[0013] In some embodiments, each touch sensing block is electrically connected to at least one of the plurality of touch signal lines via a via, and the orthographic projection of the via on the substrate does not overlap with the orthographic projection of the first connection line on the substrate.

[0014] In some embodiments, the orthographic projection of the first connecting line on the substrate partially overlaps with the orthographic projection of the touch signal line on the substrate, and a first connecting line is provided between two adjacent rows of sub-pixels in each repeating unit.

[0015] In some embodiments, each repeating unit is further provided with a compensation line, the orthographic projection of the compensation line on the substrate partially overlaps with the orthographic projection of the touch signal line on the substrate, and the touch signal line overlapping with the compensation line and the touch signal line overlapping with the first connecting line in each repeating unit are two different touch signal lines.

[0016] In some embodiments, the compensation line includes a sub-section extending along the first direction, the orthographic projection of the sub-section on the substrate partially overlapping the orthographic projection of the touch signal line on the substrate, and both opposite ends of the sub-section extending beyond the touch signal line in the first direction.

[0017] In some embodiments, the orthographic projection of the compensation line on the substrate does not overlap with the orthographic projection of the gate line and the common connection line on the substrate.

[0018] In some embodiments, the line width of the compensation line is equal to the line width of the first connecting line.

[0019] In some embodiments, the portion where the orthographic projection of the compensation line on the substrate overlaps with the orthographic projection of the touch signal line on the substrate constitutes a second overlap region, and the areas of all second overlap regions are equal to each other.

[0020] In some embodiments, the line width of the touch signal line is greater than the line width of the data line.

[0021] In some embodiments, the touch signal line includes a first portion and a second portion, wherein the line width of the first portion is smaller than the line width of the second portion.

[0022] In some embodiments, the array substrate further includes a light-shielding layer located on the side of the touch signal line and the data line away from the substrate. The light-shielding layer includes a first light-shielding portion and a second light-shielding portion. The orthographic projection of the data line onto the substrate falls within the orthographic projection of the first light-shielding portion onto the substrate, and the orthographic projection of the touch signal line onto the substrate falls within the orthographic projection of the second light-shielding portion onto the substrate. The width of the first light-shielding portion along the first direction is a first width, the width of the second light-shielding portion along the first direction is a second width, and the width of each sub-pixel along the first direction is a third width. The first width, the second width, and the third width satisfy the following condition: the ratio of the absolute value of the difference between the first width and the second width to twice the third width is less than or equal to 5%.

[0023] In some embodiments, the orthographic projection of the data line on the substrate does not overlap with the orthographic projection of the touch electrode on the substrate, and the orthographic projection of the touch signal line on the substrate does not overlap with the orthographic projection of the touch electrode on the substrate.

[0024] In some embodiments, a data line is arranged every two columns of sub-pixels, and at least some of the data lines are arranged between two adjacent columns of sub-pixels; and a touch signal line is arranged every two columns of sub-pixels, and each touch signal line is arranged between two adjacent columns of sub-pixels and between two adjacent data lines.

[0025] In some embodiments, the orthographic projection of the touch electrode within each sub-pixel onto the substrate at least partially overlaps with the orthographic projection of the pixel electrode within that sub-pixel onto the substrate. For each data line and two columns of sub-pixels located on either side of that data line, the distance between the orthographic projection of the touch electrode within each column of sub-pixels onto the substrate and the orthographic projection of the data line onto the substrate is a first distance, and the distance between the orthographic projection of the pixel electrode within each column of sub-pixels onto the substrate and the orthographic projection of the data line onto the substrate is a second distance, wherein the second distance is greater than the first distance and the difference between the second distance and the first distance is greater than or equal to a third threshold.

[0026] In some embodiments, for each touch signal line and two columns of sub-pixels located on both sides of the touch signal line, the distance between the orthographic projection of the touch electrode in each column of the two sub-pixels on the substrate and the orthographic projection of the touch signal line on the substrate is a third distance, and the distance between the orthographic projection of the pixel electrode in each column of the two sub-pixels on the substrate and the orthographic projection of the touch signal line on the substrate is a fourth distance, wherein the fourth distance is greater than the third distance and the difference between the fourth distance and the third distance is greater than or equal to the third threshold.

[0027] In some embodiments, the ratio of the number of data lines to the number of touch signal lines is 1:2, one data line is arranged every two columns of sub-pixels, two touch signal lines are arranged every two columns of sub-pixels, and the two touch signal lines are arranged between adjacent columns of sub-pixels.

[0028] In some embodiments, the touch electrode is located on the substrate, the gate line is located on the side of the touch electrode away from the substrate, the data line and the touch signal line are located on the side of the gate line away from the substrate, and the pixel electrode and the first connection line are located on the same layer and both are located on the side of the data line away from the substrate.

[0029] In some embodiments, the pixel electrode is located on the substrate, the gate line is located on the side of the pixel electrode away from the substrate, the data line and the touch signal line are located on the side of the gate line away from the substrate, and the touch electrode and the first connection line are located on the same layer and both are located on the side of the data line away from the substrate.

[0030] In some embodiments, the extension direction of the first connecting line is different from the extension direction of the touch signal line, and the orthographic projection of the first connecting line on the substrate and the orthographic projection of the touch signal line on the substrate at most overlap by a portion.

[0031] In some embodiments, each touch sensing block is electrically connected to at least one of the plurality of touch signal lines via a via, and the orthographic projection of the via on the substrate lies between the orthographic projections of two gate lines between two adjacent rows of sub-pixels on the substrate.

[0032] In some embodiments, the first connecting line extends in the same direction as the touch signal line, and the orthographic projection of the first connecting line on the substrate falls within the orthographic projection of the touch signal line on the substrate.

[0033] In some embodiments, the array substrate further includes a liquid crystal layer, the touch electrode and the pixel electrode are located on the same side of the liquid crystal layer, and the material of the touch electrode and the pixel electrode includes indium tin oxide.

[0034] In some embodiments, each pixel includes a first sub-pixel, a second sub-pixel, and a third sub-pixel arranged sequentially along the first direction. The four adjacent pixels of each repeating unit are arranged in two rows and two columns and include a first pixel, a second pixel, a third pixel, and a fourth pixel. The first pixel and the second pixel are located in the same row and the first pixel and the third pixel are located in the same column. The third pixel and the fourth pixel are located in the same row and the second pixel and the fourth pixel are located in the same column. The sources of the thin-film transistors of the first and second sub-pixels of the first pixel are both electrically connected to the first data line among the multiple data lines. The sources of the thin-film transistors of the third sub-pixel of the first pixel and the first sub-pixel of the second pixel are both electrically connected to the second data line among the multiple data lines. The sources of the thin-film transistors of the second and third sub-pixels of the second pixel are both electrically connected to the third data line among the multiple data lines. The sources of the thin-film transistors of the first and second sub-pixels of the third pixel are both electrically connected to the second data line. The sources of the thin-film transistors of the third sub-pixel of the third pixel and the first sub-pixel of the fourth pixel are both electrically connected to the third data line. Furthermore, the sources of the thin-film transistors of the second and third sub-pixels of the fourth pixel are both electrically connected to the fourth data line among the multiple data lines.

[0035] In some embodiments, the gates of the thin-film transistors of all first sub-pixels in the same row of pixels are electrically connected to the first gate line of the two gate lines, the gates of the thin-film transistors of all second sub-pixels in the same row of pixels are electrically connected to the second gate line of the two gate lines, and the gates of the thin-film transistors of the third sub-pixels of two adjacent pixels in the same row of pixels are electrically connected to the first gate line and the second gate line, respectively.

[0036] According to another aspect of this disclosure, a touch display device is provided, which includes an array substrate described in any of the preceding embodiments. Attached Figure Description

[0037] To more clearly describe the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0038] Figure 1A schematic diagram showing the arrangement of pixel structures on an array substrate according to an embodiment of the present disclosure is provided.

[0039] Figure 2 The arrangement of touch sensing blocks according to an embodiment of the present disclosure is shown;

[0040] Figure 3 It shows Figure 2 A magnified view of a portion of region I;

[0041] Figure 4 A plan view of a partial structure of an array substrate according to an embodiment of the present disclosure is shown;

[0042] Figure 5 It shows Figure 4 A magnified view of a portion of region II;

[0043] Figure 6 It shows Figure 4 A magnified view of a portion of region III;

[0044] Figure 7 It shows Figure 4 A magnified view of a portion of region IV;

[0045] Figure 8 The structural design of adjacent touch sensing blocks at the break point according to an embodiment of the present disclosure is shown;

[0046] Figure 9 A schematic diagram showing the arrangement of a partial structure of an array substrate according to an embodiment of the present disclosure is provided.

[0047] Figure 10 It shows Figure 4 A magnified view of a portion of region V;

[0048] Figure 11 It shows Figure 2 A magnified view of a portion of a touch sensor block;

[0049] Figure 12 It shows along Figure 4 A schematic diagram of the cross-section taken by the AA′ line;

[0050] Figure 13 It shows along Figure 4 A schematic diagram of the cross-section taken by the BB′ line;

[0051] Figure 14 A plan view of a partial structure of an array substrate according to another embodiment of the present disclosure is shown;

[0052] Figure 15 It shows Figure 14 A magnified view of a portion of region VI;

[0053] Figure 16 It shows Figure 14 A partial enlarged view of region VII; and

[0054] Figure 17 A block diagram of a touch display device according to an embodiment of the present disclosure is shown. Detailed Implementation

[0055] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0056] Touchscreen displays offer a more user-friendly interaction method, which can greatly improve user efficiency and comfort, and have therefore become one of the mainstream displays in the display field.

[0057] Figure 1 This is a schematic diagram of the pixel structure arrangement of the array substrate 100 according to an embodiment of the present disclosure. Figure 2 This is a schematic diagram showing the arrangement of multiple touch sensing blocks on the array substrate 100. Figure 3 yes Figure 2 A magnified view of area I, enclosed by a dashed rectangle. Figure 4 This is a planar schematic diagram of a partial structure of the array substrate 100. Figure 5 for Figure 4 A magnified view of area II, enclosed by a dashed rectangle. (See attached image.) Figures 1 to 5As shown, the array substrate 100 includes: a substrate 101, which includes a plurality of pixels arranged in an array, each pixel including a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3 arranged sequentially along a first direction D1, the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 being configurable to emit light of different colors; in one example, the first sub-pixel SP1 can be configured to emit red light, the second sub-pixel SP2 can be configured to emit green light, and the third sub-pixel SP3 can be configured to emit blue light; a plurality of pixel electrodes 102 located on the substrate 101, each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 having a pixel electrode 102 disposed therein; a plurality of touch sensing blocks 103 located on the substrate 101 and electrically insulated from each other, each touch sensing block 103 including a plurality of touch electrodes 104 electrically connected to each other and arranged in multiple rows, each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 having a touch electrode 104 disposed therein; and a first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 being arranged in multiple rows along a first direction D1; and a first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 being configurable to emit light of different colors ... Multiple touch signal lines TX extending along the second direction D2, each touch sensing block 103 is electrically connected to at least one of the multiple touch signal lines TX; multiple thin-film transistors 111 located on the substrate 101, each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 includes at least one thin-film transistor 111; multiple data lines Data extending along the second direction D2, the touch signal lines TX and the data lines Data are located on the same layer; multiple gate lines Gate extending along the first direction D1, each row of sub-pixels is electrically connected to multiple... Two gate lines in the gate line are associated; a first connection line 107 is used to electrically connect two adjacent rows of touch electrodes 104 in each touch sensing block 103; and a second connection line 109 is used to electrically connect at least a portion of the plurality of pixel electrodes 102 to the drain 111B of one of the plurality of thin film transistors 111, and the orthographic projection of the second connection line 109 on the substrate 101 does not overlap with the orthographic projection of the touch signal line TX on the substrate 101.

[0058] The gate 111A of the thin-film transistor 111 of each sub-pixel is electrically connected to the gate line Gate, the drain 111B of the thin-film transistor 111 of each sub-pixel is electrically connected to the pixel electrode 102 of that sub-pixel, and the source 111C of the thin-film transistor 111 of each sub-pixel is electrically connected to the data line Data. Every two adjacent sub-pixels in the same row form a unit group. The source 111C of the thin-film transistor 111 in each unit group is electrically connected to the same data line Data. The gate 111A of the thin-film transistor 111 in each unit group is electrically connected to different gate lines Gate. Furthermore, the source 111C of the thin-film transistor 111 of two adjacent sub-pixels in the same column is electrically connected to different data lines Data. This pixel arrangement of the array substrate 100 can be called a Z-architecture pixel. Using Z-architecture pixels, even if there are differences in the charging status of adjacent data lines Data, there will be no display differences between adjacent pixel columns, thereby avoiding defects such as vertical lines or head-shaking lines.

[0059] In a plurality of pixels, every four adjacent pixels form a repeating unit. Each repeating unit includes four adjacent sub-pixels, which are arranged in two rows and two columns. The pixel electrodes 102 of two sub-pixels located in different rows and diagonally opposite each other are electrically connected to the drain 111B of a corresponding thin-film transistor 111 via a second connection line 109. The touch electrodes 104 of the other two sub-pixels located in different rows and diagonally opposite each other are electrically connected via a first connection line 107. For example, Figure 5 The diagram illustrates the local structure of four adjacent sub-pixels within a repeating unit. These four sub-pixels are located at the i-th row and j-th column, the i-th row and (j+1)-th column, the (i+1)-th row and j-th column, and the (i+1)-th row and (j+1)-th column, where i and j are positive integers greater than or equal to 1. Figure 5 As shown, the sub-pixel located in the i-th row and j+1-th column and the sub-pixel located in the i+1-th row and j-th column are located in different rows and are obliquely opposite each other. The pixel electrodes 102 of these two sub-pixels are electrically connected to the drain 111B of a corresponding thin film transistor 111 through the second connection line 109, and the orthographic projection of the second connection line 109 on the substrate 101 does not overlap with the orthographic projection of the touch signal line TX1 on the substrate 101. The sub-pixel located in the i-th row and j-th column and the sub-pixel located in the i+1-th row and j+1-th column are located in different rows and are obliquely opposite each other. The touch electrodes 104 of these two sub-pixels are electrically connected to each other through the first connection line 107, and the orthographic projection of the first connection line 107 on the substrate 101 partially overlaps with the orthographic projection of the touch signal line TX1 on the substrate 101.

[0060] In the array substrate 100, the touch electrodes 104 of two adjacent rows of sub-pixels in each touch sensing block 103 are connected via a first connection line 107. At least some pixel electrodes 102 are connected to the drain 111B of the thin-film transistor 111 via a second connection line 109. Since the second connection line 109 does not cross the touch signal line TX, the connection via the second connection line 109 can be called a "short connection". Because the orthographic projection of the first connection line 107 on the substrate 101 partially overlaps with the orthographic projection of the touch signal line TX on the substrate 101, i.e., the first connection line 107 needs to cross the touch signal line TX, while the orthographic projection of the second connection line 109 on the substrate 101 does not overlap with the orthographic projection of the touch signal line TX on the substrate 101, i.e., the second connection line 109 does not need to cross the touch signal line TX, the first connection line 107 can be set at the location of the second connection line 109, thereby making reasonable use of wiring space and avoiding unwanted coupling caused by messy wiring.

[0061] It should be noted that in this document, the terms "source 111C of thin-film transistor 111" and "drain 111B of thin-film transistor 111" are used interchangeably; that is, the source 111C of thin-film transistor 111 can also be called the drain 111B of thin-film transistor 111, and vice versa. It should be pointed out that a sub-pixel is typically the area enclosed by a gate line and a data line. The phrase "each sub-pixel includes at least one thin-film transistor 111" means that each sub-pixel is configured with at least one thin-film transistor 111 (e.g., the pixel electrode 102 of each sub-pixel is electrically connected to the drain 111B of the thin-film transistor 111), but this does not restrict the thin-film transistor 111 to be located within the sub-pixel's area. For example, due to different connection methods of the thin-film transistor 111, the thin-film transistor 111 of some sub-pixels may not be completely located within the sub-pixel's area. Additionally, in this document, terms such as "A and B are located in the same layer" mean that A and B are fabricated from the same material using the same process, but do not require that A and B have exactly the same thickness or height. The phrase "each row of sub-pixels is associated with two of the multiple gate lines" means that the gate 111A of each thin-film transistor 111 in the same row of sub-pixels is connected to two different gate lines.

[0062] In some embodiments, the gates 111A of the thin-film transistors 111 electrically connected to the pixel electrode 102 of the first sub-pixel SP1 in the same row of pixels are all electrically connected to the first gate line of the two gate lines; the gates 111A of the thin-film transistors 111 electrically connected to the pixel electrode 102 of the second sub-pixel SP2 in the same row of pixels are all electrically connected to the second gate line of the two gate lines; and the gates 111A of the thin-film transistors 111 electrically connected to the pixel electrodes 102 of the third sub-pixels SP3 of the same row of pixels, respectively, are electrically connected to the first gate line and the second gate line, respectively. For example, Figure 1Three rows of pixels are shown. The first row of pixels is associated with the first gate line Gate1 and the second gate line Gate2. The first row of pixels includes adjacent pixels P1 and P2. The gate 111A of the thin film transistor 111 electrically connected to the pixel electrode 102 of the first sub-pixel SP1 of pixels P1 and P2 is electrically connected to the first gate line Gate1. The gate 111A of the thin film transistor 111 electrically connected to the pixel electrode 102 of the second sub-pixel SP2 of pixels P1 and P2 is electrically connected to the second gate line Gate2. The gate 111A of the thin film transistor 111 electrically connected to the pixel electrode 102 of the third sub-pixel SP3 of pixel P1 is electrically connected to the second gate line Gate2. The gate 111A of the thin film transistor 111 electrically connected to the pixel electrode 102 of the third sub-pixel SP3 of pixel P2 is electrically connected to the first gate line Gate1. The second row of pixels is associated with the first gate line Gate3 and the second gate line Gate4. The second row of pixels includes adjacent pixels P3 and P4. The gate 111A of the thin film transistor 111 electrically connected to the pixel electrode 102 of the first sub-pixel SP1 of pixels P3 and P4 is electrically connected to the first gate line Gate3. The gate 111A of the thin film transistor 111 electrically connected to the pixel electrode 102 of the second sub-pixel SP2 of pixels P3 and P4 is electrically connected to the second gate line Gate4. The gate 111A of the thin film transistor 111 electrically connected to the pixel electrode 102 of the third sub-pixel SP3 of pixel P3 is electrically connected to the second gate line Gate4. The gate 111A of the thin film transistor 111 electrically connected to the pixel electrode 102 of the third sub-pixel SP3 of pixel P4 is electrically connected to the first gate line Gate3. The third row of pixels is associated with the first gate line Gate5 and the second gate line Gate6. The third row of pixels includes adjacent pixels P5 and P6. The gate 111A of the thin film transistor 111 electrically connected to the pixel electrode 102 of the first sub-pixel SP1 of pixels P5 and P6 is electrically connected to the first gate line Gate5. The gate 111A of the thin film transistor 111 electrically connected to the pixel electrode 102 of the second sub-pixel SP2 of pixels P5 and P6 is electrically connected to the second gate line Gate6. The gate 111A of the thin film transistor 111 electrically connected to the pixel electrode 102 of the third sub-pixel SP3 of pixel P5 is electrically connected to the second gate line Gate6. The gate 111A of the thin film transistor 111 electrically connected to the pixel electrode 102 of the third sub-pixel SP3 of pixel P6 is electrically connected to the first gate line Gate5.

[0063] In the array substrate 100, every four adjacent pixels form a repeating unit, and these four adjacent pixels are arranged in two rows and two columns, including a first pixel, a second pixel, a third pixel, and a fourth pixel. For example, Figure 1In this diagram, four adjacent pixels P1, P2, P3, and P4 form a repeating unit. These four pixels are arranged in two rows and two columns. Pixel P1 can be designated as the first pixel P1, pixel P2 as the second pixel P2, pixel P3 as the third pixel P3, and pixel P4 as the fourth pixel P4. The first pixel P1 and the second pixel P2 are in the same row, and the first pixel P1 and the third pixel P3 are in the same column. The third pixel P3 and the fourth pixel P4 are in the same row, and the second pixel P2 and the fourth pixel P4 are in the same column. The source 111C of the thin-film transistor 111 electrically connected to the pixel electrode 102 of the first sub-pixel SP1 and the second sub-pixel SP2 of the first pixel P1 is electrically connected to the first data line Data1 of the multiple data lines Data. The source 111C of the thin-film transistor 111 electrically connected to the pixel electrode 102 of the third sub-pixel SP3 of the first pixel P1 and the first sub-pixel SP1 of the second pixel P2 is electrically connected to the second data line Data2 of the multiple data lines Data. The source 111C of the thin-film transistor 111 electrically connected to the pixel electrode 102 of the second sub-pixel SP2 and the third sub-pixel SP3 of the second pixel P2 is electrically connected to the third data line Data2 of the multiple data lines Data. The source 111C of the thin-film transistor 111, which is electrically connected to the pixel electrode 102 of the first sub-pixel SP1 and the second sub-pixel SP2 of the third pixel P3, is electrically connected to the second data line Data2. The source 111C of the thin-film transistor 111, which is electrically connected to the pixel electrode 102 of the third sub-pixel SP3 of the third pixel P3 and the first sub-pixel SP1 of the fourth pixel P4, is electrically connected to the third data line Data3. Furthermore, the source 111C of the thin-film transistor 111, which is electrically connected to the pixel electrode 102 of the second sub-pixel SP2 and the third sub-pixel SP3 of the fourth pixel P4, is electrically connected to the fourth data line Data4 among the multiple data lines Data.

[0064] It should be noted that, Figure 1 This example illustrates one arrangement of Z-architecture pixels on the array substrate 100. However, this does not limit the array substrate 100 to only this one pixel arrangement; other Z-architecture pixel arrangements are also possible. Using Z-architecture pixels ensures that even if adjacent data lines have different charging conditions, there will be no display differences between adjacent pixel columns, thus avoiding undesirable phenomena such as vertical lines or wavering.

[0065] The array substrate 100 can be an array substrate for a touch display device, and can be combined with Figure 2 This will give a general description of the touch control principle of a touch display device. The touch display device can be an embedded touch display device that uses self-capacitive touch technology. For example... Figure 2As shown, the array substrate 100 includes a plurality of touch sensing blocks 103 (as self-capacitance electrodes) arranged in an array and touch signal lines TX electrically connected to the touch sensing blocks 103 respectively. The touch signal lines TX electrically connect the touch sensing blocks 103 to the touch control circuit 105. When a touch is applied, the object being touched (e.g., a human finger) touches the touch display device, and the capacitance of the touch sensing block 103 located at the touch point changes. The touch control circuit 105 determines the touch position by detecting the change in self-capacitance of the touch sensing block 103.

[0066] In some embodiments, each pixel electrode 102 of the array substrate 100 is electrically connected to the drain 111B of a corresponding thin-film transistor 111 via a second connection line 109, that is, each pixel electrode 102 is electrically connected to the drain 111B of the thin-film transistor 111 in a short connection manner. In some alternative embodiments, some pixel electrodes 102 of the array substrate 100 are electrically connected to the drain 111B of a corresponding thin-film transistor 111 via the second connection line 109, and other pixel electrodes 102 of the array substrate 100 are electrically connected to the drain 111B of a corresponding thin-film transistor 111 via another connection line.

[0067] Figure 6 for Figure 4 A magnified view of area III, enclosed by a dashed rectangle, for reference. Figure 4 and Figure 6 The array substrate 100 may further include a third connection line 110, wherein a portion of the pixel electrodes 102 are electrically connected to the drain 111B of a corresponding thin-film transistor 111 via a second connection line 109, and the remaining pixel electrodes 102 are electrically connected to the drain 111B of a corresponding thin-film transistor 111 via the third connection line 110. The orthographic projection of the third connection line 110 on the substrate 101 is parallel to the touch signal line TX. Figure 6The touch signal line TX3 is shown as partially overlapping its orthographic projection on the substrate 101. Since the third connection line 110 needs to cross the touch signal line TX, the way the pixel electrode 102 is connected to the drain 111B of the thin-film transistor 111 via the third connection line 110 can be called a "long connection". In other words, in this alternative embodiment, a portion of the pixel electrode 102 is electrically connected to the drain 111B of the thin-film transistor 111 via a short connection, and a portion of the pixel electrode 102 is electrically connected to the drain 111B of the thin-film transistor 111 via a long connection. The length of the third connection line 110 is greater than the length of the second connection line 109. The specific values ​​of the lengths of the third connection line 110 and the second connection line 109 can be determined according to the specific design of the array substrate 100. In some embodiments, the first connection line 107, the second connection line 109, the third connection line 110, and the pixel electrode 102 can be located in the same layer. During the fabrication process, all four can be formed using the same material and the same photomask. Figure 4 and Figure 6 As shown, the orthographic projection of the third connection line 110 on the substrate 101 does not overlap with the orthographic projection of the first connection line 107 on the substrate 101. A first connection line 107 is provided between two adjacent rows of sub-pixels in each repeating unit. Since the first connection line 107 crosses the touch signal line TX, and the third connection line 110, located on the same layer as the first connection line 107, also crosses the touch signal line TX, the first connection line 107 is not provided at the location where the third connection line 110 is located. This avoids the first connection line 107 and the third connection line 110 from overlapping, causing crowded and messy wiring space, and thus generating undesirable parasitic capacitance. Since the second connection line 109 does not need to cross the touch signal line TX, the first connection line 107 can be provided at the location where the second connection line 109 is located, while the first connection line 107 is not provided at the location where the third connection line 110 is located.

[0068] In some embodiments, such as Figure 6 As shown, the portion where the orthographic projection of each third connection line 110 on the substrate 101 overlaps with the orthographic projection of the touch signal line TX3 on the substrate 101 constitutes a first overlap region R1, and the areas of all first overlap regions R1 are equal. In this way, it can be ensured that the overlap areas of all third connection lines 110 and touch signal lines TX are equal.

[0069] In some embodiments, a data line Data is arranged every two columns of sub-pixels, and at least some of the data lines Data are arranged between two adjacent columns of sub-pixels. A touch signal line TX is arranged every two columns of sub-pixels, and each touch signal line TX is arranged between two adjacent columns of sub-pixels and between two adjacent data lines Data.Figure 1 As shown, besides data lines Data1 and Data4, data lines Data2 and Data3 are arranged between two adjacent columns of sub-pixels. Touch signal line TX1 is arranged between two adjacent columns of sub-pixels and between data lines Data1 and Data2; touch signal line TX2 is arranged between two adjacent columns of sub-pixels and between data lines Data2 and Data3; and touch signal line TX3 is arranged between two adjacent columns of sub-pixels and between data lines Data3 and Data4. In this embodiment, the number of data lines Data in the array substrate 100 is equal to the number of touch signal lines TX, i.e., they are arranged in a 1:1 ratio. In the array substrate 100, one data line Data is arranged every two columns of sub-pixels. Compared to the conventional technology where one data line Data is arranged per column of sub-pixels, the wiring method of the array substrate 100 reduces the number of data lines by half. The remaining space can be used to arrange touch signal lines TX, thus without increasing the total number of signal lines or reducing the aperture ratio.

[0070] In some alternative embodiments, the ratio of the number of data lines (Data) to the number of touch signal lines (TX) on the array substrate 100 may not be 1:1. Instead, the ratio may be 1:2, meaning that one data line (Data) is arranged every two columns of sub-pixels, and two touch signal lines (TX) are arranged every two columns of sub-pixels, with the two touch signal lines (TX) adjacent to each other and arranged between adjacent columns of sub-pixels. Since large-size touch display panels typically require more touch electrodes 104, this wiring method is particularly suitable for large-size touch display panels, such as large-size touch displays or televisions larger than 55 inches.

[0071] The array substrate 100 can be used in In-Cell touch display panels. In On-Cell touch display panels, the touch electrodes are located on the outside of the display panel, while in-Cell touch display panels have the touch electrodes located inside the display panel. Compared to On-Cell touch display panels, In-Cell touch display panels have higher integration and are thinner and lighter, offering greater advantages in terms of cost and stability.

[0072] In some embodiments, the array substrate 100 may further include a liquid crystal layer (not shown), with the touch electrode 104 and pixel electrode 102 located on the same side of the liquid crystal layer. The pixel electrode 102 may be an electrode with a slit, and both the touch electrode 104 and the pixel electrode 102 are made of indium tin oxide (ITO). In other words, the array substrate 100 is a FIC (Full In Cell) touch process based on Advanced Super Dimension Switch (ADS) technology. ADS technology can overcome the problem of low light transmission efficiency of conventional in-plane switching (IPS) technology, and has advantages such as higher light transmission efficiency, hard screen, ultra-wide viewing angle, ultra-high color performance, and ultra-high speed motion picture processing. Therefore, it is more suitable for application in larger-sized In Cell touch display products.

[0073] Figure 7 for Figure 4 A magnified view of region IV, enclosed by a dashed rectangle. (See attached image.) Figure 7 As shown, in some embodiments, the orthographic projection of the first connecting line 107 on the substrate 101 partially overlaps with the orthographic projection of the touch signal line TX3 on the substrate 101, and the extension direction of the first connecting line 107 at the overlap is perpendicular to the extension direction of the touch signal line TX3 at the overlap. For example, the first connecting line 107 extends along a first direction D1 at the overlap, and the touch signal line TX3 extends along a second direction D2 at the overlap, with the first direction D1 and the second direction D2 being perpendicular to each other. The first connecting line 107 and the touch signal line TX3 are wired in a perpendicular crossover manner, which can reduce the overlap capacitance between the first connecting line 107 and the touch signal line TX3.

[0074] refer to Figure 3The array substrate 100 may further include a plurality of common connection lines 106 extending along a first direction D1, each common connection line 106 being arranged between two adjacent rows of sub-pixels and located on one side of either of two adjacent gate lines. In some embodiments, the common connection lines 106 and the gate lines are located on the same layer. Each touch electrode 104 located in the same row within each touch sensing block 103 is electrically connected to each other via the common connection lines 106, and each common connection line 106 is disconnected at the interval region S between two adjacent touch sensing blocks 103. Each common connection line 106 is electrically connected to the touch electrode 104 of a row, but since the touch electrodes 104 of the array substrate 100 are time-division multiplexed, each touch sensing block 103 needs to be independent of each other to achieve position detection during the touch phase. Therefore, each common connection line 106 is not continuous within the array substrate 100 and needs to be disconnected at the interval region S between adjacent touch sensing blocks 103. The common connection line 106 electrically connects the touch electrodes 104 of each row of sub-pixels in each touch sensing block 103 together, and the touch electrodes 104 of two adjacent rows of sub-pixels in each touch sensing block 103 are electrically connected via the first connection line 107. In this way, the touch electrodes 104 in each touch sensing block 103 can form an electrode network, which helps to improve the uniformity of the common voltage in the touch sensing block 103.

[0075] In the array substrate 100, the touch electrodes 104 are time-division multiplexed. During the display phase, the touch electrodes 104 serve as common electrodes; during the touch scanning phase, the touch electrodes 104 serve as touch sensing electrodes. Therefore, in the array substrate 100, the touch sensing blocks 103 need to be designed as multiple blocks that are separate from each other and electrically isolated to meet the touch position detection requirements. Each touch sensing block 103 is connected to the touch control circuit 105 through at least one touch signal line TX so that the touch control circuit 105 can locate the coordinates of the touch occurrence. In some embodiments, the shape of each touch sensing block 103 can be approximately square, and the side length of each touch sensing block 103 can be between 5mm and 15mm, depending on different panel sizes and application scenarios. The better the touch performance, the smaller the area of ​​a single touch sensing block 103 needs to be; the smaller the area of ​​the touch sensing block 103, the more touch sensing blocks 103 are required. Based on this principle, and taking into account both performance and cost, for medium and large-sized touch display products (such as TVs), one touch signal line TX can be designed within every two sub-pixels for display products of 55 inches 4K and below, and two touch signal lines TX can be designed within each sub-pixel for display products of 55 inches 4K and above.

[0076] Figure 8 The diagram illustrates the disconnection method of any four adjacent touch sensing blocks 103. The four touch sensing blocks 103 are arranged in two rows and two columns, and are independent and insulated from each other.

[0077] The disconnection of two adjacent touch sensing blocks 103 in the first direction D1 is achieved by disconnecting the common connection line 106. Specifically, a data line Data is provided at the interval region S between two adjacent touch sensing blocks 103 in the first direction D1, and the disconnected portion 106A of the common connection line 106 at the interval region S is located on the first side of the data line Data, such as... Figure 8 On the right side of the data line Data, the continuous portion of the common connection line 106 includes a first sub-section 1061, a second sub-section 1062, and a third sub-section 1063 connected in sequence. The first sub-section 1061 is located on the second side of the data line Data. The second side is, for example, Figure 8 To the left of the data line Data, the third sub-part 1063 is located on the first side of the data line Data, and the second sub-part 1062 is located between the first sub-part 1061 and the third sub-part 1063. The orthographic projection of the second sub-part 1062 onto the substrate 101 falls within the orthographic projection of the data line Data onto the substrate 101. (As...) Figure 8 As shown, the two boundaries of the second sub-section 1062 along the first direction D1 overlap with the two boundaries of the data line Data along the first direction D1, respectively. In some embodiments, the length L1 of the third sub-section 1063 along the first direction D1 is greater than or equal to a first threshold, which is, for example, the alignment deviation between the metal layer containing the common connection line 106 and the metal layer containing the data line Data during the manufacturing stage. By making the third sub-section 1063 of the common connection line 106 exceed the first threshold of the data line Data, even if the common connection line 106 and the data line Data experience alignment deviation during the manufacturing process, it can be ensured that the common connection line 106 and the data line Data overlap. The spacing of the broken portions 106A of the common connection line 106 along the first direction D1 typically needs to be greater than or equal to d, where d is the minimum resolution of the exposure machine.

[0078] The disconnection of two adjacent touch sensing blocks 103 in the second direction D2 is achieved through a disconnected fourth connection line 114. Specifically, as... Figure 8 As shown, the array substrate 100 also includes a fourth connection line 114. The first end 1141 of the fourth connection line 114 is electrically connected to the touch electrode 104 of one of the two adjacent touch sensing blocks 103 along the second direction D2, and the second end 1142 of the fourth connection line 114 is disconnected from the touch electrode 104 of the other of the two adjacent touch sensing blocks 103 along the second direction D2, thereby making the two adjacent touch sensing blocks 103 along the second direction D2 electrically insulated from each other, which is beneficial for accurate detection of touch position.

[0079] like Figure 8As shown, the orthographic projection of the fourth connection line 114 on the substrate 101 spans the orthographic projections of the two gate lines 103 located between two adjacent touch sensing blocks 103 along the second direction D2 on the substrate 101. Furthermore, the second end 1142 of the fourth connection line 114 extends beyond the gate line closest to it by a distance L2 greater than or equal to a second threshold. The second threshold is the alignment deviation between the metal layer containing the fourth connection line 114 and the metal layer containing the gate line 103 during the manufacturing stage. The fourth connection line 114 can be located on the same layer as the first connection line 107, the second connection line 109, the third connection line 110, and the pixel electrode 102. By ensuring that the distance L2 from the second end 1142 of the fourth connection line 114 to the adjacent gate line is greater than or equal to the second threshold, it can be guaranteed that even if there is an alignment deviation between the fourth connection line 114 and the gate line 103, the fourth connection line 114 can still span two adjacent gate lines 103. Since the first connection line 107 also crosses two adjacent gate lines, the load on the gate line at the location of the fourth connection line 114 is basically the same as the load on the gate line at the location of the first connection line 107. Therefore, the parasitic capacitance between the fourth connection line 114 and the gate line is basically equal to the parasitic capacitance between the first connection line 107 and the gate line.

[0080] like Figure 8 As shown, in some embodiments, the touch signal line TX includes a narrower first portion and a wider second portion. The first portion has a line width of S1 along the first direction D1, and the second portion has a line width of S2 along the first direction D1, where S1 is smaller than S2. The data line Data has a line width of S3 along the first direction D1. In some embodiments, the line width S2 of the touch signal line TX along the first direction D1 is greater than the line width S3 of the data line Data along the first direction D1. In alternative embodiments, the line width S1 of the touch signal line TX along the first direction D1 is greater than the line width S3 of the data line Data along the first direction D1.

[0081] Figure 9 The arrangement of vias 112 is shown. In the array substrate 100, each touch sensing block 103 is electrically connected to at least one of the multiple touch signal lines TX via the via 112, and the orthographic projection of the via 112 on the substrate 101 does not overlap with the orthographic projection of the first connecting line 107 on the substrate 101. The touch signal lines TX and the touch sensing blocks 103 are connected vias 112. Since the via 112 occupies a certain position, in order to ensure the optimization of pixel transmittance, the first connecting line 107 is not designed at the position where the via 112 is set.

[0082] Figure 10 yes Figure 4The image shows a magnified view of the region V enclosed by the dashed rectangle. In addition to the first connecting line 107, each repeating unit of the array substrate 100 may also be provided with a compensation line 108. The orthographic projection of the compensation line 108 on the substrate 101 partially overlaps with the orthographic projection of the touch signal line TX on the substrate 101. Furthermore, the touch signal line TX overlapping with the compensation line 108 and the touch signal line TX overlapping with the first connecting line 107 within each repeating unit are two different touch signal lines. For example, as described above, every four adjacent pixels in the array substrate 100 constitute a repeating unit, and these four adjacent pixels are arranged in two rows and two columns. Figure 4 The pixel structure of a repeating unit is shown. For example... Figure 4 As shown, the repeating unit includes a complete first connecting line 107 and a portion of the first connecting line 107. The complete first connecting line 107 spans the touch signal line TX3, thus generating parasitic capacitance with the touch signal line TX3. The portion of the first connecting line 107 spans the touch signal line TX1, thus generating parasitic capacitance with the touch signal line TX1. If the compensation line 108 is not provided, the touch signal line TX2 in the repeating unit has no overlapping signal line. Therefore, the parasitic capacitance of the touch signal line TX2 is different from that of the touch signal lines TX1 and TX3, thereby affecting the accuracy of touch position detection of the array substrate. In order to ensure that the parasitic capacitance of each touch signal line TX is equal, in the embodiment provided in this disclosure, a compensation line 108 is provided at the touch signal line TX2 of each repeating unit. The orthographic projection of the compensation line 108 on the substrate 101 partially overlaps with the orthographic projection of the touch signal line TX2 on the substrate 101, thereby generating parasitic capacitance. With this design, the parasitic capacitance of the touch signal line TX2 in the repeating unit is basically equal to that of the parasitic capacitance of the touch signal lines TX1 and TX3, which helps to improve the accuracy of touch position detection of the array substrate 100.

[0083] It should be noted that the so-called "complete first connection line 107 within the repeating unit" refers to a first connection line 107 used to connect the touch electrodes 104 in two adjacent rows of sub-pixels. Therefore, half of the first connection line 107 is located in the upper row sub-pixel, and the other half is located in the lower row sub-pixel. The first connection line 107 that overlaps with the touch signal line TX3 can be called a complete first connection line 107 within the repeating unit. However, the first connection line 107 that overlaps with the touch signal line TX1 cannot be called a complete first connection line 107 within the repeating unit, because only a portion of the first connection line 107 that overlaps with the touch signal line TX1 is located within the repeating unit.

[0084] like Figure 10As shown, in some embodiments, the portion where the orthographic projection of each compensation line 108 on the substrate 101 overlaps with the orthographic projection of the touch signal line TX2 on the substrate 101 constitutes a second overlap region R2, and the areas of all second overlap regions R2 are equal. This further ensures that the parasitic capacitance between the compensation line 108 and the touch signal line TX2 within each repeating unit is equal.

[0085] In some embodiments, the line width of the compensation line 108 is equal to the line width of the first connecting line 107. This equal line width further ensures that the parasitic capacitance generated by the first connecting line 107 and the touch signal line TX1 or TX3 is equal to the parasitic capacitance generated by the compensation line 108 and the touch signal line TX2. In some embodiments, the compensation line 108 and the pixel electrode 102 are located on the same layer.

[0086] like Figure 10 As shown, the compensation line 108 includes a sub-section 1081 extending along a first direction D1. The orthographic projection of the sub-section 1081 on the substrate 101 partially overlaps with the orthographic projection of the touch signal line TX2 on the substrate 101. Furthermore, the two opposite ends 1081A and 1081B of the sub-section 1081 in the first direction D1 both extend beyond the touch signal line TX2. The sub-section 1081 of the compensation line 108 laterally crosses the touch signal line TX2, and the end 1081A of the laterally extending sub-section 1081 of the compensation line 108 extends beyond the touch signal line TX2 by a certain distance, for example, 2-5 μm. This ensures that even if there is a misalignment between the compensation line 108 and the touch signal line TX2, the compensation line 108 can still overlap with the touch signal line TX2, thereby generating parasitic capacitance.

[0087] refer to Figure 10 The orthographic projection of compensation line 108 on substrate 101 does not overlap with the orthographic projections of gate lines Gate 4 and Gate 5 and common connection line 106 on substrate 101. In other words, compensation line 108 breaks after overlapping with touch signal line TX2 and no longer crosses gate lines Gate 4 and Gate 5 and common connection line 106. Thus, the first connection line 107 in this repeating unit crosses gate lines Gate 4 and Gate 5 and common connection line 106, and the other first connection line 107 crosses gate lines Gate 2 and Gate 3 and another common connection line 106, thereby ensuring that gate lines Gate 2, Gate 3, Gate 4, and Gate 5 have equal parasitic capacitance.

[0088] As mentioned above, the sub-pixels of pixels P1, P2, P3, and P4, totaling 12 sub-pixels, can constitute the minimum repetition period of the Z-architecture, i.e., the repetition unit. Of course, the embodiments of this disclosure do not limit the repetition unit to only this one division method, and other reasonable division methods of the repetition unit should also fall within the protection scope of this disclosure.

[0089] Figure 11 yes Figure 3 A partially enlarged schematic diagram of a touch sensing block 103. Figure 11 Each dashed rectangle in the text represents a repeating unit, such as... Figure 11 As shown, each repeating unit includes a complete first connection line 107 and a compensation line 108. Each touch sensing block 103 typically includes hundreds to thousands of sub-pixels. Assuming each touch sensing block 103 includes M sub-pixels horizontally (M is generally an even number, on the order of 10 to 103), and a touch signal line TX is provided for every two sub-pixels, then M / 2 touch signal lines TX pass through the touch sensing block 103. In some embodiments, only one of the M / 2 touch signal lines TX is the touch signal line driving the touch sensing block 103. The touch signal line TX driving the touch sensing block 103 is connected to the touch sensing block 103 via a via 112. The other touch signal lines TX in the M / 2 touch signal lines TX only pass through the touch sensing block 103 but are not connected to it. These other touch signal lines TX pass through the touch sensing block 103 and can be connected to other touch sensing blocks 103. Even if they are not connected to other touch sensing blocks 103, in order to ensure the consistency of pixel design, the touch signal lines TX in each touch sensing block 103 need to be evenly arranged.

[0090] Figure 12 For along Figure 4 A cross-sectional view taken from line AA′. Figure 13 For along Figure 4 A cross-sectional view taken from the BB' line. (See figure) Figure 12 and 13 As shown, the array substrate 100 may further include a light-shielding layer 203 located on the side of the touch signal line TX and data line Data away from the substrate 101. The light-shielding layer 203 includes a first light-shielding portion 2031 and a second light-shielding portion 2032. The orthographic projection of the data line Data onto the substrate 101 falls within the orthographic projection of the first light-shielding portion 2031 onto the substrate 101, and the orthographic projection of the touch signal line TX onto the substrate 101 falls within the orthographic projection of the second light-shielding portion 2032 onto the substrate 101. The width of the first light-shielding portion 2031 along the first direction D1 is a first width W1, the width of the second light-shielding portion 2032 along the first direction D1 is a second width W2, and the width of each sub-pixel along the first direction D1 is a third width W3 (see [reference]).Figure 1 The first width W1, the second width W2, and the third width W3 satisfy the following condition: the absolute value of the difference between the first width W1 and the second width W2 is less than or equal to twice the third width W3, that is, |W1-W2| / (2*W3)≤5%, which can ensure the uniformity of the displayed image.

[0091] like Figure 12 and Figure 13 As shown, the orthographic projection of the data line Data on the substrate 101 does not overlap with the orthographic projection of the touch electrode 104 on the substrate 101, and the orthographic projection of the touch signal line TX on the substrate 101 does not overlap with the orthographic projection of the touch electrode 104 on the substrate 101. As mentioned above, each touch sensing block 103 has not only touch signal lines TX connected to it passing through it, but also multiple touch signal lines TX that are not connected to it passing through it. Since the smaller the parasitic capacitance between the touch signal line TX and other touch sensing blocks 103 that are not electrically connected to it, the better the touch performance, in the embodiments of this disclosure, the touch electrode 104 below the touch signal line TX is removed, so that the orthographic projection of the touch signal line TX on the substrate 101 does not overlap with the orthographic projection of the touch electrode 104 on the substrate 101, thereby reducing the parasitic capacitance between the touch signal line TX and the touch electrode 104 (and therefore the touch sensing block 103).

[0092] like Figure 12 As shown, in the array substrate 100, the orthographic projection of the touch electrode 104 in each sub-pixel onto the substrate 101 at least partially overlaps with the orthographic projection of the pixel electrode 102 in that sub-pixel onto the substrate 101. For each data line Data and two columns of sub-pixels located on both sides of the data line Data, the distance between the orthographic projection of the touch electrode 104 in each column of sub-pixels onto the substrate 101 and the orthographic projection of the data line Data onto the substrate 101 is a first distance a, and the distance between the orthographic projection of the pixel electrode 102 in each column of sub-pixels onto the substrate 101 and the orthographic projection of the data line Data onto the substrate 101 is a second distance b. The second distance b is greater than the first distance a, and the difference between the second distance b and the first distance a is greater than or equal to a third threshold c, i.e., ba ≥ c. The third threshold c is the alignment deviation of the mask used to prepare the touch electrode 104 and the mask used to prepare the pixel electrode 102 during the exposure process. In some embodiments, the values ​​of a, b, and c are less than or equal to 10 μm. By ensuring that ba≥c, even if there is a misalignment between the touch electrode 104 and the pixel electrode 102, the overlapping area between the touch electrode 104 and the pixel electrode 102 will not change. This ensures that the storage capacitance of the pixel remains unchanged and improves the yield of the array substrate 100.

[0093] like Figure 13 As shown, in the array substrate 100, for each touch signal line TX and the two columns of sub-pixels located on both sides of the touch signal line TX, the distance between the orthographic projection of the touch electrode 104 in each column of sub-pixels on the substrate 101 and the orthographic projection of the touch signal line TX on the substrate 101 is the third distance a′. The distance between the orthographic projection of the pixel electrode 102 in each column of sub-pixels on the substrate 101 and the orthographic projection of the touch signal line TX on the substrate 101 is the fourth distance b′. The fourth distance b′ is greater than the third distance a′, and the difference between the fourth distance b′ and the third distance a′ is greater than or equal to the third threshold c, that is, b′-a′=ba≥c. a′ is not necessarily equal to a, and b′ is not necessarily equal to b. Generally speaking, the larger the values ​​of a′ and b′ (i.e., the farther the touch signal line TX is from the touch electrode 104 and the pixel electrode 102), the smaller the parasitic capacitance between the touch signal line TX and the touch electrode 104 and the pixel electrode 102, which is more beneficial to the touch performance; however, the farther the distance, the smaller the effective light-transmitting area of ​​the pixel. Therefore, the values ​​of a′ and b′ can be set according to the specific specifications of the array substrate 100.

[0094] In some embodiments, the touch electrode 104 is located on the substrate 101; the gate line and the common connection line 106 are located on the same layer and both are located on the side of the touch electrode 104 away from the substrate 101; the data line and the touch signal line TX are located on the same layer and both are located on the side of the gate line away from the substrate 101; the pixel electrode 102, the first connection line 107, the second connection line 109, the third connection line 110, the fourth connection line 114, and the compensation line 108 are located on the same layer and they are located on the side of the data line Data away from the substrate 101. During fabrication, the touch electrode 104 can be formed using a first photomask by patterning a first metal layer, the material of which can be, for example, ITO; the gate line and common connection line 106 can be formed using a second photomask by patterning a second metal layer; the data line and touch signal line TX can be formed using a third photomask by patterning a third metal layer; the pixel electrode 102, the first connection line 107, the second connection line 109, the third connection line 110, the fourth connection line 114, and the compensation line 108 can be formed using a fourth photomask by patterning a fourth metal layer, the material of which can be, for example, ITO. This significantly reduces the number of photomasks, saving on process steps and costs. Other required layers, such as a gate insulating layer or an active layer, can also be placed between the gate line and the data line. Similarly, other required layers, such as a passivation layer, can also be placed between the data line and the pixel electrode 102.

[0095] Figure 14 A partial planar schematic diagram of the array substrate 200 is shown. Apart from the relative positions of certain film layers, Figure 14 The array substrate 200 shown has the same characteristics as in... Figure 4 The array substrate 100 shown has a substantially similar structure. For example, the pixel structure of the array substrate 200 is also arranged as Z-architecture pixels. The array substrate 200 includes a first connection line 107 as described above, which is used to connect the touch electrodes of two adjacent rows of sub-pixels within each touch sensing block 103. The first connection line 107 is provided at the location of the second connection line 109 of the array substrate 200, but not at the location of the third connection line 110. Each repeating unit includes a compensation line 108 so that all touch signal lines TX have substantially the same parasitic capacitance. Electrical insulation between two adjacent touch sensing blocks 103 in the first direction D1 is achieved by breaking the common connection line, and electrical insulation between two adjacent touch sensing blocks 103 in the second direction D2 is achieved by breaking the fourth connection line 114, etc. For detailed structures and functions of these components, please refer to the previous section. Figure 4 The explanation will not be repeated here. For the sake of brevity, Figure 14 array substrate 200 and Figure 4 The similarities between the array substrate 100 and the array substrate 100 will not be described again; only the differences will be introduced below.

[0096] Unlike array substrate 100, in array substrate 200, pixel electrode 202 is located on substrate 101, and touch electrode 204 is located on the side of pixel electrode 202 away from substrate 101. Specifically, pixel electrode 202 is located on substrate 101; gate line is located on the side of pixel electrode 202 away from substrate 101; data line Data and touch signal line TX are located on the same layer and both are located on the side of gate line Gate away from substrate 101; touch electrode 204 is located on the side of data line Data away from substrate 101, wherein the first connection line 107, second connection line 109, third connection line 110, fourth connection line 114, compensation line 108, and common connection line 205 (see...) Figure 15 The pixel electrode 202 can be located on the same layer as the touch electrode 204. The materials of the pixel electrode 202 and the touch electrode 204 can be ITO.

[0097] Figure 15 yes Figure 14 A magnified view of region VI, enclosed by a dashed rectangle. In the array substrate 200, each touch sensing block 103 is electrically connected to at least one of a plurality of touch signal lines TX via a via 212, and the orthographic projection of the via 212 on the substrate 101 lies between the orthographic projections of the two gate lines (Gates) between two adjacent rows of sub-pixels on the substrate 101. For example, inFigure 15 In this process, the orthographic projection of via 212 on the substrate 101 is located between the orthographic projections of the two gate lines Gate2 and Gate3 between two adjacent rows of sub-pixels on the substrate 101, thereby making reasonable use of the wiring space.

[0098] Figure 16 yes Figure 14 A magnified view of area VII, enclosed by a dashed rectangle. (See attached image.) Figure 16 As shown, two adjacent touch electrodes 204 in the first direction D1 can be electrically connected via a common connection line 205. The touch electrodes 204 of two adjacent rows of sub-pixels within each touch sensing block 103 are electrically connected via a first connection line 107. The extension direction of the first connection line 107 is substantially the same as the extension direction of the touch signal line TX, and the orthographic projection of the first connection line 107 onto the substrate 101 falls within the orthographic projection of the touch signal line TX onto the substrate 101. Since the first connection line 107 and the touch electrodes 204 are located on the same layer, the first connection line 107 can be directly connected to the touch electrodes 204 without vias.

[0099] In some alternative embodiments, the extension direction of the first connecting line 107 may differ from the extension direction of the touch signal line TX. For example, the extension direction of the first connecting line 107 may have a certain tilt angle relative to the extension direction of the touch signal line TX, and the orthographic projection of the first connecting line 107 on the substrate 101 may at most overlap with the orthographic projection of the touch signal line TX on the substrate 101. This arrangement reduces the overlap area between the first connecting line 107 and the touch signal line TX, thereby reducing the coupling between them.

[0100] Other technical effects of the array substrate 200 can be found in the description of the technical effects of the array substrate 100, and will not be repeated here for the sake of brevity.

[0101] Figure 17 A block diagram of a touch display device according to an embodiment of the present disclosure is shown. The touch display device may include the array substrate 100 or 200 described in any of the preceding embodiments. In some embodiments, the touch display device may be an embedded touch display device, which includes an array substrate, a counter substrate, and a liquid crystal layer located between the array substrate and the counter substrate. The array substrate is the array substrate 100 or 200 described in any of the preceding embodiments. The touch display device includes, but is not limited to, any product or component with touch and display functions such as a liquid crystal panel, electronic paper, OLED (organic light-emitting diode) panel, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, and navigator.

[0102] The touch display device can have essentially the same technical effects as the array substrate 100 or 200 described in the previous embodiments. For the sake of brevity, the technical effects of the touch display device will not be described again here.

[0103] It will be understood that although the terms first, second, third, etc., may be used herein to describe various elements, components, areas, layers, and / or parts, these elements, components, areas, layers, and / or parts should not be limited by these terms. These terms are used only to distinguish one element, component, area, layer, or part from another. Therefore, the first element, component, area, layer, or part discussed above may be referred to as a second element, component, area, layer, or part without departing from the teachings of this disclosure.

[0104] Spatial relative terms such as “row,” “column,” “below,” “above,” “left,” “right,” etc., may be used herein for ease of description to describe the relationship between one element or feature illustrated in the figures and another element(s). It will be understood that these spatial relative terms are intended to cover different orientations of the device in use or operation, in addition to those depicted in the figures. For example, if the device in the figure is flipped, then an element described as “below other elements or features” will be oriented “above other elements or features.” Thus, the exemplary term “below” can cover both orientations above and below. Devices may be oriented in other ways (rotated 90 degrees or otherwise) and the spatial relative descriptors used herein will be interpreted accordingly. Additionally, it will be understood that when a layer is referred to as “between two layers,” it may be the only layer between those two layers, or there may be one or more intermediate layers.

[0105] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprising” and / or “including”, when used in this specification, specify the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. In the description of this specification, references to the terms “one embodiment,” “another embodiment,” etc., mean that a specific feature, structure, material, or characteristic described in connection with that embodiment is included in at least one embodiment of this disclosure. The illustrative expressions of the foregoing terms in this specification do not necessarily refer to the same embodiments or examples. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Furthermore, those skilled in the art can combine and integrate the different embodiments or examples described herein, as well as the features of the different embodiments or examples, without contradiction.

[0106] It will be understood that when a component or layer is referred to as "on another component or layer," "connected to another component or layer," "coupled to another component or layer," or "adjacent to another component or layer," it may be directly on another component or layer, directly connected to another component or layer, directly coupled to another component or layer, or directly adjacent to another component or layer, or there may be intermediate components or layers. Conversely, when a component is referred to as "directly on another component or layer," "directly connected to another component or layer," "directly coupled to another component or layer," or "directly adjacent to another component or layer," no intermediate components or layers exist. However, in any case, "on" or "directly on" should not be interpreted as requiring a layer to completely cover the layer below.

[0107] Embodiments of this disclosure are described herein with reference to illustrative illustrations (and intermediate structures) of idealized embodiments. Therefore, variations in the illustrated shapes should be expected, for example, as a result of manufacturing techniques and / or tolerances. Consequently, embodiments of this disclosure should not be construed as limited to the specific shapes of the regions illustrated herein, but should include, for example, shape deviations due to manufacturing processes. Thus, the regions illustrated are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of a device and are not intended to limit the scope of this disclosure.

[0108] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having meanings consistent with their meanings in the relevant field and / or the context of this specification, and will not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0109] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. An array substrate, comprising: A substrate includes a plurality of pixels arranged in an array, the plurality of pixels including a plurality of sub-pixels arranged in an array, each of the plurality of sub-pixels including a pixel electrode, a touch electrode, and a thin-film transistor; A plurality of touch sensing blocks are located on the substrate and electrically insulated from each other. Each touch sensing block includes a plurality of touch electrodes. The plurality of touch electrodes of each touch sensing block are electrically connected to each other and arranged in an array. Multiple gate lines extending along a first direction, with each row of sub-pixels associated with two of the multiple gate lines; Multiple touch signal lines and multiple data lines extending along a second direction, wherein the touch signal lines and the data lines are located on the same layer, and each touch sensing block is electrically connected to at least one of the multiple touch signal lines, wherein the first direction and the second direction are arranged to intersect; The first connection line connects two adjacent rows of touch electrodes in each touch sensing block to each other. as well as The second connection line connects each of at least a portion of the plurality of pixel electrodes to the drain of a corresponding thin-film transistor. The orthographic projection of the second connection line on the substrate does not overlap with the orthographic projection of the touch signal line on the substrate. In this configuration, the gate of the thin-film transistor (TFT) of each sub-pixel is electrically connected to the gate line, the drain of the TFT of each sub-pixel is electrically connected to the pixel electrode of that sub-pixel, and the source of the TFT of each sub-pixel is electrically connected to the data line. Each pair of adjacent sub-pixels in the same row forms a unit group, and the sources of the TFTs in each unit group are electrically connected to the same data line. The gates of the TFTs in each unit group are electrically connected to different gate lines, and the sources of the TFTs of adjacent sub-pixels in the same column are electrically connected to different data lines. In this configuration, every four adjacent pixels constitute a repeating unit, and each repeating unit includes four adjacent sub-pixels. The four adjacent sub-pixels are arranged in two rows and two columns. The pixel electrodes of two sub-pixels located in different rows and diagonally opposite each other are electrically connected to the drain of a corresponding thin-film transistor through the second connecting line. The touch electrodes of the other two sub-pixels located in different rows and diagonally opposite each other are electrically connected through the first connecting line.

2. The array substrate according to claim 1 further includes a third connecting line, wherein, Each of a portion of the plurality of pixel electrodes is electrically connected to the drain of a corresponding thin-film transistor via the second connection line, and each of the remaining portions of the plurality of pixel electrodes is electrically connected to the drain of a corresponding thin-film transistor via the third connection line, wherein the orthographic projection of the third connection line on the substrate partially overlaps with the orthographic projection of the touch signal line on the substrate.

3. The array substrate according to claim 2, wherein, The orthographic projection of the third connecting line on the substrate does not overlap with the orthographic projection of the first connecting line on the substrate.

4. The array substrate according to claim 2, wherein, The portion where the orthographic projection of the third connecting line on the substrate overlaps with the orthographic projection of the touch signal line on the substrate constitutes a first overlapping area, and the areas of all first overlapping areas are equal to each other.

5. The array substrate according to claim 1, further comprising a plurality of common connection lines extending along the first direction, wherein, Each of the multiple common connection lines is arranged between two adjacent rows of sub-pixels. Each touch electrode in the same row within each touch sensing block is electrically connected to each other via the common connection line, and each common connection line is disconnected at the interval between two adjacent touch sensing blocks.

6. The array substrate according to claim 5, wherein, A data line is provided at the interval between any two adjacent touch sensing blocks along the first direction. The break in the common connection line at the interval is located on the first side of the data line. The continuous part of the common connection line includes a first sub-part, a second sub-part, and a third sub-part connected in sequence. The first sub-part is located on the second side of the data line, the third sub-part is located on the first side of the data line, and the second sub-part is located between the first sub-part and the third sub-part. The orthographic projection of the second sub-part on the substrate falls within the orthographic projection of the data line on the substrate.

7. The array substrate according to claim 6, wherein, The length of the third sub-part along the first direction is greater than or equal to the first threshold.

8. The array substrate according to claim 5, further comprising a fourth connecting line, wherein, The first end of the fourth connecting line is electrically connected to the touch electrode of one of any two adjacent touch sensing blocks along the second direction, and the second end of the fourth connecting line is disconnected from the touch electrode of the other of any two adjacent touch sensing blocks along the second direction, so that the two adjacent touch sensing blocks along the second direction are electrically insulated from each other.

9. The array substrate according to claim 8, wherein, The orthographic projection of the fourth connection line on the substrate spans the orthographic projections of the two gate lines located between any two adjacent touch sensing blocks along the second direction on the substrate, and the second end of the fourth connection line extends beyond the gate line closest to the second end of the two gate lines by a distance greater than or equal to the second threshold.

10. The array substrate according to claim 1, wherein, The orthographic projection of the first connecting line on the substrate partially overlaps with the orthographic projection of the touch signal line on the substrate, and the extension direction of the first connecting line at the overlap is perpendicular to the extension direction of the touch signal line at the overlap.

11. The array substrate according to claim 1, wherein, Each touch sensing block is electrically connected to at least one of the plurality of touch signal lines via a via, and the orthographic projection of the via on the substrate does not overlap with the orthographic projection of the first connection line on the substrate.

12. The array substrate according to claim 5, wherein, The orthographic projection of the first connecting line on the substrate partially overlaps with the orthographic projection of the touch signal line on the substrate, and a first connecting line is provided between two adjacent rows of sub-pixels in each repeating unit.

13. The array substrate according to claim 12, wherein, Each repeating unit is also provided with a compensation line, the orthographic projection of the compensation line on the substrate partially overlaps with the orthographic projection of the touch signal line on the substrate, and the touch signal line that overlaps with the compensation line and the touch signal line that overlaps with the first connecting line in each repeating unit are two different touch signal lines.

14. The array substrate according to claim 13, wherein, The compensation line includes a sub-section extending along the first direction, the orthographic projection of the sub-section on the substrate partially overlapping the orthographic projection of the touch signal line on the substrate, and both opposite ends of the sub-section extending beyond the touch signal line in the first direction.

15. The array substrate according to claim 13, wherein, The orthographic projection of the compensation line on the substrate does not overlap with the orthographic projection of the gate line and the common connection line on the substrate.

16. The array substrate according to claim 13, wherein, The line width of the compensation line is equal to the line width of the first connecting line.

17. The array substrate according to claim 13, wherein, The portion where the orthographic projection of the compensation line on the substrate overlaps with the orthographic projection of the touch signal line on the substrate constitutes a second overlapping region, and the areas of all second overlapping regions are equal.

18. The array substrate according to claim 1, wherein, The width of the touch signal line is greater than the width of the data line.

19. The array substrate according to claim 18, wherein, The touch signal line includes a first part and a second part, wherein the line width of the first part is smaller than the line width of the second part.

20. The array substrate according to claim 1, further comprising a light-shielding layer located on the side of the touch signal line and the data line away from the substrate, wherein, The light-shielding layer includes a first light-shielding portion and a second light-shielding portion. The orthographic projection of the data line on the substrate falls within the orthographic projection of the first light-shielding portion on the substrate, and the orthographic projection of the touch signal line on the substrate falls within the orthographic projection of the second light-shielding portion on the substrate. The width of the first light-shielding portion along the first direction is a first width, the width of the second light-shielding portion along the first direction is a second width, and the width of each sub-pixel along the first direction is a third width. The first width, the second width, and the third width satisfy the following condition: The ratio of the absolute value of the difference between the first width and the second width to twice the third width is less than or equal to 5%.

21. The array substrate according to claim 1, wherein, The orthographic projection of the data line on the substrate does not overlap with the orthographic projection of the touch electrode on the substrate, and the orthographic projection of the touch signal line on the substrate does not overlap with the orthographic projection of the touch electrode on the substrate.

22. The array substrate according to claim 21, wherein, A data line is arranged every two columns of sub-pixels, and at least some of the data lines are arranged between adjacent columns of sub-pixels; and A touch signal line is arranged every two columns of sub-pixels, and each touch signal line is arranged between two adjacent columns of sub-pixels and between two adjacent data lines.

23. The array substrate according to claim 22, wherein, The orthographic projection of the touch electrode within each sub-pixel onto the substrate at least partially overlaps with the orthographic projection of the pixel electrode within that sub-pixel onto the substrate. For each data line and the two columns of sub-pixels located on both sides of the data line, the distance between the orthographic projection of the touch electrode in each column of the two sub-pixels on the substrate and the orthographic projection of the data line on the substrate is a first distance, and the distance between the orthographic projection of the pixel electrode in each column of the two sub-pixels on the substrate and the orthographic projection of the data line on the substrate is a second distance. The second distance is greater than the first distance, and the difference between the second distance and the first distance is greater than or equal to a third threshold.

24. The array substrate according to claim 23, wherein, For each touch signal line and the two columns of sub-pixels located on both sides of the touch signal line, the distance between the orthographic projection of the touch electrode in each column of the two sub-pixels on the substrate and the orthographic projection of the touch signal line on the substrate is a third distance. The distance between the orthographic projection of the pixel electrode in each column of the two sub-pixels on the substrate and the orthographic projection of the touch signal line on the substrate is a fourth distance. The fourth distance is greater than the third distance and the difference between the fourth distance and the third distance is greater than or equal to the third threshold.

25. The array substrate according to claim 1, wherein, The ratio of the number of data lines to the number of touch signal lines is 1:

2. One data line is arranged every two columns of sub-pixels, and two touch signal lines are arranged every two columns of sub-pixels. The two touch signal lines are arranged between two adjacent columns of sub-pixels.

26. The array substrate according to any one of claims 1-25, wherein, The touch electrode is located on the substrate, the gate line is located on the side of the touch electrode away from the substrate, the data line and the touch signal line are located on the side of the gate line away from the substrate, and the pixel electrode and the first connection line are located on the same layer and both are located on the side of the data line away from the substrate.

27. The array substrate according to any one of claims 1-9 and 12-25, wherein, The pixel electrode is located on the substrate, the gate line is located on the side of the pixel electrode away from the substrate, the data line and the touch signal line are located on the side of the gate line away from the substrate, the touch electrode and the first connecting line are located on the same layer and both are located on the side of the data line away from the substrate.

28. The array substrate according to claim 27, wherein, The extension direction of the first connecting line is different from the extension direction of the touch signal line, and the orthographic projection of the first connecting line on the substrate and the orthographic projection of the touch signal line on the substrate overlap by at most a portion.

29. The array substrate according to claim 27, wherein, Each touch sensing block is electrically connected to at least one of the plurality of touch signal lines via a via, and the orthographic projection of the via on the substrate lies between the orthographic projections of the two gate lines between two adjacent rows of sub-pixels on the substrate.

30. The array substrate according to claim 27, wherein, The first connecting line extends in the same direction as the touch signal line, and the orthographic projection of the first connecting line on the substrate falls within the orthographic projection of the touch signal line on the substrate.

31. The array substrate according to any one of claims 1-25, further comprising a liquid crystal layer, wherein, The touch electrode and the pixel electrode are located on the same side of the liquid crystal layer, and the materials of the touch electrode and the pixel electrode include indium tin oxide.

32. The array substrate according to any one of claims 1-25, wherein, Each pixel includes a first sub-pixel, a second sub-pixel, and a third sub-pixel arranged sequentially along the first direction. The four adjacent pixels of each repeating unit are arranged in two rows and two columns and include a first pixel, a second pixel, a third pixel, and a fourth pixel. The first pixel and the second pixel are located in the same row and the first pixel and the third pixel are located in the same column. The third pixel and the fourth pixel are located in the same row and the second pixel and the fourth pixel are located in the same column. The sources of the thin-film transistors of the first and second sub-pixels of the first pixel are both electrically connected to the first data line among the multiple data lines. The sources of the thin-film transistors of the third sub-pixel of the first pixel and the first sub-pixel of the second pixel are both electrically connected to the second data line among the multiple data lines. The sources of the thin-film transistors of the second and third sub-pixels of the second pixel are both electrically connected to the third data line among the multiple data lines. The sources of the thin-film transistors of the first and second sub-pixels of the third pixel are both electrically connected to the second data line. The sources of the thin-film transistors of the third sub-pixel of the third pixel and the first sub-pixel of the fourth pixel are both electrically connected to the third data line. Furthermore, the sources of the thin-film transistors of the second and third sub-pixels of the fourth pixel are both electrically connected to the fourth data line among the multiple data lines.

33. The array substrate according to claim 32, wherein, The gate of the thin-film transistor of all first sub-pixels in the same row of pixels is electrically connected to the first gate line of the two gate lines. The gate of the thin-film transistor of all second sub-pixels in the same row of pixels is electrically connected to the second gate line of the two gate lines. The gate of the thin-film transistor of the third sub-pixel of two adjacent pixels in the same row of pixels is electrically connected to the first gate line and the second gate line, respectively.

34. A touch display device comprising an array substrate according to any one of claims 1-33.

Images