Memory controller and memory system performing data search

Abstract

In certain aspects, a memory system includes a volatile memory device and a memory controller operably coupled to the volatile memory device. The volatile memory device is configured to store a logical-to-physical (L2P) mapping table. The memory controller is configured to maintain an L2P mapping table stored in the volatile memory device such that the L2P mapping table maps a first set of logical addresses to identifiers (IDs) of memory blocks of the cache, respectively.

Description

Technical Field

[0001] The present disclosure relates to a memory device and a method of operating the memory device. Background Art

[0002] A solid-state drive (SSD) is a non-volatile data storage device that has gained popularity in recent years due to its many advantages over traditional hard disk drives (HDDs), such as faster read and write speeds, durability and reliability, reduced power consumption, silent operation, and smaller form factors. SSDs typically use NAND flash memory for non-volatile storage. Some SSDs, particularly enterprise-class SSDs, also use volatile memory (e.g., dynamic random-access memory (DRAM)) to enhance their performance, allowing faster access to data and more efficient processing of read and write operations. Summary of the invention

[0003] In one aspect, a memory system includes a volatile memory device and a memory controller operably coupled to the volatile memory device. The volatile memory device is configured to store a logical-to-physical (L2P) mapping table. The memory controller is configured to maintain the L2P mapping table stored in the volatile memory device, so that the L2P mapping table maps a first set of logical addresses to identifiers (IDs) of cached storage blocks, respectively.

[0004] In some implementations, the memory controller is further configured to: cache the first set of data in the storage block. In some implementations, the first set of data is respectively associated with a first set of logical addresses.

[0005] In some implementations, the memory controller is further configured to search for the first set of data cached in the memory block based on the L2P mapping table.

[0006] In some implementations, the volatile storage device includes a cache.

[0007] In some implementations, the memory system further includes a non-volatile memory device operably coupled to the memory controller. In some implementations, the memory controller is further configured to store a second set of data in a storage area of ​​the non-volatile memory device. In some implementations, the second set of data is respectively associated with a second set of logical addresses. In some implementations, the memory controller is further configured to maintain an L2P mapping table stored in the volatile memory device, so that the L2P mapping table also maps the second set of logical addresses to physical addresses of the storage area of ​​the non-volatile memory device.

[0008] In some implementations, the volatile storage device includes DRAM and the non-volatile storage device includes NAND flash memory.

[0009] In some implementations, the memory controller is further configured to: in response to receiving a write request indicating a fragment of the first set of data associated with a first logical address in the first set of logical addresses, assign the fragment of the first set of data to a first storage block in the storage blocks. In some implementations, the first storage block has a first ID in the ID. The memory controller is further configured to: retrieve the fragment of the first set of data to cache the fragment of the first set of data in the first storage block.

[0010] In some implementations, to maintain the L2P mapping table, the memory controller includes an L2P search engine configured to: in response to fetching a segment of the first set of data to the first storage block, update the L2P mapping table to map the first logical address to the first ID.

[0011] In some implementations, the memory controller is further configured to, in response to receiving a read request indicating a fragment of the first set of data associated with a second logical address in the first set of logical addresses, obtain the fragment of the first set of data from a second storage block in the storage blocks in the cache based on the L2P mapping table.

[0012] In some implementations, the memory controller includes an L2P search engine configured to determine an address of an L2P mapping table in the volatile memory device based on the second logical address; and identify a second ID in the ID at the address of the L2P mapping table in the volatile memory device. In some implementations, the second memory block has the second ID.

[0013] On the other hand, a memory system includes: a non-volatile memory device including storage areas, each of which is associated with a physical address; a volatile memory device including storage blocks, each of which is associated with an ID; and a memory controller operably coupled to the volatile memory device and the non-volatile memory device. The volatile memory device is configured to store an L2P mapping table. The L2P mapping table maps the logical address of the data to the ID of the storage block in the volatile memory device and the physical address of the storage area in the non-volatile memory device, respectively. The memory controller is configured to search for a segment of the data based on the L2P mapping table.

[0014] In some implementations, to search for the segment of data, the memory controller is configured to: determine an address of an L2P mapping table in the volatile memory device based on a logical address associated with the segment of data; and determine a value at the address of the L2P mapping table.

[0015] In some implementations, in order to search for a fragment of data, the memory controller is further configured to: in response to a value being one of the IDs of a storage block in a volatile memory device, obtain the fragment of data from a storage block having the ID in the volatile memory device; or in response to a value being one of the addresses of a storage area in a non-volatile memory device, obtain the fragment of data from a storage area having the physical address in the non-volatile memory device.

[0016] In some implementations, in order to search for the segments of the data, the memory controller includes a plurality of L2P search engines configured to respectively search for the plurality of segments of the data in parallel based on the L2P mapping table.

[0017] In some implementations, the memory controller is further configured to: cache the segments of data in the volatile memory device, or flush the segments of data from the volatile memory device to the non-volatile memory device.

[0018] On the other hand, a memory controller includes a volatile memory device interface operably coupled to a volatile memory device, and an L2P search engine configured to maintain an L2P mapping table stored in the volatile memory device through the volatile memory device interface, such that the L2P mapping table maps a first set of logical addresses to IDs of cached memory blocks, respectively.

[0019] In some implementations, the L2P search engine is further configured to: search for a first set of data that is associated with the first set of logical addresses and is cached in the storage block based on the L2P mapping table.

[0020] In some implementations, the memory controller further comprises a non-volatile memory device interface operably coupled to the non-volatile memory device. In some implementations, the L2P search engine is further configured to: maintain an L2P mapping table stored in the volatile memory device, so that the L2P mapping table further maps the second set of logical addresses to physical addresses of the storage area of ​​the non-volatile memory device, respectively.

[0021] In some implementations, the L2P search engine is further configured to search for a second set of data that is associated with the second set of logical addresses and is stored in the storage area based on the L2P mapping table.

[0022] In some implementations, the volatile storage device includes DRAM and the non-volatile storage device includes NAND flash memory.

[0023] In some implementations, the memory controller further includes a range partitioning accelerator configured to, in response to receiving a write request indicating a fragment of the first set of data associated with a first logical address in the first set of logical addresses, assign the fragment of the first set of data to a first storage block in the storage blocks. In some implementations, the first storage block has a first ID in the ID. In some implementations, the memory controller further includes a host interface configured to obtain the fragment of the first set of data to cache the fragment of the first set of data in the first storage block.

[0024] In some implementations, to maintain the L2P mapping table, the L2P search engine is further configured to: in response to the host interface retrieving a segment of the first set of data to the first storage block, update the L2P mapping table to map the first logical address to the first ID.

[0025] In some implementations, the memory controller also includes a host interface that is configured to: in response to receiving a read request indicating a fragment of the first set of data associated with a second logical address in the first set of logical addresses, obtain the fragment of the first set of data from a second storage block in the storage block in the cache based on the L2P mapping table.

[0026] In some implementations, the L2P search engine is further configured to: determine an address of an L2P mapping table in the volatile memory device based on the second logical address; and identify a second ID at the address of the L2P mapping table in the volatile memory device in the ID, the second storage block having the second ID.

[0027] In another aspect, a method for operating a memory controller is provided. An L2P mapping table stored in a volatile memory device is generated. The L2P mapping table is maintained so that the L2P mapping table maps a first group of logical addresses to IDs of cached memory blocks, respectively.

[0028] In some implementations, the first set of data is cached in a storage block. In some implementations, the first set of data is respectively associated with a first set of logical addresses.

[0029] In some implementations, the first set of data is searched in the storage block based on the L2P mapping table.

[0030] In some implementations, the volatile storage device includes a cache.

[0031] In some implementations, the second set of data is stored in a storage area of ​​the non-volatile memory device. In some implementations, the second set of data is associated with a second set of logical addresses, respectively. In some implementations, an L2P mapping table stored in the volatile memory device is maintained, so that the L2P mapping table also maps the second set of logical addresses to physical addresses of the storage area of ​​the non-volatile memory device, respectively.

[0032] In some implementations, the volatile storage device includes DRAM and the non-volatile storage device includes NAND flash memory.

[0033] In some implementations, in response to receiving a write request indicating a fragment of the first set of data associated with a first logical address in the first set of logical addresses, the fragment of the first set of data is assigned to a first storage block in the storage blocks. In some implementations, the first storage block has a first ID in the ID. In some implementations, the fragment of the first set of data is retrieved to cache the fragment of the first set of data in the first storage block.

[0034] In some implementations, to maintain the L2P mapping table, in response to fetching a segment of the first set of data to the first storage block, the L2P mapping table is updated to map the first logical address to the first ID.

[0035] In some implementations, in response to receiving a read request indicating a segment of the first set of data associated with a second logical address in the first set of logical addresses, the segment of the first set of data is retrieved from a second storage block in the storage blocks in the cache based on the L2P mapping table.

[0036] In some implementations, an address of an L2P mapping table in the volatile memory device is determined based on the second logical address, and a second ID in the ID is identified at the address of the L2P mapping table in the volatile memory device. In some implementations, the second memory block has a second ID. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The accompanying drawings, which are incorporated herein and constitute a part of the specification, illustrate various aspects of the disclosure and, together with the description, further serve to explain the principles of the disclosure and to enable one skilled in the relevant art to make and use the disclosure.

[0038] Figure 1 A block diagram of a system including a memory system according to some aspects of the present disclosure is shown.

[0039] Figure 2A A diagram showing a memory card having a storage device according to some aspects of the present disclosure is shown.

[0040] Figure 2B A diagram showing an SSD having a storage device according to some aspects of the present disclosure.

[0041] Figure 3 A block diagram of a memory controller according to some aspects of the present disclosure is shown.

[0042] Figure 4 A schematic diagram of a NAND flash memory device including peripheral circuits according to some aspects of the present disclosure is shown.

[0043] Figure 5 A schematic diagram of a DRAM device including peripheral circuits according to some aspects of the present disclosure is shown.

[0044] Figure 6 A detailed schematic diagram of a memory system performing a data search according to some aspects of the present disclosure is shown.

[0045] Figure 7 An L2P mapping table according to some aspects of the present disclosure is shown.

[0046] Figure 8 A flow chart of a method for operating a memory controller according to some aspects of the present disclosure is shown.

[0047] Fig. 9 A flow chart of a method for processing a write request according to some aspects of the present disclosure is shown.

[0048] Fig.10 A flow chart of a method for processing a read request according to some aspects of the present disclosure is shown.

[0049] The present disclosure will be described with reference to the accompanying drawings. DETAILED DESCRIPTION

[0050] Typically, a term can be understood at least in part from usage in context. For example, the term "one or more" as used herein depends at least in part on the context and can be used to describe any feature, structure, or characteristic in a singular sense, or can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, again, terms such as "a", "an", or "the" can be understood to convey singular usage or to convey plural usage, which depends at least in part on the context. In addition, the term "based on" can be understood as not necessarily intended to convey an exclusive set of factors, and can instead allow the presence of additional factors that are not necessarily explicitly described, again, which depends at least in part on the context.

[0051] Data search in an SSD involves locating and accessing requested data stored in non-volatile storage devices (e.g., NAND flash memory). The purpose of data search is to efficiently retrieve or modify data as needed by the system. This can be achieved through the translation layer of the memory controller, which maps the logical addresses used by the operating system to physical addresses within the SSD. Therefore, the memory controller plays a vital role in managing data searches and ensuring optimal performance.

[0052] For enterprise-class SSDs, or any SSD with volatile memory (e.g., DRAM), "hot data" refers to frequently used and / or recently accessed data stored in cache. Hot data is usually cached in DRAM to speed up future access requests. However, the efficiency of known search algorithms for hot data in enterprise-class SSDs is limited by the time complexity of known search algorithms, O(n) or O(logn), and may become a performance bottleneck, especially when the amount of data is huge.

[0053] To solve one or more of the aforementioned problems, the present disclosure introduces a data search scheme in a memory system that extends the use of an L2P mapping table to both non-volatile memory and volatile memory to reduce the complexity of cache data searches in volatile memory and improve search efficiency. In some implementations, physical addresses of storage blocks in volatile memory (e.g., block identifiers (IDs)), similar to physical addresses of storage areas in non-volatile memory (e.g., physical page addresses (PPAs) in NAND flash memory), are mapped to logical addresses of host / user data (e.g., logical block addresses (LBAs)) in a unified extended L2P mapping table for data search across non-volatile memory and volatile memory. Thus, the time complexity of hot data search can be reduced to O(1). In some implementations, a memory controller maintains a unified extended L2P mapping table and updates the unified extended L2P mapping table in response to processing write and read requests from a host. In some implementations, multiple dedicated circuits (rather than firmware) are used to process data search requests in parallel to further improve search efficiency and reduce firmware overhead.

[0054] Figure 1 1 shows a block diagram of a system 100 including a memory system 102 according to some aspects of the present disclosure. The system 100 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle-mounted computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a storage device therein. Figure 1 As shown, the system 100 may include a host 108 and a memory system 102 having one or more memory devices 104 and a memory controller 106. The host 108 may be a processor of an electronic device, such as a central processing unit (CPU) or a system-on-chip (SoC), such as an application processor (AP). The host 108 may be configured to send data to or receive data (also known as user data or host data) from the memory system 102. The memory system 102 may be a storage device product (e.g., an SSD) integrating a memory controller 106 and one or more memory devices 104.

[0055] The memory device 104 may be any memory device disclosed in the present disclosure, including a non-volatile memory device (e.g., a NAND flash memory device). In some implementations, the memory device 104 also includes one or more volatile memory devices (e.g., a DRAM device or a static random access memory (SRAM) device).

[0056] According to some implementations, the memory controller 106 is operably coupled to the memory device 104 and the host 108 and is configured to control the memory device 104. The memory controller 106 can manage data stored in the memory device 104 and communicate with the host 108. In some implementations, the memory controller 106 is designed to operate in a low duty cycle environment, such as a secure digital (SD) card, a compact Flash (CF) card, a universal serial bus (USB) flash drive, or other media used in electronic devices (e.g., personal computers, digital cameras, mobile phones, etc.). In some implementations, the memory controller 106 is designed to operate in a high duty cycle environment, where an SSD or an embedded multimedia card (eMMC) is used as a data storage device for mobile devices (e.g., smart phones, tablet computers, laptop computers, etc.) and enterprise-level storage device arrays. The memory controller 106 can be configured to control the operation of the memory device 104, such as read, program / write, and / or erase operations. The memory controller 106 may also be configured to manage various functions regarding data stored or to be stored in the memory device 104, including but not limited to bad block management, garbage collection, L2P address translation, wear leveling, etc. In some implementations, the memory controller 106 is also configured to process error correction codes (ECC) regarding data read from or written to the memory device 104. Any other suitable functions (e.g., formatting the memory device 104) may also be performed by the memory controller 106. The memory controller 106 may communicate with an external device (e.g., the host 108) according to a specific communication protocol.For example, the memory controller 106 can communicate with an external device through at least one of various interface protocols (for example, a non-volatile memory express (NVMe) protocol, an NVMe-over-fabric (NVMe-oF) protocol, a PCI-express (PCI-E) protocol, a universal serial bus (USB) protocol, a multimedia card (MMC) protocol, a peripheral component interconnection (PCI) protocol, an advanced technology attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer small interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronic (IDE) protocol, a FireWire protocol, etc.).

[0057] Consistent with the scope of the present disclosure and disclosed in detail below, the memory controller 106 may be configured to maintain an L2P mapping table that maps logical addresses of host / user data to IDs of storage blocks in a volatile storage device of the storage device 104 and addresses of storage regions in a non-volatile storage device of the storage device 104, respectively. The memory controller 106 may also be configured to search for segments of data based on the L2P mapping table.

[0058] The memory controller 106 and the one or more memory devices 104 may be integrated into various types of storage devices, for example, included in the same package (e.g., a universal flash storage (UFS) package or an eMMC package). That is, the memory system 102 may be implemented and packaged into different types of final electronic products. Figure 2AIn one example shown in FIG. 1 , the memory controller 106 and the single memory device 104 may be integrated into a memory card 202. The memory card 202 may include a PC card (PCMCIA, personal computer memory card international association), a CF card, a smart media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 202 may also include a processor that connects the memory card 202 to a host (e.g., Figure 1 The host 108 in the memory card connector 204 is coupled. Figure 2B In another example shown in FIG. 1 , the memory controller 106 and the plurality of memory devices 104 may be integrated into an SSD 206. The SSD 206 may also include a processor that interfaces the SSD 206 with a host (eg, Figure 1 In some implementations, the storage capacity and / or operating speed of the SSD 206 is greater than the storage capacity and / or operating speed of the memory card 202. In some implementations, the memory system 102 is implemented as an SSD 206, which (e.g., an enterprise-class SSD) includes both a non-volatile memory device and a volatile memory device as the memory device 104.

[0059] Figure 3 1 shows a block diagram of a memory controller 300 according to some aspects of the present disclosure. The memory controller 300 may be Figure 1 An example of a memory controller 106 in FIG. Figure 3As shown in FIG. 3 , the memory controller 300 may include a processing unit 308, an SRAM 310, and a read-only memory (ROM) 311. In some implementations, the processing unit 308 is implemented by a microprocessor (e.g., a digital signal processor (DSP)) or a microcontroller (also known as a microcontroller unit (MCU)) that executes firmware and / or software modules to perform various functions described herein. The various firmware modules in the memory controller 300 described herein may be implemented as firmware codes or instructions stored in the ROM 311 and executed by the processing unit 308. In some implementations, the processing unit 308 includes one or more hardware circuits, such as fixed logic units (e.g., logic gates), multiplexers, flip-flops, state machines, field-programmable gate arrays (FPGAs), and programmable logic devices (PLDs). For example, the hardware circuit may include a dedicated circuit (e.g., an application-specific integrated circuit (ASIC)) for a given logic function, which is known when the device is manufactured.

[0060] like Figure 3 As shown in FIG. 1 , the memory controller 300 may further include various input / output (I / O) interfaces (I / F), such as a NAND interface 312 operably coupled to a NAND flash memory 302 (e.g., an example of a non-volatile memory device), a DRAM interface 314 operably coupled to a DRAM 304 (e.g., an example of a volatile memory device), and a host interface 316 operably coupled to a host 306 (e.g., an example of the host 108). The NAND interface 312, the DRAM interface 314, and the host interface 316 may be configured to transmit data, commands, clocks, or any suitable signals between the processing unit 308 and the NAND flash memory 302, the DRAM 304, and the host 306, respectively. The NAND interface 312, the DRAM interface 314, and the host interface 316 may implement any suitable communication protocol (e.g., NVMe protocol and PCI-E protocol, double data rate (DDR) protocol, to name a few) to facilitate data transfer, communication, and management.

[0061] As described above, both SRAM 310 and DRAM 304 can be considered as volatile memory devices that can be controlled and accessed by memory controller 300 in the memory system. Consistent with the scope of the present disclosure, cache can be implemented as part of the volatile memory device, for example, by SRAM 310 and / or DRAM 304. It is understood that although Figure 3 The SRAM 310 is shown as being located within the memory controller 300 and the DRAM 304 is shown as being located external to the memory controller 300 , but in some examples both the SRAM 310 and the DRAM 304 may be located within the memory controller 300 or external to the memory controller 300 .

[0062] Figure 4 4 shows a schematic circuit diagram of a NAND flash memory device 400 including a peripheral circuit 402 according to some aspects of the present disclosure. The NAND flash memory device 400 may be Figure 3 4. An example of a NAND flash memory 302 in FIG. 4. The NAND flash memory device 400 may include a memory cell array 401 and a peripheral circuit 402 operably coupled to the memory cell array 401. The memory cells 406 in the memory cell array 401 are provided in the form of an array of NAND memory strings 408, each of the NAND memory strings 408 extending vertically above a substrate (not shown). In some implementations, each NAND memory string 408 includes a plurality of memory cells 406 operably coupled in series and stacked vertically. Each memory cell 406 may hold a continuous analog value (e.g., a voltage or charge) that depends on the number of electrons trapped in the region of the memory cell 406. Each memory cell 406 may be a floating gate type memory cell including a floating gate transistor, or a charge trapping type memory cell including a charge trapping transistor.

[0063] In some implementations, each memory cell 406 is a single-level cell (SLC) having two possible levels (memory states), and can therefore store one bit of data. For example, the first state "0" can correspond to a first range of threshold voltages, and the second state "1" can correspond to a second range of threshold voltages. In some implementations, each memory cell 406 is an xLC capable of storing more than a single bit of data at more than four levels. For example, an xLC can store two bits per cell (aka, multi-level cell (MLC)), three bits per cell (aka, triple-level cell (TLC)), or four bits per cell (aka, quad-level cell (QLC)). Each xLC can be programmed to take a range of possible nominal storage values ​​(i.e., 2 of the N bits of data). N In some implementations, each storage unit 406 is set to 2 N One level among the levels corresponding to the segment of N-bit data, where N is an integer greater than 2.

[0064] like Figure 4 As shown in FIG. 4 , each NAND storage string 408 may also include a source select gate (SSG) transistor 410 at its source end and a drain select gate (DSG) transistor 412 at its drain end. The SSG transistor 410 and the DSG transistor 412 may be configured to activate the selection NAND storage string 408 (column of the array) during read and program operations. In some implementations, the sources of the NAND storage strings 408 in the same block 404 are coupled through the same source line (SL) 414 (e.g., a common SL). In other words, according to some implementations, all NAND storage strings 408 in the same block 404 have an array common source (ACS). According to some implementations, the drain of each NAND storage string 408 is coupled to a corresponding bit line 416, and data can be read from or written to the bit line 416 via an output bus (not shown). In some implementations, each NAND memory string 408 is configured to be selected or deselected by applying a selection voltage or a deselection voltage to the gate of a corresponding DSG transistor 412 via one or more DSG lines 413 and / or applying a selection voltage or a deselection voltage to the gate of a corresponding SSG transistor 410 via one or more SSG lines 415.

[0065] like Figure 4 As shown in FIG. 4 , the NAND memory string 408 can be organized into a plurality of blocks 404, each of which can have a common source line 414 (e.g., coupled to an ACS). In some implementations, each block 404 is a basic data unit for an erase operation, i.e., all memory cells 406 on the same block 404 are erased at the same time. To erase the memory cells 406 in a selected block 404, the source lines 414 coupled to the selected block 404 and the unselected blocks 404 in the same plane as the selected block 404 can be biased with an erase voltage (Vers), e.g., a high positive bias voltage (e.g., 20V or higher).

[0066] The memory cells 406 of adjacent NAND memory strings 408 may be coupled by word lines 418, which select which row of memory cells 406 is affected by read and program operations. In some implementations, each word line 418 is coupled to a physical page 420 of memory cells 406, which is the basic data unit for read and write (program) operations. The size (in bits) of one physical page 420 may be related to the number of NAND memory strings 408 coupled by word lines 418 in one block 404. Each word line 418 may include a plurality of control gates (gate electrodes) at each memory cell 406 in a corresponding physical page 420 and a gate line coupled to the control gates.

[0067] The peripheral circuit 402 may be operably coupled to the memory cell array 401 through the bit lines 416, word lines 418, source lines 414, SSG lines 415, and DSG lines 413. The peripheral circuit 402 may include any suitable analog, digital, and mixed signal circuits to facilitate the operation of the memory cell array 401 by applying a voltage signal to each selected memory cell 406 through the bit lines 416, word lines 418, source lines 414, SSG lines 415, and DSG lines 413 and / or sensing a current signal from each selected memory cell 406 through the bit lines 416, word lines 418, source lines 414, SSG lines 415, and DSG lines 413. The peripheral circuit 402 may include various types of peripheral circuits formed using complementary metal-oxide-semiconductor (CMOS) technology.

[0068] Figure 5 5 shows a schematic circuit diagram of a DRAM device 500 including a peripheral circuit 502 according to some aspects of the present disclosure. The DRAM device 500 may be Figure 3500 is an example of a DRAM 304 in FIG. 500. DRAM device 500 may include a memory cell array 501 and a peripheral circuit 502 operably coupled to memory cell array 501. Memory cells 503 may be arranged in memory cell array 501 having rows and columns. DRAM device 500 requires periodic refreshing of memory cells 503. In some implementations, each memory cell 503 includes a capacitor 507 for storing 1 bit of data as a positive charge or a negative charge and a transistor 505 for controlling access to capacitor 507. That is, according to some implementations, as Figure 5 Each memory cell 503 shown in FIG. 5 is a one-transistor, one-capacitor (1T1C) cell.

[0069] The DRAM device 500 may include: a word line 504 coupling the peripheral circuit 502 and the memory cell array 501, the word line 504 being used to control the switch of the transistor 505 in the memory cell 503 located in one row; and a bit line 506 coupling the peripheral circuit 502 and the memory cell array 501, the bit line 506 being used to send data to the memory cell 503 located in one column and / or receive data from the memory cell 503 located in one column. That is, each word line 504 is coupled to a corresponding row of the memory cell 503, and each bit line 506 is coupled to a corresponding column of the memory cell 503. The gate of the transistor 505 may be coupled to the word line 504, one of the source and the drain of the transistor 505 may be coupled to the bit line 506, the other of the source and the drain of the transistor 505 may be coupled to one electrode of the capacitor 507, and the other electrode of the capacitor 507 may be coupled to the ground.

[0070] The peripheral circuit 502 may be coupled to the memory cell array 501 through the bit line 506, the word line 504, and any other suitable metal wiring. The peripheral circuit 502 may include any suitable circuit to facilitate the operation of the memory cell array 501 by applying a voltage signal to each memory cell 503 through the word line 504 and the bit line 506 and / or sensing a current signal from each memory cell 503 through the word line 504 and the bit line 506. The peripheral circuit 502 may include various types of peripheral circuits formed using CMOS technology.

[0071] Figure 6 Detailed schematic diagram of a memory system 600 for performing data search according to some aspects of the present disclosure is shown. The memory system 600 may be Figure 1 An example of a memory system 102 in FIG. Figure 6 As shown in FIG. 6 , the memory system 600 may include a memory controller 601, a volatile memory device 602, and a non-volatile memory device 604. The memory controller 601 may be Figure 1 The volatile memory device 602 and the non-volatile memory device 604 may be an example of a memory controller 106 in FIG. Figure 1 In some implementations, the volatile memory device 602 includes a DRAM (e.g., Figure 5 DRAM device 500 in ), and non-volatile memory device 604 includes a NAND flash memory (e.g., Figure 4 NAND flash memory device 400 in FIG. 4 ). From a host (not shown) (eg, Figure 1 604). Data stored in the volatile memory device 602 (host 108 in the volatile memory device 602) can be stored as "hot data" in the volatile memory device 602, or as "cold data" in the non-volatile memory device 604. It can be understood that in some examples, "hot data" can be stored in the non-volatile memory device 604, while "cold data" can be stored in the volatile memory device 602, or both "hot data" and "cold data" can be stored in the volatile memory device 602 or the non-volatile memory device 604. As described above, "hot data" refers to data that is frequently used and / or recently accessed (for example, such data is stored in the cache 606 in the volatile memory device 602). Conversely, "cold data" refers to data stored in the non-volatile memory device 604, for example, data that is flushed from the cache 606 to the non-volatile memory device 604 under certain conditions (for example, the cache 606 is full of data, the data has not been accessed or used for a period of time, etc.). In some implementations, the memory controller 601 is also configured to cache segments of host / user data in the volatile memory device 602 or flush segments of the host / user data from the volatile memory device 602 to the non-volatile memory device 604 .

[0072] In order to enable searching and accessing cold data, the non-volatile memory device 604 may be divided into a plurality of storage areas 605, each of which has a unique physical address. In some implementations, each storage area 605 includes one or more logical pages (e.g., a portion (e.g., 1 / 2, 1 / 4, or 1 / 8) of a physical page 420 of the NAND flash memory device 400). For example, the size of each storage area 605 may be 4096 bytes. It will be appreciated that the storage area 605 may correspond to any suitable group of storage cells other than a page in the non-volatile memory device 604 (e.g., a portion of a page, a block (e.g., a block 404 of the NAND flash memory device 400), etc.). For example, when the storage area 605 corresponds to a page of the non-volatile memory device 604, the physical address of the storage area 605 may be a physical page address (PPA).

[0073] Consistent with the scope of the present disclosure, in order to enable searching and accessing hot data, the cache 606 of the volatile memory device 602 may be divided into a plurality of memory blocks 607, each of which has a unique identifier (ID), also known as a memory block ID. In some implementations, each memory block 607 includes one or more pages (e.g., rows or columns of memory cells 503 of the DRAM device 500). In some implementations, in order to enable unified data searches between the non-volatile memory device 604 and the volatile memory device 602, the size of each storage area 605 and the size of each memory block 607 may be the same. It is understood that in some examples, the size of each storage area 605 and the size of each memory block 607 may be different. For example, the size of each memory block 607 may also be 4096 bytes. It is understood that the memory block 607 may correspond to any suitable group of memory cells (e.g., a portion of a page, a codeword, etc.) in the volatile memory device 602 other than a page.

[0074] The cache 606 may be a portion of the volatile memory device 602 that temporarily stores (caches) frequently used and / or recently accessed data (i.e., hot data) to speed up read and write operations of the non-volatile memory device 604. Any suitable cache algorithm (including, for example, least recently used (LRU), most recently used (MRU), and first-in, first-out (FIFO)) may be used to determine which data should be stored in the cache 606 and when the data should be replaced. In some implementations, data from the host (host / user data) is first cached in the cache 606 of the volatile memory device 602 as hot data, and is flushed to the non-volatile memory device 604 as cold data under certain conditions based on the cache algorithm. For example, when the size of the data in the cache 606 reaches a preset threshold (maximum cache size), the data in the cache 606 may be flushed to the non-volatile memory device 604. Cache 606 may be implemented by any suitable type of volatile memory device 602 (e.g., Figure 3 This may be accomplished using DRAM 304 and / or SRAM 310 in the memory.

[0075] Consistent with the scope of the present disclosure, in order to enable unified search and access to both hot and cold data, a unified extended L2P mapping table 612 may be maintained and stored in the volatile memory device 602 to map the logical address of the data not only to the physical address 616 (e.g., PPA) of the storage area 605 in the non-volatile memory device 604, but also to the ID 614 of the storage block 607 in the cache 606 of the volatile memory device 602. The logical address may identify the host / user data and is known to the memory controller 601. In some implementations, the logical address (e.g., logical block address (LBA)) indicates the basic logical data unit for each read or write operation. In some implementations, in order to enable unified data search between the non-volatile memory device 604 and the volatile memory device 602, the size of each storage area 605, the size of each storage block 607, and the size of the data corresponding to each logical address may be the same. For example, the size of the data corresponding to each logical address may also be 4096 bytes. Since the memory controller 601 operates based on logical addresses rather than physical addresses (e.g., physical address 616 or ID 614), the L2P mapping table 612 may be used to enable conversion between logical addresses and physical addresses in a unified manner across both the non-volatile memory device 604 and the volatile memory device 602, as described in detail below.

[0076] The L2P mapping table 612 may be stored in any suitable type of volatile storage device 602 (e.g., Figure 3 In some implementations, the same volatile memory device 602 (e.g., Figure 3 DRAM 304 in SRAM 310 includes both cache 606 and L2P mapping table 612. It is understood that in some examples, cache 606 and L2P mapping table 612 can be included in different volatile memory devices 602. For example, SRAM 310 can include cache 606, and DRAM 304 can include L2P mapping table 612. Although L2P mapping table 612 is in Figure 6 6 as being outside of cache 606 , but it will be appreciated that in some examples, L2P mapping table 612 may also be stored in cache 606 .

[0077] The L2P mapping table 612 may be stored in the volatile memory device 602 using addresses in the volatile memory device 602. For example, Figure 7As shown in FIG. 1 , the L2P mapping table 612 may include addresses 704 (VMAdd) in the volatile memory device 602, each of which is associated with a value 706. The value 706 may include two types of information: an ID 614 (e.g., ID1, ID2, ID3, etc.) of a storage block 607 in the cache 606, and a physical address 616 (PPA, e.g., PPA1, PPA2, PPA3, PPA4, etc.) of a storage area 605 in the non-volatile memory device 604. Figure 7 As shown in FIG. 1 , the L2P mapping table 612 may also map a logical address 702 (LBA) of the host / user data to an ID 614 of a storage block 607 in the cache 606 and a physical address 616 of a storage area 605 in the non-volatile storage device 604 via an address 704. For example, for each fragment of the host / user data, a corresponding address 704 of the L2P mapping table 612 in the volatile storage device 602 may be determined based on a corresponding LBA 702 associated with the fragment of the host / user data. Figure 7 In one example shown in FIG. 7 , each address 704 may be calculated by adding an address offset (OFF) to a corresponding LBA 702 (e.g., 0, 1, 2, 3, 4, 5, 6, etc.). The address offset may be determined, for example, based on the location where the L2P mapping table 612 is stored in the volatile memory device 602. Therefore, a corresponding value 706 at the determined address 704 of the L2P mapping table 612 may be determined, which indicates an ID 614 of a storage block 607 in the cache or a physical address 616 of a storage area in the non-volatile memory device 604 through the address 704. Therefore, the LBA 702 of the host / user data may be mapped to an ID 614 of a storage block 607 in the cache 606 and a physical address 616 of a storage area 605 in the non-volatile memory device 604, respectively, through the L2P mapping table 612.

[0078] Return to reference Figure 6 , the memory controller 601 may include a plurality of I / O interfaces, including a volatile memory interface 620 operatively coupled to the volatile memory device 602, a non-volatile memory interface 622 operatively coupled to the non-volatile memory device 604, and a host interface 618 operatively coupled to the cache 606 of the volatile memory device 602 and a host (not shown). Examples of these I / O interfaces may include Figure 3 The DRAM interface 314, NAND interface 312 and host interface 316 can implement any suitable communication protocol (e.g., NVMe protocol and PCI-E protocol, DDR protocol, to name a few) to facilitate data transfer, communication and management.

[0079] The host interface 618 may be configured to receive write requests and read requests from the host. Each write request may indicate a segment of data associated with a logical address (e.g., LBA) to be written to the memory system 600. Similarly, each read request may indicate a segment of data associated with a logical address (e.g., LBA) to be read from the memory system 600. In some implementations, in response to receiving a write request or a read request, the host interface 618 is also configured to obtain a segment of the data from the host to temporarily store (cache) the segment of the data in the cache 606, and vice versa. For example, the host interface 618 may include a direct memory access (DMA) unit that accesses data to and from the cache 606.

[0080] The non-volatile memory interface 622 may be configured to enable the memory controller 601 to access data stored in the non-volatile memory device 604 based on the physical address (e.g., PPA) of the storage area 605. The volatile memory interface 620 may be configured to enable the memory controller 601 to access data stored in the volatile memory device 602 (e.g., maintaining the L2P mapping table 612 and accessing the data in the cache 606). In some implementations, the volatile memory interface 620 is configured to convert the ID 614 of the storage block 607 in the cache 606 into a physical address of the volatile memory device 602, which can be used directly by the memory controller 601 to operate the storage unit of the volatile memory device 602. In other words, although the ID 614 of the storage block 607 in the cache 606 can be used to facilitate hot data searches through the L2P mapping table 612, the memory controller 601 can still use the physical address of the volatile memory device 602 to access the data in the volatile memory device 602. Therefore, according to some implementations, the volatile memory device 602 does not need to be modified to accommodate hot data searches using the ID 614 of the memory block 607 .

[0081] like Figure 6 As shown in FIG. 1 , the memory controller 601 may further include a range partitioning accelerator 608 and one or more L2P search engines 610 operably coupled to the volatile memory device 602, the non-volatile memory interface 622, and the volatile memory interface 620. In some implementations, the range partitioning accelerator 608 and the L2P search engine 610 are composed of a memory device stored in a memory (e.g., Figure 3 311) in the firmware code / instructions and implemented by the processing unit (e.g., Figure 3The scope partitioning accelerator 608 and the L2P search engine 610 are firmware modules executed by the processing unit 308 in the scope partitioning accelerator 608. In some implementations, the scope partitioning accelerator 608 and the L2P search engine 610 are hardware modules implemented by dedicated circuits (e.g., ASICs) to perform the dedicated functions described herein. The hardware implementation of the scope partitioning accelerator 608 and the L2P search engine 610 can improve search parallelism and reduce firmware overhead, thereby further improving data search performance.

[0082] The range partitioning accelerator 608 may be configured to generate data search requests based on read and write requests from the host via the host interface 618, and to distribute the search requests to the L2P search engine 610. That is, the range partitioning accelerator 608 may, for example, divide the read request or the write request into search requests to be processed in parallel by a plurality of L2P search engines 610 based on different logical addresses associated with the data of the read request or the write request. For example, for each search request, the range partitioning accelerator 608 may identify an idle L2P search engine 610 to process the search request. In some implementations, in response to receiving a write request indicating a fragment of data associated with a logical address (e.g., an LBA), the range partitioning accelerator 608 is configured to assign the fragment of the data to one of the storage blocks 607 in the cache 606 having a unique ID in the ID 614, which triggers the host interface 618 to obtain the corresponding fragment of the data from the host to the corresponding storage block 607 in the cache 606.

[0083] The L2P search engine 610 may be configured to process the search request and, based on the processing of the search request, maintain the L2P mapping table 612 stored in the volatile memory device 602 through the volatile memory interface 620. In some implementations, a single L2P mapping table 612 is maintained for the memory system 600, and multiple L2P search engines 610 are configured to maintain the same L2P mapping table 612 and use the same L2P mapping table 612 for hot data searches and cold data searches. For example, multiple L2P search engines 610 may be configured to search for multiple segments of data in parallel, respectively, based on the same L2P mapping table 612. It will be appreciated that, in some examples, a single L2P search engine 610 may be used to process the search request. In some implementations, in response to the host interface 618 retrieving a segment of data from the host to a corresponding storage block 607 in the cache 606 in response to a write request, the L2P search engine 610 is configured to update the L2P mapping table 612 to map a logical address (e.g., LBA) associated with the segment of data to a unique ID 614 of the corresponding storage block 607. For example, Figure 7As shown in , assuming that the LBA 702 of the fragment of data is "3", the value 706 may be updated by the search engine 610 to become "ID3", which is the unique ID 614 of the corresponding storage block 607. The value 706 may be stored at address 704 "OFF+3" of the L2P mapping table 612 in the volatile storage device 602. In some implementations, in response to flushing the cached fragment of data in the cache 606 to a storage area having a unique physical address in the physical address 616 (e.g., PPA) in the storage area 605 in the non-volatile storage device 604, the L2P search engine 610 is also configured to update the L2P mapping table 612 to map the logical address (e.g., LBA) associated with the fragment of data to the unique physical address 616 of the corresponding storage area 605. For example, as Figure 7 As shown in , assuming that the LBA 702 of the fragment of the data is "3", the value 706 can be updated by the L2P search engine 610 to become "PPA5", which PPA5 is the unique physical address 616 of the corresponding storage area 605, because the fragment of the data associated with LBA 3 has been moved from ID3 in the cache 606 to PPA5 in the non-volatile memory 604.

[0084] In some implementations, in response to receiving a search request indicating a read request for a segment of data having a logical address (e.g., an LBA), the L2P search engine 610 is configured to search for the segment of the data based on the logical address and the L2P mapping table 612. The L2P mapping table 612 can be configured to determine an address of the L2P mapping table 612 in the volatile memory device 602 based on the logical address, and then determine a value at the address of the L2P mapping table 612. The value can be an ID 614 of a storage block 607 in a cache or a physical address 616 of a storage area 605 in a non-volatile memory device 604. In one example, as Figure 7 As shown in FIG. 6 , assuming that LBA 702 of the data segment is “0”, the search engine 610 may first add LBA 702 “0” to the address offset “OFF” to obtain address 704 “OFF”, and then identify the value 706 at address 704 “OFF” as “ID1”, which means that the data segment to be read is hot data in the storage block ID1 currently cached in the cache 606. In another example, as Figure 7As shown in , assuming that the LBA 702 of the fragment of data is "2", the L2P search engine 610 can first add LBA 702 "2" to the address offset "OFF" to obtain address 704 "OFF+2", and then identify the value 706 at address 704 "OFF+2" as "PPA1", which means that the fragment of data to be read is cold data currently stored in the storage area PPA1 in the non-volatile memory device 604.

[0085] In some implementations, in response to identifying the ID 614 of the memory block 607 in the cache 606, the L2P search engine 610 provides the identified ID 614 to the volatile memory interface 620, and the volatile memory interface 620 converts the ID 614 to a corresponding physical address in the volatile memory device 602, so that the host interface 618 can, for example, use DMA to obtain the segment of the data from the corresponding physical address in the volatile memory device 602. In some implementations, in response to identifying the physical address 616 of the storage area 605 in the non-volatile memory device 604, the L2P search engine 610 provides the identified physical address 616 (e.g., PPA) to the non-volatile memory interface 622, so that the non-volatile memory interface 622 can obtain the segment of the data from the corresponding physical address in the non-volatile memory device 604.

[0086] Figure 8 A flow chart of a method 800 for operating a memory controller according to some aspects of the present disclosure is shown. The memory controller may be any suitable memory controller disclosed herein (e.g., memory controller 601). It will be appreciated that the operations shown in method 800 may not be exhaustive, and other operations may be performed before, after, or between any of the operations shown. In addition, some of the operations may be performed simultaneously or in different order. Figure 8 The order shown in is executed.

[0087] The memory controller is operably coupled to the volatile memory device and the non-volatile memory device. The volatile memory device may include a cache. The cache is divided into a plurality of memory blocks, each of which has a corresponding unique ID in the ID. The non-volatile memory device is divided into memory areas, each of which has a corresponding unique physical address in the physical address. For example, Figure 6As shown in the figure, the volatile memory device 602 may include a cache 606, which may be divided into storage blocks 607, each of which has a unique ID 614, and the non-volatile memory device 604 may be divided into storage areas 605, each of which has a unique physical address 616.

[0088] refer to Figure 8 , method 800 begins with operation 802, at which an L2P mapping table is generated and stored in a volatile memory device. Figure 6 As shown in FIG. 6 , the memory controller 601 may generate an L2P mapping table 612 during startup of the memory system 600 and store the L2P mapping table 612 in the volatile memory device 602 during operation of the memory system 600. For example, Figure 7 As shown in FIG. 6 , the L2P mapping table 612 may include a value 706 at each address 704 thereof, which value 706 may be mapped to an LBA 702 , respectively.

[0089] like Figure 8 As shown in FIG. 8 , method 800 proceeds to operation 804, at which a first set of data is cached in a memory block of the cache. The first set of data is respectively associated with a first set of logical addresses. For example, Figure 6 As shown in FIG. 6 , the memory controller 601 can cache multiple fragments of host / user data in the storage block 607 in the cache 606, respectively. Each fragment of the host / user data can be associated with a corresponding one of the logical addresses (e.g., LBA). In one example, the host interface 618 of the memory controller 601 can use DMA to obtain the host / user data from the host to cache the host / user data in the storage block 607.

[0090] like Figure 8 As shown in FIG. 8 , method 800 proceeds to operation 806, where an L2P mapping table is maintained such that the L2P mapping table maps the first set of logical addresses to the IDs of the cached storage blocks, respectively. For example, Figure 6 and Figure 7 As shown in FIG. 6 , the memory controller 601 may maintain an L2P mapping table 612 such that a group of LBAs 702 may be mapped to IDs 614 of the memory blocks 607 via addresses 704 , respectively.

[0091] like Figure 8 As shown in FIG. 8 , method 800 proceeds to operation 808, where a second set of data is stored in a storage area of ​​the non-volatile memory device. The second set of data is respectively associated with a second set of logical addresses. For example, Figure 6 As shown in FIG. 6 , the memory controller 601 can store the segments of the host / user data separately in the storage area 605 in the non-volatile memory device 604. Each segment of the host / user data can be associated with a corresponding one of the logical addresses (e.g., LBA). In one example, the segments of the host / user data can be flushed from the cache 606 to the non-volatile memory device 604.

[0092] like Figure 8 As shown in FIG. 8 , method 800 proceeds to operation 810, where an L2P mapping table is maintained such that the L2P mapping table maps the second set of logical addresses to physical addresses of the storage area of ​​the nonvolatile memory device, respectively. Figure 6 and Figure 7 As shown in , the memory controller 601 may maintain an L2P mapping table 612 so that another set of LBAs 702 may be mapped to physical addresses 616 (eg, PPAs) of the storage region 605 via addresses 704 , respectively.

[0093] like Figure 8 As shown in FIG. 8 , method 800 proceeds to operation 812, where a segment of data is searched based on the L2P mapping table. Figure 6 As shown in FIG. 6 , the plurality of L2P search engines 610 of the memory controller 601 may perform hot data search and cold data search on the plurality of fragments of data in parallel based on the logical addresses of the plurality of fragments of data and the L2P mapping table 612 .

[0094] In some implementations, to search for a segment of data, an address of an L2P mapping table in a volatile memory device is determined based on a logical address associated with the segment of data, and a value at the address of the L2P mapping table is determined. Figure 6 and Figure 7 As shown in , each L2P search engine 610 can calculate an address 704 of an L2P mapping table 612 based on an LBA 702 and an address offset, and identify a value 706 at the address 704 as an ID or a physical address (e.g., a PPA). In some implementations, in order to search for a fragment of data, in response to a value being one of the IDs of a storage block in a volatile storage device, a fragment of the data is obtained from a storage block having the ID in the volatile storage device. In some implementations, in order to search for a fragment of data, in response to a value being one of the physical addresses of a storage area in a non-volatile storage device, a fragment of the data is obtained from a storage area having the physical address in the non-volatile storage device. For example, as Figure 6 and Figure 7As shown in FIG. 6 , if the L2P search engine 610 identifies the value 706 at the address 704 as the ID 614, the host interface 618 can, for example, use DMA to obtain the fragment of data from the storage block 607 in the cache 606 having the identified ID 614. Conversely, if the L2P search engine 610 identifies the value 706 at the address 704 as the physical address 616 (e.g., PPA), the non-volatile memory interface 622 can obtain the fragment of data from the storage area 605 in the non-volatile memory device 604 having the identified physical address 616.

[0095] In some implementations, in response to receiving a write request indicating a segment of a first set of data associated with a first logical address in the first set of logical addresses, the segment of the first set of data is assigned to a first storage block in the storage blocks having a first ID in the IDs. Fig. 9 As shown in, for example, at 902, a write request can be divided into multiple search requests by the range partitioning accelerator 608, each of which is associated with a fragment of host / user data and its logical address. For example, at 904, the range partitioning accelerator 608 can assign storage block IDs to the fragments of host / user data respectively, so that each fragment of host / user data can be associated with a corresponding storage block ID. In some implementations, a fragment of the first group of data is obtained to cache the fragment of the first group of data in a first storage block. For example, at 906, the range partitioning accelerator 608 can trigger the host interface 618 to use DMA to obtain each fragment of host / user data to a corresponding storage block.

[0096] In some implementations, in response to obtaining a fragment of the first set of data to a first storage block, the L2P mapping table is updated to map the first logical address to the first ID. For example, at 908, the storage block ID of the fragment of cached host / user data can be updated in the L2P mapping table 612 by the L2P search engine 610 to be mapped to the logical address of the fragment of the host / user data. In some implementations, in response to the fragment of data being flushed from the first storage block of the cache to a storage area with a physical address of the non-volatile storage device, the L2P mapping table is updated to map the first logical address to the physical address. For example, at 910, it can be checked whether NAND flash memory programming is complete. NAND flash memory programming can be performed by flushing cached host / user data from the cache to the NAND flash memory. Once the NAND flash memory programming is completed, each fragment of the host / user data can be stored in a corresponding one of the storage areas, wherein each of the storage areas is associated with a PPA. If the answer to 910 is "yes", then at 912, the PPA of the segment storing the host / user data in the NAND flash memory can be updated by the L2P search engine 610 in the L2P mapping table 612 to be mapped to the logical address of the segment of the host / user data, thereby replacing the storage block ID. At 914, it can be checked whether a new incoming write request is received to determine whether the process can continue from 902 again for the new incoming write request. If the answer to 910 is "no", the process can proceed directly to 914, bypassing 912 without updating the L2P mapping table 612.

[0097] In some implementations, in response to receiving a read request indicating a segment of the first set of data associated with a second logical address in the first set of logical addresses, an address of an L2P mapping table in the volatile memory device is based on the second logical address, and a second ID of a second memory block is identified at the address of the L2P mapping table in the volatile memory. Fig.10 As shown in FIG. 1002, at 1002, a read request may be divided into a plurality of search requests by a range partitioning accelerator 608, each of which is associated with a logical address. At 1004, an idle L2P search engine 610 may be identified by the range partitioning accelerator 608 to execute the search request. At 1006, the L2P search engine 610 may locate the DRAM address by calculating the logical address, for example, adding the logical address to the address offset to obtain the DRAM address. At 1008, the value at the DRAM address may be obtained by the L2P search engine 610.

[0098] In some implementations, in response to the value being one of the IDs of the storage blocks in the volatile memory device, a fragment of the first set of data is obtained from a second storage block in the storage blocks in the cache based on the L2P mapping table. For example, at 1010, it can be determined whether the fragment of the host / user data is in the NAND flash memory based on the value (storage block ID or PPA) obtained at 1008. If the answer to 1010 is "no", this means that the fragment of the host / user data is still in the cache, and at 1014, the fragment of the host / user data can be obtained from the cache by the volatile memory interface 620 based on the storage block ID obtained at the DRAM address. If the answer to 1010 is "yes", this means that the fragment of the host / user data is in the NAND flash memory, and at 1012, the fragment of the host / user data can be read from the NAND flash memory by the non-volatile memory interface 622 based on the PPA obtained at the DRAM address. In either case, at 1016, the fragment of the host / user data can be sent to the host by the host interface 618.

[0099] In various aspects of the present disclosure, the functions described herein may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored as instructions on a non-transitory computer-readable medium. Computer-readable media include computer storage media. The storage medium may be a computer program that can be accessed by a memory controller (e.g., Figure 6 Any available medium accessed by the memory controller 601 in the computer. By way of example and not limitation, such computer readable media may include RAM, ROM, electrically erasable programmable ROM (EEPROM), compact disc read-only memory (CD-ROM) or other optical disk storage devices, hard disk drives (HDD) (e.g., magnetic disk storage devices or other magnetic storage devices), flash drives, SSDs, or any other medium that can be used to carry or store the desired program code in the form of instructions or data structures that can be accessed by a processing system (e.g., a mobile device or a computer). Disks and optical disks used herein include CDs, laser disks, optical disks, digital video discs (DVDs), and floppy disks, wherein disks typically reproduce data magnetically, while optical disks reproduce data optically using lasers. The above combinations should also be included within the scope of computer readable media.

[0100] The foregoing description of specific implementations can be easily modified and / or adapted to various applications. Therefore, based on the teaching and guidance presented herein, such adaptations and modifications are intended to fall within the meaning and range of equivalents of the disclosed implementations.

[0101] The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary implementations, but should be defined only in accordance with the following claims and their equivalents.

[0102] Although specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. Therefore, other configurations and arrangements may be used without departing from the scope of the present disclosure. Moreover, the subject matter described in the present disclosure may also be used for various other applications. The functions and structural features described in the present disclosure may be combined, adjusted, modified, and rearranged with each other in a manner consistent with the scope of the present disclosure.

Claims

1. A memory system, comprising: a volatile memory device configured to store a logical-to-physical (L2P) mapping table; as well as A memory controller is operably coupled to the volatile memory device and is configured to maintain the L2P mapping table stored in the volatile memory device such that the L2P mapping table maps a first set of logical addresses to identifiers (IDs) of cached memory blocks, respectively.

2. The memory system according to claim 1, wherein: The memory controller is further configured to cache a first set of data in the storage block, the first set of data being respectively associated with the first set of logical addresses.

3. The memory system according to claim 2, wherein: The memory controller is further configured to search for the first group of data cached in the storage block based on the L2P mapping table.

4. The memory system according to any one of claims 1 to 3, wherein: The volatile memory device includes the cache memory.

5. The memory system according to any one of claims 1 to 4, further comprising: a non-volatile memory device operably coupled to the memory controller; Wherein, the memory controller is further configured as: storing a second set of data in a storage area of ​​the nonvolatile memory device, the second set of data being respectively associated with a second set of logical addresses, and The L2P mapping table stored in the volatile memory device is maintained so that the L2P mapping table further maps the second set of logical addresses to physical addresses of the storage area of ​​the non-volatile memory device, respectively.

6. The memory system according to claim 5, wherein: The volatile memory device includes a dynamic random access memory (DRAM), and the nonvolatile memory device includes a NAND flash memory.

7. The memory system according to any one of claims 1 to 6, wherein: The memory controller is further configured to: In response to receiving a write request indicating a segment of the first set of data associated with a first logical address of the first set of logical addresses, assigning the segment of the first set of data to a first storage block of the storage blocks, the first storage block having a first ID of the IDs; as well as The fragment of the first set of data is obtained to cache the fragment of the first set of data in the first storage block.

8. The memory system according to claim 7, wherein: To maintain the L2P mapping table, the memory controller includes an L2P search engine configured to: in response to fetching the segment of the first set of data to the first storage block, update the L2P mapping table to map the first logical address to the first ID.

9. The memory system according to any one of claims 1 to 6, wherein: The memory controller is also configured to, in response to receiving a read request indicating a fragment of the first set of data associated with a second logical address in the first set of logical addresses, retrieve the fragment of the first set of data from a second storage block in the storage blocks in the cache based on the L2P mapping table.

10. The memory system according to claim 9, wherein: The memory controller includes an L2P search engine configured to: determining an address of the L2P mapping table in the volatile memory device based on the second logical address; as well as A second ID among the IDs at the address of the L2P mapping table in the volatile memory device is identified, the second memory block having the second ID.

11. A memory system comprising: a non-volatile memory device, the non-volatile memory device comprising memory areas, each of the memory areas being associated with a physical address; a volatile memory device, the volatile memory device comprising memory blocks, each of the memory blocks being associated with an identifier (ID), the volatile memory device being configured to store a logical-to-physical (L2P) mapping table, wherein the L2P mapping table maps a logical address of data to the ID of the memory block in the volatile memory device and the physical address of the storage area in the non-volatile memory device, respectively; as well as A memory controller is operably coupled to the volatile memory device and the non-volatile memory device and is configured to search for a segment of the data based on the L2P mapping table.

12. The memory system according to claim 11, wherein: To search for the segment of the data, the memory controller is configured to: determining an address of the L2P mapping table in the volatile storage device based on a logical address associated with the segment of the data; as well as A value at the address of the L2P mapping table is determined.

13. The memory system according to claim 12, wherein: To search for the segment of the data, the memory controller is further configured to: In response to the value being one of the IDs of the storage blocks in the volatile memory device, retrieving the segment of the data from the storage block having the ID in the volatile memory device; or In response to the value being one of the physical addresses of the storage region in the nonvolatile storage device, the segment of the data is retrieved from the storage region having the physical address in the nonvolatile storage device.

14. The memory system according to any one of claims 11 to 13, wherein: In order to search for the segments of the data, the memory controller includes a plurality of L2P search engines configured to respectively search for the plurality of segments of the data in parallel based on the L2P mapping table.

15. The memory system according to any one of claims 11 to 14, wherein: The memory controller is further configured to cache the segments of the data in the volatile memory device or flush the segments of the data from the volatile memory device to the non-volatile memory device.

16. A memory controller comprising: a volatile memory device interface operably coupled to a volatile memory device; as well as A logical-to-physical (L2P) search engine is configured to maintain an L2P mapping table stored in the volatile memory device through the volatile memory device interface, so that the L2P mapping table maps a first set of logical addresses to identifiers (IDs) of cached memory blocks, respectively.

17. The memory controller according to claim 16, wherein: The L2P search engine is further configured to search for a first set of data, the first set of data being associated with the first set of logical addresses and being cached in the storage block based on the L2P mapping table.

18. The memory controller according to claim 16 or 17, further comprising: a non-volatile memory device interface operatively coupled to the non-volatile memory device, The L2P search engine is further configured to: maintain the L2P mapping table stored in the volatile memory device, so that the L2P mapping table further maps the second group of logical addresses to physical addresses of the storage area of ​​the non-volatile memory device respectively.

19. The memory controller according to claim 18, wherein: The L2P search engine is further configured to search for a second set of data associated with the second set of logical addresses and stored in the storage area based on the L2P mapping table.

20. The memory controller according to claim 18 or 19, wherein: The volatile memory device includes a dynamic random access memory (DRAM), and the nonvolatile memory device includes a NAND flash memory.

21. The memory controller according to any one of claims 16 to 20, further comprising: a range partitioning accelerator configured to, in response to receiving a write request indicating a segment of the first set of data associated with a first logical address in the first set of logical addresses, assign the segment of the first set of data to a first storage block in the storage blocks, the first storage block having a first ID in the IDs, and A host interface is configured to obtain the fragments of the first set of data to cache the fragments of the first set of data in the first storage block.

22. The memory controller according to claim 21, wherein: To maintain the L2P mapping table, the L2P search engine is further configured to: in response to the host interface fetching the segment of the first set of data to the first storage block, update the L2P mapping table to map the first logical address to the first ID.

23. The memory controller according to any one of claims 16-20 further includes a host interface, which is configured to: in response to receiving a read request indicating a fragment of the first group of data associated with a second logical address in the first group of logical addresses, obtain the fragment of the first group of data from a second storage block in the storage block in the cache based on the L2P mapping table.

24. The memory controller according to claim 23, wherein: The L2P search engine is further configured to: determining an address of the L2P mapping table in the volatile memory device based on the second logical address; as well as A second ID among the IDs at the address of the L2P mapping table in the volatile memory device is identified, the second memory block having the second ID.

25. A method for operating a memory controller, comprising: generating a logical-to-physical (L2P) mapping table stored in a volatile memory device; as well as The L2P mapping table is maintained such that the L2P mapping table maps the first set of logical addresses to identifiers (IDs) of cached storage blocks, respectively.

26. The method according to claim 25, further comprising: A first set of data is cached in the storage block, wherein the first set of data is respectively associated with the first set of logical addresses.

27. The method according to claim 26, further comprising: The first set of data is searched in the storage block based on the L2P mapping table.

28. The method according to any one of claims 25 to 27, wherein: The volatile memory device includes the cache memory.

29. The method according to any one of claims 25 to 28, further comprising: storing a second set of data in a storage area of ​​the non-volatile memory device, wherein the second set of data is respectively associated with a second set of logical addresses, and The L2P mapping table stored in the volatile memory device is maintained so that the L2P mapping table further maps the second set of logical addresses to physical addresses of the storage area of ​​the non-volatile memory device, respectively.

30. The method of claim 29, wherein: The volatile memory device includes a dynamic random access memory (DRAM), and the nonvolatile memory device includes a NAND flash memory.

31. The method according to any one of claims 25 to 30, further comprising: In response to receiving a write request indicating a segment of the first set of data associated with a first logical address of the first set of logical addresses, assigning the segment of the first set of data to a first storage block of the storage blocks, the first storage block having a first ID of the IDs; as well as The fragment of the first set of data is obtained to cache the fragment of the first set of data in the first storage block.

32. The method according to claim 31, wherein: Maintaining the L2P mapping table includes: in response to fetching a segment of the first set of data to the first storage block, updating the L2P mapping table to map the first logical address to the first ID.

33. The method according to any one of claims 25 to 30, further comprising: In response to receiving a read request indicating a segment of the first set of data associated with a second logical address in the first set of logical addresses, the segment of the first set of data is retrieved from a second storage block in the storage blocks in the cache based on the L2P mapping table.

34. The method of claim 33, further comprising: determining an address of the L2P mapping table in the volatile memory device based on the second logical address; as well as A second ID among the IDs at the address of the L2P mapping table in the volatile memory device is identified, the second memory block having the second ID.

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