Driving circuit, driving method, driving module and display device

Abstract

The invention discloses a driving circuit, a driving method, a driving module and a display device. The driving circuit comprises a driving signal generating circuit (10), a gating circuit (11), an output control circuit (12) and an output circuit (13); the driving signal generating circuit (10) is used for shifting the (N-1) th-stage driving signal to obtain an Nth-stage driving signal; the gating circuit (11) controls a gating input signal to be written into the first node (N1) under the control of a gating control signal; the output control circuit (12) performs NAND operation on the Nth-stage driving signal and the potential of the second end of the output control circuit (12) to obtain a first output signal; the output circuit (13) is used for inverting the first output signal to obtain and provide an output driving signal through an output driving end (NO (N)); n is a positive integer. By controlling the gating input signal provided by the gating input end (VCT), the local picture of the display screen is updated, so that the power consumption is reduced.

Description

Driving circuit, driving method, driving module and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a driving circuit, a driving method, a driving module, and a display device. Background Art

[0002] In related technologies, when an OLED (organic light-emitting diode) display updates its screen, it is necessary to initialize and write pixel voltages to all rows of pixel circuits within one frame. However, in certain special screens (such as the AOD display screen (the AOD display screen is a screen that controls the partial lighting of the screen without lighting the entire mobile phone screen), static screens, or screens that are updated less frequently), the pixel voltages of most pixel circuits on the entire screen do not need to be updated. That is, most pixel circuits can be maintained at the original display brightness through low-leakage LTPO (low-temperature polycrystalline oxide) TFTs (thin-film transistors), and repeated refreshing of these pixel circuits results in a waste of power consumption.

[0003] Summary of the Invention

[0004] In one aspect, an embodiment of the present disclosure provides a driving circuit, comprising a driving signal generating circuit, a gating circuit, an output control circuit, and an output circuit;

[0005] The driving signal generating circuit is electrically connected to the N-1th level driving signal output terminal and the Nth level driving signal output terminal respectively, and is used to perform a shift operation on the N-1th level driving signal provided by the N-1th level driving signal output terminal to obtain and output the Nth level driving signal through the Nth level driving signal output terminal;

[0006] The gating circuit is electrically connected to the first node, the gating input terminal and the gating control terminal respectively, and is used to control the gating input signal provided by the gating input terminal to be written into the first node under the control of the gating control signal provided by the gating control terminal;

[0007] The first terminal of the output control circuit is electrically connected to the N-th stage drive signal output terminal, and the second terminal of the output control circuit is electrically connected to the first node, and is configured to perform a NAND operation on the N-th stage drive signal and the potential of the second terminal of the output control circuit to obtain a first output signal;

[0008] The output circuit is used to invert the first output signal to obtain an output drive signal and provide it through the output drive terminal;

[0009] N is a positive integer.

[0010] Optionally, the gating circuit is used to control the writing of the gating input signal provided by the gating input terminal into the first node when the potential of the N-1th level driving signal is the first voltage and the potential of the Nth level driving signal is the second voltage.

[0011] Optionally, the gating circuit includes a first transistor; the gate of the first transistor is electrically connected to the gating control terminal, the first electrode of the first transistor is electrically connected to the first node, and the second electrode of the first transistor is electrically connected to the gating input terminal.

[0012] Optionally, the gating control terminal includes a first gating control terminal and a second gating control terminal; the gating circuit includes a first transistor and a second transistor;

[0013] The gate of the first transistor is electrically connected to the first selection control terminal, the first electrode of the first transistor is electrically connected to the first node, and the second electrode of the first transistor is electrically connected to the first electrode of the second transistor;

[0014] The gate of the second transistor is electrically connected to the second gate control terminal, and the second electrode of the second transistor is electrically connected to the gate input terminal;

[0015] The first strobe control terminal is an N-1th level drive signal output terminal, the second strobe control terminal is an Nth level drive signal output terminal, the first transistor is an n-type transistor, and the second transistor is a p-type transistor; or

[0016] The first strobe control terminal is an N-th level drive signal output terminal, the second strobe control terminal is an N-1-th level drive signal output terminal, the first transistor is a p-type transistor, and the second transistor is an n-type transistor; or

[0017] The first strobe control terminal is connected to the inverted signal of the N-1th level drive signal, the second strobe control terminal is the output terminal of the Nth level drive signal, and the first transistor and the second transistor are both p-type transistors; or

[0018] The first gate control terminal is an output terminal of the Nth level driving signal, and the second gate control terminal is connected to the inverted signal of the N-1th level driving signal; the first transistor and the second transistor are both p-type transistors; or,

[0019] The first gate control terminal is the N-1th level driving signal terminal, the second gate control terminal is connected to the inverted signal of the Nth level driving signal, and the first transistor and the second transistor are both n-type transistors; or

[0020] The first strobe control terminal is connected to the inverted signal of the Nth level driving signal, the second strobe control terminal is the N-1th level driving signal terminal, and the first transistor and the second transistor are both n-type transistors.

[0021] Optionally, the driving circuit according to at least one embodiment of the present disclosure further includes a first initialization circuit;

[0022] The first initialization circuit is electrically connected to the initial control terminal, the first voltage terminal and the first node respectively, and is used to control the connection between the first node and the first voltage terminal under the control of the initial control signal provided by the initial control terminal.

[0023] Optionally, the driving circuit according to at least one embodiment of the present disclosure further includes a first voltage maintaining circuit;

[0024] A first end of the first voltage maintaining circuit is electrically connected to the first node, a second end of the first voltage maintaining circuit is electrically connected to a DC voltage end or a second node, and the first voltage maintaining circuit is used to maintain the potential of the first node.

[0025] Optionally, the driving circuit according to at least one embodiment of the present disclosure further includes a second voltage maintaining circuit, and the first node is electrically connected to the second end of the output control circuit through the second voltage maintaining circuit;

[0026] The second voltage maintaining circuit includes a first inverter, a second inverter and a maintaining control circuit;

[0027] The input terminal of the first inverter is electrically connected to the first node, the output terminal of the first inverter is electrically connected to the second node, the input terminal of the second inverter is electrically connected to the second node, and the output terminal of the second inverter is electrically connected to a third node and the second terminal of the output control circuit;

[0028] The first inverter is used to invert the potential of the first node and output the inverted potential of the first node through the output terminal of the first inverter, and the second inverter is used to invert the potential of the input terminal and output the inverted potential through the output terminal of the second inverter;

[0029] The sustain control circuit is electrically connected to the sustain control terminal, the third node and the first node respectively, and is used to control the connection or disconnection between the third node and the first node under the control of the sustain control signal provided by the sustain control terminal.

[0030] Optionally, the maintenance control terminal includes a first maintenance control terminal and a second maintenance control terminal;

[0031] The sustain control circuit includes a third transistor and a fourth transistor;

[0032] The gate of the third transistor is electrically connected to the first sustain control terminal, the first electrode of the third transistor is electrically connected to the first node, and the second electrode of the third transistor is electrically connected to the third node;

[0033] The gate of the fourth transistor is electrically connected to the second sustain control terminal, the first electrode of the fourth transistor is electrically connected to the third node, and the second electrode of the fourth transistor is electrically connected to the first node;

[0034] The third transistor is a p-type transistor, and the fourth transistor is an n-type transistor;

[0035] The first sustain control terminal is the N-1th level driving signal terminal, and the second sustain control terminal is the first clock signal terminal; or

[0036] The first sustain control terminal is a second clock signal terminal, and the second sustain control terminal is a first clock signal terminal.

[0037] Optionally, the first inverter includes a fifth transistor and a sixth transistor, and the second inverter includes a seventh transistor and an eighth transistor;

[0038] The gate of the fifth transistor is electrically connected to the first node, the first electrode of the fifth transistor is electrically connected to the first voltage terminal, and the second electrode of the fifth transistor is electrically connected to the second node;

[0039] The gate of the sixth transistor is electrically connected to the first node, the first electrode of the sixth transistor is electrically connected to the second node, and the second electrode of the sixth transistor is electrically connected to the second voltage terminal;

[0040] The fifth transistor is a p-type transistor, and the sixth transistor is an n-type transistor;

[0041] The gate of the seventh transistor is electrically connected to the second node, the first electrode of the seventh transistor is electrically connected to the first voltage terminal, and the second electrode of the seventh transistor is electrically connected to the third node;

[0042] The gate of the eighth transistor is electrically connected to the second node, the first electrode of the eighth transistor is electrically connected to the third node, and the second electrode of the eighth transistor is electrically connected to the second voltage terminal;

[0043] The seventh transistor is a p-type transistor, and the eighth transistor is an n-type transistor.

[0044] Optionally, the first initialization circuit includes a ninth transistor, and the first voltage maintaining circuit includes a first capacitor;

[0045] The gate of the ninth transistor is electrically connected to the initial control terminal, the first electrode of the ninth transistor is electrically connected to the first voltage terminal, and the second electrode of the ninth transistor is electrically connected to the first node;

[0046] A first end of the first capacitor is electrically connected to the first node, and a second end of the first capacitor is electrically connected to the DC voltage end or the second node.

[0047] Optionally, the output control circuit includes a tenth transistor, an eleventh transistor, a twelfth transistor and a thirteenth transistor;

[0048] The gate of the tenth transistor is electrically connected to the Nth stage driving signal output terminal, the first electrode of the tenth transistor is electrically connected to the first voltage terminal, and the second electrode of the tenth transistor is electrically connected to the fourth node;

[0049] The gate of the eleventh transistor is electrically connected to the first node, the first electrode of the eleventh transistor is electrically connected to the first voltage terminal, and the second electrode of the eleventh transistor is electrically connected to the fourth node;

[0050] The gate of the twelfth transistor is electrically connected to the N-th stage driving signal output terminal, the first electrode of the twelfth transistor is electrically connected to the fourth node, and the second electrode of the twelfth transistor is electrically connected to the fifth node;

[0051] The gate of the thirteenth transistor is electrically connected to the first node, the first electrode of the thirteenth transistor is electrically connected to the fifth node, and the second electrode of the thirteenth transistor is electrically connected to the second voltage terminal;

[0052] The tenth transistor and the eleventh transistor are p-type transistors, and the twelfth transistor and the thirteenth transistor are n-type transistors.

[0053] Optionally, the output control circuit includes a tenth transistor, an eleventh transistor, a twelfth transistor and a thirteenth transistor;

[0054] The gate of the tenth transistor is electrically connected to the Nth stage driving signal output terminal, the first electrode of the tenth transistor is electrically connected to the first voltage terminal, and the second electrode of the tenth transistor is electrically connected to the fourth node;

[0055] The gate of the eleventh transistor is electrically connected to the third node, the first electrode of the eleventh transistor is electrically connected to the first voltage terminal, and the second electrode of the eleventh transistor is electrically connected to the fourth node;

[0056] The gate of the twelfth transistor is electrically connected to the N-th stage driving signal output terminal, the first electrode of the twelfth transistor is electrically connected to the fourth node, and the second electrode of the twelfth transistor is electrically connected to the fifth node;

[0057] The gate of the thirteenth transistor is electrically connected to the third node, the first electrode of the thirteenth transistor is electrically connected to the fifth node, and the second electrode of the thirteenth transistor is electrically connected to the second voltage terminal;

[0058] The tenth transistor and the eleventh transistor are p-type transistors, and the twelfth transistor and the thirteenth transistor are n-type transistors.

[0059] Optionally, the output circuit includes a fourteenth transistor and a fifteenth transistor;

[0060] The gate of the fourteenth transistor is electrically connected to the fourth node, the first electrode of the fourteenth transistor is electrically connected to the first voltage terminal, and the second electrode of the fourteenth transistor is electrically connected to the output driving terminal;

[0061] The gate of the fifteenth transistor is electrically connected to the fourth node, the first electrode of the fifteenth transistor is electrically connected to the output driving end, and the second electrode of the fifteenth transistor is electrically connected to the second voltage end.

[0062] Optionally, the driving signal generating circuit includes a first control circuit, a second control circuit, a third inverter and a second initialization circuit;

[0063] The first control circuit is electrically connected to the first clock signal terminal, the second clock signal terminal, the N-1th stage drive signal output terminal, and the sixth node, respectively, and is configured to shift and invert the N-1th drive signal provided by the N-1th stage drive signal output terminal under the control of the first clock signal provided by the first clock signal terminal and the second clock signal provided by the second clock signal terminal, to obtain and output the inverted signal through the sixth node;

[0064] The second control circuit is electrically connected to the first clock signal terminal, the second clock signal terminal, the N-stage drive signal output terminal, and the sixth node, respectively, and is configured to invert the N-stage drive signal provided by the N-stage drive signal output terminal under the control of the first clock signal and the second clock signal, and obtain and output the inverted signal through the sixth node;

[0065] The third inverter is electrically connected to the sixth node and the N-th stage driving signal output terminal respectively, and is used to invert the potential of the sixth node and output the inverted signal through the N-th stage driving signal output terminal;

[0066] The second initialization circuit is electrically connected to the initial control terminal, the first voltage terminal and the Nth level drive signal output terminal respectively, and is used to control the connection between the Nth level drive signal output terminal and the first voltage terminal under the control of the initial control signal provided by the initial control terminal.

[0067] Optionally, the first control circuit includes a sixteenth transistor, a seventeenth transistor, an eighteenth transistor and a nineteenth transistor;

[0068] The gate of the sixteenth transistor is electrically connected to the second clock signal terminal, the first electrode of the sixteenth transistor is electrically connected to the first voltage terminal, and the second electrode of the sixteenth transistor is electrically connected to the first electrode of the seventeenth transistor;

[0069] The gate of the seventeenth transistor is electrically connected to the N-1th stage driving signal output terminal, and the second electrode of the seventeenth transistor is electrically connected to the sixth node;

[0070] The gate of the eighteenth transistor is electrically connected to the (N-1)th stage driving signal output terminal, the first electrode of the eighteenth transistor is electrically connected to the sixth node, and the second electrode of the eighteenth transistor is electrically connected to the first electrode of the nineteenth transistor;

[0071] The gate of the nineteenth transistor is electrically connected to the first clock signal terminal, and the second electrode of the nineteenth transistor is electrically connected to the second voltage terminal;

[0072] The sixteenth transistor and the seventeenth transistor are p-type transistors, and the eighteenth transistor and the nineteenth transistor are n-type transistors.

[0073] Optionally, the second control circuit includes a twentieth transistor, a twenty-first transistor, a twenty-second transistor, and a twenty-third transistor;

[0074] a gate of the twentieth transistor electrically connected to the first clock signal terminal, a first electrode of the twentieth transistor electrically connected to the first voltage terminal, and a second electrode of the twentieth transistor electrically connected to the first electrode of the twenty-first transistor;

[0075] A gate of the twenty-first transistor is electrically connected to the Nth stage driving signal output terminal, and a second electrode of the twenty-first transistor is electrically connected to the sixth node;

[0076] a gate of the twenty-second transistor being electrically connected to the N-stage driving signal output terminal, a first electrode of the twenty-second transistor being electrically connected to the sixth node, and a second electrode of the twenty-second transistor being electrically connected to a first electrode of the twenty-third transistor;

[0077] A gate of the twenty-third transistor is electrically connected to the second clock signal terminal, and a second electrode of the twenty-third transistor is electrically connected to the second voltage terminal;

[0078] The twentieth transistor and the twenty-first transistor are p-type transistors, and the twenty-second transistor and the twenty-third transistor are n-type transistors.

[0079] Optionally, the third inverter includes a twenty-fourth transistor and a twenty-fifth transistor; the second initialization circuit includes a twenty-sixth transistor;

[0080] a gate of the twenty-fourth transistor is electrically connected to the sixth node, a first electrode of the twenty-fourth transistor is electrically connected to the first voltage terminal, and a second electrode of the twenty-fourth transistor is electrically connected to the first electrode of the twenty-fifth transistor;

[0081] A gate of the twenty-fifth transistor is electrically connected to the sixth node, and a second electrode of the twenty-fifth transistor is electrically connected to the second voltage terminal;

[0082] The twenty-fourth transistor is a p-type transistor, and the twenty-fifth transistor is an n-type transistor;

[0083] A gate of the twenty-sixth transistor is electrically connected to the initial control terminal, a first electrode of the twenty-sixth transistor is electrically connected to the first voltage terminal, and a second electrode of the twenty-sixth transistor is electrically connected to the Nth stage driving signal output terminal.

[0084] In a second aspect, an embodiment of the present disclosure provides a driving method, which is applied to the above-mentioned driving circuit. The driving method includes:

[0085] The driving signal generating circuit performs a shift operation on the N-1th level driving signal to obtain and output the Nth level driving signal through the Nth level driving signal output terminal;

[0086] The gating circuit controls, under the control of the gating control signal, to write the gating input signal provided by the gating input terminal into the first node;

[0087] The output control circuit performs a NAND operation on the N-th stage driving signal and the potential of the second terminal of the output control circuit to obtain a first output signal;

[0088] The output circuit is used to invert the first output signal to obtain and provide an output driving signal through the output driving terminal.

[0089] In a third aspect, an embodiment of the present disclosure provides a driving module comprising multiple stages of the above-mentioned driving circuits;

[0090] The Nth stage driving circuit is electrically connected to the driving signal output terminal included in the N-1th stage driving circuit; N is a positive integer.

[0091] In a third aspect, an embodiment of the present disclosure provides a display device comprising the aforementioned driving module. BRIEF DESCRIPTION OF THE DRAWINGS

[0092] FIG1 is a structural diagram of a driving circuit according to an embodiment of the present disclosure;

[0093] FIG2 is a circuit diagram of a related pixel circuit;

[0094] FIG3 is an operation timing diagram of the related pixel circuit shown in FIG2 ;

[0095] FIG4 is a circuit diagram of a related pixel circuit;

[0096] 5 is a circuit diagram of at least one embodiment of a gating circuit in a driving circuit according to an embodiment of the present disclosure;

[0097] 6 is a circuit diagram of at least one embodiment of a gating circuit in a driving circuit according to an embodiment of the present disclosure;

[0098] 7 is a circuit diagram of at least one embodiment of a gating circuit in a driving circuit according to an embodiment of the present disclosure;

[0099] FIG8 is a circuit diagram of at least one embodiment of a gating circuit in a driving circuit according to an embodiment of the present disclosure;

[0100] 9 is a circuit diagram of at least one embodiment of a gating circuit in a driving circuit according to an embodiment of the present disclosure;

[0101] FIG10 is a circuit diagram of at least one embodiment of a gating circuit in a driving circuit according to an embodiment of the present disclosure;

[0102] FIG11 is a circuit diagram of at least one embodiment of a gating circuit in a driving circuit according to an embodiment of the present disclosure;

[0103] FIG12 is a circuit diagram of at least one embodiment of a gating circuit in a driving circuit according to an embodiment of the present disclosure;

[0104] FIG13 is a circuit diagram of at least one embodiment of an inverter;

[0105] FIG14 is a circuit diagram of at least one embodiment of an inverter;

[0106] FIG15 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0107] FIG16 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0108] FIG17 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0109] FIG18 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0110] FIG19 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0111] FIG20 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0112] FIG21 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0113] FIG22 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0114] FIG23 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0115] FIG24 is an operation timing diagram of at least one embodiment of the driving circuit shown in FIG23;

[0116] FIG25 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0117] FIG26 is a structural diagram of a driving module according to at least one embodiment of the present disclosure;

[0118] FIG. 27 is an operation timing diagram of at least one embodiment of the driving module shown in FIG. 26 . DETAILED DESCRIPTION

[0119] The following will be combined with the accompanying drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the embodiments described are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of the present disclosure.

[0120] The transistors used in all embodiments of the present disclosure may be thin film transistors, field effect transistors, or other devices with the same characteristics. In the embodiments of the present disclosure, to distinguish the two electrodes of the transistor except the gate, one electrode is referred to as the first electrode and the other electrode is referred to as the second electrode.

[0121] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the first electrode may be a drain electrode, and the second electrode may be a source electrode; or, the first electrode may be a source electrode, and the second electrode may be a drain electrode.

[0122] As shown in FIG1 , the driving circuit according to the embodiment of the present disclosure includes a driving signal generating circuit 10 , a gating circuit 11 , an output control circuit 12 , and an output circuit 13 ;

[0123] The driving signal generating circuit 10 is electrically connected to the N-1-th level driving signal output terminal NS(N-1) and the N-th level driving signal output terminal NS(N), respectively, and is used to perform a shift operation on the N-1-th level driving signal provided by the N-1-th level driving signal output terminal NS(N-1), to obtain and output the N-th level driving signal through the N-th level driving signal output terminal NS(N);

[0124] The gating circuit 11 is electrically connected to the first node N1, the gating input terminal VCT and the gating control terminal CX, respectively, and is used to control the gating input signal provided by the gating input terminal VCT to be written into the first node N1 under the control of the gating control signal provided by the gating control terminal CX;

[0125] The first terminal of the output control circuit 12 is electrically connected to the N-th stage drive signal output terminal NS(N), and the second terminal of the output control circuit 12 is electrically connected to the first node N1, and is used to perform a NAND operation on the N-th stage drive signal and the potential of the second terminal of the output control circuit to obtain a first output signal;

[0126] The output circuit 13 is electrically connected to the output control circuit 12 and the output drive terminal NO(N) respectively, and is used to invert the first output signal to obtain and provide an output drive signal through the output drive terminal NO(N);

[0127] N is a positive integer.

[0128] When the embodiment of the driving circuit shown in Figure 1 of the present disclosure is in operation, the driving signal generating circuit 10 performs a shift operation on the N-1th level driving signal provided by the N-1th level driving signal output terminal NS(N-1), obtains and outputs the Nth level driving signal through the Nth level driving signal output terminal NS(N), and the gating circuit 11 writes the gating input signal into the first node N1 under the control of the gating control signal; the output control circuit 12 performs a NAND operation on the Nth level driving signal and the potential of the second terminal of the output control circuit 12 to obtain a first output signal, and the output circuit 13 inverts the first output signal to obtain and provide the output driving signal through the output driving terminal NO(N).

[0129] The embodiment of the driving circuit shown in FIG. 1 of the present disclosure may be an N-th stage driving circuit.

[0130] When the embodiment of the driving circuit shown in FIG1 of the present disclosure is working, within one frame time,

[0131] Before the Nth stage driving signal providing phase, the gating circuit 11 writes the gating input signal provided by the gating input terminal VCT into the first node N1 under the control of the gating control signal;

[0132] When the selection input signal is a high voltage signal, in the N-level driving signal providing stage, the N-level driving signal output terminal NS(N) outputs a high voltage signal, then the first output signal output by the output control circuit 12 is a low voltage signal, and the output circuit 13 provides a high voltage signal through the output driving terminal NO(N), which can control the corresponding row pixel circuit to update the pixel voltage;

[0133] When the selection input signal is a low voltage signal, in the N-th level drive signal providing stage, the N-th level drive signal output terminal NS(N) outputs a high voltage signal, then the first output signal output by the output control circuit 12 is a high voltage signal, and the output circuit 13 provides a low voltage signal through the output drive terminal NO(N), which can control the corresponding row pixel circuit not to update the pixel voltage.

[0134] The embodiment of the present disclosure can realize the update of a partial picture of the display screen by controlling the selection input signal provided by the selection input terminal VCT, thereby reducing power consumption, or realize ultra-low power consumption of OLED display products such as wearable products, mobile terminals, and NB (notebook computers) by partially updating the display picture.

[0135] As shown in FIG2 , the relevant pixel circuit may include a first display control transistor M1, a second display control transistor M2, a driving transistor M3, a fourth display control transistor M4, a fifth display control transistor M5, a sixth display control transistor M6, a seventh display control transistor M7, a storage capacitor Cst, and an organic light emitting diode O1;

[0136] The gate of M1 is electrically connected to the first reset terminal NR(N), the source of M1 is electrically connected to the initial voltage terminal I1, and the drain of M1 is electrically connected to the gate of M3;

[0137] The gate of M2 is electrically connected to the first scanning terminal NG(N), the source of M2 is electrically connected to the gate of M3, and the drain of M2 is electrically connected to the drain of M3;

[0138] The gate of M4 is electrically connected to the second scanning terminal PG(N), the source of M4 is electrically connected to the data line D1, and the drain of M4 is electrically connected to the source of M3;

[0139] The gate of M5 is electrically connected to the light emitting control terminal E(N), the source of M5 is electrically connected to the power supply voltage terminal ELVDD, and the drain of M5 is electrically connected to the source of M3;

[0140] The gate of M6 is electrically connected to the light emitting control terminal E(N), the source of M6 is electrically connected to the drain of M3, the drain of M6 is electrically connected to the anode of O1; the cathode of O1 is electrically connected to the low level terminal ELVSS;

[0141] The gate of M7 is electrically connected to the second scanning terminal PG(N), the source of M7 is electrically connected to the initial voltage terminal I1, and the drain of M7 is electrically connected to the anode of O1.

[0142] In a specific implementation, the first reset terminal NR(N) may be the first scanning terminal NG(N) of the N-1th stage, but is not limited thereto.

[0143] In the relevant pixel circuit shown in FIG2 , M1 and M2 are n-type transistors, M3, M4, M5, M6 and M7 are p-type transistors, M1 and M2 are IGZO TFTs with small leakage current, and M3, M4, M5, M6 and M7 are LTPS TFTs.

[0144] In the relevant pixel circuit shown in FIG2 , M1 and M2 are IGZO TFTs. When using low-frequency display, the IGZO TFTs can ensure that Cst can maintain the voltage of the gate of M3 for a longer period of time.

[0145] In the relevant pixel circuit shown in Figure 2, the second scanning terminal PG (N) is responsible for resetting the voltage of the anode of O1 and writing the data voltage on the data line into the source of the driving transistor, and the first scanning terminal NG (N) is responsible for resetting Cst, extracting Vth (Vth is the threshold voltage of the driving transistor) and writing the data voltage into the gate of the driving transistor.

[0146] In a specific implementation, the first scanning signal provided by the first scanning terminal NG(N) and the second scanning signal provided by the second scanning terminal PG(N) may be in opposite phases to each other, but the present invention is not limited thereto.

[0147] The driving circuit described in at least one embodiment of the present disclosure may provide the first scanning signal to the first scanning terminal NG(N) via the output driving terminal NO(N), but the present invention is not limited thereto.

[0148] As shown in FIG3 , when the relevant pixel circuit shown in FIG2 is in operation, a display cycle may include a first display control phase t1 , a second display control phase t2 , and a third display control phase t3 , which are set in sequence;

[0149] In the first display control stage t1, E(N) outputs a high voltage signal, NR(N) provides a high voltage signal, PG(N) provides a high voltage signal, NG(N) provides a low voltage signal, M5 and M6 are turned off, M1 is turned on, and the potential of the gate of M3 is pulled down to the initial voltage Vinit; the initial voltage terminal I1 is used to provide the initial voltage Vinit;

[0150] In the second display control phase t2, E(N) outputs a high voltage signal, NR(N) provides a low voltage signal, PG(N) provides a low voltage signal, NG(N) provides a high voltage signal, M5 and M6 are turned off, M1 is turned off, M2 is turned on, M4 is turned on, M2 and M3 form a diode structure, and the data voltage Vdata provided by the data line D1 charges Cst until M3 is turned off. At this time, the gate voltage of M3 is Vdata+Vth, where Vth is the threshold voltage of M3; M7 is turned on to reset the anode voltage of O1;

[0151] In the third display control phase t3, E(N) outputs a low voltage signal, NR(N) provides a low voltage signal, PG(N) provides a high voltage signal, NG(N) provides a low voltage signal, M5 and M6 are turned on, M3 drives O1 to emit light; O1 emits light according to the voltage setting of Vdata.

[0152] From the above working process of the relevant pixel circuit, it can be known that NG(N) can control whether the data voltage Vdata (the data voltage Vdata can be the pixel voltage) is written into the gate of M3 in the second display control stage.

[0153] FIG4 is a circuit diagram of a related pixel circuit.

[0154] As shown in FIG4 , the relevant pixel circuit may include a first display control transistor M1, a second display control transistor M2, a driving transistor M3, a fourth display control transistor M4, a fifth display control transistor M5, a sixth display control transistor M6, a seventh display control transistor M7, a storage capacitor Cst, and an organic light emitting diode O1;

[0155] The gate of M1 is electrically connected to the third reset terminal RST1, the source of M1 is electrically connected to the initial voltage terminal I1, and the drain of M1 is electrically connected to the drain of M3;

[0156] The gate of M2 is electrically connected to the first scanning terminal NG(N), the source of M2 is electrically connected to the gate of M3, and the drain of M2 is electrically connected to the drain of M3;

[0157] The gate of M4 is electrically connected to the second scanning terminal PG(N), the source of M4 is electrically connected to the data line D1, and the drain of M4 is electrically connected to the source of M3;

[0158] The gate of M5 is electrically connected to the light emitting control terminal E(N), the source of M5 is electrically connected to the power supply voltage terminal ELVDD, and the drain of M5 is electrically connected to the source of M3;

[0159] The gate of M6 is electrically connected to the light emitting control terminal E(N), the source of M6 is electrically connected to the drain of M3, the drain of M6 is electrically connected to the anode of O1; the cathode of O1 is electrically connected to the low level terminal ELVSS;

[0160] The gate of M7 is electrically connected to the fourth reset terminal RST2 , the source of M7 is electrically connected to the initial voltage terminal I1 , and the drain of M7 is electrically connected to the anode of O1 .

[0161] When the relevant pixel circuit shown in FIG. 4 is in operation, NG(N) can control whether the data voltage Vdata on the data line D1 is written into the gate of the driving transistor M3 .

[0162] In a specific implementation, the first scanning signal provided by NG(N) can be used to control the opening or closing of the second transistor to control whether the data voltage on the data line is written to the gate of the driving transistor, thereby controlling whether the brightness of the pixel circuit of this row is updated; when NG(N) outputs a high voltage signal, the second transistor is turned on, and the brightness of the pixel circuit of this row can be updated; when NG(N) outputs a low voltage signal, the second transistor is always turned off, and the change of the data voltage on the data line will not be written to the gate of the driving transistor, and the luminous brightness of the organic light emitting diode will not change, that is, the display brightness of the pixel circuit of the current row in the current frame remains unchanged. In summary, it can be seen that the pixel brightness can be refreshed by controlling the opening or closing of the N-type transistor. Therefore, when you want to prevent some pixels from being refreshed, just ensure that the N-type transistor is turned off.

[0163] In at least one embodiment of the present disclosure, the gating circuit is used to control the writing of the gating input signal provided by the gating input terminal into the first node when the potential of the N-1th level driving signal is the first voltage and the potential of the Nth level driving signal is the second voltage.

[0164] In a specific implementation, the gating circuit may write the gating input signal into the first node when the potential of the N-1th level driving signal is the first voltage and the potential of the Nth level driving signal is the second voltage.

[0165] Optionally, the first voltage may be a high voltage, and the second voltage may be a low voltage, but the present invention is not limited thereto. In at least one embodiment of the present disclosure, the first voltage may also be a low voltage, and the second voltage may be a high voltage.

[0166] Optionally, the gating circuit includes a first transistor; the gate of the first transistor is electrically connected to the gating control terminal, the first electrode of the first transistor is electrically connected to the first node, and the second electrode of the first transistor is electrically connected to the gating input terminal.

[0167] As shown in FIG5 , the gating circuit may include a first transistor T1;

[0168] The gate of the first transistor T1 is electrically connected to the strobe control terminal S0, the drain of the first transistor T1 is electrically connected to the first node N1, and the source of the first transistor T1 is electrically connected to the strobe input terminal VCT;

[0169] T1 is a p-type transistor.

[0170] As shown in FIG6 , the gating circuit may include a first transistor T1;

[0171] The gate of the first transistor T1 is electrically connected to the strobe control terminal S0, the source of the first transistor T1 is electrically connected to the first node N1, and the drain of the first transistor T1 is electrically connected to the strobe input terminal VCT;

[0172] T1 is an n-type transistor.

[0173] In at least one embodiment of the present disclosure, the gating control terminal includes a first gating control terminal and a second gating control terminal; the gating circuit includes a first transistor and a second transistor;

[0174] The gate of the first transistor is electrically connected to the first selection control terminal, the first electrode of the first transistor is electrically connected to the first node, and the second electrode of the first transistor is electrically connected to the first electrode of the second transistor;

[0175] The gate of the second transistor is electrically connected to the second gate control terminal, and the second electrode of the second transistor is electrically connected to the gate input terminal;

[0176] The first strobe control terminal is an N-1th level drive signal output terminal, the second strobe control terminal is an Nth level drive signal output terminal, the first transistor is an n-type transistor, and the second transistor is a p-type transistor; or

[0177] The first strobe control terminal is an N-th level drive signal output terminal, the second strobe control terminal is an N-1-th level drive signal output terminal, the first transistor is a p-type transistor, and the second transistor is an n-type transistor; or

[0178] The first strobe control terminal is connected to the inverted signal of the N-1th level drive signal, the second strobe control terminal is the output terminal of the Nth level drive signal, and the first transistor and the second transistor are both p-type transistors; or

[0179] The first gate control terminal is an output terminal of the Nth level driving signal, and the second gate control terminal is connected to the inverted signal of the N-1th level driving signal; the first transistor and the second transistor are both p-type transistors; or,

[0180] The first gate control terminal is the N-1th level driving signal terminal, the second gate control terminal is connected to the inverted signal of the Nth level driving signal, and the first transistor and the second transistor are both n-type transistors; or

[0181] The first strobe control terminal is connected to the inverted signal of the Nth level driving signal, the second strobe control terminal is the N-1th level driving signal terminal, and the first transistor and the second transistor are both n-type transistors.

[0182] As shown in FIG7 , the gating circuit may include a first transistor T1 and a second transistor T2 ;

[0183] The gate of the first transistor T1 is electrically connected to the N-1th stage driving signal output terminal NS(N-1), the source of the first transistor T1 is electrically connected to the first node N1, and the drain of the first transistor T1 is electrically connected to the drain of the second transistor T2;

[0184] The gate of the second transistor T2 is electrically connected to the N-th stage driving signal output terminal NS(N), and the source of the second transistor T2 is electrically connected to the selection input terminal VCT;

[0185] T1 is an n-type transistor, and T2 is a p-type transistor.

[0186] As shown in FIG8 , the gating circuit may include a first transistor T1 and a second transistor T2 ;

[0187] The gate of the first transistor T1 is electrically connected to the N-th stage driving signal output terminal NS(N), the drain of the first transistor T1 is electrically connected to the first node N1, and the source of the first transistor T1 is electrically connected to the source of the second transistor T2;

[0188] The gate of the second transistor T2 is electrically connected to the N-1th stage driving signal output terminal NS(N-1), and the drain of the second transistor T2 is electrically connected to the selection input terminal VCT;

[0189] T1 is a p-type transistor, and T2 is an n-type transistor.

[0190] As shown in FIG9 , the gating circuit may include a first transistor T1 and a second transistor T2 ;

[0191] The gate of the first transistor T1 is electrically connected to the first inverted driving signal terminal NGI1, the drain of the first transistor T1 is electrically connected to the first node N1, and the source of the first transistor T1 is electrically connected to the drain of the second transistor T2; the first inverted driving signal provided by the first inverted driving signal terminal NGI1 is inverted to the N-1th level driving signal provided by the N-1th level driving signal output terminal NS(N-1);

[0192] The gate of the second transistor T2 is electrically connected to the N-th stage driving signal output terminal NS(N), and the source of the second transistor T2 is electrically connected to the selection input terminal VCT;

[0193] T1 is a p-type transistor, and T2 is a p-type transistor.

[0194] As shown in FIG10 , the gating circuit may include a first transistor T1 and a second transistor T2 ;

[0195] The gate of the first transistor T1 is electrically connected to the N-th stage driving signal output terminal NS(N), the drain of the first transistor T1 is electrically connected to the first node N1, and the source of the first transistor T1 is electrically connected to the drain of the second transistor T2;

[0196] The gate of the second transistor T2 is electrically connected to the first inverted driving signal terminal NGI1, and the source of the second transistor T2 is electrically connected to the selection input terminal VCT; the first inverted driving signal provided by the first inverted driving signal terminal NGI1 is inversely proportional to the N-1-th level driving signal provided by the N-1-th level driving signal output terminal NS(N-1);

[0197] T1 is a p-type transistor, and T2 is a p-type transistor.

[0198] As shown in FIG11 , the gating circuit may include a first transistor T1 and a second transistor T2 ;

[0199] The gate of the first transistor T1 is electrically connected to the N-1th stage driving signal output terminal NS(N-1), the source of the first transistor T1 is electrically connected to the first node N1, and the drain of the first transistor T1 is electrically connected to the source of the second transistor T2;

[0200] The gate of the second transistor T2 is electrically connected to the second inverted driving signal terminal NGI2, and the drain of the second transistor T2 is electrically connected to the selection input terminal VCT; the second inverted driving signal provided by the second inverted driving signal terminal NGI2 is inverted with the N-th stage driving signal provided by the N-th stage driving signal output terminal NS(N);

[0201] T1 is an n-type transistor, and T2 is an n-type transistor.

[0202] As shown in FIG12 , the gating circuit may include a first transistor T1 and a second transistor T2 ;

[0203] The gate of the first transistor T1 is electrically connected to the second inverted driving signal terminal NGI2, the source of the first transistor T1 is electrically connected to the first node N1, and the drain of the first transistor T1 is electrically connected to the source of the second transistor T2; the second inverted driving signal provided by the second inverted driving signal terminal NGI2 is inverted with the N-stage driving signal provided by the N-stage driving signal output terminal NS(N);

[0204] The gate of the second transistor T2 is electrically connected to the N-1th stage driving signal output terminal NS(N-1), and the drain of the second transistor T2 is electrically connected to the selection input terminal VCT;

[0205] T1 is an n-type transistor, and T2 is an n-type transistor.

[0206] As shown in FIG13 , the N-1th level driving signal provided by the N-1th level driving signal output terminal NS(N-1) can be inverted by the first inverting circuit to obtain the first inverted driving signal provided by the first inverted driving signal terminal NGI1;

[0207] The first inverting circuit includes a first inverting control transistor T01 and a second inverting control transistor T02;

[0208] T01 is a p-type transistor, and T02 is an n-type transistor.

[0209] As shown in FIG14 , the N-th level driving signal provided by the N-th level driving signal output terminal NS(N) can be inverted by the second inverting circuit to obtain a second inverted driving signal provided by the second inverted driving signal terminal NGI2;

[0210] The second inverting circuit includes a third inverting control transistor T03 and a fourth inverting control transistor T04;

[0211] T03 is a p-type transistor, and T04 is an n-type transistor.

[0212] The driving circuit according to at least one embodiment of the present disclosure further includes a first initialization circuit;

[0213] The first initialization circuit is electrically connected to the initial control terminal, the first voltage terminal and the first node respectively, and is used to control the connection between the first node and the first voltage terminal under the control of the initial control signal provided by the initial control terminal.

[0214] In a specific implementation, the driving circuit may further include a first initialization circuit. The first initialization circuit controls the connection between the first node and the first voltage terminal under the control of an initial control signal.

[0215] Optionally, the first voltage terminal may be a high voltage terminal.

[0216] The driving circuit according to at least one embodiment of the present disclosure further includes a first voltage maintaining circuit;

[0217] A first end of the first voltage maintaining circuit is electrically connected to the first node, a second end of the first voltage maintaining circuit is electrically connected to a DC voltage terminal second node, and the first voltage maintaining circuit is used to maintain the potential of the first node.

[0218] In a specific implementation, the driving circuit may further include a first voltage maintaining circuit, and the first voltage maintaining circuit maintains the potential of the first node.

[0219] As shown in FIG15 , based on at least one embodiment of the driving circuit shown in FIG1 , the driving circuit according to at least one embodiment of the present disclosure may further include a first initialization circuit 21 ;

[0220] The first initialization circuit 21 is electrically connected to the initial control terminal NCX, the first voltage terminal V1 and the first node N1 respectively, and is used to control the connection between the first node N1 and the first voltage terminal V1 under the control of the initial control signal provided by the initial control terminal NCX.

[0221] When at least one embodiment of the driving circuit shown in FIG. 15 is in operation, at the beginning of a frame time, NCX provides a valid voltage signal, and the first initialization circuit 21 controls the connection between the first node N1 and the first voltage terminal V1.

[0222] As shown in FIG16 , based on at least one embodiment of the driving circuit shown in FIG15 , the driving circuit according to at least one embodiment of the present disclosure may further include a first voltage maintaining circuit 22 ;

[0223] A first end of the first voltage maintaining circuit 22 is electrically connected to the first node N1 , and a second end of the first voltage maintaining circuit 22 is electrically connected to the first voltage terminal V1 . The first voltage maintaining circuit 22 is configured to maintain the potential of the first node N1 .

[0224] In at least one embodiment of the present disclosure, the driving circuit further includes a second voltage maintaining circuit, and the first node is electrically connected to the second end of the output control circuit via the second voltage maintaining circuit;

[0225] The second voltage maintaining circuit includes a first inverter, a second inverter and a maintaining control circuit;

[0226] The input terminal of the first inverter is electrically connected to the first node, the output terminal of the first inverter is electrically connected to the second node, the input terminal of the second inverter is electrically connected to the second node, and the output terminal of the second inverter is electrically connected to a third node and the second terminal of the output control circuit;

[0227] The first inverter is used to invert the potential of the first node and output the inverted potential of the first node through the output terminal of the first inverter, and the second inverter is used to invert the potential of the input terminal and output the inverted potential through the output terminal of the second inverter;

[0228] The sustain control circuit is electrically connected to the sustain control terminal, the third node and the first node respectively, and is used to control the connection or disconnection between the third node and the first node under the control of the sustain control signal provided by the sustain control terminal.

[0229] In a specific implementation, the driving circuit may further include a second voltage maintaining circuit, the first node may be electrically connected to the second terminal of the output control circuit via the second voltage maintaining circuit, and the second voltage maintaining circuit may include a first inverter, a second inverter, and a maintenance control circuit; the first inverter inverts the potential of the first node, and the second inverter inverts the potential of its input terminal; the maintenance control circuit controls the connection or disconnection between the third node and the first node under the control of a maintenance control signal provided by the maintenance control terminal;

[0230] The sustain control circuit may control the third node to be disconnected from the first node when the gating circuit controls the gating input signal to be written into the first node.

[0231] When the driving circuit described in at least one embodiment of the present disclosure is in operation, by adding a second voltage maintaining circuit, the first inverter and the second inverter included in the second voltage maintaining circuit can control the connection between the third node and the high voltage end when the potential of the first node is a high voltage, so that the potential of the third node can be higher than the potential of the first node, and can control the connection between the third node and the low voltage end when the potential of the first node is a low voltage, so that the potential of the third node can be lower than the potential of the first node, so that the third node can better control the transistor included in the output control circuit, whose gate is electrically connected to the third node.

[0232] As shown in FIG17 , based on at least one embodiment of the driving circuit shown in FIG15 ,

[0233] The driving circuit may further include a second voltage maintaining circuit; the maintaining control terminal includes the N-1th stage driving signal output terminal NS(N-1) and the first clock signal terminal GCK;

[0234] The first node N1 is electrically connected to the second end of the output control circuit 12 through the second voltage maintaining circuit;

[0235] The second voltage maintaining circuit includes a first inverter F1, a second inverter F2 and a maintaining control circuit W1;

[0236] An input terminal of the first inverter F1 is electrically connected to the first node N1, and an output terminal of the first inverter F1 is electrically connected to the second node N2;

[0237] The input end of the second inverter F2 is electrically connected to the second node N2, and the output end of the second inverter F2 is electrically connected to the third node N3 and the second end of the output control circuit 12;

[0238] The first inverter F1 is used to invert the potential of the first node N1 and output the inverted potential of the first node through the output terminal of the first inverter F1;

[0239] The second inverter F2 is used to invert the potential of its input terminal and output the inverted potential through the output terminal of the second inverter F2;

[0240] The maintenance control circuit W1 is electrically connected to the N-1th level drive signal output terminal NS(N-1), the first clock signal terminal GCK, the third node N3 and the first node N1, respectively, and is used to control the connection or disconnection between the third node N3 and the first node N1 under the control of the N-1th level drive signal provided by the N-1th level drive signal output terminal NS(N-1), and to control the connection or disconnection between the third node N3 and the first node N1 under the control of the first clock signal provided by the first clock signal terminal GCK.

[0241] In at least one embodiment shown in FIG. 17 , the N−1th stage driving signal output terminal may be replaced by a second clock signal terminal, but the present invention is not limited thereto.

[0242] Optionally, the maintenance control terminal includes a first maintenance control terminal and a second maintenance control terminal;

[0243] The sustain control circuit includes a third transistor and a fourth transistor;

[0244] The gate of the third transistor is electrically connected to the first sustain control terminal, the first electrode of the third transistor is electrically connected to the first node, and the second electrode of the third transistor is electrically connected to the third node;

[0245] The gate of the fourth transistor is electrically connected to the second sustain control terminal, the first electrode of the fourth transistor is electrically connected to the third node, and the second electrode of the fourth transistor is electrically connected to the first node;

[0246] The third transistor is a p-type transistor, and the fourth transistor is an n-type transistor;

[0247] The first sustain control terminal is the N-1th level driving signal terminal, and the second sustain control terminal is the first clock signal terminal; or

[0248] The first sustain control terminal is a second clock signal terminal, and the second sustain control terminal is a first clock signal terminal.

[0249] Optionally, the first inverter includes a fifth transistor and a sixth transistor, and the second inverter includes a seventh transistor and an eighth transistor;

[0250] The gate of the fifth transistor is electrically connected to the first node, the first electrode of the fifth transistor is electrically connected to the first voltage terminal, and the second electrode of the fifth transistor is electrically connected to the second node;

[0251] The gate of the sixth transistor is electrically connected to the first node, the first electrode of the sixth transistor is electrically connected to the second node, and the second electrode of the sixth transistor is electrically connected to the second voltage terminal;

[0252] The fifth transistor is a p-type transistor, and the sixth transistor is an n-type transistor;

[0253] The gate of the seventh transistor is electrically connected to the second node, the first electrode of the seventh transistor is electrically connected to the first voltage terminal, and the second electrode of the seventh transistor is electrically connected to the third node;

[0254] The gate of the eighth transistor is electrically connected to the second node, the first electrode of the eighth transistor is electrically connected to the third node, and the second electrode of the eighth transistor is electrically connected to the second voltage terminal;

[0255] The seventh transistor is a p-type transistor, and the eighth transistor is an n-type transistor.

[0256] Optionally, the first initialization circuit includes a ninth transistor, and the first voltage maintaining circuit includes a first capacitor;

[0257] The gate of the ninth transistor is electrically connected to the initial control terminal, the first electrode of the ninth transistor is electrically connected to the first voltage terminal, and the second electrode of the ninth transistor is electrically connected to the first node;

[0258] A first end of the first capacitor is electrically connected to the first node, and a second end of the first capacitor is electrically connected to the DC voltage end or the second node.

[0259] Optionally, the output control circuit includes a tenth transistor, an eleventh transistor, a twelfth transistor and a thirteenth transistor;

[0260] The gate of the tenth transistor is electrically connected to the Nth stage driving signal output terminal, the first electrode of the tenth transistor is electrically connected to the first voltage terminal, and the second electrode of the tenth transistor is electrically connected to the fourth node;

[0261] The gate of the eleventh transistor is electrically connected to the first node, the first electrode of the eleventh transistor is electrically connected to the first voltage terminal, and the second electrode of the eleventh transistor is electrically connected to the fourth node;

[0262] The gate of the twelfth transistor is electrically connected to the N-th stage driving signal output terminal, the first electrode of the twelfth transistor is electrically connected to the fourth node, and the second electrode of the twelfth transistor is electrically connected to the fifth node;

[0263] The gate of the thirteenth transistor is electrically connected to the first node, the first electrode of the thirteenth transistor is electrically connected to the fifth node, and the second electrode of the thirteenth transistor is electrically connected to the second voltage terminal;

[0264] The tenth transistor and the eleventh transistor are p-type transistors, and the twelfth transistor and the thirteenth transistor are n-type transistors.

[0265] Optionally, the output control circuit includes a tenth transistor, an eleventh transistor, a twelfth transistor and a thirteenth transistor;

[0266] The gate of the tenth transistor is electrically connected to the Nth stage driving signal output terminal, the first electrode of the tenth transistor is electrically connected to the first voltage terminal, and the second electrode of the tenth transistor is electrically connected to the fourth node;

[0267] The gate of the eleventh transistor is electrically connected to the third node, the first electrode of the eleventh transistor is electrically connected to the first voltage terminal, and the second electrode of the eleventh transistor is electrically connected to the fourth node;

[0268] The gate of the twelfth transistor is electrically connected to the N-th stage driving signal output terminal, the first electrode of the twelfth transistor is electrically connected to the fourth node, and the second electrode of the twelfth transistor is electrically connected to the fifth node;

[0269] The gate of the thirteenth transistor is electrically connected to the third node, the first electrode of the thirteenth transistor is electrically connected to the fifth node, and the second electrode of the thirteenth transistor is electrically connected to the second voltage terminal;

[0270] The tenth transistor and the eleventh transistor are p-type transistors, and the twelfth transistor and the thirteenth transistor are n-type transistors.

[0271] Optionally, the output circuit includes a fourteenth transistor and a fifteenth transistor;

[0272] The gate of the fourteenth transistor is electrically connected to the fourth node, the first electrode of the fourteenth transistor is electrically connected to the first voltage terminal, and the second electrode of the fourteenth transistor is electrically connected to the output driving terminal;

[0273] The gate of the fifteenth transistor is electrically connected to the fourth node, the first electrode of the fifteenth transistor is electrically connected to the output driving end, and the second electrode of the fifteenth transistor is electrically connected to the second voltage end.

[0274] In at least one embodiment of the present disclosure, the driving signal generating circuit may include a first control circuit, a second control circuit, a third inverter, and a second initialization circuit;

[0275] The first control circuit is electrically connected to the first clock signal terminal, the second clock signal terminal, the N-1th stage drive signal output terminal, and the sixth node, respectively, and is configured to shift and invert the N-1th drive signal provided by the N-1th stage drive signal output terminal under the control of the first clock signal provided by the first clock signal terminal and the second clock signal provided by the second clock signal terminal, to obtain and output the inverted signal through the sixth node;

[0276] The second control circuit is electrically connected to the first clock signal terminal, the second clock signal terminal, the N-stage drive signal output terminal, and the sixth node, respectively, and is configured to invert the N-stage drive signal provided by the N-stage drive signal output terminal under the control of the first clock signal and the second clock signal, and obtain and output the inverted signal through the sixth node;

[0277] The third inverter is electrically connected to the sixth node and the N-th stage driving signal output terminal respectively, and is used to invert the potential of the sixth node and output the inverted signal through the N-th stage driving signal output terminal;

[0278] The second initialization circuit is electrically connected to the initial control terminal, the first voltage terminal and the Nth level drive signal output terminal respectively, and is used to control the connection between the Nth level drive signal output terminal and the first voltage terminal under the control of the initial control signal provided by the initial control terminal.

[0279] In a specific implementation, the drive signal generating circuit may include a first control circuit, a second control circuit, a third inverter and a second initialization circuit; the first control circuit shifts and inverts the N-1th drive signal under the control of the first clock signal and the second clock signal, and outputs the inverted signal through the sixth node; the second control circuit inverts the Nth level drive signal under the control of the first clock signal and the second clock signal, and outputs the inverted signal through the sixth node; the third inverter inverts the potential of the sixth node, and outputs the inverted signal through the Nth level drive signal output terminal; the second initialization circuit controls the connection between the Nth level drive signal output terminal and the first voltage terminal under the control of the initial control signal.

[0280] As shown in FIG18 , based on at least one embodiment of the driving circuit shown in FIG16 , the driving signal generating circuit may include a first control circuit 31 , a second control circuit 32 , a third inverter F3 , and a second initialization circuit 30 ;

[0281] The first control circuit 31 is electrically connected to the first clock signal terminal GCK, the second clock signal terminal GCB, the N-1th stage drive signal output terminal NS(N-1), and the sixth node N6, respectively, and is configured to shift and invert the N-1th drive signal provided by the N-1th stage drive signal output terminal NS(N-1) under the control of the first clock signal provided by the first clock signal terminal GCK and the second clock signal provided by the second clock signal terminal GCB, to obtain and output the inverted signal through the sixth node N6;

[0282] The second control circuit 32 is electrically connected to the first clock signal terminal GCK, the second clock signal terminal GCB, the N-th stage driving signal output terminal NS(N), and the sixth node N6, respectively, and is configured to invert the N-th stage driving signal provided by the N-th stage driving signal output terminal NS(N) under the control of the first clock signal and the second clock signal, and obtain and output the inverted signal through the sixth node N6;

[0283] The third inverter F3 is electrically connected to the sixth node N6 and the N-th stage driving signal output terminal NS(N), respectively, for inverting the potential of the sixth node N6 and outputting the inverted signal through the N-th stage driving signal output terminal NS(N);

[0284] The second initialization circuit 30 is electrically connected to the initial control terminal NCX, the first voltage terminal V1 and the N-th level drive signal output terminal NS(N), respectively, and is used to control the connection between the N-th level drive signal output terminal NS(N) and the first voltage terminal V1 under the control of the initial control signal provided by the initial control terminal NCX.

[0285] As shown in FIG19 , based on at least one embodiment of the driving circuit shown in FIG17 , the driving signal generating circuit may include a first control circuit 31 , a second control circuit 32 , a third inverter F3 , and a second initialization circuit 30 ;

[0286] The first control circuit 31 is electrically connected to the first clock signal terminal GCK, the second clock signal terminal GCB, the N-1th stage drive signal output terminal NS(N-1), and the sixth node N6, respectively, and is configured to shift and invert the N-1th drive signal provided by the N-1th stage drive signal output terminal NS(N-1) under the control of the first clock signal provided by the first clock signal terminal GCK and the second clock signal provided by the second clock signal terminal GCB, to obtain and output the inverted signal through the sixth node N6;

[0287] The second control circuit 32 is electrically connected to the first clock signal terminal GCK, the second clock signal terminal GCB, the N-th stage driving signal output terminal NS(N), and the sixth node N6, respectively, and is configured to invert the N-th stage driving signal provided by the N-th stage driving signal output terminal NS(N) under the control of the first clock signal and the second clock signal, and obtain and output the inverted signal through the sixth node N6;

[0288] The third inverter F3 is electrically connected to the sixth node N6 and the N-th stage driving signal output terminal NS(N), respectively, for inverting the potential of the sixth node N6 and outputting the inverted signal through the N-th stage driving signal output terminal NS(N);

[0289] The second initialization circuit 30 is electrically connected to the initial control terminal NCX, the first voltage terminal V1 and the N-th level drive signal output terminal NS(N), respectively, and is used to control the connection between the N-th level drive signal output terminal NS(N) and the first voltage terminal V1 under the control of the initial control signal provided by the initial control terminal NCX.

[0290] Optionally, the first control circuit includes a sixteenth transistor, a seventeenth transistor, an eighteenth transistor and a nineteenth transistor;

[0291] The gate of the sixteenth transistor is electrically connected to the second clock signal terminal, the first electrode of the sixteenth transistor is electrically connected to the first voltage terminal, and the second electrode of the sixteenth transistor is electrically connected to the first electrode of the seventeenth transistor;

[0292] The gate of the seventeenth transistor is electrically connected to the N-1th stage driving signal output terminal, and the second electrode of the seventeenth transistor is electrically connected to the sixth node;

[0293] The gate of the eighteenth transistor is electrically connected to the (N-1)th stage driving signal output terminal, the first electrode of the eighteenth transistor is electrically connected to the sixth node, and the second electrode of the eighteenth transistor is electrically connected to the first electrode of the nineteenth transistor;

[0294] The gate of the nineteenth transistor is electrically connected to the first clock signal terminal, and the second electrode of the nineteenth transistor is electrically connected to the second voltage terminal;

[0295] The sixteenth transistor and the seventeenth transistor are p-type transistors, and the eighteenth transistor and the nineteenth transistor are n-type transistors.

[0296] Optionally, the second control circuit includes a twentieth transistor, a twenty-first transistor, a twenty-second transistor, and a twenty-third transistor;

[0297] a gate of the twentieth transistor electrically connected to the first clock signal terminal, a first electrode of the twentieth transistor electrically connected to the first voltage terminal, and a second electrode of the twentieth transistor electrically connected to the first electrode of the twenty-first transistor;

[0298] A gate of the twenty-first transistor is electrically connected to the Nth stage driving signal output terminal, and a second electrode of the twenty-first transistor is electrically connected to the sixth node;

[0299] a gate of the twenty-second transistor being electrically connected to the N-stage driving signal output terminal, a first electrode of the twenty-second transistor being electrically connected to the sixth node, and a second electrode of the twenty-second transistor being electrically connected to a first electrode of the twenty-third transistor;

[0300] A gate of the twenty-third transistor is electrically connected to the second clock signal terminal, and a second electrode of the twenty-third transistor is electrically connected to the second voltage terminal;

[0301] The twentieth transistor and the twenty-first transistor are p-type transistors, and the twenty-second transistor and the twenty-third transistor are n-type transistors.

[0302] Optionally, the third inverter includes a twenty-fourth transistor and a twenty-fifth transistor; the second initialization circuit includes a twenty-sixth transistor;

[0303] a gate of the twenty-fourth transistor is electrically connected to the sixth node, a first electrode of the twenty-fourth transistor is electrically connected to the first voltage terminal, and a second electrode of the twenty-fourth transistor is electrically connected to the first electrode of the twenty-fifth transistor;

[0304] A gate of the twenty-fifth transistor is electrically connected to the sixth node, and a second electrode of the twenty-fifth transistor is electrically connected to the second voltage terminal;

[0305] The twenty-fourth transistor is a p-type transistor, and the twenty-fifth transistor is an n-type transistor;

[0306] A gate of the twenty-sixth transistor is electrically connected to the initial control terminal, a first electrode of the twenty-sixth transistor is electrically connected to the first voltage terminal, and a second electrode of the twenty-sixth transistor is electrically connected to the Nth stage driving signal output terminal.

[0307] Optionally, the first voltage end may be a high voltage end, and the second voltage end may be a low voltage end, but the present invention is not limited thereto.

[0308] The difference between at least one embodiment of the driving circuit shown in FIG. 20 and at least one embodiment of the driving circuit shown in FIG. 18 is that at least one embodiment of the driving circuit shown in FIG. 20 does not include a first voltage maintaining circuit.

[0309] The difference between at least one embodiment of the driving circuit shown in FIG21 and at least one embodiment of the driving circuit shown in FIG19 is that at least one embodiment of the driving circuit shown in FIG21 further includes a first voltage maintaining circuit 22;

[0310] A first end of the first voltage maintaining circuit 22 is electrically connected to the first node N1 , and a second end of the first voltage maintaining circuit 22 is electrically connected to the first voltage terminal V1 . The first voltage maintaining circuit 22 is configured to maintain the potential of the first node N1 .

[0311] As shown in FIG22, based on at least one embodiment of the driving circuit shown in FIG20,

[0312] The gating circuit may include a first transistor T1 and a second transistor T2;

[0313] The gate of the first transistor T1 is electrically connected to the N-1th stage driving signal output terminal NS(N-1), the source of the first transistor T1 is electrically connected to the first node N1, and the drain of the first transistor T1 is electrically connected to the drain of the second transistor T2;

[0314] The gate of the second transistor T2 is electrically connected to the N-th stage driving signal output terminal NS(N), and the source of the second transistor T2 is electrically connected to the selection input terminal VCT;

[0315] T1 is an n-type transistor and T2 is a p-type transistor;

[0316] The first initialization circuit includes a ninth transistor T9;

[0317] The gate of the ninth transistor T9 is electrically connected to the initial control terminal NCX, the source of the ninth transistor T9 is electrically connected to the high voltage terminal VGH, and the drain of the ninth transistor T9 is electrically connected to the first node N1;

[0318] The output control circuit includes a tenth transistor T10, an eleventh transistor T11, a twelfth transistor T12 and a thirteenth transistor T13;

[0319] The gate of the tenth transistor T10 is electrically connected to the N-th stage driving signal output terminal NS(N), the source of the tenth transistor T10 is electrically connected to the high voltage terminal VGH, and the source of the tenth transistor T10 is electrically connected to the fourth node N4;

[0320] The gate of the eleventh transistor T11 is electrically connected to the first node N1, the source of the eleventh transistor T11 is electrically connected to the high voltage terminal VGH, and the drain of the eleventh transistor T11 is electrically connected to the fourth node N4;

[0321] The gate of the twelfth transistor T12 is electrically connected to the N-th stage driving signal output terminal NS(N), the source of the twelfth transistor T12 is electrically connected to the fourth node N4, and the drain of the twelfth transistor T12 is electrically connected to the fifth node N5;

[0322] The gate of the thirteenth transistor T13 is electrically connected to the first node N1, the source of the thirteenth transistor T13 is electrically connected to the fifth node N5, and the drain of the thirteenth transistor T13 is electrically connected to the low voltage terminal VGL;

[0323] The tenth transistor T10 and the eleventh transistor T11 are p-type transistors, and the twelfth transistor T12 and the thirteenth transistor T13 are n-type transistors;

[0324] The output circuit includes a fourteenth transistor T14 and a fifteenth transistor T15;

[0325] The gate of the fourteenth transistor T14 is electrically connected to the fourth node N4, the source of the fourteenth transistor T14 is electrically connected to the high voltage terminal VGH, and the drain of the fourteenth transistor T14 is electrically connected to the output driving terminal NO (N);

[0326] The gate of the fifteenth transistor T15 is electrically connected to the fourth node N4, the source of the fifteenth transistor T15 is electrically connected to the output driving terminal NO(N), and the drain of the fifteenth transistor T15 is electrically connected to the low voltage terminal VGL;

[0327] The first control circuit includes a sixteenth transistor T16, a seventeenth transistor T17, an eighteenth transistor T18 and a nineteenth transistor T19;

[0328] The gate of the sixteenth transistor T16 is electrically connected to the second clock signal terminal GCB, the source of the sixteenth transistor T16 is electrically connected to the high voltage terminal VGH, and the drain of the sixteenth transistor T16 is electrically connected to the source of the seventeenth transistor T17;

[0329] The gate of the seventeenth transistor T17 is electrically connected to the N-1th stage driving signal output terminal NS(N-1), and the drain of the seventeenth transistor T17 is electrically connected to the sixth node N6;

[0330] The gate of the eighteenth transistor T18 is electrically connected to the N-1th stage driving signal output terminal NS(N-1), the source of the eighteenth transistor T18 is electrically connected to the sixth node N6, and the drain of the eighteenth transistor T18 is electrically connected to the source of the nineteenth transistor T19;

[0331] The gate of the nineteenth transistor T19 is electrically connected to the first clock signal terminal GCK, and the source of the nineteenth transistor T19 is electrically connected to the low voltage terminal VGL;

[0332] The sixteenth transistor T16 and the seventeenth transistor T17 are p-type transistors, and the eighteenth transistor T18 and the nineteenth transistor T19 are n-type transistors;

[0333] The second control circuit includes a twentieth transistor T20, a twenty-first transistor T21, a twenty-second transistor T22 and a twenty-third transistor T23;

[0334] a gate of the 20th transistor T20 electrically connected to the first clock signal terminal GCK, a source of the 20th transistor T20 electrically connected to the high voltage terminal VGH, and a drain of the 20th transistor T20 electrically connected to the source of the 21st transistor T21;

[0335] A gate of the twenty-first transistor T21 is electrically connected to the N-th stage driving signal output terminal NS(N), and a drain of the twenty-first transistor T21 is electrically connected to the sixth node N6;

[0336] a gate of the twenty-second transistor T22 being electrically connected to the N-th stage driving signal output terminal NS(N), a source of the twenty-second transistor T22 being electrically connected to the sixth node N6, and a source of the twenty-second transistor T22 being electrically connected to a drain of the twenty-third transistor T23;

[0337] A gate of the twenty-third transistor T23 is electrically connected to the second clock signal terminal GCB, and a drain of the twenty-third transistor T23 is electrically connected to the low voltage terminal VGL;

[0338] The 20th transistor T20 and the 21st transistor T21 are p-type transistors, and the 22nd transistor T22 and the 23rd transistor T23 are n-type transistors;

[0339] The third inverter includes a twenty-fourth transistor T24 and a twenty-fifth transistor T25; the second initialization circuit includes a twenty-sixth transistor T26;

[0340] The gate of the twenty-fourth transistor T24 is electrically connected to the sixth node N6, the source of the twenty-fourth transistor T24 is electrically connected to the high voltage terminal VGH, and the drain of the twenty-fourth transistor T24 is electrically connected to the source of the twenty-fifth transistor T25;

[0341] A gate of the twenty-fifth transistor T25 is electrically connected to the sixth node N6, and a drain of the twenty-fifth transistor T25 is electrically connected to the low voltage terminal VGL;

[0342] The twenty-fourth transistor T24 is a p-type transistor, and the twenty-fifth transistor T25 is an n-type transistor;

[0343] A gate of the twenty-sixth transistor T26 is electrically connected to the initial control terminal NCX, a source of the twenty-sixth transistor T26 is electrically connected to the high voltage terminal VGH, and a second electrode of the twenty-sixth transistor is electrically connected to the N-th stage driving signal output terminal NS(N);

[0344] The twenty-sixth transistor T26 is a p-type transistor.

[0345] In at least one embodiment of the present disclosure, the structure of the drive signal generating circuit is not limited to that shown in FIG. 22 . The drive signal generating circuit may be, for example, a 16T3C circuit, a 13T3C circuit, a 12T3C circuit, a 10T3C circuit, etc., but is not limited thereto.

[0346] At least one embodiment of the driving circuit shown in FIG. 22 of the present disclosure is in operation.

[0347] 1. When GCK provides a high voltage signal, T19 is turned on and T20 is turned off. GCB provides a low voltage signal, T16 is turned on and T23 is turned off. At this time, the drive signal generation circuit is in the transmission state.

[0348] When NS(N) provides a low voltage signal, T17 is turned on, T18 is turned off, the potential of N6 is high voltage, T25 is turned on, T24 is turned off, NS(N) provides a low voltage signal, and NS(N-1) provides a low voltage signal;

[0349] When NS(N) provides a high voltage signal, T17 is closed, T18 is opened, the potential of N6 is low voltage, T25 is closed, T24 is opened, and both NS(N) and NS(N-1) provide high voltage signals;

[0350] 2. When GCK provides a low voltage signal, T19 is closed and T20 is opened. GCB provides a high voltage signal, T16 is closed and T23 is opened. At this time, the circuit is in the registered state. T21, T22, T23 and T11 form a latch circuit. The potential of N6 and the signal provided by NS (N) maintain the previous state unchanged.

[0351] 3. When the signal provided by NS(N-1) switches from a low voltage signal to a high voltage signal, GCK provides a low voltage signal, closes T19, opens T20, GCB provides a high voltage signal, closes T16, and opens T23. At this time, the circuit is in the register state. T21, T22, T23, and T11 form a latch circuit. The potential of N6 and the signal provided by NS(N) maintain the previous low voltage state unchanged, completing the shift. At the next moment, GCK provides a high voltage signal, opens T19, closes T20, GCB provides a low voltage signal, opens T16, and closes T23. At this time, the circuit is in the transmission state. NS(N-1) provides a high voltage signal, closes T17, opens T18, the potential of N6 is low, closes T25, and opens T24. NS(N) and NS(N-1) both provide high voltage signals, realizing the shift register from NS(N-1) to NS(N).

[0352] 4. When NS(N-1) switches from providing a high voltage signal to providing a low voltage signal, GCK provides a low voltage signal, turns off T19, turns on T20, GCB provides a high voltage signal, turns off T16, and turns on T23. At this time, the circuit is in the register state. T21, T22, T23 and T11 form a latch circuit. The potential of N6 and the signal provided by NS(N) remain at the previous high voltage state unchanged, completing the shift; at the next moment, GCK provides a high voltage signal, turns on T19, turns off T20, GCB provides a low voltage signal, turns on T16, and turns off T23. At this time, the circuit is in the transmission state, NS(N-1) provides a low voltage signal, turns on T17, turns off T18, the potential of N6 is high voltage, turns on T25, and turns off T24. NS(N) and NS(N-1) both provide low voltage signals to realize the shift registration from NS(N-1) to NS(N).

[0353] At least one embodiment of the driving circuit shown in FIG. 22 of the present disclosure is in operation.

[0354] When NS(N-1) provides a high voltage signal, T1 is turned on; when NS(N) provides a low voltage signal, T2 is turned on. By simultaneously selecting the two signals, the state of the selection input signal provided by VCT within a high-low frequency switching period H can be obtained and written to the first node N1. Then, T1 and T2 will not be turned on simultaneously at other times, preventing the potential of N1 from being affected by the potential change of the selection input signal provided by VCT. T10, T11, T12, and T13 form a NAND gate, the input signals of which are the signal provided by NS(N) and the potential of N1, respectively, and the output of which is electrically connected to the fourth node N4. T24 and T25 form a third inverter, the input of which is electrically connected to N4, and the output of which is electrically connected to NO(N);

[0355] If VCT provides a high voltage signal when T1 and T2 are turned on, N1 will be written to a high voltage, and the gate state of the NAND gate can ensure that NS(N) is normally passed to NO(N);

[0356] If VCT provides a low voltage signal when T1 and T2 are turned on, N1 will be written to a low voltage, and the NAND gate is in the cut-off state, ensuring that NO(N) provides a low voltage signal, thereby achieving low-level maintenance of NO(N).

[0357] Optionally, when the display starts (that is, when the display device is turned on), in the power-on stage before the first stage, NCX outputs a low voltage signal, T9 is turned on to control the potential of N1 to a high voltage, and T26 is turned on to enable NS(N) to provide a high voltage signal; at this time, T12 and T13 are both turned on, the potential of N4 is a low voltage, T14 is turned on, T15 is turned off, and NO(N) outputs a high voltage signal, which can turn on the second display control transistor M2 included in all pixel circuits in the effective display area, clear the residual charge in the storage capacitor Cst, and improve the screen flickering problem when the device is turned on;

[0358] Afterwards, when NS(N-1) outputs a high voltage signal and NS(N) outputs a low voltage signal, T1 and T2 are turned on.

[0359] When VCT provides a low voltage signal, the potential of N1 is a low voltage signal, and C1 maintains the potential of N1; T11 is turned on, T10 is turned on, the potential of N4 is a high voltage, T15 is turned on, and NO (N) outputs a low voltage signal;

[0360] When VCT provides a high voltage signal, the potential of N1 is a high voltage signal, C1 maintains the potential of N1, T11 is turned off, T10 is turned on, the potential of N4 is a high voltage, T15 is turned on, and NO (N) outputs a low voltage signal;

[0361] Afterwards, in the Nth stage driving signal providing phase, NS(N) outputs a high voltage signal.

[0362] When the potential of N1 is low voltage, T10 is turned off, T11 is turned on, the potential of N4 is high voltage, T15 is turned on, and NO(N) outputs a low voltage signal;

[0363] When the potential of N1 is high voltage, T10 is turned off, T11 is turned off, T12 and T13 are turned on, the potential of N4 is low voltage, T14 is turned on, and NO(N) outputs a high voltage signal;

[0364] After the Nth stage of driving signal supply, NS(N) outputs a low voltage signal.

[0365] When the potential of N1 is a low voltage signal, T10 is turned on, T11 is turned on, the potential of N4 is a high voltage, and NO(N) outputs a low voltage signal;

[0366] When the potential of N1 is a high voltage signal, T10 is turned on, T11 is turned off, the potential of N4 is a high voltage, and NO(N) outputs a low voltage signal.

[0367] When at least one embodiment of the driving circuit shown in Figure 22 of the present disclosure is in operation, when NS(N-1) outputs a high voltage signal and NS(N) outputs a low voltage signal, T1 and T2 are turned on. By simultaneously selecting the above two signals, the selection input signal state within a high-low frequency switching cycle can be obtained.

[0368] In FIG22 , the node labeled N7 is the seventh node, and the seventh node N7 is electrically connected to the drain of T1 . The seventh node N7 is electrically connected to the drain of T1 .

[0369] As shown in FIG23 , based on at least one embodiment of the driving circuit shown in FIG22 of the present disclosure, the driving circuit according to at least one embodiment of the present disclosure further includes a second voltage maintaining circuit; the first node N1 is electrically connected to the gate of T11 through the second voltage maintaining circuit;

[0370] The second voltage maintaining circuit includes a first inverter, a second inverter and a maintaining control circuit;

[0371] The sustain control circuit includes a third transistor T3 and a fourth transistor T4;

[0372] The gate of the third transistor T3 is electrically connected to the N-1th stage driving signal output terminal NS(N-1), the source of the third transistor T3 is electrically connected to the first node N1, and the drain of the third transistor T3 is electrically connected to the third node N3;

[0373] The gate of the fourth transistor T4 is electrically connected to the first clock signal terminal GCK, the source of the fourth transistor T4 is electrically connected to the third node N3, and the drain of the fourth transistor T4 is electrically connected to the first node N1;

[0374] The first inverter includes a fifth transistor T5 and a sixth transistor T6, and the second inverter includes a seventh transistor T7 and an eighth transistor T8;

[0375] The gate of the fifth transistor T5 is electrically connected to the first node N1, the source of the fifth transistor T5 is electrically connected to the high voltage terminal VGH, and the drain of the fifth transistor T5 is electrically connected to the second node N2;

[0376] The gate of the sixth transistor T6 is electrically connected to the first node N1, the source of the sixth transistor T6 is electrically connected to the second node N2, and the drain of the sixth transistor T6 is electrically connected to the low voltage terminal VGL;

[0377] The gate of the seventh transistor T7 is electrically connected to the second node N2, the source of the seventh transistor T7 is electrically connected to the high voltage terminal VGH, and the drain of the seventh transistor T7 is electrically connected to the third node N3;

[0378] The gate of the eighth transistor T8 is electrically connected to the second node N2, the source of the eighth transistor T8 is electrically connected to the third node N3, and the drain of the eighth transistor T8 is electrically connected to the low voltage terminal VGL;

[0379] The third node N3 is electrically connected to the gate of T11 and the gate of T13 respectively.

[0380] In at least one embodiment of the driving circuit shown in FIG23 , the third transistor T3 is a p-type transistor, the fourth transistor T4 is an n-type transistor; the fifth transistor T5 is a p-type transistor, the sixth transistor T6 is an n-type transistor; the seventh transistor T7 is a p-type transistor, and the eighth transistor T8 is an n-type transistor.

[0381] In at least one embodiment of the driving circuit shown in FIG23 of the present disclosure, since the p-type transistor has a threshold voltage loss when transmitting a low voltage and the n-type transistor has a threshold voltage loss when transmitting a high voltage, the absolute value of the potential of N1 will be lower. The absolute value of the potential of N1 can be controlled to increase by the first inverter and the second inverter, thereby better controlling the corresponding transistors in the output circuit to be turned on or off, and maintaining the control circuit control when T1 and T2 are turned on, controlling the disconnection between N1 and N3 so as not to affect the writing of the potential of N1.

[0382] FIG. 24 is an operation timing diagram of at least one embodiment of the driving circuit shown in FIG. 23 of the present disclosure.

[0383] The difference between at least one embodiment of the driving circuit shown in FIG25 and at least one embodiment of the driving circuit shown in FIG22 is that: at least one embodiment of the driving circuit shown in FIG25 further includes a first capacitor C1;

[0384] A first end of the first capacitor C1 is electrically connected to the first node N1, and a second end of the first capacitor C1 is electrically connected to the low voltage terminal VGL;

[0385] C1 is used to stabilize the potential of N1.

[0386] The driving method described in the embodiment of the present disclosure is applied to the above-mentioned driving circuit, and the driving method includes:

[0387] The driving signal generating circuit performs a shift operation on the N-1th level driving signal to obtain and output the Nth level driving signal through the Nth level driving signal output terminal;

[0388] The gating circuit controls, under the control of the gating control signal, to write the gating input signal provided by the gating input terminal into the first node;

[0389] The output control circuit performs a NAND operation on the N-th stage driving signal and the potential of the second terminal of the output control circuit to obtain a first output signal;

[0390] The output circuit is used to invert the first output signal to obtain and provide an output driving signal through the output driving terminal.

[0391] The driving module described in the embodiment of the present disclosure includes multiple stages of the above-mentioned driving circuits;

[0392] The Nth stage driving circuit is electrically connected to the driving signal output terminal included in the N-1th stage driving circuit; N is a positive integer.

[0393] As shown in FIG26 , the first-stage driving circuit is labeled S1, the second-stage driving circuit is labeled S2, the third-stage driving circuit is labeled S3, the fourth-stage driving circuit is labeled S4, the fifth-stage driving circuit is labeled S5, the sixth-stage driving circuit is labeled S6, the seventh-stage driving circuit is labeled S7, the eighth-stage driving circuit is labeled S8, the ninth-stage driving circuit is labeled S9, the tenth-stage driving circuit is labeled S10, the eleventh-stage driving circuit is labeled S11, and the twelfth-stage driving circuit is labeled S12.

[0394] The terminal labeled NS(1) is the drive signal output terminal of S1, and the terminal labeled NO(1) is the output drive terminal of S1;

[0395] The terminal labeled NS(2) is the drive signal output terminal of S2, and the terminal labeled NO(2) is the output drive terminal of S2; S2 is electrically connected to NS(1);

[0396] The terminal labeled NS (3) is the drive signal output terminal of S3, and the terminal labeled NO (3) is the output drive terminal of S3; S3 is electrically connected to NS (2);

[0397] The terminal labeled NS (4) is the drive signal output terminal of S4, and the terminal labeled NO (4) is the output drive terminal of S4; S4 is electrically connected to NS (3);

[0398] The terminal labeled NS (5) is the drive signal output terminal of S5, and the terminal labeled NO (5) is the output drive terminal of S5; S5 is electrically connected to NS (4);

[0399] The terminal labeled NS (6) is the drive signal output terminal of S6, and the terminal labeled NO (6) is the output drive terminal of S6; S6 is electrically connected to NS (5);

[0400] The terminal labeled NS (7) is the drive signal output terminal of S7, and the terminal labeled NO (7) is the output drive terminal of S7; S7 is electrically connected to NS (6);

[0401] The terminal labeled NS (8) is the drive signal output terminal of S8, and the terminal labeled NO (8) is the output drive terminal of S8; S8 is electrically connected to NS (7);

[0402] The terminal labeled NS (9) is the drive signal output terminal of S9, and the terminal labeled NO (9) is the output drive terminal of S9; S9 is electrically connected to NS (8);

[0403] The terminal labeled NS (10) is the drive signal output terminal of S10, and the terminal labeled NO (10) is the output drive terminal of S10; S10 is electrically connected to NS (9);

[0404] The terminal labeled NS (11) is the drive signal output terminal of S11, and the terminal labeled NO (11) is the output drive terminal of S11; S11 is electrically connected to NS (10);

[0405] The terminal labeled NS (12) is the drive signal output terminal of S12, and the terminal labeled NO (12) is the output drive terminal of S12; S12 is electrically connected to NS (11);

[0406] S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11 and S12 are all electrically connected to the selection input terminal VCT;

[0407] S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11 and S12 are all electrically connected to the first clock signal terminal GCK;

[0408] S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11 and S12 are all electrically connected to the second clock signal terminal GCB.

[0409] In FIG26 , the terminal labeled STV is a starting voltage terminal, and S1 is electrically connected to STV.

[0410] FIG. 27 is an operation timing diagram of at least one embodiment of the driving module shown in FIG. 26 .

[0411] In at least one embodiment of the driving module shown in FIG. 26 of the present disclosure, when NS(N-1) outputs a high voltage signal and NS(N) outputs a low voltage signal, if VCT outputs a low voltage signal, then when NS(N) outputs a high voltage signal, NO(N) outputs a low voltage signal;

[0412] When NS(N-1) outputs a high voltage signal and NS(N) outputs a low voltage signal, if VCT outputs a high voltage signal, then when NS(N) outputs a high voltage signal, NO(N) outputs a high voltage signal.

[0413] The display device described in the embodiment of the present disclosure includes the above-mentioned driving module.

[0414] The above is a preferred embodiment of the present disclosure. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles described in the present disclosure. These improvements and modifications should also be regarded as the scope of protection of the present disclosure.

Claims

1. A driving circuit, comprising a driving signal generating circuit, a gating circuit, an output control circuit and an output circuit; The driving signal generating circuit is electrically connected to the N-1th driving signal output terminal and the Nth driving signal output terminal respectively, and is used to perform a shift operation on the N-1th driving signal provided by the N-1th driving signal output terminal, and obtain and output the Nth driving signal through the Nth driving signal output terminal; The gating circuit is electrically connected to the first node, the gating input terminal and the gating control terminal respectively, and is used for controlling the gating input signal provided by the gating input terminal to be written into the first node under the control of the gating control signal provided by the gating control terminal; The first end of the output control circuit is electrically connected to the N-th level drive signal output end, and the second end of the output control circuit is electrically connected to the first node, and is used to perform a negative AND operation on the N-th level drive signal and the potential of the second end of the output control circuit to obtain a first output signal; The output circuit is used to invert the first output signal to obtain an output drive signal and provide it through the output drive terminal; N is a positive integer.

2. The driving circuit according to claim 1, wherein: The gating circuit is used for controlling the gating input signal provided by the gating input terminal to be written into the first node when the potential of the N-1th level driving signal is the first voltage and the potential of the Nth level driving signal is the second voltage.

3. The driving circuit according to claim 1, wherein: The gating circuit includes a first transistor; a gate of the first transistor is electrically connected to the gating control terminal, a first electrode of the first transistor is electrically connected to the first node, and a second electrode of the first transistor is electrically connected to the gating input terminal.

4. The driving circuit according to claim 1, wherein: The gating control terminal includes a first gating control terminal and a second gating control terminal; the gating circuit includes a first transistor and a second transistor; The gate of the first transistor is electrically connected to the first selection control terminal, the first electrode of the first transistor is electrically connected to the first node, and the second electrode of the first transistor is electrically connected to the first electrode of the second transistor; The gate of the second transistor is electrically connected to the second gate control terminal, and the second electrode of the second transistor is electrically connected to the gate input terminal; The first gating control terminal is an N-1th level driving signal output terminal, the second gating control terminal is an Nth level driving signal output terminal, the first transistor is an n-type transistor, and the second transistor is a p-type transistor; or, The first gating control terminal is an N-th level driving signal output terminal, the second gating control terminal is an N-1-th level driving signal output terminal, the first transistor is a p-type transistor, and the second transistor is an n-type transistor; or, The first gating control terminal is connected to the inverted signal of the N-1th level driving signal, the second gating control terminal is the output terminal of the Nth level driving signal, and the first transistor and the second transistor are both p-type transistors; or The first gating control terminal is an output terminal of the Nth level driving signal, and the second gating control terminal is connected to the inverted signal of the N-1th level driving signal; the first transistor and the second transistor are both p-type transistors; or, The first gating control terminal is an N-1th level driving signal terminal, the second gating control terminal is connected to an inverted signal of the Nth level driving signal, and the first transistor and the second transistor are both n-type transistors; or, The first gating control terminal is connected to the inverted signal of the Nth level driving signal, the second gating control terminal is the N-1th level driving signal terminal, and the first transistor and the second transistor are both n-type transistors.

5. The driving circuit according to claim 1, wherein: Also includes a first initialization circuit; The first initialization circuit is electrically connected to the initial control terminal, the first voltage terminal and the first node respectively, and is used to control the connection between the first node and the first voltage terminal under the control of the initial control signal provided by the initial control terminal.

6. The driving circuit according to claim 5, wherein: Also included is a first voltage maintaining circuit; The first end of the first voltage maintaining circuit is electrically connected to the first node, the second end of the first voltage maintaining circuit is electrically connected to a DC voltage end or a second node, and the first voltage maintaining circuit is used to maintain the potential of the first node.

7. The driving circuit according to any one of claims 1 to 6, wherein: Also comprising a second voltage maintaining circuit, the first node is electrically connected to the second end of the output control circuit through the second voltage maintaining circuit; The second voltage maintaining circuit includes a first inverter, a second inverter and a maintaining control circuit; The input terminal of the first inverter is electrically connected to the first node, the output terminal of the first inverter is electrically connected to the second node, the input terminal of the second inverter is electrically connected to the second node, and the output terminal of the second inverter is electrically connected to a third node and the second terminal of the output control circuit; The first inverter is used to invert the potential of the first node and output the inverted potential of the first node through the output terminal of the first inverter, and the second inverter is used to invert the potential of its input terminal and output the inverted potential through the output terminal of the second inverter; The sustain control circuit is electrically connected to the sustain control terminal, the third node and the first node respectively, and is used to control the connection or disconnection between the third node and the first node under the control of a sustain control signal provided by the sustain control terminal.

8. The driving circuit according to claim 7, wherein: The maintenance control end includes a first maintenance control end and a second maintenance control end; The sustain control circuit includes a third transistor and a fourth transistor; The gate of the third transistor is electrically connected to the first sustain control terminal, the first electrode of the third transistor is electrically connected to the first node, and the second electrode of the third transistor is electrically connected to the third node; The gate of the fourth transistor is electrically connected to the second sustain control terminal, the first electrode of the fourth transistor is electrically connected to the third node, and the second electrode of the fourth transistor is electrically connected to the first node; The third transistor is a p-type transistor, and the fourth transistor is an n-type transistor; The first sustain control terminal is the N-1th level driving signal terminal, and the second sustain control terminal is the first clock signal terminal; or, The first sustain control terminal is a second clock signal terminal, and the second sustain control terminal is a first clock signal terminal.

9. The driving circuit according to claim 7, wherein: The first inverter includes a fifth transistor and a sixth transistor, and the second inverter includes a seventh transistor and an eighth transistor; The gate of the fifth transistor is electrically connected to the first node, the first electrode of the fifth transistor is electrically connected to the first voltage terminal, and the second electrode of the fifth transistor is electrically connected to the second node; The gate of the sixth transistor is electrically connected to the first node, and the first The first electrode of the sixth transistor is electrically connected to the second node, and the second electrode of the sixth transistor is electrically connected to the second voltage terminal; The fifth transistor is a p-type transistor, and the sixth transistor is an n-type transistor; The gate of the seventh transistor is electrically connected to the second node, the first electrode of the seventh transistor is electrically connected to the first voltage terminal, and the second electrode of the seventh transistor is electrically connected to the third node; The gate of the eighth transistor is electrically connected to the second node, the first electrode of the eighth transistor is electrically connected to the third node, and the second electrode of the eighth transistor is electrically connected to the second voltage terminal; The seventh transistor is a p-type transistor, and the eighth transistor is an n-type transistor.

10. The driving circuit according to claim 6, wherein: The first initialization circuit includes a ninth transistor, and the first voltage maintaining circuit includes a first capacitor; The gate of the ninth transistor is electrically connected to the initial control terminal, the first electrode of the ninth transistor is electrically connected to the first voltage terminal, and the second electrode of the ninth transistor is electrically connected to the first node; The first end of the first capacitor is electrically connected to the first node, and the second end of the first capacitor is electrically connected to the DC voltage end or the second node.

11. The driving circuit according to any one of claims 1 to 6, wherein: The output control circuit includes a tenth transistor, an eleventh transistor, a twelfth transistor and a thirteenth transistor; The gate of the tenth transistor is electrically connected to the Nth stage driving signal output terminal, the first electrode of the tenth transistor is electrically connected to the first voltage terminal, and the second electrode of the tenth transistor is electrically connected to the fourth node; The gate of the eleventh transistor is electrically connected to the first node, the first electrode of the eleventh transistor is electrically connected to the first voltage terminal, and the second electrode of the eleventh transistor is electrically connected to the fourth node; The gate of the twelfth transistor is electrically connected to the Nth stage driving signal output terminal, the first electrode of the twelfth transistor is electrically connected to the fourth node, and the second electrode of the twelfth transistor is electrically connected to the fifth node; The gate of the thirteenth transistor is electrically connected to the first node, the first electrode of the thirteenth transistor is electrically connected to the fifth node, and the second electrode of the thirteenth transistor is electrically connected to the second voltage terminal; The tenth transistor and the eleventh transistor are p-type transistors, and the twelfth transistor and the thirteenth transistor are n-type transistors.

12. The driving circuit according to claim 7, wherein: The output control circuit includes a tenth transistor, an eleventh transistor, a twelfth transistor and a thirteenth transistor; The gate of the tenth transistor is electrically connected to the Nth stage driving signal output terminal, the first electrode of the tenth transistor is electrically connected to the first voltage terminal, and the second electrode of the tenth transistor is electrically connected to the fourth node; The gate of the eleventh transistor is electrically connected to the third node, the first electrode of the eleventh transistor is electrically connected to the first voltage terminal, and the second electrode of the eleventh transistor is electrically connected to the fourth node; The gate of the twelfth transistor is electrically connected to the Nth stage driving signal output terminal, the first electrode of the twelfth transistor is electrically connected to the fourth node, and the second electrode of the twelfth transistor is electrically connected to the fifth node; The gate of the thirteenth transistor is electrically connected to the third node, the first electrode of the thirteenth transistor is electrically connected to the fifth node, and the second electrode of the thirteenth transistor is electrically connected to the second voltage terminal; The tenth transistor and the eleventh transistor are p-type transistors, and the twelfth transistor and the thirteenth transistor are n-type transistors.

13. The driving circuit according to any one of claims 1 to 6, wherein: The output circuit includes a fourteenth transistor and a fifteenth transistor; The gate of the fourteenth transistor is electrically connected to the fourth node, the first electrode of the fourteenth transistor is electrically connected to the first voltage terminal, and the second electrode of the fourteenth transistor is electrically connected to the output driving terminal; A gate of the fifteenth transistor is electrically connected to the fourth node, a first electrode of the fifteenth transistor is electrically connected to the output driving end, and a second electrode of the fifteenth transistor is electrically connected to the second voltage end.

14. The driving circuit according to any one of claims 1 to 6, wherein: The driving signal generating circuit includes a first control circuit, a second control circuit, a third inverter and a second initialization circuit; The first control circuit is electrically connected to the first clock signal terminal, the second clock signal terminal, the N-1th stage driving signal output terminal and the sixth node respectively, and is used for controlling the N-1th stage driving signal output terminal under the control of the first clock signal provided by the first clock signal terminal and the second clock signal provided by the second clock signal terminal. shifting and inverting the N-1th driving signal provided by the stage driving signal output terminal, and obtaining and outputting the inverted signal through the sixth node; The second control circuit is electrically connected to the first clock signal terminal, the second clock signal terminal, the Nth level driving signal output terminal and the sixth node respectively, and is used to invert the Nth level driving signal provided by the Nth level driving signal output terminal under the control of the first clock signal and the second clock signal, and obtain and output the inverted signal through the sixth node; The third inverter is electrically connected to the sixth node and the Nth stage drive signal output terminal respectively, and is used to invert the potential of the sixth node and output the inverted signal through the Nth stage drive signal output terminal; The second initialization circuit is electrically connected to the initial control terminal, the first voltage terminal and the Nth level drive signal output terminal respectively, and is used to control the connection between the Nth level drive signal output terminal and the first voltage terminal under the control of the initial control signal provided by the initial control terminal.

15. The driving circuit according to claim 14, wherein: The first control circuit includes a sixteenth transistor, a seventeenth transistor, an eighteenth transistor and a nineteenth transistor; The gate of the sixteenth transistor is electrically connected to the second clock signal terminal, the first electrode of the sixteenth transistor is electrically connected to the first voltage terminal, and the second electrode of the sixteenth transistor is electrically connected to the first electrode of the seventeenth transistor; The gate of the seventeenth transistor is electrically connected to the N-1th stage driving signal output terminal, and the second electrode of the seventeenth transistor is electrically connected to the sixth node; The gate of the eighteenth transistor is electrically connected to the N-1th stage driving signal output terminal, the first electrode of the eighteenth transistor is electrically connected to the sixth node, and the second electrode of the eighteenth transistor is electrically connected to the first electrode of the nineteenth transistor; The gate of the nineteenth transistor is electrically connected to the first clock signal terminal, and the second electrode of the nineteenth transistor is electrically connected to the second voltage terminal; The sixteenth transistor and the seventeenth transistor are p-type transistors, and the eighteenth transistor and the nineteenth transistor are n-type transistors.

16. The driving circuit according to claim 14, wherein: The second control circuit includes a twentieth transistor, a twenty-first transistor, a twenty-second transistor and a twenty-third transistor; The gate of the twentieth transistor is electrically connected to the first clock signal terminal. The first electrode of the body transistor is electrically connected to the first voltage terminal, and the second electrode of the 20th transistor is electrically connected to the first electrode of the 21st transistor; A gate of the twenty-first transistor is electrically connected to the Nth stage driving signal output terminal, and a second electrode of the twenty-first transistor is electrically connected to the sixth node; A gate of the 22nd transistor is electrically connected to the Nth stage driving signal output terminal, a first electrode of the 22nd transistor is electrically connected to the sixth node, and a second electrode of the 22nd transistor is electrically connected to a first electrode of the 23rd transistor; A gate of the twenty-third transistor is electrically connected to the second clock signal terminal, and a second electrode of the twenty-third transistor is electrically connected to the second voltage terminal; The 20th transistor and the 21st transistor are p-type transistors, and the 22nd transistor and the 23rd transistor are n-type transistors.

17. The driving circuit according to claim 14, wherein: The third inverter includes a twenty-fourth transistor and a twenty-fifth transistor; the second initialization circuit includes a twenty-sixth transistor; a gate of the twenty-fourth transistor is electrically connected to the sixth node, a first electrode of the twenty-fourth transistor is electrically connected to the first voltage terminal, and a second electrode of the twenty-fourth transistor is electrically connected to a first electrode of the twenty-fifth transistor; A gate of the twenty-fifth transistor is electrically connected to the sixth node, and a second electrode of the twenty-fifth transistor is electrically connected to the second voltage terminal; The twenty-fourth transistor is a p-type transistor, and the twenty-fifth transistor is an n-type transistor; A gate of the twenty-sixth transistor is electrically connected to the initial control terminal, a first electrode of the twenty-sixth transistor is electrically connected to the first voltage terminal, and a second electrode of the twenty-sixth transistor is electrically connected to the Nth stage driving signal output terminal.

18. A driving method, applied to the driving circuit according to any one of claims 1 to 17, the driving method comprising: The driving signal generating circuit performs a shift operation on the N-1th level driving signal to obtain and output the Nth level driving signal through the Nth level driving signal output terminal; The gating circuit controls, under the control of the gating control signal, to write the gating input signal provided by the gating input terminal into the first node; The output control circuit controls the Nth level driving signal and the second end of the output control circuit. Performing a bit AND-NOT operation to obtain a first output signal; The output circuit is used to invert the first output signal to obtain and provide an output drive signal through the output drive terminal.

19. A driving module, comprising a plurality of driving circuits according to any one of claims 1 to 17; The Nth stage driving circuit is electrically connected to the driving signal output terminal included in the N-1th stage driving circuit; N is a positive integer.

20. A display device comprising the driving module according to claim 19.

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