Display panel and display device

Abstract

The invention provides a display panel and a display device. The display panel comprises a pixel driving circuit, wherein the pixel driving circuit comprises a second transistor; the display panel further comprises a substrate, a shielding layer and an active layer, the shielding layer is located on one side of the substrate, and the shielding layer is connected with a first signal; the active layer is located on the side, away from the substrate, of the shielding layer, the active layer comprises a second active part, and the second active part is used for forming a channel region of a second transistor; wherein the orthographic projection of the shielding layer on the substrate covers the orthographic projection of the second active part on the substrate. According to the display panel disclosed by the invention, free charges on the bottom layer can be prevented from diffusing to the channel region of the second transistor at high temperature through the arranged shielding layer, so that the influence of the free charges on the characteristics of the second transistor can be avoided; therefore, the problem of abnormal display caused by diffusion of free charges after the high-temperature reliability test of the display panel is solved.

Description

Display panel and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] Organic Light Emitting Diodes (OLEDs) are active light-emitting display devices with advantages such as self-luminescence, wide viewing angles, high contrast, low power consumption, extremely fast response times, thinness, and flexibility. OLED displays are increasingly being used. However, some related technologies have been found to exhibit color shift after reliability testing.

[0003] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute prior art known to ordinary technicians in the field.

[0004] Summary of the Invention

[0005] The purpose of the present disclosure is to overcome the above-mentioned deficiencies of the prior art and to provide a display panel and a display device.

[0006] According to one aspect of the present disclosure, a display panel is provided, which includes a pixel driving circuit, the pixel driving circuit including a second transistor and a driving transistor, the first electrode of the second transistor being connected to the gate of the driving transistor; the display panel also includes: a base substrate; an auxiliary layer located on one side of the base substrate, the auxiliary layer being connected to a first signal; an active layer located on a side of the auxiliary layer facing away from the base substrate, the active layer including: a second active portion for forming a channel region of the second transistor; and a third active portion for forming a channel region of the driving transistor; wherein the orthographic projection of the auxiliary layer on the base substrate covers the orthographic projections of the second active portion and the third active portion on the base substrate.

[0007] In an exemplary embodiment of the present disclosure, the display panel includes a plurality of pixel driving circuits arrayed along row and column directions, the auxiliary layer includes a plurality of auxiliary units arrayed along row and column directions, and the auxiliary units are arranged corresponding to the pixel driving circuits; the second active portion includes a third sub-active portion and a fourth sub-active portion; the auxiliary unit includes: a first auxiliary portion, whose orthographic projection on the base substrate covers the orthographic projection of the third active portion on the base substrate; and a second auxiliary portion, whose orthographic projection on the base substrate respectively covers the orthographic projections of the third sub-active portion and the fourth sub-active portion on the base substrate.

[0008] In an exemplary embodiment of the present disclosure, the active layer further includes: a tenth active portion connected between the third sub-active portion and the fourth sub-active portion; wherein the orthographic projection of the second auxiliary portion on the base substrate does not overlap with the orthographic projection of the tenth active portion on the base substrate.

[0009] In an exemplary embodiment of the present disclosure, the active layer also includes: a tenth active portion, connected between the third sub-active portion and the fourth sub-active portion; wherein, the second auxiliary portion includes a first sub-auxiliary portion and a second sub-auxiliary portion, the orthographic projection of the first sub-auxiliary portion on the base substrate covers the orthographic projection of the third sub-active portion and the fourth sub-active portion on the base substrate, and the orthographic projection of the second sub-auxiliary portion on the base substrate covers the orthographic projection of the tenth active portion on the base substrate.

[0010] In an exemplary embodiment of the present disclosure, the display panel also includes: a second conductive layer, located on a side of the active layer away from the auxiliary layer, the second conductive layer including: a first conductive block, whose orthographic projection on the base substrate is located on the orthographic projection of the tenth active portion on the base substrate; a second source-drain metal layer, located on a side of the second conductive layer away from the base substrate, the second source-drain metal layer including: a first power line, whose orthographic projection on the base substrate extends along a column direction, the first power line is coupled to the first conductive block through a third via; wherein, the orthographic projection of the second sub-auxiliary portion on the base substrate also covers the orthographic projection of the third via on the base substrate.

[0011] In an exemplary embodiment of the present disclosure, the active layer further includes: a first active portion connected to one side of the second active portion, the first active portion being used to form a channel region of the first transistor; the auxiliary unit further includes: a fourth auxiliary portion connected to the second auxiliary portion, the orthographic projection of the fourth auxiliary portion on the base substrate covering the orthographic projection of the first active portion on the base substrate.

[0012] In an exemplary embodiment of the present disclosure, the first active portion includes a first sub-active portion and a second sub-active portion; the active layer also includes: a ninth active portion, connected between the first sub-active portion and the second sub-active portion; wherein the orthographic projection of the fourth auxiliary portion on the base substrate also covers the orthographic projection of the ninth active portion on the base substrate.

[0013] In an exemplary embodiment of the present disclosure, the pixel driving circuit also includes a fourth transistor; the active layer also includes: a fourth active portion, the fourth active portion is used to form a channel region of the fourth transistor; the auxiliary unit also includes: a third connecting portion, connected between two adjacent auxiliary units in the column direction, the positive projection of the third connecting portion on the substrate extends along the column direction; a sixth auxiliary portion, connected to the third connecting portion, the positive projection of the sixth auxiliary portion on the substrate extends along the row direction and covers the positive projection of the fourth active portion on the substrate.

[0014] In an exemplary embodiment of the present disclosure, the auxiliary unit further includes: a third connecting portion, connected between two adjacent auxiliary units in the column direction, and the orthographic projection of the third connecting portion on the substrate extends along the column direction; a first connecting portion, connected to a side of the second auxiliary portion in the column direction away from the first auxiliary portion, and in two adjacent auxiliary units in the column direction, the third connecting portion of the auxiliary unit in the upper row is connected to the first connecting portion of the auxiliary unit in the next row, and the orthographic projection of the first connecting portion on the substrate does not overlap with the orthographic projection of the first active portion on the substrate.

[0015] In an exemplary embodiment of the present disclosure, the first active portion includes a first sub-active portion and a second sub-active portion; the active layer also includes: a ninth active portion, connected between the first sub-active portion and the second sub-active portion; wherein the orthographic projection of the first connecting portion on the base substrate does not overlap with the orthographic projection of the ninth active portion on the base substrate.

[0016] In an exemplary embodiment of the present disclosure, the pixel driving circuit also includes a fourth transistor; the active layer also includes a fourth active portion, and the fourth active portion is used to form a channel region of the fourth transistor; the auxiliary unit also includes: a third connecting portion, connected between two adjacent auxiliary units in the column direction, and the positive projection of the third connecting portion on the substrate extends along the column direction; a sixth auxiliary portion, connected to the third connecting portion, and the positive projection of the sixth auxiliary portion on the substrate extends along the row direction and covers the positive projection of the fourth active portion on the substrate.

[0017] In an exemplary embodiment of the present disclosure, the pixel driving circuit further includes a first transistor, wherein the second electrode of the first transistor is connected to the gate of the driving transistor; the active layer further includes: a first active portion connected to one side of the second active portion, the first active portion being used to form a channel region of the first transistor; the auxiliary unit further includes: a second connecting portion connecting the first auxiliary portion and the second auxiliary portion respectively, the orthographic projection of the second connecting portion on the substrate extending along the row direction, and two adjacent auxiliary units in the row direction are connected via the second connecting portion; a third connecting portion connected between two adjacent auxiliary units in the column direction, the orthographic projection of the third connecting portion on the substrate extending along the column direction; a first connecting portion or a fourth auxiliary portion connected to a side of the second auxiliary portion in the column direction away from the first auxiliary portion, and of two adjacent auxiliary units in the column direction, the third connecting portion of the auxiliary unit in the upper row is connected to the first connecting portion or the fourth auxiliary portion of the auxiliary unit in the lower row, wherein the first connecting portion and the orthographic projection of the first active portion on the substrate do not overlap, and the orthographic projection of the fourth auxiliary portion on the substrate covers the orthographic projection of the first active portion on the substrate.

[0018] In an exemplary embodiment of the present disclosure, the display panel further includes: a first source-drain metal layer and / or a second source-drain metal layer, located on the side of the active layer away from the base substrate, the first source-drain metal layer and / or the second source-drain metal layer includes: a second power line and / or a first power line, the orthographic projection of which on the base substrate extends along the column direction, and the second power line and / or the first power line is connected to the auxiliary layer through a via in the non-display area of ​​the display panel.

[0019] In an exemplary embodiment of the present disclosure, the display panel further includes: a second conductive layer, located on a side of the active layer away from the base substrate, the second conductive layer including: a first initialization signal line, whose orthographic projection on the base substrate extends in a row direction; a second initialization signal line, whose orthographic projection on the base substrate extends in a row direction; a first source-drain metal layer, located on a side of the second conductive layer away from the base substrate, the first source-drain metal layer including: a third initialization signal line, whose orthographic projection on the base substrate extends in a column direction, the third initialization signal line is connected to the first initialization signal line through a first via; and / or a fourth initialization signal line, whose orthographic projection on the base substrate extends in a column direction, the fourth initialization signal line is connected to the second initialization signal line through a second via.

[0020] In an exemplary embodiment of the present disclosure, the display panel includes a first pixel column and a second pixel column alternately distributed in a row direction; the orthographic projection of the third initialization signal line on the base substrate is at least partially located in the area where the second pixel column is located, the orthographic projection of the fourth initialization signal line on the base substrate is located in the area where the first pixel column is located, and the first via and the second via are both located in the first pixel column.

[0021] In an exemplary embodiment of the present disclosure, the pixel driving circuit further includes a storage capacitor, a first electrode of the storage capacitor is connected to the gate of the driving transistor, and a second electrode is connected to the second power supply terminal; the display panel further includes: a first conductive layer, located on a side of the active layer away from the base substrate, the first conductive layer including: a second conductive block, the orthographic projection on the base substrate covers the orthographic projection of the third active portion on the base substrate, the second conductive block is used to form the first electrode of the storage capacitor; a second conductive layer, located on a side of the first conductive layer away from the base substrate, the second conductive layer including: a third conductive block, the orthographic projection on the base substrate is located on the orthographic projection of the second conductive block on the base substrate, the first conductive layer including: a third conductive block, the orthographic projection on the base substrate is located on the orthographic projection of the second conductive block on the base substrate, Three conductive blocks are used to form the second electrode of the storage capacitor; the first conductive block, the orthographic projection on the substrate is located on the orthographic projection of the tenth active part on the substrate; the first source-drain metal layer is located on the side of the second conductive layer away from the substrate, and the first source-drain metal layer includes: a first power transfer line, which is connected to the third conductive block through a via, and the power transfer line is also connected to the first conductive block in the adjacent pixel driving circuit through a via; a second power transfer line, which is connected to the third conductive block through a via, and the extension length of the orthographic projection of the substrate along the column direction is greater than the extension length of the first power transfer line along the column direction of the substrate.

[0022] In an exemplary embodiment of the present disclosure, the first power adapter line includes a first adapter portion, a second adapter portion and a third adapter portion, the orthographic projections of the first adapter portion and the third adapter portion on the base substrate both extend along the column direction, the orthographic projection of the second adapter portion on the base substrate extends along the row direction, and the first adapter portion and the third adapter portion are connected through the second adapter; the first adapter portion is connected to the third conductive block and the first power line through vias, respectively, and the third adapter portion is located in another pixel driving circuit adjacent in the row direction and is connected to the first conductive block through a via.

[0023] In an exemplary embodiment of the present disclosure, the auxiliary unit further includes: a second connecting portion, respectively connecting the first auxiliary portion and the second auxiliary portion, the orthographic projection of the second connecting portion on the base substrate extending along the row direction, and two adjacent auxiliary units in the row direction are connected through the second connecting portion; wherein the orthographic projection of the second adapter portion on the base substrate partially overlaps with the orthographic projection of the second connecting portion on the base substrate.

[0024] In an exemplary embodiment of the present disclosure, the first conductive layer further includes: a gate signal line, including a main extension portion and an additional portion, the main extension portion extends in the row direction of the orthographic projection of the substrate and covers the orthographic projection of the third sub-active portion on the substrate, the additional portion extends in the column direction of the orthographic projection of the substrate and covers the orthographic projection of the fourth sub-active portion on the substrate, and a partial structure of the gate signal line is used to form the gate of the second transistor; the second conductive layer further includes: a first initialization signal line, the orthographic projection of the substrate extends in the row direction; the first source-drain metal layer further includes: a third initialization signal line, the orthographic projection on the substrate extends in the column direction, the third initialization signal line is connected to the first initialization signal line through a via; wherein the third transfer portion and the main extension portion have a first overlapping portion in the orthographic projection of the substrate, the third initialization signal line and the additional portion have a second overlapping portion in the orthographic projection of the substrate, and the second auxiliary portion covers the first overlapping portion and the second overlapping portion in the orthographic projection of the substrate.

[0025] In an exemplary embodiment of the present disclosure, the pixel driving circuit also includes a fifth transistor, the gate of the fifth transistor is connected to the enable signal line, the first electrode is connected to the first power supply terminal, and the second electrode is connected to the second electrode of the driving transistor; the active layer also includes: a fifth active portion, used to form a channel region of the fifth transistor; a sixteenth active portion, connected between the fifth active portion and the third active portion, used to form the second electrode of the fifth transistor and the second electrode of the driving transistor; a seventeenth active portion, connected to the side of the fifth active portion away from the sixteenth active portion, the seventeenth active portion is used to form the first electrode of the fifth transistor; the first conductive layer also includes: an enable signal line, the positive projection of which on the substrate extends along the row direction and covers the positive projection of the fifth active portion on the substrate, and a partial structure of the enable signal line is used to form the gate of the fifth transistor; wherein the seventeenth active portion is connected to the first power line through a via.

[0026] In an exemplary embodiment of the present disclosure, the pixel driving circuit further includes a fourth transistor and a sixth transistor, the gate of the second transistor is connected to the gate signal terminal, and the second electrode is connected to the first electrode of the driving transistor; the gate of the fourth transistor is connected to the second reset signal terminal, the first electrode is connected to the second electrode of the driving transistor, and the second electrode is connected to the second electrode of the fifth transistor; the gate of the sixth transistor is connected to the enable signal terminal, the first electrode is connected to the first electrode of the driving transistor, and the second electrode is connected to the anode of the light-emitting device; the active layer further includes: a sixteenth active portion, connected to one side of the third active portion, and the sixteenth active portion is used to form the second electrode of the driving transistor and the anode of the fifth transistor a second electrode; a fourteenth active portion, connected to the second bridge portion located in the first source-drain metal layer through a via, the second bridge portion is further connected to the sixteenth active portion through a via, the fourteenth active portion is used to form the first electrode of the fourth transistor; a fourth active portion, connected to the fourteenth active portion, the fourth active portion is used to form the channel region of the fourth transistor; a fifteenth active portion, connected to a side of the fourth active portion away from the fourteenth active portion, the fifteenth active portion is used to form the second electrode of the fourth transistor; a fifth active portion is used to form the channel region of the fifth transistor; a sixth active portion is used to form the channel region of the sixth transistor; a seventh active portion is used to form the seventh transistor The first conductive layer further comprises: a first reset signal line, the orthographic projection of which on the substrate covers the orthographic projection of the first active portion on the substrate, and a partial structure of the first reset signal line is used to form the gate of the first transistor; a gate signal line, the orthographic projection of which on the substrate covers the orthographic projection of the second active portion on the substrate, and a partial structure of the gate signal line is used to form the gate of the second transistor; an enable signal line, the orthographic projection of which on the substrate covers the orthographic projection of the fifth active portion and the sixth active portion on the substrate, and a partial structure of the enable signal line is used to form the gate and partial structure of the fifth transistor Used to form the gate of the sixth transistor; a second reset signal line, the orthographic projection of which on the substrate covers the orthographic projections of the fourth active portion and the seventh active portion on the substrate, part of the structure of the second reset signal line is used to form the gate of the fourth transistor, and part of the structure is used to form the gate of the seventh transistor; wherein the orthographic projections of the first reset signal line, the gate signal line, the enable signal line and the second reset signal line on the substrate all extend in the row direction and are distributed in sequence in the column direction, and the orthographic projections of the gate signal line and the enable signal line on the substrate are located on both sides of the orthographic projection of the third active portion on the substrate.

[0027] In an exemplary embodiment of the present disclosure, the display panel includes a pixel driving circuit, the pixel driving circuit includes a second transistor and a driving transistor, and the first electrode of the second transistor is connected to the gate of the driving transistor; the display panel also includes: a base substrate, the base substrate includes an organic layer; an auxiliary layer, located on one side of the base substrate; an active layer, located on the side of the auxiliary layer away from the base substrate, the active layer includes: a second active portion, used to form a channel region of the second transistor; a third active portion, used to form a channel region of the driving transistor; wherein the orthographic projection of the auxiliary layer on the base substrate covers the orthographic projections of the second active portion and the third active portion on the base substrate.

[0028] In an exemplary embodiment of the present disclosure, the display panel includes a plurality of pixel driving circuits arrayed along row and column directions, the auxiliary layer includes a plurality of auxiliary units arrayed along row and column directions, and the auxiliary units are arranged corresponding to the pixel driving circuits; the second active portion includes a third sub-active portion and a fourth sub-active portion; the auxiliary unit includes: a first auxiliary portion, whose orthographic projection on the base substrate covers the orthographic projection of the third active portion on the base substrate; a second auxiliary portion, whose orthographic projection on the base substrate respectively covers the orthographic projections of the third sub-active portion and the fourth sub-active portion on the base substrate.

[0029] In an exemplary embodiment of the present disclosure, the pixel driving circuit also includes a first transistor, the second electrode of the first transistor is connected to the gate of the driving transistor; the active layer also includes: a first active portion, connected to one side of the second active portion, the first active portion being used to form a channel region of the first transistor; the auxiliary unit also includes: a second connecting portion, respectively connecting the first auxiliary portion and the second auxiliary portion, the orthographic projection of the second connecting portion on the base substrate extending along the row direction, and two adjacent auxiliary units in the row direction are connected through the second connecting portion; a fourth auxiliary portion, connected to the second auxiliary portion, the orthographic projection of the fourth auxiliary portion on the base substrate covering the orthographic projection of the first active portion on the base substrate.

[0030] According to another aspect of the present disclosure, a display device is provided, comprising the display panel described in any embodiment of the present disclosure.

[0031] The display panel provided by the present disclosure is provided with an auxiliary layer at the bottom of the active layer, the auxiliary layer is connected to the first signal, and the orthographic projection of the auxiliary layer on the base substrate covers the orthographic projection of the second active part on the base substrate, that is, the auxiliary layer forms a structure covering the channel region of the second transistor at the bottom of the active layer. This can prevent the free charges in the bottom layer from diffusing to the channel region of the second transistor at high temperature, thereby avoiding the free charges from affecting the characteristics of the second transistor, thereby improving the display abnormality problem of the display panel caused by the diffusion of free charges after high-temperature reliability testing and copper rod friction testing.

[0032] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0034] FIG1 is a schematic diagram of a circuit structure of a pixel driving circuit in a display panel according to an embodiment of the present disclosure;

[0035] FIG2 is a timing diagram of each node in a driving method of the pixel driving circuit in FIG1 ;

[0036] FIG3 is a structural diagram of a display panel according to an embodiment of the present disclosure;

[0037] FIG4 is a structural diagram of the auxiliary layer in FIG3 ;

[0038] FIG5 is a structural diagram of the active layer in FIG3;

[0039] FIG6 is a stacking layout of the auxiliary layer and the active layer in FIG3;

[0040] FIG7 is a schematic diagram showing the connection of the auxiliary layers in row and column directions in FIG3 ;

[0041] FIG8 is a structural diagram of the auxiliary layer in FIG3 according to another embodiment;

[0042] FIG9 is a schematic diagram of an auxiliary layer blocking charges according to an embodiment of the present disclosure;

[0043] FIG10 is a structural diagram of a display panel according to another embodiment of the present disclosure;

[0044] FIG11 is a structural diagram of the auxiliary layer in FIG10 ;

[0045] FIG12 is a stacking layout of the auxiliary layer and the active layer in FIG10;

[0046] FIG13 is a stacked layout of the auxiliary layer, the active layer, and the second conductive layer in FIG10;

[0047] FIG14 is a structural diagram of a display panel according to another embodiment of the present disclosure;

[0048] FIG15 is a structural diagram of the auxiliary layer in FIG14;

[0049] FIG16 is a stacked layout of the auxiliary layer and the active layer in FIG14 ;

[0050] FIG17 is a schematic diagram showing the connection of the auxiliary layers in row and column directions in FIG14;

[0051] FIG18 is a structural diagram of a display panel according to another embodiment of the present disclosure;

[0052] FIG19 is a structural diagram of the auxiliary layer in FIG18 ;

[0053] FIG20 is a stacking layout of the auxiliary layer and the active layer in FIG18;

[0054] FIG21 is a structural diagram of a display panel according to another embodiment of the present disclosure;

[0055] FIG22 is a structural diagram of the auxiliary layer in FIG21;

[0056] FIG23 is a stacking layout of the auxiliary layer and the active layer in FIG21;

[0057] FIG24 is a stacked layout of the auxiliary layer, the active layer, and the second conductive layer in FIG21;

[0058] 25 to 34 are diagrams of stacking the auxiliary layer and the active layer according to other embodiments of the present disclosure;

[0059] FIG35 is a structural diagram of an auxiliary layer according to another embodiment of the present disclosure;

[0060] FIG36 is a structural diagram of the first conductive layer in FIG3 ;

[0061] FIG37 is a structural diagram of the second conductive layer in FIG3;

[0062] FIG38 is a structural diagram of the first source / drain metal layer in FIG3 ;

[0063] FIG39 is a structural layout diagram of the second source / drain metal layer in FIG3 ;

[0064] FIG40 is a stacked layout diagram of the auxiliary layer, the active layer, and the first source / drain metal layer in FIG3 ;

[0065] FIG41 is a stacked layout diagram of the auxiliary layer, the first conductive layer, and the first source / drain metal layer in FIG3 ;

[0066] FIG42 is a cross-sectional view along the AA direction in FIG3 . DETAILED DESCRIPTION

[0067] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art. Like reference numerals in the figures represent identical or similar structures, and thus their detailed descriptions will be omitted. Furthermore, the figures are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.

[0068] FIG1 is a schematic diagram of the circuit structure of a pixel driving circuit in a display panel according to an embodiment of the present disclosure. The pixel driving circuit may include: a first transistor T1, a second transistor T2, a driving transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a storage capacitor C. The first electrode of the first transistor T1 is connected to the first initial signal terminal Vinit1, the second electrode is connected to the first node N1, and the gate is connected to the first reset signal terminal Reset(n); the first electrode of the second transistor T2 is connected to the gate of the driving transistor T3, the second electrode is connected to the first electrode of the driving transistor, and the gate is connected to the gate signal terminal Gate; the gate of the driving transistor T3 is connected to the first node N1; the second electrode of the fourth transistor T4 is connected to the data signal terminal V Data, the first electrode is connected to the second electrode of the driving transistor T3, and the gate is connected to the gate signal terminal Gate; the second electrode of the fifth transistor T5 is connected to the second electrode of the driving transistor T3, the first electrode is connected to the first power supply terminal VDD, and the gate is connected to the enable signal terminal EM; the first electrode of the sixth transistor T6 is connected to the first electrode of the driving transistor T3, and the gate is connected to the enable signal terminal EM; the first electrode of the seventh transistor T7 is connected to the second initial signal terminal Vinit2, the second electrode is connected to the second electrode of the sixth transistor T6, and the gate is connected to the second reset signal terminal Reset(n+1). The first electrode of the storage capacitor C is connected to the first node N1, and the second electrode is connected to the first power supply terminal VDD. The pixel driving circuit can be connected to a light-emitting unit OLED for driving the light-emitting unit OLED to emit light. The light-emitting unit OLED can be connected between the second electrode of the sixth transistor T6 and the second power supply terminal VSS. Among them, each transistor disclosed in the present invention can be a P-type transistor. For example, the first transistor T1 to the seventh transistor T7 can all be P-type low-temperature polycrystalline silicon transistors. P-type low-temperature polycrystalline silicon transistors have high carrier mobility, which is conducive to realizing display panels with high resolution, high response speed, high pixel density, and high aperture ratio. The first initial signal terminal Vinit1 and the second initial signal terminal Vinit2 can output the same or different voltage signals according to actual conditions.

[0069] It should be noted that the transistors used in each embodiment of the present disclosure can be thin film transistors, field effect transistors, or other devices with the same characteristics. In this specification, the first electrode can be a drain electrode and the second electrode can be a source electrode, or the first electrode can be a source electrode and the second electrode can be a drain electrode.

[0070] FIG2 is a timing diagram of each node in a driving method of the pixel driving circuit in FIG1. ​​As shown in FIG2, in the figure, Gate represents the timing of the gate signal terminal Gate, Re1 represents the timing of the first reset signal terminal Reset(n), Re2 represents the timing of the second reset signal terminal Reset(n+1), EM represents the timing of the enable signal terminal EM, and Da represents the timing of the data signal terminal V Data The driving method of the pixel driving circuit may include a first reset phase t1, a compensation phase t2, a second reset phase t3, and a light emitting phase t4. In the first reset phase t1: the first reset signal terminal Reset(n) outputs a low-level signal, the first transistor T1 is turned on, and the first initial signal terminal Vinit1 inputs the first initial signal to the first node N1. In the compensation phase t2: the gate signal terminal Gate outputs a low-level signal, the second transistor T2 and the fourth transistor T4 are turned on, and the data signal terminal V DataA data signal is output to write a voltage Vdata+Vth (i.e., the sum of the voltages Vdata and Vth) to the first node N1, where Vdata is the voltage of the drive signal and Vth is the threshold voltage of the drive transistor T3. During the second reset phase t3, the second reset signal terminal Reset(n+1) outputs a low-level signal, turning on the seventh transistor T7. The second initial signal terminal Vinit2 inputs a second initial signal to the second electrode of the sixth transistor T6. During the light-emitting phase t4, the enable signal terminal EM outputs a low-level signal, turning on the sixth transistor T6 and the fifth transistor T5. The drive transistor T3, under the action of the voltage Vdata+Vth stored in the storage capacitor C, provides a drive current, causing the light-emitting device OLED to emit light.

[0071] According to the output current formula of the driving transistor I=(μWCox / 2L)(Vgs-Vth) 2 , where μ is the carrier mobility; Cox is the gate storage capacitance per unit area, W is the width of the driver transistor channel, L is the length of the driver transistor channel, Vgs is the gate-source voltage difference of the driver transistor, and Vth is the threshold voltage of the driver transistor. The output current of the driver transistor in the pixel driving circuit of the present disclosure is I = (μWCox / 2L)(Vdata+Vth-Vdd-Vth) 2 The pixel driving circuit can avoid the influence of the threshold voltage change of the driving transistor on its output current.

[0072] In the related art, the luminous efficiency of light-emitting devices is getting higher and higher to meet the demand for longer life and lower power consumption of display devices. However, the excessively high luminous efficiency makes it more sensitive to changes in TFT characteristics, which will affect the TFT characteristics in the panel after the reliability test. Because the luminous efficiency of each device is different, after the reliability test or the copper rod friction test, the charge moves into the active layer Poly, causing the panel to have color deviation problems. In addition, when users use terminal products such as mobile phones, the charge on their hands will accumulate on the panel. If the screen is used for a long time and at a high frequency, the charge will affect the TFT characteristics, resulting in local color deviation problems in places where static electricity accumulates. The display panel disclosed in the present invention is used to solve the above problems.

[0073] The display panel provided by the present disclosure may include a plurality of pixel driving circuits distributed in an array along the row direction X and the column direction Y. The pixel driving circuit is used to drive the light-emitting device to emit light. The row direction X and the column direction Y intersect. The pixel driving circuit may include a second transistor T2 and a driving transistor T3. The first electrode of the second transistor T2 is connected to the gate of the driving transistor T3. The pixel driving circuit may be as shown in FIG1. ​​Of course, in other exemplary embodiments, the pixel driving circuit in the display panel may also be other structures, such as 8T1C, 9T1C, etc. FIG3 is a structural layout diagram of a display panel according to an embodiment of the present disclosure. FIG4 is a structural layout diagram of the auxiliary layer in FIG3. FIG5 is a structural layout diagram of the active layer in FIG3. FIG6 is a stacked layout diagram of the auxiliary layer and the active layer in FIG3. FIG7 is a schematic diagram of the connection of the auxiliary layer in the row and column directions in FIG3. FIG8 is a structural layout diagram of the auxiliary layer in FIG3 of another embodiment. As shown in FIG3 to FIG8, the display panel may also include a base substrate, an auxiliary layer BSM and an active layer Poly, wherein the auxiliary layer BSM is located on one side of the base substrate, and the auxiliary layer BSM is located on one side of the base substrate. The auxiliary layer BSM can be connected to the first signal or not; the active layer Poly is located on the side of the auxiliary layer BSM away from the base substrate, and the active layer Poly includes a second active portion POL2 and a third active portion POL3. The second active portion POL2 is used to form a channel region of the second transistor T2, and the third active portion POL3 is used to form a channel region of the driving transistor T3; the orthographic projection of the auxiliary layer BSM on the base substrate covers the orthographic projections of the second active portion POL2 and the third active portion POL3 on the base substrate.

[0074] The display panel provided by the present disclosure provides an auxiliary layer BSM at the bottom of the active layer Poly, and the orthographic projection of the auxiliary layer BSM on the base substrate covers the orthographic projection of the second active portion POL2 on the base substrate. That is, the auxiliary layer BSM forms a structure at the bottom of the active layer Poly that covers the channel region of the second transistor T2. This can prevent free charges in the bottom layer from diffusing into the channel region of the second transistor T2 at high temperatures, thereby reducing or even preventing the free charges from affecting the characteristics of the second transistor T2. This improves the display abnormality problem of the display panel caused by the diffusion of free charges after high-temperature reliability testing and copper rod friction testing.

[0075] The substrate disclosed herein can be a flexible substrate, such as a flexible substrate made of PI material. A large amount of free charge exists in the flexible substrate. When the temperature rises, the free charge diffuses into the channel region of the transistor, causing the threshold voltage of the transistor to drift positively. Taking the pixel drive circuit shown in FIG1 as an example, after the threshold voltage of the second transistor T2 drifts positively, the voltage of the first node N1 decreases, thereby decreasing the gate-source voltage of the driving transistor T3. This increases the drive current provided by the pixel drive circuit, causing the screen to be brighter than before the reliability test. Furthermore, because the G sub-pixel has the highest luminous efficiency, the brighter display after the friction test is usually manifested as a greenish tint after the test. This phenomenon is more easily perceived by the human eye when displaying at low grayscales, i.e., it is more obvious at low grayscales.

[0076] The orthographic projection of a certain structure A described in the present disclosure on the substrate covers the orthographic projection of another structure B on the substrate. It can be understood that the outline of the projection of structure B on the substrate plane is completely inside the outline of the projection of structure A in the same plane. For the purposes of the present disclosure, the orthographic projection of the auxiliary layer BSM on the substrate covers the orthographic projection of the second active portion POL2 on the substrate, that is, the outline of the orthographic projection of the second active portion POL2 on the substrate is completely inside the outline of the orthographic projection of the auxiliary layer BSM on the substrate. In this way, it is equivalent to the auxiliary layer BSM forming a structure covering the channel region of the second transistor T2 at the bottom of the active layer Poly. As shown in Figure 9, the free charge will be intercepted by the auxiliary layer BSM and will not diffuse into the active layer Poly, thereby ensuring the channel stability of the second transistor T2 and avoiding the problem of positive threshold voltage drift of the second transistor T2. This can reduce the characteristic difference of the transistor after the high-temperature reliability test, thereby improving the display abnormality problem of the display panel after the high-temperature reliability test.

[0077] For example, the orthographic projection of the auxiliary layer BSM on the base substrate covers the orthographic projection of the second active portion POL2 on the base substrate, which is equivalent to having an auxiliary layer structure below the second active portion POL2 that is opposite to the second active portion POL2 and has a larger area than the second active portion POL2, that is, the boundary of the auxiliary layer structure must exceed the boundary of the second active portion POL2. Obviously, the auxiliary layer structure can block the free charges from diffusing toward the second active portion POL2, thereby reducing the characteristic difference of the second transistor T2 before and after the high-temperature reliability test, and avoiding display abnormality problems after the reliability test.

[0078] It is worth noting that the auxiliary layer BSM of the present invention can block free charges from entering the channel region of the transistor when it is connected to the first signal or not. When the auxiliary layer BSM is not connected to the first signal, because the auxiliary layer BSM has no potential, it will not form a parasitic effect with other conductors, and therefore will not affect the transistor. When connected to the first signal, the auxiliary layer BSM forms an equipotential surface, which can improve the blocking effect for free charges; secondly, since the threshold voltage of the transistor in the pixel circuit will drift after a long period of operation, by setting an auxiliary layer and connecting it to a voltage signal, the threshold voltage of the transistor can also be corrected and restored, thereby improving the display effect of the display panel. The first signal can be a constant voltage signal. For example, the first signal can be a voltage signal provided by the first power supply terminal VDD in Figure 1, or it can be an initialization signal provided by the first initial signal terminal Vinit1 or the second initial signal terminal Vinit2 in Figure 1.

[0079] In addition, the auxiliary layer BSM described in the present disclosure can be a metal auxiliary layer formed of a metal material, such as at least one of silver, copper, molybdenum, titanium, and aluminum; it can also be a transparent conductive layer, such as at least one of indium tin oxide (ITO), cadmium stannate (TCO), graphene, metal nanowires, and carbon nanotubes; or it can be an auxiliary layer formed by converting a semiconductor material layer into a conductor, such as doped polycrystalline silicon, amorphous silicon, and other semiconductor materials; or it can be a semiconductor material, such as single crystal silicon, amorphous silicon, polycrystalline silicon, and microcrystalline silicon. The present disclosure does not specifically limit the material of the auxiliary layer BSM.

[0080] The present disclosure will be further described below with reference to the accompanying drawings.

[0081] As shown in Figures 3 and 5, the active layer Poly may include a first active portion POL1 to a nineteenth active portion POL19. The first active portion POL1 may be used to form the channel region of the first transistor T1, the second active portion POL2 may be used to form the channel region of the second transistor T2, the third active portion POL3 may be used to form the channel region of the driving transistor T3, and the fourth active portion POL4 to the seventh active portion POL7 may be used to form the channel region of the fourth transistor T4 to the channel region of the seventh transistor T7, respectively. The active layer Poly of the present disclosure may be formed around the third active portion POL3 to form each transistor in the pixel driving circuit. The active layer Poly of the present disclosure may be formed of polycrystalline silicon semiconductor material. Accordingly, the transistors in the display panel of the present disclosure may be P-type low-temperature polycrystalline silicon thin film transistors.

[0082] In this exemplary embodiment, the first transistor T1 and the second transistor T2 may have a dual-gate structure. Therefore, the first active portion POL1 may include a first sub-active portion POL1-1 and a second sub-active portion POL1-2. The first sub-active portion POL1-1 and the second sub-active portion POL1-2 are respectively used to form two channel regions of the first transistor T1. The first sub-active portion POL1-1 and the second sub-active portion POL1-2 are connected via a ninth active portion POL9. That is, the ninth active portion POL9 is used to connect the dual channels of the first transistor T1, thereby forming a conductor structure T1M between the dual channels of the first transistor T1. The second active portion POL2 may include a third sub-active portion POL2-3 and a fourth sub-active portion POL2-4. The third sub-active portion POL2-3 and the fourth sub-active portion POL2-4 are respectively used to form two channel regions of the second transistor T2. The third sub-active portion POL2-3 and the fourth sub-active portion POL2-4 may be connected via a tenth active portion POL10. That is, the tenth active portion POL10 is used to connect the dual channels of the second transistor T2, thereby forming a conductive structure T2M between the dual channels of the second transistor T2.

[0083] The eleventh active portion POL11 is connected between the first sub-active portion POL1-1 and the fourth sub-active portion POL2-4 and can be used to form the second electrode of the first transistor T1 and the first electrode of the second transistor T2. The eleventh active portion POL11 can be connected to the first bridge portion 31 of the first source-drain metal layer SD1 through a via, thereby connecting the second electrode of the first transistor T1 and the first electrode of the second transistor T2 to the gate of the driving transistor T3 through the first bridge portion 31.

[0084] The twelfth active portion POL12 may be used to form the second electrode of the first transistor T1. In an exemplary embodiment, the display panel may include first and second pixel columns P1 and P2 alternately arranged in the row direction X. In each pixel driving circuit of the first pixel column P1, the twelfth active portion POL12 may be connected to the third initialization signal line Vinit3 of the first source-drain metal layer SD1 via a via, thereby connecting the twelfth active portion POL12 to the first initialization signal line Vinit1 via the third initialization signal line Vinit3. In each pixel driving circuit of the second pixel column P2, the twelfth active portion POL12 may be connected to the third bridge portion 33 of the first source-drain metal layer SD1 via a via, thereby connecting the twelfth active portion POL12 to the first initialization signal line Vinit1 via the third bridge portion 33.

[0085] The thirteenth active portion POL13 is connected between the third sub-active portion POL2 - 3 and the third active portion POL3 , and may be used to form the second electrode of the second transistor T2 , the first electrode of the sixth transistor T6 , and the first electrode of the driving transistor T3 .

[0086] The sixteenth active portion POL16 is connected between the fifth active portion POL5 and the third active portion POL3 , and the sixteenth active portion POL16 may be used to form the second electrode of the driving transistor T3 and the second electrode of the fifth transistor T5 .

[0087] The seventeenth active portion POL17 is connected to a side of the fifth active portion POL5 away from the sixteenth active portion POL16. The seventeenth active portion POL17 can be used to form the first electrode of the fifth transistor T5. The seventeenth active portion POL17 located in each pixel driving circuit of the first pixel column P1 can be connected to the first power transfer line VDDL1 of the first source-drain metal layer SD1 through a via, thereby connecting to the first power line VDD of the second source-drain metal layer SD2 through the first power transfer line VDDL1. The seventeenth active portion POL17 located in the second pixel column P2 can be connected to the second power transfer line VDDL2 of the first source-drain metal layer SD1 through a via, thereby connecting to the first power line VDD of the second source-drain metal layer SD2 through the second power transfer line VDDL2. Thus, the first electrode of the fifth transistor T5 is connected to the first power terminal via the first power transfer line VDDL1 and the second power transfer line VDDL2, respectively.

[0088] The fourteenth active portion POL14 and the fifteenth active portion POL15 are connected to both sides of the fourth active portion POL4. The fourteenth active portion POL14 can be used to form the first electrode of the fourth transistor T4, and the fifteenth active portion POL15 can be used to form the second electrode of the fourth transistor T4. The fourteenth active portion POL14 can be connected to the second bridge portion 32 located on the first source-drain metal layer SD1 through a via, thereby connecting the first electrode of the fourth transistor T4 to the second electrode of the driving transistor T3 through the second bridge portion 32. The fifteenth active portion POL15 can be connected to the data transfer portion VdataL located on the first source-drain metal layer SD1 through a via, thereby connecting to the data signal line Vdata of the second source-drain metal layer SD2 through the data transfer portion VdataL, thereby connecting the second electrode of the fourth transistor T4 to the data signal terminal.

[0089] The eighteenth active portion POL18 is connected between the sixth active portion POL6 and the seventh active portion POL7. The eighteenth active portion POL18 can be used to form the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7. The eighteenth active portion POL18 can be connected to the anode transition portion 35 of the first source-drain metal layer SD1 through a via hole, so as to connect the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7 to the anode of the light-emitting device through the anode transition portion 35.

[0090] The nineteenth active portion POL19 is connected to the other side of the seventh active portion POL7. The nineteenth active portion POL19 can be used to form the first electrode of the seventh transistor T7. The nineteenth active portion POL19 can be connected to the second initialization signal line Vinit2 of the second conductive layer Gate2 through a via hole to connect the first electrode of the seventh transistor T7 to the second initial signal end.

[0091] As shown in FIG. 3 and FIG. 4 , in an exemplary embodiment, the auxiliary layer BSM may include a plurality of auxiliary units BSM0 , which are arrayed in row and column directions, and one auxiliary unit BSM0 is correspondingly provided for one pixel driving circuit.

[0092] As shown in FIG4 , the auxiliary unit BSM0 may include a second auxiliary portion B2. The second auxiliary portion B2 may be disposed corresponding to the second active portion POL2, that is, disposed below the second active portion POL2. As described above, in the display panel of the present disclosure, the second transistor T2 may have a dual-gate structure. Thus, as shown in FIG6 , the orthographic projection of the second auxiliary portion B2 on the base substrate may overlap the orthographic projections of the third sub-active portion POL2-3 and the fourth sub-active portion POL2-4 on the base substrate. Thus, the second auxiliary portion B2 isolates the channel region of the second transistor T2 from free charges in the underlying layer. Furthermore, in this exemplary embodiment, the orthographic projection of the second auxiliary portion B2 on the base substrate may not overlap with the orthographic projection of the tenth active portion POL10 on the base substrate, meaning that the second auxiliary portion B2 does not block the tenth active portion POL10. In other words, the auxiliary unit BSM0 only blocks the channel region of the second transistor T2 and does not block the conductive structure T2M between the dual channels of the second transistor T2. For example, as shown in FIG. 4 , the second auxiliary portion B2 may be provided with a notch B0 , and the orthographic projection of the tenth active portion POL10 on the base substrate is located within the orthographic projection of the notch B0 on ​​the base substrate, so that the second auxiliary portion B2 does not block the tenth active portion POL10 .

[0093] As shown in Figures 4 and 6, in this exemplary embodiment, the auxiliary unit BSM0 may further include a first auxiliary portion B1, which is connected to the second auxiliary portion B2. The first auxiliary portion B1 is arranged corresponding to the third active portion POL3, and the orthographic projection of the first auxiliary portion B1 on the base substrate can cover the orthographic projection of the third active portion POL3 on the base substrate, that is, the auxiliary layer BSM is also provided with a metal isolation structure at a position corresponding to the channel region of the driving transistor T3 to shield the channel region of the driving transistor T3. In this way, the auxiliary layer BSM can prevent the charge generated by friction from entering the third active portion POL3, thereby avoiding the problem of glowing after friction with the copper rod and after high-temperature reliability testing.

[0094] It should be understood that the orthographic projection of a certain structure A described in the present disclosure on the substrate covers the orthographic projection of another structure B on the substrate. It can be understood that the outline of the projection of structure B on the plane of the substrate is completely inside the outline of the projection of structure A in the same plane.

[0095] As shown in Figure 4, in an exemplary embodiment, the auxiliary unit BSM0 may further include a first connection portion B11 to a third connection portion B13, the first connection portion B11 is connected to a side of the second auxiliary portion B2 away from the first auxiliary portion B1 in the column direction, and the orthographic projection of the first connection portion B11 on the base substrate does not overlap with the orthographic projection of the first active portion POL1 on the base substrate, that is, the area covered by the orthographic projection of the first connection portion B11 on the base substrate avoids the area covered by the orthographic projection of the first active portion POL1 on the base substrate. In other words, there is no auxiliary layer structure below the first active portion POL1.

[0096] The second connection portion B12 is connected to one side of the first auxiliary portion B1 in the row direction, and its orthographic projection on the substrate can extend along the row direction. The third connection portion B13 is connected to the side of the first auxiliary portion B1 in the column direction away from the second auxiliary portion B2, and its orthographic projection on the substrate can extend along the column direction. As shown in FIG7 , in two adjacent auxiliary cells BSM0 in the row direction, the second connection portion B12 in one auxiliary cell BSM0 connects to the first auxiliary portion B1 in the other auxiliary cell BSM0, thereby connecting the two adjacent auxiliary cells BSM0 in the row direction via the second connection portion B12. In two adjacent auxiliary cells BSM0 in the column direction, the third connection portion B13 in the previous row connects to the first connection portion B11 in the next row, thereby connecting the two adjacent auxiliary cells BSM0 in the column direction via the third connection portion B13. This results in the auxiliary cells BSM0 in the auxiliary layer BSM forming a crisscross grid structure. This grid structure can reduce the IR drop of the first signal connected to it, thereby minimizing voltage drop losses. Furthermore, the auxiliary layer BSM forms an equipotential surface in a grid structure, which can improve the auxiliary effect on the free charges of the active layer and is beneficial to the stabilization of the characteristics of each transistor in the pixel driving circuit.

[0097] In addition, in an exemplary embodiment, the auxiliary layer BSM may not be connected to the first signal. For example, as shown in FIG8 , the auxiliary unit BSM0 may not include a connecting portion, that is, each auxiliary portion in the auxiliary unit BSM may be an isolated structure. For example, in FIG8 , the first auxiliary portion B1 and the second auxiliary portion B2 are not connected, and the two adjacent auxiliary units BSM0 are also not connected. Each independent auxiliary portion can also block free charge from entering the transistor at the corresponding position. It should be understood that FIG8 only uses the example of providing an auxiliary portion below the second transistor T2 and the driving transistor T3 as an example for illustrative purposes. The auxiliary unit BSM0 may also include more isolated auxiliary portions to shield each transistor, which will not be expanded here one by one.

[0098] A certain structure A described in the present disclosure extends along direction B, which means that A may include a main part and a secondary part connected to the main part, the main part is a line, a line segment or a strip-shaped body, the main part extends along direction B, and the length of the main part extending along direction B is greater than the length of the secondary part extending along other directions.

[0099] Figure 10 is a structural layout diagram of a display panel according to another embodiment of the present disclosure. Figure 11 is a structural layout diagram of the auxiliary layer in Figure 10. Figure 12 is a stacking layout diagram of the auxiliary layer and active layer in Figure 10. Figure 13 is a stacking layout diagram of the auxiliary layer, active layer, and second conductive layer in Figure 10. The active layer Poly to the second source / drain metal layer SD2 in the display panel shown in Figure 10 correspond to all the features of the active layer Poly to the second source / drain metal layer SD2 in the display panel shown in Figure 3. It should be understood that the via shown in Figure 13 is an insulating layer opened on the second conductive layer Gate2. The metal structure of the Gate2 layer corresponding to the via position is connected to the corresponding structure of the first source / drain metal layer SD1 through the via.

[0100] On the basis of the above embodiments, as shown in Figures 10 and 11, in this exemplary embodiment, the second auxiliary portion B2 may include a first sub-auxiliary portion B21 and a second sub-auxiliary portion B22, the orthographic projection of the first sub-auxiliary portion B21 on the substrate covers the orthographic projection of the third sub-active portion POL2-3 and the fourth sub-active portion POL2-4 on the substrate, and the orthographic projection of the second sub-auxiliary portion B22 on the substrate covers the orthographic projection of the tenth active portion POL10 on the substrate, that is, a corresponding auxiliary portion is also provided under the conductive structure T2M between the dual channels of the second transistor T2 for charge blocking, so that the second auxiliary portion B2 in this exemplary embodiment not only blocks the dual channels of the second transistor T2, but also blocks the conductive structure T2M between the dual channels of the second transistor T2. In this way, the auxiliary unit BSM0 can further block charges from entering the conductive structure T2M between the two channels connecting the second transistor T2. Because the second transistor T2 is turned on during the data writing stage, it has a greater impact on the driving current provided by the driving circuit. Therefore, this exemplary embodiment can further improve the overall stability of the second transistor T2 by setting the second sub-auxiliary part B22, and avoid its characteristic deviation before and after the high-temperature reliability test and the copper rod friction test. This can further ensure that the display panel does not have color deviation problems before and after the test.

[0101] Further, as shown in Figure 13, in an exemplary embodiment, the second conductive layer Gate2 is generally provided with a first conductive block 21, which is located above the tenth active part POL10, and the first conductive block 21 is connected to the first power line VDD of the second source-drain metal layer SD2 through the third via H3 of the interlayer dielectric layer to provide a stable voltage source for the first conductive block 21 through the first power line VDD, so that the first conductive block 21 can stabilize the tenth active part POL10. On this basis, the orthographic projection of the second sub-auxiliary part B22 on the base substrate also covers the orthographic projection of the third via H3 on the base substrate, that is, the area covered by the orthographic projection of the third via H3 on the base substrate is completely located within the area covered by the orthographic projection of the second sub-auxiliary part B22 on the base substrate. This ensures that there is a flat auxiliary layer structure below the third via H3, so that there is no thickness step difference below the third via H3, thereby avoiding deformation of the third via H3. If the third via H3 is deformed, it will cause a capacitance change between the auxiliary layer BSM and the second conductive layer Gate2 at the conductor structure T2M of the second transistor T2. Therefore, when the third via H3 is deformed due to process fluctuations, it will cause display stripes between different sub-pixels due to the capacitance difference between the conductor structure T2M of the second transistor T2 and the second conductive layer Gate2. In this exemplary embodiment, the area covered by the orthographic projection of the third via H3 on the base substrate is completely located within the area covered by the orthographic projection of the second sub-auxiliary part B22 on the base substrate, which can avoid the occurrence of Mura-type display defects between different sub-pixels due to the different capacitances of the auxiliary layer BSM and the second conductive layer Gate2 at the tenth active part POL10.

[0102] Figure 14 is a structural layout diagram of a display panel according to another embodiment of the present disclosure. Figure 15 is a structural layout diagram of the auxiliary layer in Figure 14. Figure 16 is a stacking layout diagram of the auxiliary layer and active layer in Figure 14. Figure 17 is a schematic diagram of the row and column connections of the auxiliary layer in Figure 14. The active layer Poly to the second source and drain metal layer SD2 in the display panel shown in Figure 14 have all the features of the active layer Poly to the second source and drain metal layer SD2 in the display panel shown in Figure 3.

[0103] On the basis of the above embodiments, as shown in Figures 14, 15 and 17, the difference from the layout structure shown in Figure 3 is that in this exemplary embodiment, the auxiliary unit BSM0 may further include a fourth auxiliary portion B4 and is arranged corresponding to the first active portion POL1, the fourth auxiliary portion B4 is connected to the second auxiliary portion B2, and the orthographic projection of the fourth auxiliary portion B4 on the base substrate can cover the orthographic projection of the first active portion POL1 on the base substrate, that is, the auxiliary unit BSM0 in this exemplary embodiment does not have the first connecting portion B11. Under this structure, in two adjacent auxiliary units BSM0 in the column direction, the third connecting portion B13 of the upper row is connected to the fourth auxiliary portion B4 of the lower row, so that the auxiliary units BSM0 in the same column are connected in sequence. At the same time, the auxiliary units BSM0 in the same row are also connected in sequence, so that in the layout structure shown in Figure 14, the auxiliary layer BSM also has a criss-cross grid structure.

[0104] As described above, the first active portion POL1 may include a first sub-active portion POL1-1 and a second sub-active portion POL1-2. As shown in Figures 14 and 16, in this exemplary embodiment, the orthographic projection of the fourth auxiliary portion B4 on the base substrate may specifically cover the orthographic projections of the first sub-active portion POL1-1 and the second sub-active portion POL1-2 on the base substrate, respectively. That is, the area covered by the orthographic projections of the first sub-active portion POL1-1 and the second sub-active portion POL1-2 on the base substrate is completely located within the area covered by the orthographic projection of the fourth auxiliary portion B4 on the base substrate. As a result, the auxiliary layer BSM shields the first active portion POL1 through the fourth auxiliary portion B4, thereby preventing free charges from entering the first active portion POL1, thereby ensuring that the characteristics of the first transistor T1 remain stable before and after the high-temperature reliability test and the copper rod friction test. It can be known that after the free charges enter the channel region of the first transistor T1, the threshold voltage of the first transistor T1 will be forward-biased. The forward-biased threshold voltage of the first transistor T1 will also cause the driving current to increase. The increased driving current will cause the display brightness to be brighter than before the reliability test. Therefore, this exemplary embodiment can maintain the stability of the characteristics of the first transistor T1 by providing the fourth auxiliary part B4 in the auxiliary layer BSM, thereby further avoiding display defects such as the display being too bright on the display panel before and after the high-temperature reliability test.

[0105] Based on the above embodiment, Figure 18 is a structural layout diagram of a display panel according to another embodiment of the present disclosure, Figure 19 is a structural layout diagram of the auxiliary layer in Figure 18, and Figure 20 is a stacking layout diagram of the auxiliary layer and active layer in Figure 18. The active layer Poly to the second source and drain metal layer SD2 in the display panel shown in Figure 18 correspond to all the features of the active layer Poly to the second source and drain metal layer SD2 in the display panel shown in Figure 3.

[0106] As shown in Figures 18 to 20 , in this exemplary embodiment, unlike the layout structure shown in Figure 14 , the orthographic projection of the fourth auxiliary portion B4 on the base substrate also covers the orthographic projection of the ninth active portion POL9 on the base substrate. As described above, the first transistor T1 is a dual-channel transistor, and variations in the characteristics of the first transistor T1 can cause variations in the drive current. In this exemplary embodiment, the area covered by the orthographic projection of the ninth active portion POL9 on the base substrate is located within the area covered by the orthographic projection of the fourth auxiliary portion B4 on the base substrate. Consequently, the fourth auxiliary portion B4 also shields the ninth active portion POL9, and thus also shields the conductive structure T1M between the dual channels of the first transistor T1. Consequently, the fourth auxiliary portion B4 can also block free charge from the underlying layer from entering the conductive structure T1M between the dual channels of the first transistor T1. This further helps prevent threshold voltage drift of the first transistor T1, maintaining the stability of the characteristics of the first transistor T1 and preventing the display panel from displaying too brightly before and after high-temperature reliability testing and copper bar friction testing.

[0107] Based on the above embodiment, Figure 21 is a structural layout diagram of a display panel according to another embodiment of the present disclosure. Figure 22 is a structural layout diagram of the auxiliary layer in Figure 21. Figure 23 is a stacking layout diagram of the auxiliary layer and active layer in Figure 21. Figure 24 is a stacking layout diagram of the auxiliary layer, active layer, and second conductive layer in Figure 21. The active layer Poly to the second source and drain metal layer SD2 in the display panel shown in Figure 21 have all the features of the active layer Poly to the second source and drain metal layer SD2 in the display panel shown in Figure 3.

[0108] As shown in Figures 21 and 22, in this exemplary embodiment, the second auxiliary portion B2 may include both a first sub-auxiliary portion B21 and a second sub-auxiliary portion B22, and the auxiliary unit BSM0 may further include a fourth auxiliary portion B4. Specifically, the auxiliary unit BSM0 shields the conductive structure T2M between the dual channels of the second transistor T2 while also shielding the first transistor T1. Similar to the layout structure shown in Figure 10, the second sub-auxiliary portion B22 connects to the second auxiliary portion B2. Its orthographic projection on the substrate overlaps the orthographic projection of the tenth active portion POL10. Specifically, the second sub-auxiliary portion B22 is also provided below the conductive structure T2M between the dual channels of the second transistor T2 to provide charge blocking. Furthermore, as shown in Figure 24, the orthographic projection of the second sub-auxiliary portion B22 on the substrate also overlaps the orthographic projection of the third via H3 on the substrate. Specifically, the area covered by the orthographic projection of the third via H3 on the substrate is completely within the area covered by the orthographic projection of the second sub-auxiliary portion B22 on the substrate. Thus, the second sub-auxiliary portion B22 in this exemplary embodiment can have the same function as the second sub-auxiliary portion B22 in the layout structure shown in FIG. 10 .

[0109] Furthermore, as shown in Figures 21 and 22 , in this exemplary embodiment, the fourth auxiliary portion B4 is connected to the second auxiliary portion B2, and the orthographic projection of the fourth auxiliary portion B4 on the base substrate can overlap the orthographic projection of the first active portion POL1 on the base substrate. This means that the fourth auxiliary portion B4 can have the layout structure shown in Figure 14 , and accordingly, it also has the beneficial effects of the fourth auxiliary portion B4 in the layout structure shown in Figure 14 . Alternatively, the orthographic projection of the fourth auxiliary portion B4 on the base substrate can simultaneously overlap the orthographic projections of the first active portion POL1 and the ninth active portion POL9 on the base substrate. This means that the fourth auxiliary portion B4 can have the layout structure shown in Figure 18 , and accordingly, it also has the beneficial effects of the fourth auxiliary portion B4 in the layout structure shown in Figure 18 . This will not be further elaborated here.

[0110] In addition, based on the above embodiment, the auxiliary unit BSM0 can also include a sixth auxiliary part B6, which is connected to the third connecting part B13, and the sixth auxiliary part B6 is arranged corresponding to the fourth active part POL4. The orthographic projection of the sixth auxiliary part B6 on the base substrate extends along the row direction and covers the orthographic projection of the fourth active part POL4 on the base substrate.

[0111] For example, in some embodiments, the auxiliary unit BSM0 can form the layout structure shown in Figure 25 based on the layout structure shown in Figure 4, and the active layer Poly~second source and drain metal layer SD2 correspond to all the features of the active layer Poly~second source and drain metal layer SD2 in the display panel in Figure 3, and the stacked layout of the auxiliary layer BSM and the active layer Poly is shown in Figure 26.

[0112] In other embodiments, the auxiliary unit BSM0 can also form a layout structure shown in Figure 27 based on the layout structure shown in Figure 11, and the active layer Poly~second source and drain metal layer SD2 correspond to all the characteristics of the active layer Poly~second source and drain metal layer SD2 in the display panel shown in Figure 10, and the stacked layout of the auxiliary layer BSM and the active layer Poly is shown in Figure 28.

[0113] In other embodiments, the auxiliary unit BSM0 can also form a layout structure shown in Figure 29 based on the layout structure shown in Figure 15, and the active layer Poly~second source and drain metal layer SD2 correspond to all the characteristics of the active layer Poly~second source and drain metal layer SD2 in the display panel of Figure 14, and the stacked layout of the auxiliary layer BSM and the active layer Poly is shown in Figure 30.

[0114] In some further embodiments, the auxiliary unit BSM0 may further form a layout structure as shown in FIG31 based on the layout structure shown in FIG19 , and the active layer Poly to the second source / drain metal layer SD2 may have all the features of the active layer Poly to the second source / drain metal layer SD2 in the display panel of FIG18 . The stacked layout of the auxiliary layer BSM and the active layer Poly is shown in FIG32 .

[0115] In some further embodiments, the auxiliary unit BSM0 can also form a layout structure as shown in Figure 33 based on the layout structure shown in Figure 22, and the active layer Poly~second source and drain metal layer SD2 correspond to all the characteristics of the active layer Poly~second source and drain metal layer SD2 in the display panel of Figure 21, and the stacked layout of the auxiliary layer BSM and the active layer Poly is shown in Figure 34.

[0116] Of course, in other embodiments of the present disclosure, the orthographic projection of the auxiliary unit BSM0 on the base substrate may also cover the orthographic projections of all transistors in the corresponding pixel driving circuit on the base substrate. For example, as shown in FIG35 , the orthographic projection of the auxiliary unit BSM0 in the auxiliary layer BSM on the base substrate may be similar to the orthographic projection of the active layer structure in the corresponding pixel driving circuit on the base substrate, and the orthographic projection of the active layer structure of a pixel driving circuit on the base substrate is located within the orthographic projection of the auxiliary unit BSM0 at the corresponding position on the base substrate, so that the auxiliary unit BSM0 can shield all transistors below the corresponding pixel driving circuit, further enhancing the blocking effect on free charges.

[0117] The display panel disclosed herein may further include a first conductive layer Gate1, a second conductive layer Gate2, a first source-drain metal layer SD1, and a second source-drain metal layer SD2 stacked on the side of the active layer Poly facing away from the base substrate. The first conductive layer Gate1 may be a first gate metal layer, the second conductive layer Gate2 may be a second gate metal layer, and an insulating layer may be provided between two adjacent conductive layers. For example, a first gate insulating layer may be provided between the first conductive layer Gate1 and the active layer Poly, a second gate insulating layer may be provided between the second conductive layer Gate2 and the first conductive layer Gate1, an interlayer dielectric layer may be provided between the first source-drain metal layer SD1 and the second conductive layer Gate2, and a passivation layer and a planarization layer may be provided between the second source-drain metal layer SD2 and the first source-drain metal layer SD1.

[0118] Figure 36 is the structural layout of the first conductive layer in Figure 3, Figure 37 is the structural layout of the second conductive layer in Figure 3, Figure 38 is the structural layout of the first source-drain metal layer in Figure 3, Figure 39 is the structural layout of the second source-drain metal layer in Figure 3, Figure 40 is the stacked layout of the auxiliary layer, the active layer and the first source-drain metal layer in Figure 3, and Figure 41 is the stacked layout of the auxiliary layer, the first conductive layer and the first source-drain metal layer in Figure 3.

[0119] As shown in Figures 3 and 36, in an exemplary embodiment, the first conductive layer Gate1 may include a second conductive block 12, a first reset signal line Reset(n), a gate signal line Gate, an enable signal line EM and a second reset signal line Reset(n+1), and the positive projections of the first reset signal line Reset(n), the gate signal line Gate, the second conductive block 12, the enable signal line EM and the second reset signal line Reset(n+1) on the substrate may all extend along the row direction and be spaced apart in the column direction, and the first reset signal line Reset(n) and the gate signal line Gate are located on the same side of the second conductive block 12, and the enable signal line EM and the second reset signal line Reset(n+1) are located on the other side of the second conductive block 12.

[0120] The orthographic projection of the second conductive block 12 on the substrate can overlap the orthographic projection of the third active portion POL3 on the substrate. The second conductive block 12 can be used to form the gate of the driving transistor T3 and the first electrode of the storage capacitor Cst. Thus, in the layout structure, the first reset signal line Reset(n) and the gate signal line Gate are located on the same side of the driving transistor T3, while the enable signal line EM and the second reset signal line Reset(n+1) are located on the other side of the driving transistor T3.

[0121] The first reset signal line Reset(n) can be used to provide the first reset signal terminal in Figure 1. The orthographic projection of the first reset signal line Reset(n) on the substrate can cover the orthographic projections of the first sub-active portion POL1-1 and the second sub-active portion POL1-2 on the substrate, so that a portion of the structure of the first reset signal line Reset(n) is used to form the gate of the first transistor T1, and the first transistor T1 forms a dual-gate structure.

[0122] The gate signal line Gate can be used to provide the gate signal terminal shown in Figure 1. The orthographic projection of the gate signal line Gate on the base substrate can overlap the orthographic projection of the second active portion POL2 on the base substrate. Part of the structure of the gate signal line Gate forms the gate of the second transistor T2. In this exemplary embodiment, the second active portion POL2 of the active layer Poly can include a third sub-active portion POL2-3 and a fourth sub-active portion POL2-4, that is, the second transistor T2 includes two channel regions. The gate signal line Gate can include a main extension portion Gate-0 and an additional portion Gate-1. The orthographic projection of the main extension portion Gate-0 on the base substrate can overlap the orthographic projection of the third sub-active portion POL2-3 on the base substrate, and the orthographic projection of the additional portion Gate-1 on the base substrate can overlap the orthographic projection of the fourth sub-active portion POL2-4 on the base substrate, resulting in the second transistor T2 forming a dual-gate structure.

[0123] The enable signal line EM can be used to provide the enable signal terminal in Figure 1. The orthographic projection of the enable signal line EM on the substrate can respectively cover the orthographic projections of the fifth active portion POL5 and the sixth active portion POL6 on the substrate. Part of the structure of the enable signal line EM can be used to form the gate of the fifth transistor T5, and part of the structure can be used to form the gate of the sixth transistor T6.

[0124] The second reset signal line Reset(n+1) can be used to provide the second reset signal terminal in Figure 1. The orthographic projection of the second reset signal line Reset(n+1) on the base substrate can cover the orthographic projection of the seventh active portion POL7 on the base substrate. Part of the structure of the second reset signal line Reset(n+1) can be used to form the gate of the seventh transistor T7.

[0125] The display panel disclosed herein can use the first conductive layer Gate1 as a mask to perform conductor processing on the active layer Poly, that is, the active layer Poly covered by the first conductive layer Gate1 forms a channel region of the transistor, and the region not covered by the first conductive layer Gate1 forms a conductor structure.

[0126] As shown in Figures 3 and 37, in an exemplary embodiment, the second conductive layer Gate2 may include a third conductive block 23 and a first initialization signal line Vinit1 and a second initialization signal line Vinit2 extending along the row direction and located on the same side of the third conductive block 23. The orthographic projection of the third conductive block 23 on the substrate can be located on the orthographic projection of the second conductive block 12 on the substrate. The third conductive block 23 can be used to form a second electrode of the storage capacitor Cst.

[0127] As shown in Figure 37, in an exemplary embodiment, the third conductive block 23 can be connected to the power transfer line VDDL located in the first source and drain metal layer SD1 through a via, and then connected to the first power line VDD of the second source and drain metal layer SD2 through the power transfer line VDDL, thereby connecting the third conductive block 23 to the first power line VDD.

[0128] As shown in Figure 37, in an exemplary embodiment, two adjacent third conductive blocks 23 in the row direction are connected by a connecting line 24, so that the first power line VDD forms a grid structure with staggered rows and columns through the laterally extended third conductive block 23. The first power line VDD in the grid structure can reduce the impedance of the first power line VDD, thereby reducing the RC load of the first power line VDD, and further reducing the power consumption of the display panel.

[0129] As shown in Figure 37, in an exemplary embodiment, the first initialization signal line Vinit1 may include a main signal line Vinit10 and an auxiliary part Vinit11, the main signal line Vinit10 may extend in the row direction, the auxiliary part Vinit11 may be connected to one side of the main signal line in the column direction, and the auxiliary part Vinit11 may be connected to the third initialization signal line Vinit3 located in the first source and drain metal layer SD1 through a via, so as to connect the first initialization signal line Vinit1 with the twelfth active part POL12 of the active layer Poly through the third initialization signal line Vinit3, so as to connect the first electrode of the first transistor T1 to the first initialization signal line Vinit1. At the same time, the third initialization signal line Vinit3 extends along the column direction and connects to the first initialization signal line Vinit1 in each row, forming a grid structure with alternating rows and columns. This reduces the impedance of the first initialization signal line Vinit1 and its RC load, thereby reducing power consumption. Furthermore, the third initialization signal line Vinit3 can be connected to the auxiliary layer BSM via a via in the non-display area. This connection of the third initialization signal line Vinit3 allows the first initialization signal line Vinit1 to provide a first signal to the auxiliary layer BSM, ensuring stable display characteristics before and after high-temperature reliability testing and copper bar testing. In other embodiments, the first initialization signal line Vinit1 can be directly connected to the auxiliary layer BSM via a via in the non-display area. For example, the first initialization signal line Vinit1 can be formed into a ring in the non-display area and then connected to the auxiliary layer BSM via a via.

[0130] As shown in FIG37 , in an exemplary embodiment, the second initialization signal line Vinit2 can be connected to the fourth initialization signal line Vinit4 located in the first source / drain metal layer SD1 via a second via H2. This fourth initialization signal line Vinit4 can then be connected to the nineteenth active portion POL19 of the active layer Poly, thereby connecting the first electrode of the seventh transistor T7 to the second initialization signal line Vinit2. Similarly, the fourth initialization signal line Vinit4 can be used to form a grid structure with staggered rows and columns along the second initialization signal line Vinit2. Furthermore, the fourth initialization signal line Vinit4 can be used to connect the auxiliary layer BSM in the non-display area to provide the first signal to the auxiliary layer BSM. Similarly, in other embodiments, the second initialization signal line Vinit2 can be directly connected to the auxiliary layer BSM in the non-display area through a via, which will not be further described here.

[0131] As shown in FIG37 , in an exemplary embodiment, the second conductive layer Gate2 may further include a first conductive block 21. The orthographic projection of the first conductive block 21 on the base substrate may be located on the orthographic projection of the tenth active portion POL10 on the base substrate, that is, the first conductive block 21 may cover the conductive structure between the two channel regions of the second transistor T2. In addition, the first conductive block 21 may be connected to the power adapter line VDDL located on the first source-drain metal layer SD1 through the third via H3, so as to connect the first conductive block 21 to the first power line VDD of the second source-drain metal layer SD2 through the power adapter line VDDL. In this way, the first conductive block 21 has a voltage stabilizing effect on the tenth active portion POL10, that is, the first conductive block 21 can stabilize the voltage of the conductive structure connecting the two channel regions of the second transistor T2, thereby reducing leakage of the second transistor T2T2, and assisting in preventing interference of the alternating voltage on the data signal line Vdata on the tenth active portion POL10, thereby reducing voltage fluctuations of the pixel driving circuit driving the transistor T3 during the light-emitting phase and improving picture quality. It is worth noting that the third via H3 here refers to a via opened in the insulating layer between the first conductive block 21 and the power adapter line VDDL, that is, the via connecting the first conductive block 21 to the power adapter line VDDL. The power adapter line VDDL can be connected to the first power line VDD of the second source-drain metal layer SD2 through a via at another location, that is, the location of the via connecting the first power line VDD to the power adapter line VDDL can be different from the location of the third via H3. Of course, in other embodiments, the first power line VDD can also be connected to the power adapter line VDDL at the location corresponding to the third via H3.

[0132] In addition, as shown in Figures 3 and 37, in an exemplary embodiment, due to the existence of the first conductive block 21, it is necessary to open a third via H3 in the interlayer dielectric layer located on the second conductive layer Gate2 to connect the power transfer line VDDL of the first source and drain metal layer SD1 through the third via H3. On this basis, the orthographic projection of the auxiliary unit BSM0 in the auxiliary layer BSM on the base substrate can also cover the orthographic projection of the third via H3 on the base substrate. Specifically, as shown in Figures 37 and 40, the second auxiliary part B2 in the auxiliary layer BSM can include a first sub-auxiliary part B21 and a second sub-auxiliary part B22. The auxiliary portion B22, the orthographic projection of the second sub-auxiliary portion B22 on the base substrate can cover the orthographic projection of the first conductive block 21 and the third via H3 on the base substrate, so as to avoid the unevenness under the via hole of the interlayer dielectric layer due to process fluctuations. It can be known that when the area under the via hole is uneven, the via hole will be deformed, resulting in display defects such as display stripes between different sub-pixels. Therefore, this exemplary embodiment can avoid the deformation of the third via hole H3 by completely covering the third via hole H3 with the auxiliary layer BSM, thereby avoiding the problem of display stripes caused by the deformation of the via hole on the interlayer dielectric layer.

[0133] As shown in Figures 3, 38, and 40, in an exemplary embodiment, the first source / drain metal layer SD1 may include a third initialization signal line Vinit3 and a fourth initialization signal line Vinit4. Both the third initialization signal line Vinit3 and the fourth initialization signal line Vinit4 may extend in the column direction. The third initialization signal line Vinit3 may be connected to the first initialization signal line Vinit1 via a first via H1, forming a parallel structure with the first initialization signal line Vinit1. In this manner, the third initialization signal line Vinit3 extending in the column direction may be connected to the auxiliary layer BSM when it extends into the non-display area, providing the auxiliary layer BSM with a first signal. The fourth initialization signal line Vinit4 may be connected to the second initialization signal line Vinit2 via a second via, forming a parallel structure with the second initialization signal line Vinit2. In this manner, the fourth initialization signal line Vinit4 may be connected to the auxiliary layer BSM when it extends into the non-display area, providing the auxiliary layer BSM with a first signal. In other words, the first signal may be provided to the auxiliary layer BSM via the first initialization signal line Vinit1 or via the second initialization signal line Vinit2.

[0134] As shown in Figures 38 and 40, in an exemplary embodiment, the display panel may include a first pixel column P1 and a second pixel column P2 alternately arranged in the row direction. The third initialization signal line Vinit3 may be located in the second pixel column P2, and the fourth initialization signal line Vinit4 may be located in the first pixel column P1. The first via H1 and the second via H2 are both located in the first pixel column P1. Furthermore, in this exemplary embodiment, the pixel driver circuit located in the first pixel column P1 may be a first pixel driver circuit, and the pixel driver circuit located in the second pixel column P2 may be a second pixel driver circuit. The display panel may include a plurality of repeating units arranged in an array in the row and column directions, with each repeating unit including a first pixel driver circuit and a second pixel driver circuit adjacent to the first pixel driver circuit in the row direction. It should be understood that when a structure A described in the present disclosure is located in a pixel column B, it can be understood that the orthographic projection of the structure A on the substrate is located in the region where the pixel column B is located.

[0135] For example, as shown in FIG38 , the third initialization signal line Vinit3 may include a first main portion Vinit30, a first extension portion Vinit31, and a second extension portion Vinit32. The first main portion Vinit30 may be located in the second pixel column P2, the first extension portion Vinit31 is connected between the first main portion Vinit30 and the second extension portion Vinit32, and one end of the second extension portion Vinit32 is connected to the first initialization signal line Vinit1 via a first via H1, and the other end is connected to the twelfth active portion POL12 via another via. Thus, the third initialization signal line Vinit3 is connected to the first initialization signal line Vinit1 and to the first electrode of the first transistor T1 in the first pixel column P1. Furthermore, the first source-drain metal layer SD1 may further include a third bridge portion 33 located in the second pixel column P2 to connect the first electrode of the first transistor T1 to the first initialization signal line Vinit1 in the second pixel column P2.

[0136] As shown in Figure 38, the fourth initialization signal line Vinit4 may include a second main body Vinit40, a third extension portion Vinit43 and a fourth extension portion Vinit44, the third extension portion Vinit43 is connected between the second main body portion Vinit40 and the fourth extension portion Vinit44, one end of the fourth extension portion Vinit44 is connected to the second initialization signal line Vinit2 through a second via H2, and the other end is connected to the nineteenth active portion POL19 through another via, so that the fourth initialization signal line Vinit4 is connected to the second initialization signal line Vinit2 on the one hand, and is also connected to the first electrode of the seventh transistor T7 in the first pixel column P1 on the other hand. At the same time, the first source-drain metal layer SD1 may also include a fourth bridge portion 34, which is located in the second pixel column P2. The orthographic projection of the fourth bridge portion 34 on the substrate may extend along the column direction. The fourth bridge portion 34 may be connected to the nineteenth active portion POL19 and the second initialization signal line Vinit2 through vias, respectively, so that the first electrode of the seventh transistor T7 is connected to the second initialization signal line Vinit2 through the fourth bridge portion 34 in the second pixel column P2.

[0137] It can be seen that in this exemplary embodiment, within the same repeating unit, the first initialization signal line Vinit1 is connected to the first electrode of the first transistor T1 in the first pixel driving circuit via the third initialization signal line Vinit3 and is connected to the first electrode of the first transistor T1 in the second pixel driving circuit via the third bridge portion 33. The second initialization signal line Vinit2 is connected to the first electrode of the seventh transistor T7 in the first pixel driving circuit via the fourth initialization signal line Vinit4 and is connected to the first electrode of the seventh transistor T7 in the second pixel driving circuit via the fourth bridge portion 34.

[0138] As shown in Figures 38 and 40, in an exemplary embodiment, the first source-drain metal layer SD1 may further include a power transfer line VDDL, and the power transfer line VDDL may include a first transfer part VDDL-1, a second transfer part VDDL-2 and a third transfer part VDDL-3. For example, the first power transfer line VDDL1 may include three transfer parts: a first transfer part VDDL1-1, a second transfer part VDDL1-2 and a third transfer part VDDL1-3, and the second power transfer line VDDL2 may include three transfer parts: a first transfer part VDDL2-1, a second transfer part VDDL2-2 and a third transfer part VDDL2-3. The orthographic projections of the first adapter portion VDDL-1 and the third adapter portion VDDL-3 on the substrate extend in the column direction, and the orthographic projection of the second adapter portion VDDL-2 on the substrate extends in the row direction. The first adapter portion VDDL-1 and the third adapter portion VDDL-3 are connected through the second adapter portion VDDL-2, that is, the power adapter line VDDL is bent, and part of the structure is located in the current pixel driving circuit, and part of the structure is located in the adjacent pixel driving circuit in the row direction, so that the power adapter line VDDL is respectively connected to the third conductive block 23 and the first power line VDD through the first adapter portion VDDL-1 located in the current pixel driving circuit, and is connected to the first conductive block 21 of the adjacent pixel driving circuit through the third adapter portion VDDL-3 located in the adjacent pixel driving circuit, thereby connecting the third conductive block 23 in the current pixel driving circuit and the first conductive block 21 of the adjacent pixel column to the first power line VDD of the second source and drain metal layer SD2.

[0139] Furthermore, as described above, the display panel may include a first pixel column P1 and a second pixel column P2 alternately arranged in a row direction. On this basis, the power transfer line VDDL may include a first power transfer line VDDL1 and a second power transfer line VDDL2, wherein the first power transfer line VDDL1 is located in the first pixel column P1 and the second power transfer line VDDL2 is located in the second pixel column P2. The first power transfer line VDDL1 may connect to the third conductive block 23 of the second conductive layer Gate2 and to the first power line VDD of the second source-drain metal layer SD2 through a via in the first pixel column P1, thereby connecting the second electrode of the storage capacitor Cst to the first power line VDD. Furthermore, after crossing over the third conductive block 23 of the first pixel column P1, the first power transfer line VDDL1 bends toward the second pixel column P2, so as to connect to the first conductive block 21 of the second pixel column P2 in the same repeating unit through a via in the first pixel column P1, thereby connecting the first conductive block 21 in the second pixel column P2 in the same repeating unit to the first power line VDD.

[0140] The second power transfer line VDDL2 can be connected to the third conductive block 23 of the second conductive layer Gate2 and to the first power line VDD of the second source-drain metal layer SD2 in the second pixel column P2 through a via, thereby connecting the second electrode of the storage capacitor Cst in the second pixel column to the first power line VDD. Furthermore, after crossing the third conductive block 23 of the second pixel column P2, the second power transfer line VDDL2 bends toward another adjacent repeating unit in the row direction to connect to the first conductive block 21 of the first pixel column P1 in another adjacent repeating unit in the row direction through a via, thereby connecting the first conductive block 21 of the first pixel column P1 in the adjacent repeating unit in the row direction to the first power line VDD.

[0141] Furthermore, as shown in FIG38 , in this exemplary embodiment, the length of the orthographic projection of the second power adapter line VDDL2 along the column direction on the substrate is greater than the length of the orthographic projection of the first power adapter line VDDL1 along the column direction on the substrate. FIG38 shows that the first power adapter line VDDL1 is an isolated structure, meaning that the first power adapter lines VDDL1 located in different pixel driver circuits in the same column are not connected. In contrast, the second power adapter line VDDL2 is a continuous structure, meaning that the second power adapter lines VDDL2 located in different pixel driver circuits in the same column are connected to form a continuous structure. Therefore, the length of the orthographic projection of the second power adapter line VDDL2 along the column direction on the substrate is greater than the length of the orthographic projection of the first power adapter line VDDL1 along the column direction on the substrate. Furthermore, the second power adapter line VDDL2 can be connected to the auxiliary layer BSM via vias in the non-display area of ​​the display panel, providing the auxiliary layer BSM with a first signal. As described above, the power adapter line may include multiple adapter parts in a pixel driving circuit, and the orthographic projections of some adapter parts extend along the column direction, and the orthographic projections of some adapter parts extend along the row direction. Therefore, the extension length of a power adapter line mentioned here in the orthographic projection of the substrate along the column direction can be specifically understood as the sum of the extension lengths of the various parts of the power adapter line extending along the column direction in the orthographic projection of the substrate. In this way, the extension length of the second power adapter line VDDL2 in the column direction is greater than the extension length of the first power adapter line VDDL1 in the column direction, that is, the sum of the extension lengths of the various parts of the orthographic projection of the second power adapter line VDDL2 extending along the column direction is greater than the sum of the extension lengths of the various parts of the orthographic projection of the first power adapter line VDDL1 extending along the column direction.

[0142] As shown in Figures 38 and 41, in this exemplary embodiment, the second adapter portion VDDL-2 and the second connection portion B12 of the auxiliary layer BSM at least partially overlap in their orthographic projection on the base substrate. Taking the first power adapter line VDDL1 as an example, as shown in Figure 41, at the dotted box M in the figure, the second adapter portion VDDL-2 of the first power adapter line VDDL1 and the orthographic projection of the second connection portion B12 located below it on the base substrate can partially overlap. By overlapping the second adapter portion VDDL-2 and the second connection portion B12, the total space occupied by the wiring at that location in the layout can be reduced, and the saved space can improve light transmittance.

[0143] In addition, the orthographic projection of the connecting line 24 connecting the third conductive blocks 23 in the two adjacent pixel driving circuits in the second conductive layer Gate2 on the substrate can be located within the orthographic projection of the second transfer portion VDDL-2 on the substrate. Thus, the second connecting portion B12 of the auxiliary layer BSM, the connecting line 24 of the second conductive layer Gate2 and the second transfer portion VDDL-2 of the first source-drain metal layer SD1 are overlapped at this position, and the connecting line 24 of the second conductive layer Gate2 and the second transfer portion VDDL-2 of the first source-drain metal layer SD1 are at the same potential, and no signal crosstalk is generated. Thus, the overlapping arrangement of these three structures can further save the wiring space at this position and improve the light transmittance.

[0144] In other embodiments, the orthographic projection of the second connecting portion B12 on the base substrate may also cover the orthographic projection of the second adapter portion VDDL-2 on the base substrate. That is, the second connecting portion B12 completely shields the connecting wire 24 and the second adapter portion VDDL-2 from below. Compared to a partially overlapping arrangement, this can further save wiring space and improve light transmittance.

[0145] In combination with Figures 38 and 41, in this exemplary embodiment, the third transfer portion VDDL-3 located in the first source and drain metal layer SD1 and the main extension portion Gate-0 of the gate signal line Gate in the first conductive layer Gate1 have a first overlapping portion S1 in the orthographic projection of the base substrate, and the third initialization signal line Vinit3 of the first source and drain metal layer SD1 and the additional portion Gate-1 of the gate signal line Gate in the first conductive layer Gate1 have a second overlapping portion S2 in the orthographic projection of the base substrate. The orthographic projection of the second auxiliary portion B2 on the base substrate can cover the first overlapping portion S1 and the second overlapping portion S2, that is, the first overlapping portion S1 and the second overlapping portion S2 are both located within the orthographic projection of the second auxiliary portion B2 on the base substrate, which is equivalent to enlarging the second auxiliary portion B2 so that the second auxiliary portion B2 can cover the two overlapping portions, so that the coupling capacitance of the auxiliary layer BSM at the two channel positions of the second transistor T2 is consistent, thereby eliminating the poor display caused by the difference in coupling capacitance.

[0146] As shown in Figures 38 and 40, in an exemplary embodiment, the first source-drain metal layer SD1 may further include a first bridge portion 31. The first bridge portion 31 may extend along the column direction. One end of the first bridge portion 31 may be connected to the eleventh active portion POL11 via a via, thereby connecting the second electrode of the first transistor T1 and the first electrode of the second transistor T2. The other end of the first bridge portion 31 may be connected to the second conductive block 12 via a via, thereby connecting to the gate of the driving transistor T3. In this way, the second electrode of the first transistor T1 and the first electrode of the second transistor T2 are connected to the gate of the driving transistor T3 via the first bridge portion 31.

[0147] As shown in Figures 38 and 40, in an exemplary embodiment, the first source-drain metal layer SD1 may further include an anode transition portion 35, one end of the anode transition portion 35 may be connected to the eighteenth active portion POL18 through a via to connect the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7; the other end of the anode transition portion 35 may be connected to the anode connection portion 41 of the second source-drain metal layer SD2 through a via to connect the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7 to the anode of the light-emitting device through the anode connection portion 41.

[0148] As shown in Figures 3 and 39, in an exemplary embodiment, the second source-drain metal layer SD2 may include a first power line VDD and a data signal line Vdata. The orthographic projections of the first power line VDD and the data signal line Vdata on the substrate may both extend in the column direction. The first power line VDD may be used to provide the first power terminal shown in Figure 1. The first power line VDD may be connected to a power transfer line VDDL of the first source-drain metal layer SD1 via a via, thereby connecting the second electrode of the storage capacitor Cst to the first electrode of the fifth transistor T5 via the power transfer line VDDL. Furthermore, in this exemplary embodiment, the first power line VDD may be connected to an auxiliary layer via a via in the non-display area of ​​the display panel to provide a first signal to the auxiliary layer. In other embodiments of the present disclosure, the display panel may further include a second power line located in the first source-drain metal layer SD1, and the second power line may be connected to the auxiliary layer via a via in the non-display area to provide the first signal to the auxiliary layer. For example, the second power line may be the power transfer line VDDL described in the above embodiment, which may be connected to the auxiliary layer via a via after extending to the non-display area.

[0149] It should be understood that the present disclosure can choose one of the first initialization signal line Vinit1, the second initialization signal line Vinit2, the first power line VDD and the second power line to be connected to the auxiliary layer, that is, the present disclosure can provide the first signal to the auxiliary layer by the first initialization signal line Vinit1 or the second initialization signal line Vinit2 or the first power line VDD or the second power line.

[0150] The data signal line Vdata can be used to provide the data signal terminal in FIG. 1 . The data signal line Vdata can be connected to the data transfer portion VdataL of the first source / drain metal layer SD1 through a via, so as to be connected to the second electrode of the fourth transistor T4 through the data transfer portion VdataL.

[0151] As shown in FIG39 , the second source-drain metal layer SD2 may further include an anode connecting portion 41 and an anode flat portion 42. The orthographic projection of the anode connecting portion 41 on the substrate is located above the orthographic projection of the anode transition portion 35 on the substrate. The anode connecting portion 41 is located below and connected to the anode of the light-emitting device. Thus, the anode of the light-emitting device can be connected to the second electrode of the seventh transistor T7 and the second electrode of the sixth transistor T6 via the anode connecting portion 41. Because the anode connecting portion 41 exists, a certain protrusion exists below the anode. On this basis, by adding the anode flat portion 42 to the second source-drain metal layer SD2, the height of the protrusion of the anode connecting portion 41 can be balanced by the anode flat portion 42, thereby preventing the anode from being higher on one side and lower on the other side below the anode. This prevents the anode from tilting, thereby ensuring normal display of the light-emitting device.

[0152] It should be understood that the terms "first", "second" and "third" used in the present disclosure are only used as labels to distinguish the names of different structures, and are not intended to limit the quantity of their objects and have no sequential relationship.

[0153] Figures 41 and 42 are cross-sectional views taken along the AA direction in Figure 3. The display panel may further include a buffer layer 72, a first insulating layer 73, a second insulating layer 74, a first dielectric layer 75, a passivation layer 77, and a second dielectric layer 77. The base substrate 71, auxiliary layer BSM, buffer layer 72, active layer Poly, first insulating layer 73, first conductive layer Gate1, second insulating layer 74, second conductive layer Gate2, first dielectric layer 75, first source / drain metal layer SD1, passivation layer 76, second dielectric layer 77, and second source / drain metal layer SD2 are sequentially stacked. The first insulating layer 73 may be an organic insulating layer, the second insulating layer 74 may be silicon oxide, the first dielectric layer 75 and the second dielectric layer 77 may be silicon nitride layers, and the passivation layer 77 and buffer layer 72 may be made of silicon oxide, silicon nitride, or the like. The base substrate 71 may include a glass substrate, a barrier layer, and a polyimide layer stacked sequentially. The barrier layer may be an inorganic material. The material of the first conductive layer Gate1 and the second conductive layer Gate2 can be one of molybdenum, aluminum, copper, titanium, niobium, or an alloy thereof, or a molybdenum / titanium alloy or a stacked layer, etc. The material of the first source / drain metal layer SD1 and the second source / drain metal layer SD2 can include a metal material, for example, one of molybdenum, aluminum, copper, titanium, niobium, or an alloy thereof, or a molybdenum / titanium alloy or a stacked layer, etc., or a titanium / aluminum / titanium stacked layer.

[0154] The present disclosure also provides a display device, which may include the display panel described in any of the above embodiments.

[0155] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the appended claims.

Claims

1. A display panel, wherein: The display panel comprises a pixel driving circuit, the pixel driving circuit comprises a second transistor and a driving transistor, a first electrode of the second transistor is connected to a gate of the driving transistor; The display panel further includes: substrate substrate; An auxiliary layer, located on one side of the substrate, the auxiliary layer being connected to a first signal; An active layer is located on a side of the auxiliary layer away from the substrate, and the active layer includes: a second active portion, used to form a channel region of the second transistor; a third active portion, used to form a channel region of the driving transistor; The orthographic projection of the auxiliary layer on the base substrate covers the orthographic projections of the second active portion and the third active portion on the base substrate.

2. The display panel according to claim 1, wherein: The display panel includes a plurality of pixel driving circuits arranged in an array along a row and a column direction, the auxiliary layer includes a plurality of auxiliary units arranged in an array along a row and a column direction, and the auxiliary units are arranged corresponding to the pixel driving circuits; The second active portion includes a third sub-active portion and a fourth sub-active portion; The auxiliary unit comprises: A first auxiliary portion, whose orthographic projection on the base substrate covers the orthographic projection of the third active portion on the base substrate; A second auxiliary portion, wherein the orthographic projection of the second auxiliary portion on the base substrate respectively covers the orthographic projections of the third sub-active portion and the fourth sub-active portion on the base substrate.

3. The display panel according to claim 2, wherein: The active layer further comprises: a tenth active portion connected between the third sub-active portion and the fourth sub-active portion; The orthographic projection of the second auxiliary portion on the base substrate does not overlap with the orthographic projection of the tenth active portion on the base substrate.

4. The display panel according to claim 2, wherein: The active layer further comprises: a tenth active portion connected between the third sub-active portion and the fourth sub-active portion; The second auxiliary portion includes a first sub-auxiliary portion and a second sub-auxiliary portion, wherein the orthographic projection of the first sub-auxiliary portion on the base substrate covers the orthographic projections of the third sub-active portion and the fourth sub-active portion on the base substrate, and the second sub-auxiliary portion on the base substrate The orthographic projection of the tenth active portion covers the orthographic projection of the tenth active portion on the base substrate.

5. The display panel according to claim 4, wherein: The display panel further includes: A second conductive layer is located on a side of the active layer away from the auxiliary layer, and the second conductive layer includes: a first conductive block, the orthographic projection of which on the base substrate is located on the orthographic projection of the tenth active portion on the base substrate; The second source-drain metal layer is located on a side of the second conductive layer away from the substrate, and the second source-drain metal layer includes: A first power line, an orthographic projection of which on the base substrate extends along a column direction, and the first power line is coupled to the first conductive block through a third via hole; The orthographic projection of the second sub-auxiliary portion on the base substrate also covers the orthographic projection of the third via hole on the base substrate.

6. The display panel according to claim 1, wherein: The active layer further comprises: a first active portion connected to one side of the second active portion, the first active portion being used to form a channel region of the first transistor; The auxiliary unit also includes: A fourth auxiliary portion is connected to the second auxiliary portion, and an orthographic projection of the fourth auxiliary portion on the base substrate covers an orthographic projection of the first active portion on the base substrate.

7. The display panel according to claim 6, wherein: The first active portion includes a first sub-active portion and a second sub-active portion; The active layer further comprises: a ninth active portion connected between the first sub-active portion and the second sub-active portion; The orthographic projection of the fourth auxiliary portion on the base substrate also covers the orthographic projection of the ninth active portion on the base substrate.

8. The display panel according to claim 7, wherein: The pixel driving circuit further includes a fourth transistor; The active layer further comprises: a fourth active portion, the fourth active portion being used to form a channel region of the fourth transistor; The auxiliary unit also includes: A third connecting portion connected between two adjacent auxiliary units in the column direction, wherein the orthographic projection of the third connecting portion on the base substrate extends along the column direction; A sixth auxiliary portion is connected to the third connecting portion, and an orthographic projection of the sixth auxiliary portion on the base substrate extends along a row direction and covers an orthographic projection of the fourth active portion on the base substrate.

9. The display panel according to claim 1, wherein: The auxiliary unit also includes: A third connecting portion connected between two adjacent auxiliary units in the column direction, wherein the orthographic projection of the third connecting portion on the base substrate extends along the column direction; A first connecting portion is connected to a side of the second auxiliary portion in a column direction away from the first auxiliary portion, and in two adjacent auxiliary units in the column direction, the third connecting portion of the auxiliary unit in an upper row is connected to the first connecting portion of the auxiliary unit in a lower row, and the orthographic projection of the first connecting portion on the substrate does not overlap with the orthographic projection of the first active portion on the substrate.

10. The display panel according to claim 9, wherein: The first active portion includes a first sub-active portion and a second sub-active portion; The active layer further comprises: a ninth active portion connected between the first sub-active portion and the second sub-active portion; The orthographic projection of the first connecting portion on the base substrate does not overlap with the orthographic projection of the ninth active portion on the base substrate.

11. The display panel according to claim 9, wherein: The pixel driving circuit further includes a fourth transistor; The active layer further includes a fourth active portion, and the fourth active portion is used to form a channel region of the fourth transistor; The auxiliary unit also includes: A third connecting portion connected between two adjacent auxiliary units in the column direction, wherein the orthographic projection of the third connecting portion on the base substrate extends along the column direction; A sixth auxiliary portion is connected to the third connecting portion, and an orthographic projection of the sixth auxiliary portion on the base substrate extends along a row direction and covers an orthographic projection of the fourth active portion on the base substrate.

12. The display panel according to claim 1, wherein: The pixel driving circuit further comprises a first transistor, a second electrode of the first transistor being connected to a gate electrode of the driving transistor; The active layer further comprises: a first active portion connected to one side of the second active portion, the first active portion being used to form a channel region of the first transistor; The auxiliary unit also includes: a second connecting portion, respectively connecting the first auxiliary portion and the second auxiliary portion, wherein the orthographic projection of the second connecting portion on the base substrate extends along a row direction, and two adjacent auxiliary units in the row direction are connected via the second connecting portion; A third connecting portion connected between two adjacent auxiliary units in the column direction, wherein the orthographic projection of the third connecting portion on the base substrate extends along the column direction; The first connecting part or the fourth auxiliary part is connected to a side of the second auxiliary part in the column direction away from the first auxiliary part, and in two adjacent auxiliary units in the column direction, the third connecting part of the auxiliary unit in the upper row is connected to the first connecting part or the fourth auxiliary part of the auxiliary unit in the lower row, wherein the first connecting part does not overlap with the orthographic projection of the first active part on the substrate, and the orthographic projection of the fourth auxiliary part on the substrate covers the orthographic projection of the first active part on the substrate.

13. The display panel according to claim 1, wherein: The display panel further includes: The first source-drain metal layer and / or the second source-drain metal layer are located on a side of the active layer away from the substrate, and the first source-drain metal layer and / or the second source-drain metal layer include: The orthographic projection of the second power line and / or the first power line on the base substrate extends along the column direction, and the second power line and / or the first power line is connected to the auxiliary layer through a via in the non-display area of ​​the display panel.

14. The display panel according to claim 1, wherein: The display panel further includes: A second conductive layer is located on a side of the active layer away from the substrate, and the second conductive layer includes: A first initialization signal line, an orthographic projection of which on the substrate extends along a row direction; A second initialization signal line, an orthographic projection of which on the base substrate extends along a row direction; A first source-drain metal layer is located on a side of the second conductive layer away from the substrate, and the first source-drain metal layer includes: A third initialization signal line, an orthographic projection of which on the base substrate extends along a column direction, and the third initialization signal line is connected to the first initialization signal line through a first via hole; and / or a fourth initialization signal line, the orthographic projection of which on the base substrate extends along the column direction, and the fourth initialization signal line is connected to the second initialization signal line through a second via hole.

15. The display panel according to claim 14, wherein: The display panel comprises first pixel columns and second pixel columns which are alternately distributed in sequence in a row direction; The orthographic projection of the third initialization signal line on the base substrate is at least partially located in the area where the second pixel column is located, the orthographic projection of the fourth initialization signal line on the base substrate is located in the area where the first pixel column is located, and the first via hole and the second via hole are both located in the first pixel column.

16. The display panel according to claim 3, wherein: The pixel driving circuit further comprises a storage capacitor, a first electrode of the storage capacitor is connected to the gate of the driving transistor, and a second electrode of the storage capacitor is connected to the second power supply terminal; The display panel further includes: A first conductive layer is located on a side of the active layer away from the substrate, and the first conductive layer includes: a second conductive block, whose orthographic projection on the base substrate covers the orthographic projection of the third active portion on the base substrate, and the second conductive block is used to form a first electrode of the storage capacitor; The second conductive layer is located on a side of the first conductive layer away from the substrate, and the second conductive layer includes: a third conductive block, whose orthographic projection on the substrate is located on the orthographic projection of the second conductive block on the substrate, and the third conductive block is used to form a second electrode of the storage capacitor; a first conductive block, the orthographic projection of which on the base substrate is located on the orthographic projection of the tenth active portion on the base substrate; A first source-drain metal layer is located on a side of the second conductive layer away from the substrate. The first source-drain metal layer comprises: First power adapters are connected to the third conductive blocks through vias, and the power adapters are also connected to the first conductive blocks in adjacent pixel driving circuits through vias; The second power adapter wires are connected to the third conductive blocks through vias, and the extension length of the orthographic projection of the base substrate along the column direction is greater than the extension length of the first power adapter wire along the column direction of the base substrate.

17. The display panel according to claim 16, wherein: The first power adapter includes a first adapter portion, a second adapter portion and a third adapter portion, wherein the orthographic projections of the first adapter portion and the third adapter portion on the base substrate extend along the column direction, the orthographic projection of the second adapter portion on the base substrate extends along the row direction, and the first adapter portion and the third adapter portion are connected via the second adapter; The first adapter is connected to the third conductive block and the first power line through via holes respectively. The third adapter is located in another pixel driving circuit adjacent to the first conductive block in the row direction and is connected to the first conductive block through a via hole.

18. The display panel according to claim 17, wherein: The auxiliary unit also includes: a second connecting portion, respectively connecting the first auxiliary portion and the second auxiliary portion, wherein the orthographic projection of the second connecting portion on the base substrate extends along a row direction, and two adjacent auxiliary units in the row direction are connected via the second connecting portion; The orthographic projection of the second transition portion on the base substrate partially overlaps with the orthographic projection of the second connection portion on the base substrate.

19. The display panel according to claim 17, wherein: The first conductive layer further comprises: a gate signal line, comprising a main extension portion and an additional portion, wherein the main extension portion extends along a row direction on an orthographic projection of the base substrate and covers an orthographic projection of the third sub-active portion on the base substrate, and the additional portion extends along a column direction on an orthographic projection of the base substrate and covers an orthographic projection of the fourth sub-active portion on the base substrate, and a partial structure of the gate signal line is used to form a gate of the second transistor; The second conductive layer further comprises: A first initialization signal line, the orthographic projection of which on the substrate extends along a row direction; The first source-drain metal layer further includes: A third initialization signal line, an orthographic projection of which on the substrate extends along a column direction, and the third initialization signal line is connected to the first initialization signal line through a via hole; Among them, the third transfer portion and the main extension portion have a first overlapping portion in the orthographic projection of the base substrate, the third initialization signal line and the additional portion have a second overlapping portion in the orthographic projection of the base substrate, and the second auxiliary portion covers the first overlapping portion and the second overlapping portion in the orthographic projection of the base substrate.

20. The display panel according to claim 16, wherein: The pixel driving circuit further comprises a fifth transistor, wherein a gate of the fifth transistor is connected to an enable signal line, a first electrode is connected to a first power supply terminal, and a second electrode is connected to a second electrode of the driving transistor; The active layer further comprises: a fifth active portion, used to form a channel region of the fifth transistor; a sixteenth active portion connected between the fifth active portion and the third active portion, and used to form a second electrode of the fifth transistor and a second electrode of the driving transistor; a seventeenth active portion connected to a side of the fifth active portion away from the sixteenth active portion, the seventeenth active portion being used to form a first electrode of the fifth transistor; The first conductive layer further comprises: an enable signal line, the orthographic projection of which on the base substrate extends along the row direction and covers the orthographic projection of the fifth active portion on the base substrate, and a partial structure of the enable signal line is used to form a gate of the fifth transistor; Wherein, the seventeenth active portion is connected to the first power line through a via hole.

21. The display panel according to claim 20, wherein: The pixel driving circuit further includes a fourth transistor and a sixth transistor, wherein the gate of the second transistor is connected to the gate signal terminal, and the second electrode is connected to the first electrode of the driving transistor; the gate of the fourth transistor is connected to the second reset signal terminal, the first electrode is connected to the second electrode of the driving transistor, and the second electrode is connected to the second electrode of the fifth transistor; The gate of the sixth transistor is connected to the enable signal terminal, the first electrode is connected to the first electrode of the driving transistor, and the second electrode is connected to the anode of the light emitting device; The active layer further comprises: a sixteenth active portion connected to one side of the third active portion, the sixteenth active portion being used to form a second electrode of the driving transistor and a second electrode of the fifth transistor; a fourteenth active portion, connected to the second bridge portion located in the first source-drain metal layer through a via hole, the second bridge portion is further connected to the sixteenth active portion through a via hole, and the fourteenth active portion is used to form a first electrode of the fourth transistor; a fourth active portion connected to the fourteenth active portion, the fourth active portion being used to form a channel region of the fourth transistor; a fifteenth active portion connected to a side of the fourth active portion away from the fourteenth active portion, the fifteenth active portion being used to form a second electrode of the fourth transistor; a fifth active portion, used to form a channel region of the fifth transistor; a sixth active portion, used to form a channel region of the sixth transistor; a seventh active portion, used to form a channel region of the seventh transistor; The first conductive layer further comprises: a first reset signal line, whose orthographic projection on the base substrate covers the orthographic projection of the first active portion on the base substrate, and a partial structure of the first reset signal line is used to form a gate of the first transistor; a gate signal line, the orthographic projection of which on the base substrate covers the orthographic projection of the second active portion on the base substrate, and a partial structure of the gate signal line is used to form a gate of the second transistor; an enable signal line, the orthographic projection of which on the base substrate covers the orthographic projections of the fifth active portion and the sixth active portion on the base substrate, a part of the structure of the enable signal line being used to form the gate of the fifth transistor, and a part of the structure of the enable signal line being used to form the gate of the sixth transistor; a second reset signal line, the orthographic projection of which on the base substrate covers the orthographic projections of the fourth active portion and the seventh active portion on the base substrate, a part of the structure of the second reset signal line being used to form the gate of the fourth transistor, and a part of the structure of the second reset signal line being used to form the gate of the seventh transistor; Among them, the orthographic projections of the first reset signal line, the gate signal line, the enable signal line and the second reset signal line on the base substrate all extend along the row direction and are sequentially spaced in the column direction, and the orthographic projections of the gate signal line and the enable signal line on the base substrate are located on both sides of the orthographic projection of the third active portion on the base substrate.

22. A display panel, wherein: The display panel comprises a pixel driving circuit, the pixel driving circuit comprises a second transistor and a driving transistor, a first electrode of the second transistor is connected to a gate of the driving transistor; The display panel further includes: a base substrate, the base substrate comprising an organic layer; An auxiliary layer, located on one side of the substrate; An active layer is located on a side of the auxiliary layer away from the substrate, and the active layer includes: a second active portion, used to form a channel region of the second transistor; a third active portion, used to form a channel region of the driving transistor; The orthographic projection of the auxiliary layer on the base substrate covers the orthographic projections of the second active portion and the third active portion on the base substrate.

23. The display panel according to claim 22, wherein: The display panel includes a plurality of pixel driving circuits arranged in an array along a row and a column direction, the auxiliary layer includes a plurality of auxiliary units arranged in an array along a row and a column direction, and the auxiliary units are arranged corresponding to the pixel driving circuits; The second active portion includes a third sub-active portion and a fourth sub-active portion; The auxiliary unit comprises: A first auxiliary portion, whose orthographic projection on the base substrate covers the orthographic projection of the third active portion on the base substrate; The orthographic projection of the second auxiliary portion on the base substrate respectively covers the orthographic projections of the third sub-active portion and the fourth sub-active portion on the base substrate.

24. The display panel according to claim 23, wherein: The pixel driving circuit further comprises a first transistor, a second electrode of the first transistor being connected to a gate electrode of the driving transistor; The active layer further comprises: a first active portion connected to one side of the second active portion, the first active portion being used to form a channel region of the first transistor; The auxiliary unit also includes: a second connecting portion, respectively connecting the first auxiliary portion and the second auxiliary portion, wherein the orthographic projection of the second connecting portion on the base substrate extends along a row direction, and two adjacent auxiliary units in the row direction are connected via the second connecting portion; A fourth auxiliary portion is connected to the second auxiliary portion, and an orthographic projection of the fourth auxiliary portion on the base substrate covers an orthographic projection of the first active portion on the base substrate.

25. A display device, wherein: A display panel comprising any one of claims 1-24.

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