A semiconductor device, a manufacturing method thereof, and a storage system

Abstract

The application discloses a semiconductor device and a manufacturing method thereof, a storage system; the device comprises a plurality of semiconductor columns extending in a third direction, a plurality of gate structures extending in a first direction and shielding structures; the gate structures and the shielding structures are staggered in a second direction, and the semiconductor columns are located between adjacent shielding structures and gate structures; wherein the size of the gate structure along the first direction is smaller than the size of the shielding structure along the first direction, and the orthographic projection of the gate structure along the second direction is located within the range of the orthographic projection of the shielding structure.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, specifically to a semiconductor device and its fabrication method, and a storage system. Background Technology

[0002] As the feature size of memory cells approaches the lower limit of process technology, planar processes and manufacturing techniques become challenging and costly, causing the storage density of 2D memory structures to approach its upper limit.

[0003] To overcome the limitations of 2D memory structures, the industry has developed memory with three-dimensional structures to increase storage density.

[0004] However, as the integration requirements of memory increase, how to properly arrange the layout of various gate lines to reduce mutual interference between gate lines remains a problem to be overcome. Summary of the Invention

[0005] This application provides a semiconductor device and its fabrication method, as well as a memory system, which can improve the yield and reliability of the memory.

[0006] A first region, the first region comprising a semiconductor pillar array, the semiconductor pillar array comprising a plurality of semiconductor pillars arranged in an array along a first direction and a second direction and extending upward in a third direction; the first direction, the second direction and the third direction intersect each other; and,

[0007] Each of the semiconductor pillars has a gate structure extending along the first direction on one side wall;

[0008] A shielding structure extending along the first direction is provided between adjacent semiconductor pillars; the gate structures on the sidewalls of adjacent semiconductor pillars are located on different sides, and the gate structures and the shielding structures are located on different sides of the same semiconductor pillar;

[0009] Wherein, the dimension of the gate structure along the first direction is smaller than the dimension of the shielding structure along the first direction, and the orthogonal projection of the gate structure along the second direction is within the range of the orthogonal projection of the shielding structure.

[0010] Secondly, this application also provides a method for fabricating a semiconductor device, comprising:

[0011] Provide a substrate;

[0012] A first groove is formed in the substrate, extending along a second direction and spaced apart along a first direction; the first direction intersects the second direction.

[0013] Deposit a dielectric material in the first groove;

[0014] A second groove and a third groove extending along the first direction are formed in the substrate. The second groove and the third groove are arranged alternately along the second direction, and the size of the second groove along the first direction is smaller than the size of the third groove along the first direction. The orthographic projection of the second groove along the second direction is located within the range of the orthographic projection of the third groove.

[0015] A grid structure is formed within the second groove;

[0016] A shielding structure is formed within the third groove.

[0017] Thirdly, this application also provides a storage system, including: a memory controller and a three-dimensional memory, the memory controller being coupled to the three-dimensional memory and used to control the storage of data in the three-dimensional memory, the three-dimensional memory including one or more semiconductor devices as described in the first aspect.

[0018] The beneficial effects of this application are as follows: The extension dimension of the shielding structure in the first direction is larger than the extension dimension of the gate structure in the first direction. With this design, the shielding structure can be led out through the end of the extension that exceeds the gate structure in the first direction, which facilitates the lead-out while reducing interference between different signals and improving the stability of the semiconductor device. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a cross-sectional view of the semiconductor device provided in the embodiments of this application;

[0021] Figure 2 This is a top view of the substrate of the semiconductor device provided in the embodiments of this application;

[0022] Figure 3 This is a top view of the formation of the first groove provided in an embodiment of this application;

[0023] Figure 4 The first groove is formed in the embodiment of this application. Figure 3 A cross-sectional view of the EE' cutting line;

[0024] Figure 5 This is a top view of the deposition medium material in the first groove provided in an embodiment of this application;

[0025] Figure 6This is a cross-sectional view of the medium material deposited in the first groove according to an embodiment of this application;

[0026] Figure 7 This is a top view of the formation of the second and third grooves provided in the embodiments of this application;

[0027] Figure 8 The second and third grooves provided in the embodiments of this application are formed in Figure 7 A cross-sectional view of the AA' cutting line;

[0028] Figure 9 This is a top view of the shielding structure and gate structure provided in the embodiments of this application;

[0029] Figure 10 This is a cross-sectional view of the shielding structure and gate structure provided in an embodiment of this application;

[0030] Figure 11 This is a cross-sectional view of the shielding structure and gate structure provided in the embodiments of this application;

[0031] Figure 12 This is a top view of a semiconductor device provided in an embodiment of this application;

[0032] Figure 13 The semiconductor device provided in the embodiments of this application is in Figure 12 A cross-sectional view of the cutting line BB' in the middle;

[0033] Figure 14 This is another top view of the semiconductor device provided in the embodiments of this application;

[0034] Figure 15 and Figure 16 The semiconductor device provided in the embodiments of this application is in Figure 14 A cross-sectional view of the CC' cutting line;

[0035] Figure 17 and Figure 18 The semiconductor device provided in the embodiments of this application is in Figure 14 A cross-sectional view of the DD' cutting line;

[0036] Figure 19 This is another top view of the semiconductor device provided in the embodiments of this application;

[0037] Figure 20 and Figure 21 The semiconductor device provided in the embodiments of this application is in Figure 19 A cross-sectional view of the DD' cutting line;

[0038] Figure 22 This is a structural diagram of the semiconductor device provided in the embodiments of this application;

[0039] Figure 23 This is a schematic flowchart of a method for fabricating a semiconductor device according to an embodiment of this application;

[0040] Figure 24 This is a schematic diagram of the storage system provided in an embodiment of this application. Detailed Implementation

[0041] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. In addition, it should be understood that the specific embodiments described herein are only for illustration and explanation of this application and are not intended to limit this application. In this application, unless otherwise stated, directional terms such as "upper" and "lower" generally refer to the upper and lower positions of the device in actual use or operation, specifically the drawing directions in the accompanying drawings; while "inner" and "outer" refer to the outline of the device.

[0042] As the density of semiconductor memory devices continues to increase, memory cells are shrinking in physical size. Word lines within a memory cell are physically closer together, increasing capacitive coupling between adjacent word lines. When the number of accesses to a particular row in a memory cell exceeds a threshold, it can cause data anomalies in nearby rows. This phenomenon is commonly known as the row hammer effect. The row hammer effect refers to the phenomenon where, when a word line is repeatedly accessed repeatedly over a certain period, an adjacent word line sharing a bit line with that word line may open, resulting in the loss of information from its capacitor.

[0043] Dynamic Random Access Memory (DRAM) is a commonly used semiconductor storage device in computers. It consists of many repeating memory cells, and different memory cells need to be selected via word lines and bit lines. DRAM includes a memory cell region composed of multiple memory cells and a peripheral area composed of control circuitry. Each memory cell contains a transistor electrically connected to a capacitor. The transistor controls the storage or release of charge in the capacitor to achieve the purpose of storing data. The control circuitry uses word lines (WL) and bit lines (BL) that span the memory region and are electrically connected to each memory cell to locate each memory cell and control its data access.

[0044] As the manufacturing processes of semiconductor devices such as Dynamic Random Access Memory (DRAM) become more refined, row hammer effects often occur as device sizes shrink. Because DRAM contains a large number of word lines arranged adjacent to each other, when a row hammer effect occurs on a particular word line, memory cells on adjacent word lines may experience data errors.

[0045] In some related technologies, DRAM periodically performs refresh operations to retain the charge stored in the memory cells and prevent data loss. Increasing the frequency of the refresh cycle can mitigate the damage caused by the row hammer effect to some extent, ensuring that each row is refreshed before the row hammer effect can cause sufficient damage to the cell charge to produce an error. However, the above method consumes unnecessary time or power to refresh other rows that have not experienced the row hammer effect, making it impossible for the memory device receiving the refresh command to limit its refresh range to the row hammer-affected rows. Therefore, it requires increased system power and also reduces system performance because the additional refresh cycles reduce the memory system bandwidth.

[0046] like Figure 1 The diagram shows a partial cross-sectional view of a semiconductor device 1000 with a transistor array (not shown). The transistor array includes columnar channels 103 and comprises transistors arranged in an array. Each of the columnar channels 103 in the transistor array is distributed along a first direction and a second direction. The extending direction of each columnar channel 103 is perpendicular to the plane formed by the first and second directions. Each columnar channel 103 has a gate oxide layer 104 and a gate structure 102 on one sidewall. The gate structure 102 extends along the first direction. Each columnar channel 103 has a source region 101 and a drain region 105 at its two ends along the extending direction. In some embodiments, the positions of the source region 101 and the drain region 105 can be interchanged. Here, the X direction is the first direction, and the Y direction is the second direction. However, as... Figure 1As shown, the columnar channel 103 coupled to the unselected word line adjacent to the selected word line is easily affected. This is mainly manifested in the fact that activity on the adjacent word line can cause charge changes in the cells of the unselected word line, posing a risk to the information stored therein. For example, when the selected word line connected to columnar channel 103a is active, it can interfere with the adjacent columnar channel 103b, affecting the device's performance, thus requiring further improvement. In some related technologies, an air gap structure is formed between adjacent columnar channels 103, but this method has high requirements for process consistency. Alternatively, in other related technologies, a metal layer (not shown in the figure) is formed between adjacent columnar channels 103 for electrical isolation of the adjacent columnar channels 103. However, since subsequent processes require the implementation of bit lines, word lines, and metal layers, the circuit wiring in the memory array area is more complex, the manufacturing process is more difficult, and the cost increases.

[0047] To improve the above problems, refer to Figures 2 to 24 As shown, embodiments of this application provide a semiconductor device 100, its fabrication method, and a memory system. The shielding structure 30 has an extension dimension in a first direction that is larger than the gate structure 10's extension dimension in the first direction. This allows the shielding structure 30 to be led out through an end extending beyond the gate structure 10 along the first direction. This separate lead-out of the shielding structure 30 not only facilitates its exit but also eliminates the hammer effect. The semiconductor device 100 of this application has low manufacturing costs and improves the yield loss problem caused by the hammer effect, reducing the requirements for process consistency, simplifying the manufacturing process, and lowering manufacturing costs.

[0048] Please see Figure 23 The diagram shown is a flowchart illustrating the fabrication method of the semiconductor device 100 provided in this embodiment of the application. A detailed flowchart is provided below. Figures 2 to 22 The structural diagram may include the following steps:

[0049] Step S100, as follows Figure 2 As shown, a substrate 1 is provided;

[0050] Step S200, as follows Figure 3 A first groove K1 is formed in the substrate 1, extending along the second direction Y and spaced along the first direction X; the first direction X intersects the second direction Y.

[0051] In some embodiments, there is an angle between the first direction X and the second direction Y, and an angle between the third direction Z and the plane containing the first direction X and the second direction Y, wherein the angle is less than or equal to 90 degrees. For example, in some embodiments of this application, the first direction X is defined as the X direction, the second direction Y as the Y direction, and the third direction Z as the Z direction.

[0052] In some embodiments of this application, the substrate 1 may include, for example: Figure 12 and Figure 14 The first region R1 is shown. The first region R1 may include a core device region for forming transistor arrays, memory cells, and / or other desired components. The transistor array includes multiple transistors, each transistor including a semiconductor pillar 20, and additionally, as shown... Figure 22 As shown, the semiconductor pillar 20 extends along the third direction Z at opposite ends to form the source 145 and drain 141 of the transistor, respectively, and the sidewall of the semiconductor pillar 20 is provided with the gate structure 10 of the transistor.

[0053] In some embodiments, substrate 1 is a material used to fabricate semiconductor device 100. The material of substrate 1 may include silicon (e.g., single-crystal silicon, polycrystalline silicon), silicon germanium (SiGe), silicon carbide (SiC), gallium nitride (GaN), indium phosphide (InP), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any suitable combination thereof. Substrate 1 may include a wafer formed from cylindrical single-crystal silicon through steps such as grinding, polishing, and slicing.

[0054] Figures 2-22 This is a schematic diagram of the manufacturing process of a semiconductor device 100 provided in an embodiment of this application. It should be noted that, as in the embodiments of this application... Figures 2-22 The following explanation is based on the example of gate structures 10 on the sidewalls of adjacent semiconductor pillars 20 located on different sides.

[0055] In some embodiments, step S200, which involves forming first grooves K1 extending along the second direction Y and spaced apart along the first direction X in the substrate 1, includes: from... Figure 2 The substrate 1 shown is etched to form first grooves K1 extending along the second direction Y and spaced apart along the first direction X, and the first grooves K1 can extend to the substrate 1 along the third direction Z. That is, as shown Figure 1 , Figure 2 and Figure 3 As shown, the substrate 1 is etched from the surface of the substrate 1 along the third direction Z to form a plurality of first grooves K1 extending along the second direction Y and spaced apart along the first direction X.

[0056] In some embodiments, the substrate 1 can be etched using processes such as photolithography (PH) or dry etching (ET), for example, electron beam lithography, plasma etching, or reactive ion etching. Some embodiments of this application are not limited to these methods.

[0057] like Figure 2 , Figure 3 and Figure 4 As shown, during the etching process of substrate 1, a portion of the surface of substrate 1, i.e., the areas where the first groove K1 needs to be formed, can be covered by a mask (not shown in the figure). Then, the surface of substrate 1 is etched along the thickness direction of substrate 1 (i.e., the third direction Z). Outside the area covered by the mask, a portion of the semiconductor material of substrate 1 is etched away to form a groove of a certain depth, i.e., the aforementioned first groove K1.

[0058] In some embodiments, the etching depth for forming the first groove K1 is less than the initial thickness of the substrate 1, i.e., the etching process will not penetrate the substrate 1, thereby removing a portion of the semiconductor material of the substrate 1 to form the first groove K1.

[0059] In some embodiments of this application, by etching the entire surface of the substrate 1 to simultaneously form multiple first grooves K1 with the same depth, the manufacturing process can be simplified and efficiency improved.

[0060] Step S300: Deposit medium material 401 in the first groove K1.

[0061] In some embodiments of this application, Figure 5 A top view of the deposition medium material 401 in the first groove K1 provided for some embodiments of this application. Figure 6 A cross-sectional view of a medium material 401 deposited in a first groove K1, provided for some embodiments of this application. Formed as... Figure 3 and Figure 4 After the first groove K1 shown, as Figure 5 and Figure 6 As shown, a medium material 401 is deposited in the first groove K1 using a deposition process.

[0062] In some embodiments, the dielectric material 401 includes, but is not limited to, any one or any combination of polycrystalline silicon, silicon nitride, silicon oxide, and aluminum oxide. Here, silicon oxide refers to silicon oxide compounds, such as SixOy, and silicon nitride refers to silicon nitrogen compounds, such as SixNy.

[0063] Due to such Figure 3 and Figure 4 As shown, a first groove K1 is formed, and multiple first grooves K1 are arranged at intervals along the first direction X. Therefore, in the substrate 1, there are raised structures 211 between the first grooves K1 formed by removing part of the semiconductor material to separate adjacent first grooves K1. It should be noted that during the actual deposition of the dielectric material 401, the dielectric material 401 will cover the surface of the raised structure 211, such as... Figure 5As shown, each protruding structure 211 is surrounded by a dielectric material 401. Additionally, after deposition, a chemical mechanical polishing (CMP) process can be used to remove excess dielectric material 401.

[0064] In some embodiments of this application, the deposition method of the dielectric material 401 may be, but is not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma-enhanced chemical vapor deposition (PECVD), sputtering, metal-organic chemical vapor deposition (MOCVD), and atomic layer deposition (ALD).

[0065] Step S400: A second groove K2 and a third groove K3 extending along the first direction X are formed in the substrate 1. The second groove K2 and the third groove K3 are arranged alternately along the second direction Y. The size of the second groove K2 along the first direction X is smaller than the size of the third groove K3 along the first direction X. The orthographic projection of the second groove K2 along the second direction Y is located within the range of the orthographic projection of the third groove K3.

[0066] In some embodiments of this application, after the first groove K1 is filled with dielectric material 401, a second groove K2 and a third groove K3 extending along the first direction X are formed in the substrate 1. A plurality of second grooves K2 and a plurality of third grooves K3 are staggered along the second direction Y, and the semiconductor pillar 20 is located between adjacent second grooves K2 and third grooves K3, i.e. Figure 7 , Figure 8 As shown, the second groove K2 and the third groove K3 are staggered along the second direction Y. Simultaneously forming the second groove K2 extending along the first direction X and the third groove K3 extending along the first direction X simplifies the manufacturing process and improves efficiency. Of course, in this embodiment, the second groove K2 and the third groove K3 can also be formed sequentially in stages.

[0067] like Figure 7As shown, the first etching length of the second groove K2 (i.e., the extension dimension L1 of the second groove K2 along the first direction X) is less than the second etching length of the third groove K3 (i.e., the extension dimension L2 of the second groove K2 along the first direction X). The etching length can be controlled by etching process parameters (e.g., etching time, gas flow rate, ratio, pressure, temperature, etc.). For example, with a constant etching rate, a longer etching time results in a wider groove in the first direction X. In one embodiment of this application, the etching process parameters can be adjusted so that the second etching length of the third groove K3 is greater than the first etching length of the second groove K2. The etching method can be dry etching, such as plasma etching.

[0068] In some embodiments of this application, the method of manufacturing the semiconductor device 100 may further include the steps of: making the size of the second groove K2 along the third direction Z larger than the size of the third groove K3 along the third direction Z, and the orthographic projection of the second groove K2 along the second direction Y is located within the range of the orthographic projection of the third groove K3, wherein the first direction X, the second direction Y and the third direction Z intersect each other.

[0069] In some embodiments, etching the substrate 1 can be performed, for example, using a dry etching process or a wet etching process. If a dry etching process is used to etch the substrate 1, the extension dimensions of the second groove K2 and the third groove K3 along the third direction Z can be controlled by controlling the dry etching time, such as... Figure 8 As shown, the first etching depth of the second groove K2 (i.e., the extension dimension H1 along the third direction Z) is greater than the second etching depth of the third groove K3 (i.e., the extension dimension H2 along the third direction Z).

[0070] In some embodiments, the etching depth can be controlled by etching process parameters (e.g., etching time, gas flow rate, ratio, pressure, temperature, etc.). For example, with a constant etching rate, a longer etching time results in a deeper groove in the third direction (Z). In one embodiment of this application, the etching process parameters can be adjusted so that the first etching depth of the second groove K2 is greater than the second etching depth of the third groove K3. The etching method can be dry etching, such as plasma etching.

[0071] Figure 7 A top view showing the etching forming of the second groove K2 and the third groove K3, provided for some embodiments of this application. Figure 8 Cross-sectional views showing the etching forming of the second groove K2 and the third groove K3, provided for some embodiments of this application. (See attached image.) Figure 7 and Figure 8As shown, a portion of the dielectric material filling the spaces between the protrusions 211 in the substrate 1 is removed to form a second groove K2 and a third groove K3. Multiple second grooves K2 and third grooves K3, spaced apart along the second direction Y, expose adjacent protrusions, thereby forming a shape along the second direction Y as shown in the diagram. Figure 7 The semiconductor pillars 20 shown are arrayed between the second groove K2 and the third groove K3.

[0072] The semiconductor pillars 20 are used to transfer or stop charge transfer under the action of an applied electric field, thereby turning the transistor on or off. Each semiconductor pillar 20 extends perpendicularly to the substrate 1. Here, the extension direction of the semiconductor pillars 20 corresponds to the direction of the current when the transistor is on. The semiconductor pillars 20 are arranged in an array along the first direction X and the second direction Y.

[0073] In some embodiments, such as Figure 7 and Figure 8 As shown, the second groove K2 exposes the semiconductor pillars 20 distributed in the array, with the semiconductor pillars 20 located in the same column; the gate structures 10 of the semiconductor pillars 20 located in the same column are interconnected, and the interconnected gate structures 10 are word lines of the semiconductor pillars 20 in the same column. The word lines can provide word line voltages, and the word line voltages control the conduction or cutoff of each transistor.

[0074] Step S500: Form a grid structure in the second groove K2;

[0075] Step S600: A shielding structure 30 is formed in the third groove K3.

[0076] In some embodiments, such as Figure 7 and Figure 8 As shown, after forming the second groove K2 and the third groove K3, it can be as follows: Figure 9 As shown, sacrificial material is deposited in the second groove K2. A mask can be used to remove a portion of the sacrificial material filling the third groove K3, and then metal material is deposited to form a shielding structure 30. Sacrificial material is also deposited in the third groove K3. A mask can be used to remove a portion of the sacrificial material filling the second groove K2, and then a gate dielectric layer 510 is formed along the inner wall of the second groove K2. Metal material is then deposited on the sidewalls of the gate dielectric layer 510 to form a gate structure 10.

[0077] In some embodiments, a grid structure can be formed in the second groove K2 first, and then a shielding structure 30 can be formed in the third groove K3. Alternatively, a shielding structure 30 can be formed in the third groove K3 first, and then a grid structure can be formed in the second groove K2. Or, a grid structure can be formed simultaneously in the second groove K2 and a shielding structure 30 can be formed in the third groove K3.

[0078] In some embodiments, the deposition method for metallic materials may include, but is not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma-enhanced chemical vapor deposition (PECVD), sputtering, metal-organic chemical vapor deposition (MOCVD), and atomic layer deposition (ALD).

[0079] In some embodiments of this application, the shielding structure 30 is formed simultaneously with the formation process of the gate structure 10, so that the shielding structure 30 can be formed without adding additional process steps. This can shield the interference of the gate structure 10 to the adjacent semiconductor pillars 20, thereby improving the coupling effect between the gate structure 10 and the adjacent semiconductor pillars 20.

[0080] In some embodiments, the above steps S100 to S600 are used to form a... Figure 12 The semiconductor device 100 shown includes:

[0081] A first region R1, the first region R1 including a semiconductor pillar array, the semiconductor pillar array including a plurality of semiconductor pillars 20 arranged in a first direction X and a second direction Y and extending in a third direction Z; the first direction X, the second direction Y and the third direction Z intersect each other; and,

[0082] Multiple gate structures 10 and shielding structures 30 extending along a first direction X; the gate structures 10 and the shielding structures 30 are staggered along a second direction Y, and the semiconductor pillars 20 are located between adjacent shielding structures 30 and gate structures 10;

[0083] Wherein, the size of the gate structure 10 along the first direction X is smaller than the size of the shielding structure 30 along the first direction X, and the orthographic projection of the gate structure 10 along the second direction Y is within the range of the orthographic projection of the shielding structure 30.

[0084] Specifically, the shielding structure 30 overlaps with the orthographic projection of the gate structure 10 in the first direction X. The extension dimension of the shielding structure 30 in the first direction X is larger than the extension dimension of the gate structure 10 in the first direction X. Furthermore, the orthographic projection of the end of the gate structure 10 in the first direction X in the second direction Y overlaps within the orthographic projection of the end of the shielding structure 30 in the first direction X in the second direction Y. In one embodiment of this application, the etching process parameters can be adjusted to achieve the following... Figure 7 The second etching length (extension dimension L2 in the first direction X) of the third groove K3 shown is greater than the first etching length (extension dimension L1 in the first direction X) of the second groove K2. Thus, as... Figure 9 , Figure 12 and Figure 14 As shown, the shielding structure 30 formed in the third groove K3 can have an extension dimension l2 in the first direction X that is greater than the extension dimension l1 in the first direction X of the gate structure 10 formed in the second groove K2, and the end of the gate structure 10 in the first direction X is located within the range of the end of the shielding structure 30 in the first direction X.

[0085] In some embodiments, the dimension of the gate structure 10 along the third direction Z is greater than the dimension of the shielding structure 30 along the third direction Z, and the orthogonal projection of the gate structure 10 along the second direction Y is within the range of the orthogonal projection of the shielding structure 30.

[0086] Specifically, the shielding structure 30 overlaps with the orthographic projection of the gate structure 10 in the third direction Z. The extension dimension of the shielding structure 30 in the third direction Z is smaller than the extension dimension of the gate structure 10 in the third direction Z. Furthermore, the orthographic projection of the shielding structure 30 in the third direction Z in the second direction Y overlaps within the orthographic projection of the end of the gate structure 10 in the third direction Z in the second direction Y. In one embodiment of this application, the etching process parameters can be adjusted so that the first etching depth of the second groove K2 (extension dimension H1 in the third direction Z) is greater than the second etching depth of the third groove K3 (extension dimension H2 in the third direction Z). Thus, as... Figure 10 , Figure 11 and Figure 13 As shown, the extension dimension h1 of the gate structure 10 formed in the second groove K2 in the third direction Z is greater than the extension dimension h2 of the shield structure 30 formed in the third groove K3 in the third direction Z, and the end of the shield structure 30 in the third direction Z is located within the range of the end of the gate structure 10 in the third direction Z.

[0087] In some embodiments, the first surface of the shielding structure 30 that is away from the substrate 1 is not higher than the first surface of the gate structure 10 that is away from the substrate 1, and the second surface of the shielding structure 30 that is close to the substrate 1 is not lower than the second surface of the gate structure 10 that is close to the substrate 1.

[0088] For example, such as Figure 10 As shown, the top surface of the first surface of the shielding structure 30 away from the substrate 1 along the third direction Z (hereinafter referred to as the top surface for ease of description) is flush with the top surface of the gate structure 10 along the third direction Z, and the second surface of the shielding structure 30 close to the substrate 1 along the third direction Z (hereinafter referred to as the bottom surface for ease of description) is higher than the bottom surface of the gate structure 10 along the third direction Z.

[0089] For example, such as Figure 11 , Figure 13 and Figure 15 As shown, the top surface of the shielding structure 30 along the third direction Z is lower than the top surface of the gate structure 10 along the third direction Z, and the bottom surface of the shielding structure 30 along the third direction Z is higher than the bottom surface of the gate structure 10 along the third direction Z.

[0090] In some embodiments of this application, the gate structure 10 includes a first gate 111 and a second gate 112 adjacent to each other in the second direction Y, wherein the first gate 111 and the second gate 112 are respectively located on one side of the semiconductor pillar 20 adjacent to it.

[0091] In some embodiments, such as Figure 13 As shown, the gate structure 10 includes a first gate 111 and a second gate 112 extending along a first direction X. The first gate 111 and the second gate 112 in the same gate structure 10 are adjacent in the second direction Y, and the first gate 111 and the second gate 112 are respectively located on one side of the adjacent semiconductor pillar 20. For example, as... Figure 13 As shown, semiconductor pillars 20a and 20b are adjacent in the second direction Y, and a gate structure 10 is located between semiconductor pillars 20a and 20b. In the gate structure 10, the first gate 111 is located on the side closer to semiconductor pillar 20a along the second direction Y, and the second gate 112 is located on the side closer to semiconductor pillar 20b along the second direction Y.

[0092] In some embodiments of this application, such as Figure 7 , Figure 8 , Figure 9 and Figure 10As shown, the exposed sidewalls of the semiconductor pillar 20 are oxidized through the second groove K2 to form a gate dielectric layer 510 on the sidewalls of the semiconductor pillar 20. The oxidation process for the exposed sidewalls of the semiconductor pillar 20 within the second groove K2 includes, but is not limited to, direct oxidation, alkaline oxidation, or acidic oxidation. In some embodiments of this application, direct oxidation is performed by heating, causing the silicon on the sidewalls of the semiconductor pillar 20 to chemically react with a gas containing oxidizing substances at high temperature, thereby generating a dense silicon dioxide film on the silicon surface, forming the gate dielectric layer 510 located on the sidewalls of the semiconductor pillar 20. The gate dielectric layer 510 includes an insulating material, such as silicon oxide or silicon oxynitride. The gate dielectric layer 510 is located between the semiconductor pillar 20 and... Figure 9 , Figure 10 , Figure 11 and Figure 22 Between the first gate 111 or the second gate 112 of the formed gate structure 10, the gate dielectric layer 510 is used to isolate the gate structure 10 from the semiconductor pillar 20, so as to avoid direct contact between the gate structure 10 and the semiconductor pillar 20 and charge leakage.

[0093] like Figure 9 , Figure 10 and Figure 11 As shown, the specific description of the gate structure 10 and the shielding structure 30 formed in the second groove K2 and the third groove K3 respectively can be found in the corresponding embodiments of S500 to S600 above, and will not be repeated here.

[0094] In some embodiments, such as Figure 7 , Figure 12 , Figure 14 and Figure 19 As shown, the extension dimension l2 of the shielding structure 30 along the first direction X is greater than the extension dimension l1 of the gate structure 10 along the first direction X, i.e., l2 > l1. Figure 10 , Figure 11 , Figure 12 , Figure 13 , Figure 15 and Figure 22 As shown, the extension dimension h1 of the shielding structure 30 along the extension direction (i.e., the third direction Z) of the semiconductor pillar 20 is smaller than the extension dimension h2 of the gate structure 10 along the extension direction (i.e., the third direction Z) of the semiconductor pillar 20, i.e., h1 < h2. The aforementioned extension dimensions along the first direction X and along the third direction Z can be adjusted as follows: Figure 7 and Figure 8 The etching length and etching depth of the third groove K3 and the second groove K2 shown are controlled by the etching process parameters, including but not limited to etching time, etching gas flow rate, ratio, pressure, temperature, etc.

[0095] In some embodiments, the semiconductor device 100 further includes a second region R2, which is arranged with the first region R1 along the first direction X; the second region R2 includes a first conductive portion 210, which includes a first lead-out structure 40 extending along the third direction Z and a first connector 60 extending along the first direction X; the two ends of the first lead-out structure 40 along the third direction Z are respectively contacted and connected to the first connector 60 and the gate structure 10; the first conductive portion 210 is located on one side of the shielding structure 30 along the third direction Z.

[0096] Specifically, the second region R2 may include, but is not limited to, a transition region for connecting the first region R1. For example... Figure 14 and Figure 19 As shown, a first region R1 and a second region R2 are arranged in a first direction X. The second region R2 includes a first conductive portion 210, and the gate structure 10 in the first region R1 can be connected to the first conductive portion 210 in the second region R2. (Reference) Figure 15 , Figure 16 and Figure 22 The first conductive part 210 includes a first lead-out structure 40 and a first connector 60, such as Figure 15 and Figure 16 The first connector 60 shown extends along the first direction X, as... Figure 22 The first lead-out structure 40 shown extends along the third direction Z. As... Figure 15 and Figure 16 As shown, the two ends of the first lead-out structure 40 along the third direction Z are respectively connected to the first connector 60 and the gate structure 10. The first conductive part 210 can be located on any side of the shielding structure 30 along the third direction Z.

[0097] In some examples, the first conductive portion 210 may be located on a first side of the shielding structure 30 along the third direction Z. For example... Figure 15 As shown, the bottom surface of the gate structure 10 along the third direction Z is connected to the top surface of the first lead-out structure 40 along the third direction Z, and the bottom surface of the first lead-out structure 40 along the third direction Z is connected to the top surface of the first connector 60 along the third direction Z. The bottom surface of the first connector 60 along the third direction Z can be connected to the peripheral circuit. In this way, the first conductive part 210 can be led out from the front side of the substrate 1.

[0098] In some examples, the first conductive portion 210 may be located on the second side of the shielding structure 30 along the third direction Z. For example... Figure 16As shown, the top surface of the gate structure 10 along the third direction Z is connected to the bottom surface of the first lead-out structure 40 along the third direction Z, and the top surface of the first lead-out structure 40 along the third direction Z is connected to the bottom surface of the first connector 60 along the third direction Z. The top surface of the first connector 60 along the third direction Z can be connected to the peripheral circuit, so that the first conductive part 210 can be led out from the back side of the substrate 1.

[0099] In some embodiments, the semiconductor device 100 includes a plurality of first regions R1 and a plurality of second regions R2, two adjacent first regions R1 along the first direction X are connected through a second region R2, and the gate structures 10 in two adjacent first regions R1 are connected through the first conductive portion 210.

[0100] Specifically, such as Figure 14 and Figure 19 Only two alternately connected first regions R1 and one second region R2 are shown as an example, with first region R1a connected to first region R1b via second region R2. In other embodiments, semiconductor device 100 may also include three or two alternately connected first regions R1. Of course, semiconductor device 100 including other numbers and arrangements of first regions R1 and second regions R2 are all within the scope of protection of this application and are not limited thereto.

[0101] For ease of explanation, this application uses the example of two alternating first regions R1 and one second region R2 along the first direction X, as shown below. Figure 14 and Figure 19 As shown, two first regions R1 and a second region R2 are arranged alternately in the first direction X. The second region R2 is located between two adjacent first regions R1. The second region R2 includes a first conductive part 210. The gate structures 10 in two adjacent first regions R1 are connected through the first lead-out structure 40 of the first conductive part 210. Then the first lead-out structure 40 is connected to the first connector 60 of the first conductive part 210, so that multiple gate structures 10 in two adjacent first regions R1 are connected through the first conductive part 210 in the second region R2.

[0102] In some embodiments, the materials of the first connector 60 and the first lead-out structure 40 of the first conductive portion 210 may include conductive materials, including but not limited to: tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicides, or any combination thereof.

[0103] In some embodiments, the second region R2 further includes a second conductive portion 220 extending along the second direction Y, and the plurality of shielding structures 30 in the first region R1 are connected through the second conductive portion 220.

[0104] Specifically, this application illustrates this by using the example of two alternating first regions R1 and one second region R2 along the first direction X, such as... Figure 14 and Figure 19 As shown, two first regions R1 and a second region R2 are arranged alternately in the first direction X. The second region R2 is located between two adjacent first regions R1. The second region R2 includes a second conductive part 220. The shielding structures 30 in two adjacent first regions R1 are connected through the second conductive part 220, so that multiple shielding structures 30 in two adjacent first regions R1 are connected through the second conductive part 220 in the second region R2.

[0105] like Figure 14 , Figures 17 to 21 As shown, the second region R2 also includes a second conductive part 220. The plurality of shielding structures 30 in the first region R1 are connected through the second conductive part 220, meaning one end of each shielding structure 30 is connected to the second conductive part 220. The second conductive part 220 can be located on any side of the shielding structure 30 along the third direction Z.

[0106] In some embodiments, the first region R1 further includes:

[0107] A bit line 120 located on one side of the semiconductor pillar 20 and connected to the drain of the semiconductor pillar 20 along the third direction Z, the bit line 120 extending along the second direction Y;

[0108] The second conductive portion 220 along the third direction Z is located on the side of the shielding structure 30 that is relatively close to the bit line 120.

[0109] Specifically, such as Figure 13 , Figure 14 , Figure 19 and Figure 22 As shown, the first region also includes a bit line 120. The semiconductor pillar 20 includes a source 145 and a drain 141 located on opposite sides along the third direction Z. The source 145 and drain 141 of the transistor are located on opposite sides of the semiconductor pillar 20 along the third direction Z. It can be understood that the source 145 and drain 141 of the transistor are relative concepts, and the source 145 and drain 141 can be either end of the semiconductor pillar 20 along the third direction Z. The bit line 120 extending along the first direction X is located on one side of the semiconductor pillar 20 along the third direction Z. The bit line 120 is connected to the drain 141 of the semiconductor pillar 20. The second conductive portion 220 along the third direction Z is located on the side of the shielding structure 30 relatively close to the bit line 120.

[0110] In some embodiments, a bit line 120 is located on one side of the semiconductor pillar 20 and connected to the drain of the semiconductor pillar 20 along the third direction Z, and the bit line 120 extends along the second direction Y.

[0111] The second conductive portion 220 along the third direction Z is located on the side of the shielding structure 30 that is relatively far away from the bit line 120.

[0112] like Figure 13 , Figure 14 , Figure 19 and Figure 22 As shown, the first region also includes a bit line 120. The semiconductor pillar 20 includes a source 145 and a drain 141 located on opposite sides along the third direction Z. The source 145 and drain 141 of the transistor are located on opposite sides of the semiconductor pillar 20 along the third direction Z. It can be understood that the source 145 and drain 141 of the transistor are relative concepts, and the source 145 and drain 141 can be either end of the semiconductor pillar 20 along the third direction Z. The bit line 120 extending along the first direction X is located on one side of the semiconductor pillar 20 along the third direction Z. The bit line 120 is connected to the drain 141 of the semiconductor pillar 20. The second conductive portion 220 along the third direction Z is located on the side of the shielding structure 30 relatively away from the bit line 120. The following description is based on a specific device of the second conductive portion 220.

[0113] In some embodiments, the second conductive portion 220 includes a second connector 80 extending along the second direction Y, the second connector 80 being connected to a plurality of the shielding structures 30, and the side of the gate structure 10 closest to the second connector 80 having a distance L3 from the second connector 80 in the first direction X.

[0114] Specifically, such as Figure 14 , Figure 17 , Figure 18 and Figure 19 As shown, the second conductive portion 220 includes a second connector 80 extending along the second direction Y. A plurality of shielding structures 30 are connected to the second connector 80, and the side of the gate structure 10 closest to the second connector 80 has a distance L3 between it and the second connector 80 in the first direction X. The value of the distance L3 can be set by the user. Figure 14 and Figure 19 As shown, the side of the gate structure 10 closest to the second connector 80, i.e. the side closest to the first lead-out structure 40 in the first conductive part 210, has a distance L3 between it and the second connector 80 extending along the second direction Y in the first direction X, which facilitates the lead-out of the gate structure 10.

[0115] In some embodiments, the second conductive portion 220 may include a second connector 80 located on a first side of the shielding structure 30 along the third direction Z. Furthermore, the second conductive portion 220 may also include a second connector 80 located on a second side of the shielding structure 30 along the third direction Z. The second conductive portion 220 may also include a second connector 80 located on the first side of the shielding structure 30 along the third direction Z, and another second connector 80 located on the second side of the shielding structure 30 along the third direction Z. The material of the second connector 80 may include a conductive material, including but not limited to: tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicides, or any combination thereof.

[0116] In some embodiments, the second conductive portion 220 further includes at least one second lead-out structure 70 extending along the third direction Z, the second lead-out structure 70 being connected to the second connector 80, and the second lead-out structure 70 being located at one end of the second connector 80 away from the plurality of shielding structures 30 in the second direction Y.

[0117] Specifically, such as Figure 14 , Figure 17 , Figure 18 and Figure 19 As shown, the second conductive portion 220 further includes at least one second lead-out structure 70 extending in the third direction Z. Figure 17 and Figure 18 As shown, the second lead-out structure 70 is connected to the second connector 80, and the second lead-out structure 70 is located at the end of the second connector 80 away from the plurality of shielding structures 30 in the second direction Y. That is, the end of the second connector 80 along the second direction Y has a certain distance from the outermost shielding structures 30 arranged at intervals in the second direction Y. For example, as Figure 17 As shown, the second lead-out structure 70 is located at one end of the second connector 80 in the second direction Y, away from the outermost shielding structure 30a among the plurality of shielding structures 30, or the second lead-out structure 70 is located at one end of the second connector 80 in the second direction Y, away from the outermost shielding structure 30b among the plurality of shielding structures 30. This arrangement, where a second lead-out structure 70 is located away from the outermost shielding structure 30a (or 30b) along the second direction Y, creates a gap between the second lead-out structure 70 and the outermost shielding structure 30a (or 30b), which helps reduce the crosstalk / coupling effect between the shielding structure 30 (including conductive material) and the second lead-out structure 70, thereby improving device performance.

[0118] The second lead-out structure 70 is made of a conductive material, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicides, or any combination thereof. The second lead-out structure 70 is connected to the second connector 80 and is located at one end along the second direction Y, away from the plurality of spaced-apart shielding structures 30. For example, as... Figure 14 , Figure 17 , Figure 18 and Figure 19 A second lead-out structure 70a is connected to the first end of the second connector 80 away from the outermost shielding structure 30a in the second direction Y, and another second lead-out structure 70b is connected to the second end of the second connector 80 away from the outermost shielding structure 30b in the second direction Y. The first end of the second connector 80 and the second end of the second connector 80 can be the ends of the second connector 80 along the second direction Y, respectively.

[0119] In some embodiments, the shielding structure 30 and the second lead-out structure 70 are located on opposite sides of the second connector 80 along the third direction Z.

[0120] Specifically, such as Figure 17 and 20 As shown, the shielding structure 30 and the second lead-out structure 70 are located on opposite sides of the second connector 80 along the third direction Z. By distributing the shielding structure 30 and the second lead-out structure 70 in the second conductive part 220 on opposite sides of the second connector 80 along the third direction Z, the occupied device area can be reduced, thereby reducing the size of the semiconductor device 100.

[0121] In some examples, such as Figure 17 The second lead-out structure 70 can be located on the side of the shielding structure 30 away from the bit line 120 along the third direction Z, so that the second conductive part 220 can be led out from the front side of the substrate 1.

[0122] In some examples, such as Figure 18 The second lead-out structure 70 can also be located on the side of the shielding structure 30 away from the bit line 120 along the third direction Z. In this way, the second conductive part 220 can be led out from the back side of the substrate 1.

[0123] In some embodiments, the shielding structure 30 is in contact with the second connector 80. Specifically, such as... Figure 17 and 18 As shown, each shielding structure 30 is in direct contact with the second connector 80.

[0124] In some embodiments, the second conductive portion 220 further includes at least one third lead-out structure 71 extending along the third direction Z, each of the shielding structures 30 being connected to the second connector 80 via one of the third lead-out structures 71, the third lead-out structure 71 and the second lead-out structure 70 being located on different sides of the second connector 80 along the third direction Z.

[0125] Specifically, such as Figure 14 , Figure 19 , Figure 20 and Figure 21 As shown, the second conductive part 220 also includes at least one third lead-out structure 71 extending along a third direction Z. The number of third lead-out structures 71 can be the same as or different from the number of shielding structures 30. Multiple shielding structures 30 arranged side-by-side at intervals along the second direction Y are each connected to a second connector 80 extending along the second direction Y via a third lead-out structure 71. That is, in the third direction Z, the third lead-out structure 71 is located between the second connector 80 and the shielding structure 30, meaning that both ends of the third lead-out structure 71 in the third direction Z are in contact with the second connector 80 and the shielding structure 30 respectively, thereby enabling each shielding structure 30 to be indirectly connected to the second connector 80. It should be noted that the third lead-out structure 71 and the second lead-out structure 70 are located on different sides of the second connector 80 along the third direction Z; that is, along the third direction Z, the second connector 80 is located between the third lead-out structure 71 and the second lead-out structure 70.

[0126] The material of the third lead-out structure 71 includes conductive materials, including but not limited to: tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicides, or any combination thereof.

[0127] In some embodiments, the second conductive portion 220 further includes a third connector 50 extending along the first direction X, the third connector 50 being connected to the second connector 80 via the second lead-out structure 70.

[0128] Specifically, such as Figure 14 , Figure 17 , Figure 18 , Figure 19 , Figure 20 and Figure 21 As shown, the second conductive portion 220 also includes a third connector 50 extending along a first direction X. The third connector 50 is connected to the second connector 80 via a second lead-out structure 70, that is, the second lead-out structure 70 is located on different sides of the second connector 80 and the third connector 50 in the third direction Z, i.e., the second lead-out structure 70 is located between the third connector 50 and the second connector 80 along the third direction Z.

[0129] The material of the third connector 50 includes conductive materials, including but not limited to: tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicides, or any combination thereof.

[0130] In some embodiments, the second lead-out structure 70 and the third lead-out structure 71 may be made of the same material, and their shapes may be trapezoidal along the third direction Z, rectangular, or any other arbitrary shape. For example, the dimension of the top surface of the third lead-out structure 71 along the first direction X is smaller than the dimension of the bottom surface of the third lead-out structure 71 along the first direction X, and the dimension of the top surface of the second lead-out structure 70 along the first direction X is smaller than the dimension of the bottom surface of the second lead-out structure 70 along the first direction X.

[0131] In some embodiments, the shielding structure 30 is located on the side of the second connector 80 that is relatively far from the bit line 120 along the third direction Z.

[0132] Specifically, such as Figure 17 , Figure 18 , Figure 20 and Figure 21 As shown, along the third direction Z, the third connector 50, the second lead-out structure 70, the second connector 80, and the third lead-out structure 71 are connected to the shielding structure 30 as a whole as a second conductive part 220. If the shielding structure 30 is located on the side of the second connector 80 that is relatively far away from the bit line 120 along the third direction Z, then it is equivalent to the second conductive part 220230 being located on the side of the shielding structure 30 that is relatively close to the bit line 120 along the third direction Z. That is, the shielding structure 30 is located above the second connector 80 along the third direction Z, which also means that the shielding structure 30 is relatively far away from the bit line 120 along the third direction Z, and the second connector 80 is relatively close to the bit line 120 compared to the shielding structure 30 along the third direction Z.

[0133] In some embodiments, the shielding structure 30 is located on the side of the second connector 80 that is relatively close to the bit line 120 along the third direction Z.

[0134] Specifically, continuing from the above, since the third connector 50, the second lead-out structure 70, the second connector 80, and the third lead-out structure 71 are connected to the shielding structure 30 as a whole as a second conductive part 220 along the third direction Z, if the shielding structure 30 is located on the side of the second connector 80 relatively close to the bit line 120 along the third direction Z, then it is equivalent to the second conductive part 220230 being located on the side of the shielding structure 30 relatively far away from the bit line 120 along the third direction Z. That is to say, the shielding structure 30 is located below the second connector 80 along the third direction Z, which also means that the shielding structure 30 is relatively close to the bit line 120 along the third direction Z, and the second connector 80 is relatively far away from the bit line 120 compared to the shielding structure 30 along the third direction Z.

[0135] In specific applications, depending on different needs, the first conductive part 210 and the second conductive part 220 can be disposed on the same side or different sides of the shielding structure 30 along the third direction Z.

[0136] The gate structure 10 is led out through the first conductive part 210, and the shielding structure 30 is led out through the second conductive part 220, as shown below. Figure 22 As shown, bit line 120 is connected to the drain of semiconductor pillar 20, and as... Figure 12 , Figure 14 , Figure 19 As shown, the lead-out pads 130 of the bit line 120 are staggered along the second direction Y. When the spacing between the gate structure 10 and the shield structure 30 is small, the second conductive portion 220 of the lead-out shield structure 30 and the first conductive portion 210 of the lead-out gate structure 10 need to be staggered (set on different sides along the third direction Z). This can prevent short circuits between the gate structure 10 and the shield structure 30, and at the same time reduce the device size and improve space utilization.

[0137] Of course, in other embodiments, if the spacing between the gate structure 10 and the shielding structure 30 allows, the second conductive portion 220 leading out of the shielding structure 30 and the first conductive portion 210 leading out of the gate structure 10 can be disposed on the same side along the third direction Z, which is convenient for actual control.

[0138] The shielding structure 30, gate structure 10, semiconductor pillar 20, first conductive portion 210, and second conductive portion 220 in the above embodiments can be integrated into, for example, Figure 22 In the first semiconductor structure 601 shown.

[0139] In some embodiments, the first region further includes:

[0140] A capacitor structure located on the side of the semiconductor pillar 20 that is relatively far from the bit line 120 along the third direction Z, and extending along the third direction Z;

[0141] The capacitor structure includes a first end connected to the source of the semiconductor pillar 20, and a second end connected to the common terminal.

[0142] In this configuration, the bit line 120 is connected to the drain of the semiconductor pillar 20, one electrode of the capacitor structure 90 is connected to the source of the semiconductor pillar 20, and the other electrode of the capacitor structure 90 is connected to a common terminal (not shown in the figure). Specifically, the capacitor structure 90 is used to store data written to the semiconductor device 100. In some embodiments, the common terminal may include a low-voltage terminal and a ground terminal, wherein the low voltage may include -0.5V, -1V, etc.

[0143] In some embodiments, the shielding structure 30 is connected to a common terminal. In practical applications, the shielding structure 30 can be configured to be powered independently without being connected to a common terminal, depending on the requirements. In some embodiments of this application, applying a low voltage to the shielding structure 30 or grounding the shielding structure 30 enables the shielding structure 30 to shield word lines from interference to adjacent semiconductor pillars 20.

[0144] Specifically, the semiconductor pillar 20 includes a source 145 and a drain 141 located on opposite sides along the third direction Z. The source 145 and drain 141 of the transistor are respectively located on opposite sides of the semiconductor pillar 20 along the third direction Z. It can be understood that the source 145 and drain 141 of the transistor are relative concepts, and the source 145 and drain 141 can be any surface of the semiconductor pillar 20 along the third direction Z. A capacitor structure 90 extending along the third direction Z is located on a first side of the semiconductor pillar 20 along the third direction Z, and a bit line 120 extending along the first direction X is located on a second side of the semiconductor pillar 20 along the third direction Z. The bit line 120 is connected to the drain 141 of the semiconductor pillar 20. The capacitor structure 90 includes a first end connected to the source of the semiconductor pillar 20 and a second end connected to a common terminal.

[0145] Furthermore, the capacitor array 604 composed of the aforementioned capacitor structure 90 can be integrated with the transistor array (including the shielding structure 30, gate structure 10, semiconductor pillar 20, first conductive portion 210, and second conductive portion 220 in the above embodiment) and other device structures in the substrate 1 of the aforementioned first semiconductor structure 601. In some applications of this application, references Figure 22 As shown, the capacitor structure 90 described above is integrated with the transistor array on the same semiconductor substrate 1. Figure 22 In the substrate 1 of the first semiconductor structure 601 shown, the driving circuit of the memory device can be integrated into another semiconductor substrate 1, i.e. Figure 22In the substrate 1 of the second semiconductor structure 602 shown, there are some non-device blank areas in the substrate 1 where the memory device is integrated. These blank areas can be used to form the capacitor array 604 described above, without the need to add additional areas to form capacitors, thereby further improving the integration of the semiconductor device 100.

[0146] Reference Figure 22 As shown, in the first semiconductor structure 601, a capacitor array 604 and a transistor array are stacked in the Z direction. One electrode of the capacitor structure 90 in the capacitor array 604 is coupled to the drain 141 of the transistor in the transistor array. A capacitor structure 90 and a transistor (including a semiconductor pillar 20, a gate structure 10, and drains 141 and sources 145 on opposite sides of the semiconductor pillar 20 along the third Z direction) constitute a DRAM memory cell. By turning the transistor on and off, the connected capacitor structure 90 can be selected or deselected, thereby enabling read, write, or erase operations on the selected memory cell. The embodiments of this application do not limit the number of capacitor structures 90 and transistors; the capacitor array 604 and the transistor array can be coupled to form a DRAM memory array.

[0147] It is understandable that the source 145 and drain 141 of a transistor are relative concepts, related to the actual way the transistor is connected in the circuit, and unrelated to the physical location of the source 145 and drain 141 on the transistor. In some examples, after the transistor is connected to the circuit, the input terminal of the transistor connected to the circuit can be used as the source 145, and the output terminal as the drain 141, with charge carriers flowing from the source 145 to the drain 141. To better explain the coupling relationship between the capacitor structure 90 and the transistor in the embodiments of this application, the end of the transistor coupled to the capacitor structure 90 is used as the drain 141, while the source 145 of the transistor can be coupled to the bit line 120 to which the operating voltage is applied.

[0148] In some embodiments, such as Figure 22 As shown, the first semiconductor structure 601 further includes a first conductive plug 114a, which is coupled to the bit line 120. An insulating first fill layer 142a is disposed between adjacent transistors, which supports the transistors and forms electrical isolation.

[0149] In some embodiments, such as Figure 22 As shown, an insulating second fill layer 142b is disposed between the gate structure 10 and the gate dielectric layer.

[0150] In some examples, the constituent materials of the first filling layer 142a and the second filling layer may include insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, polysiloxane, or polysilazane.

[0151] In some embodiments, such as Figure 22 As shown, the second semiconductor structure 602 includes various devices, including a CMOS structure. In the Z direction, the first semiconductor structure 601 and the second semiconductor structure 602 are stacked and interconnected by bonding technology. The bonding may include hybrid bonding.

[0152] Reference Figure 22 As shown, before bonding is completed, the bonding surfaces of the first semiconductor structure 601 and the second semiconductor structure 602 respectively have bonding contacts 132. The bonding contacts 132 lead the electrical signals of the semiconductor structure to the bonding surface. The bonding contacts 132 may include conductive structures such as pads, conductive lines, and conductive plugs. Figure 22 The pads shown are for illustrative purposes only. The bonding planes of the first semiconductor structure 601 and the second semiconductor structure 602 are bonded together, and the interface where the bonding planes of the two semiconductor structures contact is the bonding interface 131. The bonding contacts 132 of the first semiconductor structure 601 and the second semiconductor structure 602 contact at the bonding interface 131, achieving electrical signal interconnection between the first semiconductor structure 601 and the second semiconductor structure 602.

[0153] The bonding contact 132 may be composed of conductive materials such as tungsten, gold, silver, platinum, copper, aluminum, titanium, or nickel. The bonding interface 131 may be composed of silicon oxide, silicon nitride, or metal silicides. In this embodiment, the bonding interface 131 includes metal silicides, which can increase the adhesion to the bonding contact 132, reduce the stress on the bonding interface 131, reduce the bending deformation of the bonding interface 131, and improve the manufacturing yield.

[0154] A first conductive plug 114a can be provided to lead out the electrical signal of the transistor and couple it to the pads on the bonding surface of the first semiconductor structure 601. A second conductive plug 114b can be provided to lead out the electrical signals of the first CMOS structure 121 and the second CMOS structure 122 in the second semiconductor structure 602 and couple them to the pads on the bonding surface of the second semiconductor structure 602. In the z-direction, the pads on the first semiconductor structure 601 and the pads on the second semiconductor structure 602 serve as bonding contacts 132, realizing the interconnection of electrical signals between the two semiconductor structures after bonding is completed.

[0155] In some embodiments, refer to Figure 22 As shown, the first semiconductor structure 601 further includes:

[0156] Interconnect layer 118 is located at the end of capacitor structure 90 along the third direction Z, away from the transistor; interconnect layer 118 is coupled to capacitor structure 90. The constituent materials of interconnect layer 118 may include conductive materials such as tungsten, gold, silver, platinum, copper, aluminum, titanium, or nickel. Electrical signals from interconnect layer 118 can be led out to bonding interface 131 through third conductive plug 114c, achieving electrical signal interconnection with the second semiconductor structure 602.

[0157] In some embodiments, refer to Figure 22 As shown, an interconnect structure 133 is also provided on the side of the first semiconductor structure 601 away from the bonding interface 131. The interconnect structure 133 can be coupled to the interconnect layer 118 to supply power to the interconnect layer 118. In some other embodiments, the interconnect structure 133 can also be coupled to other interconnect layers to supply power.

[0158] This application provides a semiconductor device 100 and a method for manufacturing the same, through some embodiments. The source 145 and drain 141 of the transistor array formed by this method are located at opposite ends of a semiconductor pillar 20 extending perpendicularly to the substrate 1. A gate structure 10 is located on one sidewall of the semiconductor pillar 20. This significantly reduces the area of ​​the transistor array and increases the device's storage density. Furthermore, a shielding structure 30 is formed between adjacent semiconductor pillars 20, which can shield word lines from interference to adjacent semiconductor pillars 20.

[0159] Based on the above-described semiconductor device 100 and its fabrication method, refer to Figure 24 As shown, this embodiment of the invention also provides a storage system 300, including a memory controller 310 and a three-dimensional memory 320. The memory controller 310 is coupled to the three-dimensional memory 320 and is used to control the three-dimensional memory 320 to store data. The three-dimensional memory 320 includes any of the above-mentioned semiconductor devices 100.

[0160] Specifically, such as Figure 24 As shown, the storage system 300 includes a memory controller 310 and one or more 3D memories 320. Each 3D NAND Flash memory 320 includes an array memory structure 321 and peripheral circuitry 322. The array memory structure 321 includes any of the aforementioned semiconductor devices 100. The storage system 300 can communicate with the host 400 via the memory controller 310, which can be connected to one or more 3D memories 320 via channels in the 3D memories 320. Each 3D memory 320 can be managed by the memory controller 310 via channels in the 3D memories 320.

[0161] Specifically, the array storage structure 321 is used to store information, while the peripheral circuit 322 can be located above or below the array storage structure 321, or around the array storage structure 321. The peripheral circuit 322 is used to control the corresponding array storage structure 321. Furthermore, this semiconductor device 100 can also be applied to other microelectronic devices, such as non-volatile flash memory (Nor Flash), etc., without specific limitations. In addition, the semiconductor device 100 in this embodiment of the invention can be a three-dimensional memory 320, or a part of a peripheral memory, without particular limitation.

[0162] The above provides a detailed description of a semiconductor device 100, its fabrication method, and a storage system 300 provided in the embodiments of this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the methods and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A semiconductor device, wherein, include: A first region, the first region including a semiconductor pillar array, the semiconductor pillar array including a plurality of semiconductor pillars arranged in an array along a first direction and a second direction and extending upward in a third direction; the first direction, the second direction and the third direction intersect each other; as well as, Multiple gate structures and shielding structures extending along a first direction; the gate structures and shielding structures are staggered along a second direction, and the semiconductor pillars are located between adjacent shielding structures and gate structures; Wherein, the dimension of the gate structure along the first direction is smaller than the dimension of the shielding structure along the first direction, and the orthogonal projection of the gate structure along the second direction is within the range of the orthogonal projection of the shielding structure.

2. The semiconductor device according to claim 1, wherein, The dimension of the gate structure along the third direction is greater than the dimension of the shielding structure along the third direction, and the orthogonal projection of the gate structure along the second direction is within the range of the orthogonal projection of the shielding structure.

3. The semiconductor device according to claim 1, wherein, It also includes a second region, which is arranged along the first direction with the first region; The second region includes a first conductive portion, the first conductive portion including a first lead-out structure extending along the third direction and a first connector extending along the first direction; The two ends of the first lead-out structure along the third direction are respectively in contact with the first connector and the gate structure; The first conductive part is located on one side of the shielding structure along the third direction.

4. The semiconductor device according to claim 3, wherein, It includes multiple first regions and multiple second regions, with two adjacent first regions connected by a second region along the first direction, and the gate structures in two adjacent first regions connected by the first conductive portion.

5. The semiconductor device according to claim 4, wherein, The second region also includes a second conductive part, through which the plurality of shielding structures in the first region are connected.

6. The semiconductor device according to claim 5, wherein, The first region also includes: A bit line located on one side of the semiconductor pillar and connected to the drain of the semiconductor pillar along the third direction, the bit line extending along the second direction; The second conductive portion is located on the side of the shielding structure that is relatively close to the bit line, extending upwards along the third direction.

7. The semiconductor device according to claim 5, wherein, The first region also includes: A bit line located on one side of the semiconductor pillar and connected to the drain of the semiconductor pillar along the third direction, the bit line extending along the second direction; The second conductive portion is located on the side of the shielding structure that is relatively far from the bit line, extending upwards along the third direction.

8. The semiconductor device according to claim 6 or 7, wherein, The second conductive portion includes a second connector extending along the second direction, the second connector being connected to a plurality of the shielding structures, and the side of the gate structure closest to the second connector having a gap with the second connector in the first direction.

9. The semiconductor device according to claim 8, wherein, The second conductive portion further includes: at least one second lead-out structure extending along the third direction, the second lead-out structure being connected to the second connector, and the second lead-out structure being located at one end of the second connector away from the plurality of shielding structures in the second direction.

10. The semiconductor device according to claim 9, wherein, The shielding structure and the second lead-out structure are located on opposite sides of the second connector along the third direction.

11. The semiconductor device according to claim 10, wherein, The shielding structure is in contact with the second connector.

12. The semiconductor device according to claim 10, wherein, The second conductive portion further includes: at least one third lead-out structure extending along the third direction, each of the shielding structures being connected to the second connector via at least one of the third lead-out structures, the third lead-out structures and the second lead-out structures being located on different sides of the second connector along the third direction.

13. The semiconductor device according to claim 10, wherein, The second conductive part further includes a third connector extending along the first direction, the third connector being connected to the second connector via the second lead-out structure.

14. The semiconductor device according to claim 11, wherein, The shielding structure is located on the side of the second connector that is relatively far from the bit line, along the third direction.

15. The semiconductor device according to claim 11, wherein, The shielding structure is located on the side of the second connector that is relatively close to the bit line, along the third direction.

16. The semiconductor device according to claim 6 or 7, wherein, The first region also includes: A capacitor structure located on the side of the semiconductor pillar that is relatively far from the bit line along the third direction and extending along the third direction; The capacitor structure includes a first end connected to the source of the semiconductor pillar and a second end connected to a common terminal.

17. The semiconductor device according to claim 1, wherein, The gate structure includes a first gate and a second gate adjacent to each other in the second direction, the first gate and the second gate being located on one side of the semiconductor pillar adjacent to them.

18. A method for fabricating a semiconductor device, wherein, include: Provide a substrate; A first groove is formed in the substrate, extending along a second direction and spaced apart along a first direction; The first direction intersects the second direction; Deposit a dielectric material in the first groove; A second groove and a third groove extending along the first direction are formed in the substrate. The second groove and the third groove are arranged alternately along the second direction, and the size of the second groove along the first direction is smaller than the size of the third groove along the first direction. The orthographic projection of the second groove along the second direction is located within the range of the orthographic projection of the third groove. A grid structure is formed within the second groove; A shielding structure is formed within the third groove.

19. The method for fabricating a semiconductor device according to claim 18, wherein, Also includes: The second groove is larger in size along the third direction than the third groove in size along the third direction, and the orthographic projection of the second groove along the second direction is within the range of the orthographic projection of the third groove, with the first direction, the second direction and the third direction intersecting each other.

20. A storage system, wherein, include: A memory controller and a three-dimensional memory, the memory controller being coupled to the three-dimensional memory and used to control the storage of data in the three-dimensional memory, the three-dimensional memory comprising one or more semiconductor devices as described in any one of claims 1 to 17.

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