Display substrate and display device

Abstract

The invention discloses a display substrate and a display device. The display substrate comprises a plurality of first data connecting lines (71) extending in the first direction, a plurality of data signal lines (81) extending in the second direction, a plurality of first power lines (82) and a plurality of second data connecting lines (84). Any column of sub-pixels is electrically connected with one of the data signal lines (81) and one of the first power lines (82), and any one of the first power lines (82) is electrically connected with a plurality of sub-pixels in one column of sub-pixels; at least a part of the data signal lines (81) are electrically connected with at least a part of the second data connecting lines (84) through at least a part of the first data connecting lines (71); a second data connecting line (84) is arranged between every two adjacent first power lines (82), and in the first direction, the second data connecting lines (84) and the data signal lines (81) are arranged on the two sides of the first power lines (82).

Description

Display substrate, display device Technical Field

[0001] The present disclosure relates to, but is not limited to, the field of display technology, and in particular to a display substrate and a display device. Background Art

[0002] Organic Light Emitting Diodes (OLEDs) and Quantum-dot Light Emitting Diodes (QLEDs) are active light-emitting display devices with advantages such as self-luminescence, wide viewing angles, high contrast, low power consumption, extremely fast response times, thinness, flexibility, and low cost. With the continuous advancement of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and thin-film transistors (TFTs) for signal control have become mainstream products in the display field.

[0003] Summary of the Invention

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] In a first aspect, embodiments of the present disclosure provide a display substrate, comprising: a substrate, and a plurality of data signal lines, a plurality of first power lines, a plurality of first data connection lines, a plurality of second data connection lines, and a plurality of sub-pixels arranged in an array, disposed on the substrate; in a plane parallel to the display substrate, the first data connection lines extend along a first direction, and the data signal lines, the first power lines, and the second data connection lines extend along a second direction, the first direction intersecting the second direction; the first data connection lines, the data signal lines, the first power lines, and the second data connection lines being located on a different conductive layer;

[0006] Any column of sub-pixels is electrically connected to one of the data signal lines and one of the first power lines, and any first power line is electrically connected to multiple sub-pixels in one column of sub-pixels; at least a portion of the data signal lines is electrically connected to at least a portion of the second data connection lines through at least a portion of the first data connection lines; a second data connection line is provided between two adjacent first power lines, and in the first direction, the second data connection line and the data signal line are arranged on both sides of the first power line.

[0007] In an exemplary embodiment, the sub-pixel includes a plurality of transistors, and orthographic projections of the plurality of second data link lines on the substrate do not overlap with orthographic projections of channels of the plurality of transistors on the substrate.

[0008] In an exemplary embodiment, the plurality of first data connection lines are disposed between two adjacent sub-pixel rows, and orthographic projections of the plurality of first data connection lines on the substrate do not overlap with orthographic projections of channels of the plurality of transistors on the substrate.

[0009] In an exemplary embodiment, the invention further includes a plurality of first power connection lines, wherein a main portion of the first power connection lines extends along the first direction, the plurality of first power connection lines are arranged along the second direction, and the plurality of first power connection lines are electrically connected to the plurality of sub-pixels through the plurality of first power connection lines;

[0010] On a plane perpendicular to the display substrate, orthographic projections of the plurality of first power connection lines on the base at least partially overlap with orthographic projections of the plurality of second data connection lines on the base.

[0011] In an exemplary embodiment, the first power connection line is electrically connected to a plurality of sub-pixels in one sub-pixel row, and the first power line is electrically connected to a plurality of sub-pixels in a column of sub-pixels through a plurality of first power connection lines.

[0012] In an exemplary embodiment, at least one sub-pixel includes a pixel driving circuit, the pixel driving circuit including a plurality of transistors, the plurality of transistors including a driving transistor, a first transistor, and a second transistor, the first transistor being configured to provide an initialization signal to a gate of the driving transistor, a first electrode of the second transistor being connected to the gate of the driving transistor, and a second electrode of the second transistor being connected to the second electrode of the driving transistor; the plurality of first power lines and the plurality of data signal lines being alternately arranged along the first direction, with two adjacent first power lines being mirror-symmetrical with respect to the second data connection line; the first power connection line including a plurality of first protrusions, the plurality of first protrusions being located on one side of a main portion of the first power connection line in the second direction, an orthographic projection of the first protrusion on the substrate at least partially overlapping with an orthographic projection of two adjacent first power lines on the substrate, and the orthographic projection of the first protrusion on the substrate covering an orthographic projection of a channel of the first transistor and a channel of the second transistor located on both sides of the second data connection line on the substrate.

[0013] In an exemplary embodiment, the first power connection cable further includes a plurality of second protrusions, wherein the plurality of first protrusions and the plurality of second protrusions are alternately arranged along the first direction in the same first power connection cable, and the plurality of first protrusions and the plurality of second protrusions are located on both sides of the main body of the first power connection cable in the second direction;

[0014] The orthographic projection of the second protrusion on the substrate at least partially overlaps with the orthographic projections of two adjacent data signal lines on the substrate.

[0015] In an exemplary embodiment, the display substrate further includes a fifth conductive layer, a sixth conductive layer, and an anode conductive layer, the first power connection line and the first data connection line are located in the fifth conductive layer, the data signal line, the first power line, and the second data connection line are located in the sixth conductive layer, the anode conductive layer is located on a side of the sixth conductive layer away from the substrate, the anode conductive layer includes a plurality of anodes, and the orthographic projections of the plurality of anodes on the substrate overlap with the orthographic projection of the first protrusion on the substrate, or overlap with the orthographic projection of the second protrusion on the substrate.

[0016] In an exemplary embodiment, the second data connection line is located between two adjacent columns of sub-pixels, and the two adjacent columns of sub-pixels are mirror-symmetrical with respect to the second data connection line. In a first direction, the two first transistors in the two adjacent columns of sub-pixels are located on both sides of the second data connection line, and the two second transistors in the two adjacent columns of sub-pixels are located on both sides of the second data connection line; in the same sub-pixel, the second electrode of the first transistor is electrically connected to the second electrode of the second transistor.

[0017] In an exemplary embodiment, the multiple transistors also include a sixth transistor, the conductive layer where the first power connection line is located also includes a first anode connection electrode, the second electrode of the sixth transistor is connected to the first anode connection electrode, and in the first direction, the two sixth transistors of two adjacent columns of sub-pixels are located on both sides of the second data connection line, and the positive projection of the channel of the sixth transistor on the substrate is located within the range of the positive projection of the first anode connection electrode on the substrate.

[0018] In an exemplary embodiment, a second flat layer is provided between the fifth conductive layer and the sixth conductive layer, and the second flat layer located on the first protruding portion and the flat layer located on the second protruding portion are located on the same plane at a side away from the substrate.

[0019] In an exemplary embodiment, the multiple transistors also include a fourth transistor, which is configured to provide a data signal to the driving transistor, and the data signal line includes an integrally formed first part and a second part, the first part extends along the second direction, the second part is a bent structure, the orthographic projection of the second part on the substrate overlaps with the orthographic projection of the second protrusion on the substrate, the orthographic projection of the channel region and the first region of the fourth transistor on the substrate overlaps with the orthographic projection of the first part on the substrate, and the first part in two adjacent sub-pixels in the first direction forms a first opening.

[0020] In an exemplary embodiment, a middle portion of the second portion of the data signal line is bent toward the adjacent first power line, and a second opening is formed in the middle portions of two adjacent second portions in the first direction.

[0021] In an exemplary embodiment, both ends of the second portion are bent away from the first power line adjacent thereto, and a ratio of a distance between two adjacent data signal lines at the first opening to a distance between two adjacent data signal lines at the second opening is 1.1 to 1.6.

[0022] A ratio of a distance between two adjacent data signal lines at the first opening position to a distance along the first direction between two adjacent data signal line ends at the first opening position or the second opening position is 1 to 8.

[0023] In an exemplary embodiment, the display substrate further includes a first initial signal line extending along the first direction, and an orthographic projection of the first initial signal line on the substrate overlaps with an orthographic projection of the first data link line on the substrate.

[0024] In an exemplary embodiment, the display substrate includes a display area and a binding area, and in the second direction, the binding area is located on one side of the display area; the display area includes a first display area and a second display area, and in the first direction, the first display area is located on both sides of the second display area, and a plurality of data signal lines located in the first display area are electrically connected to a plurality of second data connection lines located in the second display area through a plurality of first data connection lines, respectively, and a plurality of data signal lines and a plurality of second data connection lines located in the second display area are connected to the binding area.

[0025] In an exemplary embodiment, in the first direction, on one side of the second center line, a plurality of data signal lines arranged in a direction from the second display area to the first display area in the first display area are electrically connected in sequence to a plurality of second data connection lines in a direction from the second display area to the second center line through a plurality of first data connection lines in a direction from the binding area to the display area; wherein the second center line is the center line of the display substrate extending along the second direction.

[0026] In a second aspect, an embodiment of the present disclosure further provides a display device, comprising the display substrate described in any of the above embodiments.

[0027] In a third aspect, an embodiment of the present disclosure further provides a display device, comprising the above-mentioned display substrate including the first opening, the display device also comprising a photosensitive element, the orthographic projection of the photosensitive element on the base of the display substrate being within the range of the orthographic projection of the first opening of the display substrate on the base.

[0028] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The accompanying drawings are intended to provide a further understanding of the technical solutions of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solutions of the present disclosure and do not constitute a limitation of the technical solutions of the present disclosure. The shapes and sizes of each component in the drawings do not reflect the actual scale and are intended only to illustrate the contents of the present disclosure.

[0030] FIG1 is a schematic structural diagram of a display device;

[0031] FIG2 is a schematic structural diagram of a display substrate;

[0032] FIG3 is a schematic diagram of a planar structure of a display area in a display substrate;

[0033] FIG4 is a schematic diagram of a cross-sectional structure of a display area in a display substrate;

[0034] FIG5 is a schematic diagram of an equivalent circuit of a pixel driving circuit;

[0035] FIG6 is a timing diagram of an operation of a pixel driving circuit;

[0036] FIG7 a is a schematic structural diagram of a display substrate provided by an embodiment of the present disclosure;

[0037] FIG7 b is a schematic structural diagram of a display substrate provided by an exemplary embodiment of the present disclosure;

[0038] FIG7 c is a schematic diagram showing a planar structure of a display area in a display substrate provided by an exemplary embodiment of the present disclosure;

[0039] FIG8 is a schematic diagram showing an equivalent circuit of a pixel driving circuit provided by an exemplary embodiment of the present disclosure;

[0040] FIG9 is a schematic diagram showing a display substrate provided by an exemplary embodiment of the present disclosure after a shielding layer pattern is formed;

[0041] FIG10 a is a schematic diagram showing a display substrate provided by an exemplary embodiment of the present disclosure after a first semiconductor layer pattern is formed;

[0042] FIG10 b is a schematic diagram showing a first semiconductor layer in a display substrate provided by an exemplary embodiment of the present disclosure;

[0043] FIG11a is a schematic diagram showing a display substrate provided by an exemplary embodiment of the present disclosure after a first conductive layer pattern is formed;

[0044] FIG11 b is a schematic diagram of a first conductive layer in a display substrate provided by an exemplary embodiment of the present disclosure;

[0045] FIG12a is a schematic diagram showing a display substrate provided by an exemplary embodiment of the present disclosure after a second conductive layer pattern is formed;

[0046] FIG12 b is a schematic diagram showing a second conductive layer in a display substrate provided by an exemplary embodiment of the present disclosure;

[0047] FIG13a is a schematic diagram showing a display substrate provided by an exemplary embodiment of the present disclosure after a second semiconductor layer pattern is formed;

[0048] FIG13 b is a schematic diagram showing a second semiconductor layer in a display substrate provided by an exemplary embodiment of the present disclosure;

[0049] FIG14a is a schematic diagram showing a display substrate provided by an exemplary embodiment of the present disclosure after a third conductive layer pattern is formed;

[0050] FIG14 b is a schematic diagram showing a third conductive layer in a display substrate provided by an exemplary embodiment of the present disclosure;

[0051] FIG15 is a schematic diagram showing a display substrate provided by an exemplary embodiment of the present disclosure after a sixth insulating layer pattern is formed;

[0052] FIG16a is a schematic diagram showing a display substrate provided by an exemplary embodiment of the present disclosure after a fourth conductive layer pattern is formed;

[0053] FIG16 b is a schematic diagram showing a fourth conductive layer in a display substrate provided by an exemplary embodiment of the present disclosure;

[0054] FIG17 is a schematic diagram showing a first planarization layer pattern formed according to an exemplary embodiment of the present disclosure;

[0055] FIG18a is a schematic diagram showing a display substrate provided by an exemplary embodiment of the present disclosure after a fifth conductive layer pattern is formed;

[0056] FIG18 b is a schematic diagram showing a fifth conductive layer in a display substrate provided by an exemplary embodiment of the present disclosure;

[0057] FIG19a is a schematic diagram showing a display substrate provided by an exemplary embodiment of the present disclosure after a second planarization layer pattern is formed;

[0058] FIG19 b is a schematic diagram showing a display substrate provided by an exemplary embodiment of the present disclosure after a second planarization layer pattern is formed;

[0059] FIG20 a is a schematic diagram showing a display substrate provided by an exemplary embodiment of the present disclosure after a sixth conductive layer pattern is formed;

[0060] FIG20 b is a schematic diagram of a sixth conductive layer in a display substrate provided by an exemplary embodiment of the present disclosure;

[0061] FIG20c is a schematic diagram showing a display substrate provided by an exemplary embodiment of the present disclosure after a sixth conductive layer pattern is formed;

[0062] FIG21 is a schematic diagram showing a display substrate provided by an exemplary embodiment of the present disclosure after a third planarization layer pattern is formed;

[0063] FIG22a is a schematic diagram showing a display substrate provided by an exemplary embodiment of the present disclosure after an anode conductive layer pattern is formed;

[0064] FIG22 b is a schematic diagram showing an anode conductive layer in a display substrate provided by an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0065] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. The embodiments can be implemented in a number of different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. Unless there is a conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other. In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of some known functions and known components. The drawings of the embodiments of the present disclosure only involve structures related to the embodiments of the present disclosure. Other structures can refer to the general design

[0066] The scales of the figures in this disclosure are intended to serve as a reference for actual processes, but are not intended to be limiting. For example, the thickness and spacing of each film layer, and the width and spacing of each signal line, can be adjusted based on actual conditions. The figures described in this disclosure are merely schematic diagrams of the structures, and one embodiment of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0067] In this specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0068] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and is not intended to indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced depending on the circumstances.

[0069] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure.

[0070] In this specification, a transistor refers to a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0071] In this specification, the first electrode can be a drain electrode and the second electrode can be a source electrode, or the first electrode can be a source electrode and the second electrode can be a drain electrode. In cases where transistors with opposite polarities are used or the direction of current changes during circuit operation, the functions of the "source electrode" and "drain electrode" are sometimes interchangeable. Therefore, in this specification, "source electrode" and "drain electrode" can be interchangeable, and "source terminal" and "drain terminal" can be interchangeable. In the disclosed embodiments, the gate electrode can be referred to as the control electrode.

[0072] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transfer of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0073] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0074] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0075] The triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not in the strict sense, but may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0076] The term "about" in the embodiments of the present disclosure does not strictly define the limits and allows for numerical values ​​within the range of process and measurement errors.

[0077] Figure 1 is a schematic diagram of the structure of a display device. As shown in Figure 1, the display device may include a timing controller, a data driver, a scan driver, a light-emitting driver, and a pixel array. The timing controller is respectively connected to the data driver, the scan driver, and the light-emitting driver. The data driver is respectively connected to a plurality of data signal lines (D1 to Dn), the scan driver is respectively connected to a plurality of scan signal lines (S1 to Sm), and the light-emitting driver is respectively connected to a plurality of light-emitting signal lines (E1 to Eo). The pixel array may include a plurality of sub-pixels Pxij, where i and j may be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light-emitting device connected to the circuit unit. The circuit unit may include at least one scan signal line, at least one data signal line, at least one light-emitting signal line, and a pixel driving circuit. In an exemplary embodiment, the timing controller may provide grayscale values ​​and control signals suitable for the specifications of the data driver to the data driver, may provide clock signals, scan start signals, etc. suitable for the specifications of the scan driver to the scan driver, and may provide clock signals, emission stop signals, etc. suitable for the specifications of the light-emitting driver to the light-emitting driver. The data driver can generate data voltages to be supplied to data signal lines D1, D2, D3, ..., and Dn using grayscale values ​​and control signals received from a timing controller. For example, the data driver can sample grayscale values ​​using a clock signal and apply data voltages corresponding to the grayscale values ​​to data signal lines D1 to Dn on a per-pixel basis, where n can be a natural number. The scan driver can generate scan signals to be supplied to scan signal lines S1, S2, S3, ..., and Sm by receiving clock signals, scan start signals, and the like from the timing controller. For example, the scan driver can sequentially supply scan signals having on-level pulses to scan signal lines S1 to Sm. For example, the scan driver can be configured as a shift register and can sequentially transmit scan start signals provided in the form of on-level pulses to the next-stage circuit under the control of a clock signal, where m can be a natural number. The light driver can generate emission signals to be supplied to light signal lines E1, E2, E3, ..., and Eo by receiving clock signals, emission stop signals, and the like from the timing controller. For example, the light emitting driver may sequentially provide an emission signal having an off-level pulse to the light emitting signal lines E1 to Eo. For example, the light emitting driver may be configured in the form of a shift register and may generate an emission signal in a manner such that an emission stop signal provided in the form of an off-level pulse is sequentially transmitted to a next-stage circuit under the control of a clock signal. o may be a natural number.

[0078] FIG2 is a schematic diagram of the structure of a display substrate. As shown in FIG2 , the display substrate may include a display area 100, a binding area 200 located on one side of the display area 100, and a border area 300 located on the other side of the display area 100. In an exemplary embodiment, the display area 100 may be a flat area including a plurality of sub-pixels Pxij constituting a pixel array, wherein the plurality of sub-pixels Pxij are configured to display dynamic images or still images, and the display area 100 may be referred to as an active area (AA). In an exemplary embodiment, the display substrate may be a flexible substrate, and thus the display substrate may be deformable, such as curling, bending, folding, or rolling up. In an exemplary embodiment, the display substrate may further include a display area boundary BD, which may be the edge of the display area 100 on the side close to the binding area 200.

[0079] In an exemplary embodiment, the binding area 200 may include a fan-out area, a bending area, a driver chip area, and a binding pin area arranged in sequence along a direction away from the display area. The fan-out area is connected to the display area and includes a plurality of data fan-out lines. The data fan-out lines are configured to connect the data signal lines (Data Line) of the display area in a fan-out routing manner. The fan-out area occupies a large space, resulting in a larger width of the lower frame. The bending area is connected to the fan-out area and may include a composite insulating layer provided with a groove, which is configured to bend the binding area to the back of the display area. The driver chip area may include an integrated circuit (IC) configured to be connected to a plurality of data fan-out lines. The binding pin area may include a binding pad configured to be bound and connected to an external flexible printed circuit (FPC).

[0080] In an exemplary embodiment, the border area 300 may include a circuit area, a power line area, a crack dam area, and a cutting area, which are arranged in sequence along a direction away from the display area. The circuit area is connected to the display area and may include at least a gate drive circuit, which is connected to the first scan signal line, the second scan signal line, the third scan signal line, and the light-emitting control line of the pixel drive circuit in the display area. The power line area is connected to the circuit area and may include at least a power lead, which extends in a direction parallel to the edge of the display area and is connected to the cathode in the display area. The crack dam area is connected to the power line area and may include at least a plurality of cracks provided on the composite insulating layer. The cutting area is connected to the crack dam area and may include at least a cutting groove provided on the composite insulating layer, and the cutting groove is configured so that after all the film layers of the display substrate are prepared, the cutting equipment cuts along the cutting grooves respectively.

[0081] In an exemplary embodiment, the fan-out area in the binding area 200 and the power line area in the border area 300 may be provided with a first isolation dam and a second isolation dam, and the first isolation dam and the second isolation dam may extend in a direction parallel to the edge of the display area to form a ring structure surrounding the display area, and the edge of the display area is the edge on one side of the display area binding area or the border area.

[0082] FIG3 is a schematic diagram of a planar structure of a display area in a display substrate. As shown in FIG3 , the display substrate may include a plurality of pixel units P arranged in a matrix. At least one pixel unit P may include a first sub-pixel P1 that emits a first color light, a second sub-pixel P2 that emits a second color light, and a third sub-pixel P3 and a fourth sub-pixel P4 that emit a third color light. Each sub-pixel may include a circuit unit and a light-emitting device. The circuit unit may include at least a pixel driving circuit. The pixel driving circuit is respectively connected to a scan signal line, a data signal line, and a light-emitting signal line. The pixel driving circuit is configured to receive a data voltage transmitted by the data signal line under the control of the scan signal line and the light-emitting signal line, and output a corresponding current to the light-emitting device. The light-emitting device in each sub-pixel is respectively connected to the pixel driving circuit of the sub-pixel in which it is located. The light-emitting device is configured to emit light of a corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel in which it is located.

[0083] In an exemplary embodiment, the first sub-pixel P1 may be a red sub-pixel (R) that emits red light, the second sub-pixel P2 may be a blue sub-pixel (B) that emits blue light, and the third sub-pixel P3 and the fourth sub-pixel P4 may be green sub-pixels (G) that emit green light. In an exemplary embodiment, the sub-pixels may be rectangular, rhombus, pentagonal, or hexagonal, and the four sub-pixels may be arranged in a diamond shape to form an RGBG pixel arrangement. In other exemplary embodiments, the four sub-pixels may be arranged horizontally, vertically, or in a square, etc., which is not limited in this disclosure.

[0084] In an exemplary embodiment, a pixel unit may include three sub-pixels, and the three sub-pixels may be arranged in a horizontal parallel arrangement, a vertical parallel arrangement, or a triangular arrangement, which is not limited in the present disclosure.

[0085] Figure 4 is a schematic cross-sectional view of the display region of a display substrate, illustrating the structure of four sub-pixels within the display region. As shown in Figure 4, in a plane perpendicular to the display substrate, the display substrate may include a drive circuit layer 102 disposed on a substrate 101, a light-emitting structure layer 103 disposed on a side of the drive circuit layer 102 facing away from the substrate 101, and an encapsulation structure layer 104 disposed on a side of the light-emitting structure layer 103 facing away from the substrate 101. In some possible implementations, the display substrate may include other film layers, such as a touch-sensitive structure layer, which is not limited in this disclosure.

[0086] In an exemplary embodiment, the substrate 101 may be a flexible substrate or a rigid substrate. The driving circuit layer 102 of each sub-pixel may include a pixel driving circuit composed of a plurality of transistors and a storage capacitor. The light-emitting structure layer 103 of each sub-pixel may include a light-emitting device composed of a plurality of film layers, and the plurality of film layers may include at least an anode, a pixel definition layer, an organic light-emitting layer and a cathode. The anode is connected to the pixel driving circuit, the organic light-emitting layer is connected to the anode, and the cathode is connected to the organic light-emitting layer. The organic light-emitting layer emits light of corresponding colors under the drive of the anode and the cathode. The encapsulation structure layer 104 may include a stacked first encapsulation layer, a second encapsulation layer and a third encapsulation layer. The first encapsulation layer and the third encapsulation layer may be made of inorganic materials, and the second encapsulation layer may be made of organic materials. The second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer to form an inorganic material / organic material / inorganic material stacked structure, which can ensure that external water vapor cannot enter the light-emitting structure layer 103.

[0087] In an exemplary embodiment, the organic light-emitting layer may include an emissive layer (EML) and any one or more of the following layers: a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). In an exemplary embodiment, one or more of the hole injection layer, hole transport layer, electron blocking layer, hole blocking layer, electron transport layer, and electron injection layer of all sub-pixels may each be a connected common layer, and the emissive layers of adjacent sub-pixels may have a small overlap or may be isolated from each other.

[0088] FIG5 is a schematic diagram of an equivalent circuit of a pixel driving circuit. In an exemplary embodiment, the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. As shown in FIG5 , the pixel driving circuit may include 7 transistors (a first transistor T1 to a seventh transistor T7) and a storage capacitor C. The pixel driving circuit is connected to 10 signal lines (a data signal line D, a first scan signal line S1, a second scan signal line S2, a third scan signal line S3, a fourth scan signal line S4, a light emitting signal line E, a first initial signal line INIT1, a second initial signal line INIT2, a first power line VDD, and a second power line VSS).

[0089] In an exemplary embodiment, the pixel driving circuit may include a first node N1, a second node N2, and a third node N3. The first node N1 is respectively connected to the first electrode of the third transistor T3, the second electrode of the fourth transistor T4, and the second electrode of the fifth transistor T5, the second node N2 is respectively connected to the second electrode of the first transistor T1, the control electrode of the third transistor T3, and the second end of the storage capacitor C, and the third node N3 is respectively connected to the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the first electrode of the sixth transistor T6.

[0090] In an exemplary embodiment, a first end of the storage capacitor C is connected to the first power line VDD, and a second end of the storage capacitor C is connected to the second node N2 , ie, the second end of the storage capacitor C is connected to the control electrode of the third transistor T3 .

[0091] In an exemplary embodiment, a control electrode of the first transistor T1 is connected to the second scan signal line S2, a first electrode of the first transistor T1 is connected to the first initialization signal line INIT1, and a second electrode of the first transistor T1 is connected to the second node N2. When a turned-on scan signal is applied to the second scan signal line S2, the first transistor T1 transmits a first initialization voltage to the second end of the storage capacitor C, thereby initializing the storage capacitor C.

[0092] In an exemplary embodiment, a control electrode of the second transistor T2 is connected to the fourth scan signal line S4, a first electrode of the second transistor T2 is connected to the second electrode of the first transistor T1, and a second electrode of the second transistor T2 is connected to the third node N3. When a turned-on scan signal is applied to the fourth scan signal line S4, the second transistor T2 connects the control electrode of the third transistor T3 to the second electrode of the third transistor T3.

[0093] In an exemplary embodiment, the control electrode of the third transistor T3 is connected to the second node N2, that is, the control electrode of the third transistor T3 is connected to the second end of the storage capacitor C, the first electrode of the third transistor T3 is connected to the first node N1, and the second electrode of the third transistor T3 is connected to the third node N3. The third transistor T3 can be called a driving transistor. The third transistor T3 determines the magnitude of the driving current flowing between the first power line VDD and the light-emitting device based on the potential difference between the control electrode and the first electrode.

[0094] In an exemplary embodiment, a control electrode of the fourth transistor T4 is connected to the third scan signal line S3, a first electrode of the fourth transistor T4 is connected to the data signal line D, and a second electrode of the fourth transistor T4 is connected to the first node N1. When a turned-on scan signal is applied to the third scan signal line S3, the fourth transistor T4 inputs a data voltage of the data signal line D to the first node N1.

[0095] In an exemplary embodiment, a control electrode of the fifth transistor T5 is connected to the light-emitting signal line E, a first electrode of the fifth transistor T5 is connected to the first power line VDD, and a second electrode of the fifth transistor T5 is connected to the first node N1. A control electrode of the sixth transistor T6 is connected to the light-emitting signal line E, a first electrode of the sixth transistor T6 is connected to the third node N3, and a second electrode of the sixth transistor T6 is connected to the first electrode of the light-emitting device. When a conductive light-emitting signal is applied to the light-emitting signal line E, the fifth transistor T5 and the sixth transistor T6 form a drive current path between the first power line VDD and the light-emitting device, causing the light-emitting device to emit light.

[0096] In an exemplary embodiment, a control electrode of the seventh transistor T7 is connected to the first scan signal line S1, a first electrode of the seventh transistor T7 is connected to the second initialization signal line INIT2, and a second electrode of the seventh transistor T7 is connected to the first electrode of the light-emitting device. When a turned-on scan signal is applied to the first scan signal line S1, the seventh transistor T7 transmits the second initialization voltage to the first electrode of the light-emitting device to initialize or release the charge accumulated in the first electrode of the light-emitting device.

[0097] In an exemplary embodiment, the light-emitting device can be an OLED, including a stacked first pole (anode), an organic light-emitting layer and a second pole (cathode), or can be a QLED, including a stacked first pole (anode), a quantum dot light-emitting layer and a second pole (cathode).

[0098] In an exemplary embodiment, the second electrode of the light emitting device is connected to the second power line VSS, the signal of the second power line VSS is a low level signal, and the signal of the first power line VDD is a continuously high level signal.

[0099] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 may be a P-type transistor or an N-type transistor. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the manufacturing difficulty of the display panel, and improve the product yield. In some possible implementations, the first transistor T1 to the seventh transistor T7 may include P-type transistors and N-type transistors.

[0100] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 may be low-temperature polysilicon transistors, or oxide transistors, or low-temperature polysilicon transistors and metal oxide transistors. The active layer of the low-temperature polysilicon transistor is made of low-temperature polysilicon (LTPS), and the active layer of the metal oxide transistor is made of metal oxide semiconductor (Oxide). Low-temperature polysilicon transistors have advantages such as high mobility and fast charging, while oxide transistors have advantages such as low leakage current. Integrating low-temperature polysilicon transistors and metal oxide transistors on a display substrate to form an LTPO (Low Temperature Poly-Silicon + Oxide, LTPO, Chinese full name: Low-Temperature Polycrystalline Oxide) display substrate can utilize the advantages of both, achieve low-frequency driving, reduce power consumption, and improve display quality.

[0101] FIG6 is a timing diagram of an operation of a pixel driving circuit. The following illustrates an exemplary embodiment of the present disclosure through the operation process of the pixel driving circuit illustrated in FIG5. The pixel driving circuit in FIG5 includes seven transistors (a first transistor T1 to a seventh transistor T7) and a storage capacitor C. The first transistor T1 and the second transistor T2 are N-type oxide transistors, and the third transistor T3 to the seventh transistor T7 are P-type low-temperature polysilicon transistors. In an exemplary embodiment, the operation process of the pixel driving circuit may include:

[0102] The first phase A1, known as the reset phase, is characterized by the signal on the second scan signal line S2 being a high-level signal, while the signals on the first scan signal line S1, the third scan signal line S3, the fourth scan signal line S4, and the light-emitting signal line E are disconnected. The on-signal on the second scan signal line S2 turns on the first transistor T1, and the signal on the first initialization signal line INIT1 is provided to the second node N2 via the first transistor T1, initializing (resetting) the storage capacitor C and clearing the existing charge in the storage capacitor. The off-signals on the first scan signal line S1, the third scan signal line S3, the fourth scan signal line S4, and the light-emitting signal line E turn off the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7. During this phase, the OLED does not emit light.

[0103] In the second phase A2, also known as the data writing phase or threshold compensation phase, the signals on the first, third, and fourth scan signal lines S1, S3, and S4 are on, the signals on the second scan signal line S2 and the light-emitting signal line E are off, and the data signal line D outputs a data voltage. During this phase, the second end of the storage capacitor C is at a low level, turning on the third transistor T3. The on-state signals from the first, third, and fourth scan signal lines S1, S3, and S4 turn on the second, fourth, and seventh transistors T2 and T4, causing the data voltage output by the data signal line D to be supplied to the second node N2 via the first node N1, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2. The difference between the data voltage output by the data signal line D and the threshold voltage of the third transistor T3 is then charged into the storage capacitor C. The voltage at the second end of the storage capacitor C (second node N2) is Vd-|Vth|, where Vd is the data voltage output by the data signal line D and Vth is the threshold voltage of the third transistor T3. The seventh transistor T7 is turned on to provide the signal of the second initialization signal line INIT2 to the first electrode of the OLED, thereby initializing (resetting) the first electrode of the OLED and clearing the pre-stored voltage therein, completing the initialization and ensuring that the OLED does not emit light. The off signal of the second scanning signal line S2 turns off the first transistor T1, and the off signal of the light-emitting signal line E turns off the fifth transistor T5 and the sixth transistor T6.

[0104] In the third phase A3, referred to as the light-emitting phase, the signal on the light-emitting signal line E is an on signal, while the signals on the first scan signal line S1, the second scan signal line S2, the third scan signal line S3, and the fourth scan signal line S4 are off signals. The on signal on the light-emitting signal line E turns on the fifth transistor T5 and the sixth transistor T6. The power supply voltage output from the first power supply line VDD provides a driving voltage to the first electrode of the OLED through the turned-on fifth transistor T5, the third transistor T3, and the sixth transistor T6, driving the OLED to emit light.

[0105] During the driving process of the pixel driving circuit, the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its gate electrode and the first electrode. Since the voltage of the second node N2 is Vdata-|Vth|, the driving current of the third transistor T3 is: I=K*(Vgs-Vth) 2 =K*[(Vdd-Vd+|Vth|)-Vth] 2 =K*[(Vdd-Vd)] 2

[0106] Wherein, I is the driving current flowing through the third transistor T3, that is, the driving current driving the OLED, K is a constant, Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor T3, Vth is the threshold voltage of the third transistor T3, Vd is the data voltage output by the data signal line D, and Vdd is the power supply voltage output by the first power supply line VDD.

[0107] With the development of OLED display technology, consumers have increasingly higher requirements for the display effects of display products, and extremely narrow bezels have become a new trend in the development of display products. Therefore, narrowing the bezel or even bezel-free design has received increasing attention in the design of OLED display products. At present, it is difficult to design a narrow lower bezel (the bezel on the side of the binding area) of a display device. In order to reduce the width of the lower bezel, some display substrates mainly adopt FIAA (data fan-out line located in the display area, the full English name is Fanout in AA, abbreviated as FIAA) or FIP (fan-out through the panel, the full English name is Fanout In Panel, abbreviated as FIP) technology, that is, adding new signal lines in the display area, and the data signals of some data signal lines are transmitted by the newly added signal lines. Signal interference often occurs between the newly added signal lines in the display area and the adjacent data signal lines, resulting in the defect of display unevenness (mura) of the display substrate due to signal interference, thereby affecting the display effect of the display substrate.

[0108] An exemplary embodiment of the present disclosure provides a display substrate, which may include: a substrate, and a plurality of data signal lines, a plurality of first power lines, a plurality of first data connection lines, a plurality of second data connection lines, and a plurality of sub-pixels arranged in an array, disposed on the substrate; on a plane parallel to the display substrate, the first data connection lines extend along a first direction, and the data signal lines, the first power lines, and the second data connection lines extend along a second direction, the first direction intersecting the second direction; the first data connection lines, the data signal lines, the first power lines, and the second data connection lines are located on a different conductive layer;

[0109] Any column of sub-pixels is electrically connected to one of the data signal lines and one of the first power lines, and any first power line is electrically connected to multiple sub-pixels in one column of sub-pixels; at least a portion of the data signal lines is electrically connected to at least a portion of the second data connection lines through at least a portion of the first data connection lines; a second data connection line is provided between two adjacent first power lines, and in the first direction, the second data connection line and the data signal line are arranged on both sides of the first power line.

[0110] In a display substrate provided by an embodiment of the present disclosure, any column of sub-pixels in the display substrate is electrically connected to one of the data signal lines and one of the first power lines, any first power line is electrically connected to multiple sub-pixels in one column of sub-pixels, at least a portion of the data signal lines are electrically connected to at least a portion of the second data connection lines through at least a portion of the first data connection lines, a second data connection line is provided between two adjacent first power lines, and in a first direction, the second data connection line and the data signal line are provided on both sides of the first power line, thereby largely avoiding signal interference between the second data connection line and the data signal line, and overcoming the defect of uneven display caused by signal interference.

[0111] As shown in FIG7a to FIG7c, the display substrate provided by the embodiment of the present disclosure may include a substrate 10 and a plurality of data signal lines 81, a plurality of first power lines 82, a plurality of first data connection lines 71, a plurality of second data connection lines 84, and a plurality of sub-pixels Pxij arranged in an array on the substrate 10. In a plane parallel to the display substrate, the first data connection lines 71 extend along a first direction X, and the data signal lines 81, the first power lines 82, and the second data connection lines 84 extend along a second direction Y, where the first direction X intersects the second direction Y. The first data connection lines 71 and the data signal lines 81, the first power lines 82, and the second data connection lines 84 are located on different conductive layers.

[0112] Any column of sub-pixels is electrically connected to one of the data signal lines 81 and one of the first power lines 82, and any first power line 82 is electrically connected to multiple sub-pixels in one column of sub-pixels; at least a portion of the data signal lines 81 are electrically connected to at least a portion of the second data connection lines 84 through at least a portion of the first data connection lines 71; a second data connection line 84 is provided between two adjacent first power lines 82, and in the first direction X, the second data connection line 84 and the data signal line 81 are arranged on both sides of the first power line 82.

[0113] In an exemplary embodiment, the data signal line 81, the first power line 82 and the second data connection line 84 extend along the second direction Y. It can be understood that the main parts of the data signal line 81, the first power line 82 and the second data connection line 84 extend along the second direction Y. For example, the data signal line 81 can be a folded line structure with the main part extending along the second direction Y.

[0114] In the disclosed embodiment, a data fan-out structure (i.e., first data connection lines 71 and second data connection lines 84) is employed, in which data fan-out lines are located in the display area (Fanout in AA, or FIAA for short). For example, as shown in FIG7b , one end of a plurality of second data connection lines 84 located in display area AA2 is located in the display area of ​​the display substrate and is connected to a plurality of data signal lines 81 located in display area AA1 via a plurality of first data connection lines 71. The other ends of the plurality of second data connection lines 84 located in display area AA2 extend to the binding area 200 and are connected to the integrated circuits located in the binding area 200. Because fan-shaped diagonal lines are not required in the binding area 200, the width of the fan-out area is reduced, effectively reducing the width of the bottom frame of the display substrate. Because the second data connection lines 84 are located on the side of the first power line away from the data signal lines, interference between the second data connection lines and adjacent data signal lines can be avoided while reducing the frame, thereby preventing uneven display on the display substrate due to signal interference.

[0115] In an exemplary embodiment, as shown in FIG. 7 a , a sub-pixel in a display substrate may include a plurality of transistors, and orthographic projections of the plurality of second data connection lines 84 on the substrate do not overlap with orthographic projections of channels of the plurality of transistors on the substrate.

[0116] In the embodiment of the present disclosure, the orthographic projection of the second data connection line 84 on the substrate does not overlap with the orthographic projections of the channels of the multiple transistors on the substrate, thereby preventing the signal of the second data connection line 84 from affecting the channels of the transistors.

[0117] In an exemplary embodiment, as shown in FIG7a , a plurality of first data connection lines 71 are disposed between two adjacent sub-pixel rows, and the orthographic projections of the plurality of first data connection lines 71 on the substrate do not overlap with the orthographic projections of the channels of the plurality of transistors on the substrate. In the disclosed embodiment, the orthographic projections of the plurality of first data connection lines 71 on the substrate do not overlap with the orthographic projections of the channels of the plurality of transistors on the substrate, thereby preventing the first data connection lines 71 from affecting the channels of the plurality of transistors.

[0118] In an exemplary embodiment, as shown in FIG. 7 a and FIG. 18 a to FIG. 18 b , the display substrate may further include a plurality of first power connection lines 73 , wherein a main portion of the first power connection lines 73 extends along the first direction X, and the plurality of first power connection lines 73 are arranged along the second direction Y, and the plurality of first power lines 82 are electrically connected to the plurality of sub-pixels through the plurality of first power connection lines 73 ;

[0119] On a plane perpendicular to the display substrate, orthographic projections of the plurality of first power connection lines 73 on the substrate at least partially overlap with orthographic projections of the plurality of second data connection lines 84 on the substrate.

[0120] In an exemplary embodiment, the conductive layer where the plurality of first power connection lines 73 are located is located between the film layer where the plurality of transistors in the sub-pixels are located and the conductive layer where the plurality of second data connection lines 84 are located.

[0121] In the embodiment of the present disclosure, the orthographic projections of the multiple first power connection lines 73 on the substrate overlap with the orthographic projections of the multiple second data connection lines 84 on the substrate, and on a plane perpendicular to the display substrate, the first power connection lines 73 are located between the multiple transistors and the second data connection lines 84. To a certain extent, the multiple first power connection lines 73 can shield the interference of the signals on the second data connection lines 84 on the channels of the transistors, thereby protecting the channels of the multiple transistors in the sub-pixels.

[0122] In an exemplary embodiment, as shown in Figures 7a and 20c, a first power connection line 73 is electrically connected to multiple sub-pixels in a sub-pixel row, and a first power line 82 is electrically connected to multiple sub-pixels in a sub-pixel column via multiple first power connection lines 73. In the disclosed embodiment, multiple sub-pixels in the same sub-pixel row are electrically connected to one first power connection line 73, and any one first power line 82 is electrically connected to multiple sub-pixels in a sub-pixel column via multiple first power connection lines 73. Thus, the first power connection lines 73 and the first power lines 82 can form a grid-like structure, reducing the load on the first power supply voltage routing line, ensuring that the first power supply voltage provided to multiple sub-pixels in the display substrate is as consistent as possible, which is beneficial for improving the uniformity of the panel, avoiding display defects on the display substrate, and ensuring the display quality of the display substrate.

[0123] In an exemplary embodiment, as shown in Figures 7a and 20c, at least one sub-pixel includes a pixel driving circuit, which may include a plurality of transistors, including a driving transistor, a first transistor, and a second transistor, wherein the first transistor is configured to provide an initialization signal to a gate of the driving transistor, a first electrode of the second transistor is connected to the gate of the driving transistor, and a second electrode of the second transistor is connected to the second electrode of the driving transistor; a plurality of first power lines 82 and a plurality of data signal lines 81 are alternately arranged along a first direction X, and two adjacent first power lines 82 are mirror-symmetrical with respect to a second data connection line 84; the first power connection line 73 may include a plurality of first protrusions 731, and in the second direction Y, the plurality of first protrusions 731 are located on one side of a main portion of the first power connection line 73, and the orthographic projections of the first protrusions 731 on the substrate at least partially overlap with the orthographic projections of two adjacent first power lines 82 on the substrate, and the orthographic projections of the first protrusions 731 on the substrate cover the orthographic projections of the channels of the first transistor T1 and the second transistor T2 on both sides of the second data connection line 84 on the substrate.

[0124] In the embodiment of the present disclosure, the two adjacent first power lines are mirror-symmetrical with respect to the second data connection line, and can be absolutely symmetrical or roughly symmetrical, that is, the two adjacent first power lines 82 can be exactly the same in shape or have slightly different shapes.

[0125] In the embodiment of the present disclosure, the first power connection line 73 is provided with a plurality of first protrusions 731, so that the orthographic projections of the plurality of first protrusions 731 on the substrate cover the orthographic projections of the channels of the first transistor T1 and the second transistor T2 located on both sides of the second data connection line 84 on the substrate. The first protrusions 731 shield the interference caused by the signal of the second data connection line 84 on the channels of the first transistor T1 and the second transistor T2, thereby protecting the channels of the first transistor T1 and the second transistor T2 in the sub-pixel.

[0126] In an exemplary embodiment, as shown in FIG7a and FIG20c , the first power connection line 73 may further include a plurality of second protrusions 732. In the same first power connection line 73, the plurality of first protrusions 731 and the plurality of second protrusions 732 are alternately arranged along the first direction X, and in the second direction Y, the plurality of first protrusions 731 and the plurality of second protrusions 732 are located on both sides of the main portion of the first power connection line 73.

[0127] The orthographic projection of the second protrusion 732 on the substrate at least partially overlaps with the orthographic projections of two adjacent data signal lines 81 on the substrate.

[0128] In the disclosed embodiment, by providing a second protrusion 732 on the first power connection line 73, the second protrusion 732 between two adjacent data signal lines 81 can be flush with the first protrusion 731, thereby ensuring that the height and flatness of the anodes of multiple pixels are as consistent as possible. In other words, the anodes of multiple sub-pixels are positioned on the same horizontal plane as much as possible, thereby improving the display uniformity of the display substrate. As shown in Figure 20c, the second protrusion 732 can ensure that the height and flatness of the anode at the second position M2 are consistent with the height and flatness of the anode at the first position M1 where the first protrusion 731 is located.

[0129] In an exemplary embodiment, the pixel driving circuit may further include a storage capacitor, the plurality of transistors may include a plurality of low-temperature polysilicon transistors and at least one oxide transistor, and the display substrate may include, on a plane perpendicular to the display substrate, a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, a fourth conductive layer, a fifth conductive layer, a sixth conductive layer, and an anode conductive layer sequentially stacked on a base;

[0130] The first semiconductor layer includes: an active layer of a plurality of low temperature polysilicon transistors;

[0131] The first conductive layer includes: control electrodes of a plurality of polysilicon transistors and a first electrode plate of a storage capacitor;

[0132] The second conductive layer includes: a second plate of the storage capacitor;

[0133] The second semiconductor layer includes: an active layer of at least one oxide transistor;

[0134] The third conductive layer includes: a control electrode of at least one oxide transistor;

[0135] The fourth conductive layer includes: first and second electrodes of a plurality of low-temperature polysilicon transistors, and first and second electrodes of at least one oxide transistor;

[0136] The fifth conductive layer includes: a plurality of first data connection lines 71 and a plurality of first power connection lines 73;

[0137] The sixth conductive layer includes: a plurality of data signal lines 81, a plurality of first power lines 82 and a plurality of second data connection lines 84;

[0138] Anode conductive layer: includes multiple anodes.

[0139] In an exemplary embodiment, as shown in Figures 22a and 22b, the first power connection line 73 and the first data connection line 74 are located in the fifth conductive layer, the data signal line 81, the first power line 82 and the second data connection line 84 are located in the sixth conductive layer, and the anode conductive layer is located on the side of the sixth conductive layer away from the substrate. The anode conductive layer may include a plurality of anodes 90, and the orthographic projections of the plurality of anodes 90 on the substrate overlap with the orthographic projection of the first protrusion 731 on the substrate, or overlap with the orthographic projection of the second protrusion 732 on the substrate, so that the height and flatness of the anodes in multiple sub-pixels can be kept consistent.

[0140] In an exemplary embodiment, the second data connection line 84 is located between two adjacent columns of sub-pixels, and the two adjacent columns of sub-pixels are mirror-symmetrical with respect to the second data connection line 84. In the first direction X, the two first transistors T1 in the two adjacent columns of sub-pixels are located on both sides of the second data connection line 84, and the two second transistors T2 in the two adjacent columns of sub-pixels are located on both sides of the second data connection line 84; in the same sub-pixel, the second electrode of the first transistor is electrically connected to the second electrode of the second transistor.

[0141] In the embodiment of the present disclosure, two adjacent columns of sub-pixels are mirror-symmetrical with respect to the second data connection line 84 , which may be absolutely symmetrical or roughly symmetrical, that is, the two adjacent sub-pixels may have exactly the same shape or slightly different shapes.

[0142] In an exemplary embodiment, the orthographic projections of the channels of the first transistor T1 and the second transistor T2 in two adjacent columns of sub-pixels located on both sides of the second data connection line 84 are located within the range of the orthographic projection of the first protrusion 731 on the substrate, so that the first protrusion 731 can shield the signal of the second data connection line 84, thereby preventing the signal of the second data connection line 84 from interfering with the channels of the first transistor T1 and the second transistor T2, and can effectively protect the channels of the first transistor T1 and the second transistor T2.

[0143] In an exemplary embodiment, as shown in Figures 7a, 18a and 18b, and 20a to 20c, the multiple transistors may further include a sixth transistor T6, the fifth conductive layer may further include a first anode connection electrode 74, the second electrode of the sixth transistor T6 is connected to the first anode connection electrode 74, and the first electrode of the sixth transistor T6 is connected to the second electrode of the driving transistor. In the first direction X, the two sixth transistors T6 of two adjacent columns of sub-pixels are located on both sides of the second data connection line 84, and the orthographic projection of the channel of the sixth transistor T6 on the substrate is located within the range of the orthographic projection of the first anode connection electrode 74 on the substrate.

[0144] In an exemplary embodiment, the orthographic projection of the channel of the sixth transistor T6 on the substrate is located within the range of the orthographic projection of the first anode connection electrode 74 on the substrate, so that the first anode connection electrode 74 can shield the signal of the second data connection line 84, thereby preventing the signal of the second data connection line 84 from interfering with the sixth transistor T6, thereby protecting the channel of the sixth transistor T6.

[0145] In this exemplary embodiment, a second planar layer is provided between the film layer where the first power connection line is located and the film layer where the first power line is located. The second planar layer located on the first protrusion 731 and the planar layer located on the second protrusion 732 are located on the same plane on the side away from the substrate. This ensures that the height and flatness of the anodes of the multiple sub-pixels located on the second planar layer are largely consistent, thereby improving the display effect. As shown in Figure 20c, the height and flatness of the second planar layer at the first position M1 and the second position M2 are consistent, thereby ensuring that the height and flatness of the anodes located at the first position M1 and the second position M2 are largely consistent.

[0146] In an exemplary embodiment, as shown in Figures 7a and 20a to 20c, the portion where the data signal line 81 overlaps with the second protrusion 732 can be bent toward the first power line 82 adjacent thereto, so that the flatness of the anode located at the second position M2 is consistent with the flatness of the anode located at the first position M1.

[0147] In an exemplary embodiment, as shown in Figures 7a and 20a to 20c, the multiple transistors may further include a fourth transistor T4, which is configured to provide a data signal to the driving transistor. The data signal line 81 includes an integrally formed first portion 811 and a second portion 812. The first portion 811 extends along the second direction Y, and the second portion 812 has a bent structure. The orthographic projection of the second portion 812 on the substrate 10 overlaps with the orthographic projection of the second protrusion on the substrate 10. The orthographic projections of the channel region and the first region of the fourth transistor T4 on the substrate 10 overlap with the orthographic projection of the first portion 811 on the substrate 10. The first portion 811 in two adjacent sub-pixels in the first direction X forms a first opening K1.

[0148] In an exemplary embodiment, the middle portion 8120 of the second portion 812 of the data signal line 81 is bent toward the adjacent first power line 82 , and a second opening K2 is formed in the middle of two adjacent second portions 812 in the first direction X.

[0149] In an exemplary embodiment, the two end portions of the second portion 812 are structures bent in a direction away from the first power line adjacent thereto, and the ratio of the distance R1 between the two data signal lines 81 adjacent to each other at the first opening K1 to the distance R2 between the two data signal lines 81 adjacent to each other at the second opening K2 is 1.1 to 1.6; the ratio of the distance R1 between the two data signal lines 81 adjacent to each other at the first opening K1 to the distance (R31, R32) along the first direction X between the ends of the two data signal lines 81 adjacent to each other at the first opening K1 or the second opening K2 is 1 to 8.

[0150] In an exemplary embodiment, as shown in Figure 20b, the two ends of the second portion 812 may include a first end 8121 and a second end 8122, and the first end 8121 and the second end 8122 are structures that are bent in a direction away from the first power line 82 adjacent thereto, and the ratio of the distance R31 between two adjacent first ends 8121 in the first direction X to the distance R32 between two adjacent second ends 8122 in the first direction X may be 1 to 1.5.

[0151] In an exemplary embodiment, the distance R1 between two adjacent data signal lines 81 at the first opening K1 is greater than the distance R2 between two adjacent data signal lines 81 at the second opening K2; the distance R1 between two adjacent data signal lines 81 at the first opening K1 is greater than the distance R31 between two adjacent first ends 8121 in the first direction X; and the distance R2 between two adjacent data signal lines 81 at the second opening K2 is greater than the distance R32 between two adjacent second ends 8122 in the first direction X.

[0152] In an exemplary embodiment, a distance R1 between two adjacent data signal lines 81 at the first opening K1 may be 15 to 25 micrometers, and a distance R2 between two adjacent data signal lines 81 at the second opening K2 may be 10 to 20 micrometers.

[0153] For example, the distance R1 between two adjacent data signal lines 81 at the first opening K1 can be 19.2 microns, the distance R2 between two adjacent data signal lines 81 at the second opening K2 can be 14.4 microns, the distance R31 between two adjacent first ends 8121 in the first direction X can be 2 microns to 19.2 microns, and the distance R32 between two adjacent second ends 8122 in the first direction X can be 2 microns to 14.4 microns.

[0154] In an exemplary embodiment, as shown in FIG20b , the first end 8121 and the second end 8122 of the second portion 812 of the data signal line 81 bend at an angle of 30 to 60 degrees, away from the adjacent first power line 82. The first end 8121 may include a first bend line a1 and a second bend line a2. A first angle f1 formed between the first bend line a1 and the first portion 811 may be 30 to 60 degrees, and a second angle f2 formed between the second bend line a2 and the first portion 811 may be 30 to 60 degrees. The second end 8122 may include a third bend line a3 and a fourth bend line a4. A third angle f3 formed between the third bend line a3 and the first portion 811 may be 30 to 60 degrees, and a fourth angle f4 formed between the fourth bend line a4 and the first portion 811 may be 80 to 100 degrees. For example, the first angle f1 to the third angle f3 may be 45 degrees, and the fourth angle f4 may be 90 degrees.

[0155] In an exemplary embodiment, a sensing element may be provided at the position of the first opening K1 . For example, the sensing element may be a photosensitive element, such as a photosensor.

[0156] As shown in FIG8 , it is a schematic diagram of an equivalent circuit of a pixel driving circuit provided in an embodiment of the present disclosure. The structural diagram of the pixel driving circuit shown in FIG8 can refer to FIG7 a and FIG20 c .

[0157] In an exemplary embodiment, as shown in Figures 7a and 20c, two adjacent columns of sub-pixels may be symmetrically arranged along a mirror center line Q1-Q1, and the mirror center line Q1-Q1 may be a center line extending along the second direction Y between the two adjacent columns of sub-pixels. The sub-pixels may include first to eighth transistors T1 to T8. In the first direction X, the fourth transistor T4 and the fifth transistor T5 are located on one side of the third transistor T3, the first transistor T1, the second transistor T2, and the sixth transistor T6 are located on the other side of the third transistor T3, and the seventh transistor T7 and the eighth transistor T8 are located between the fifth transistor T5 and the sixth transistor T6. In the second direction Y, the fifth transistor T5 to the eighth transistor T8 are located on one side of the third transistor T3, and the first transistor T1, the second transistor T2, and the fourth transistor T4 are located on the other side of the third transistor T3.

[0158] In an exemplary embodiment, as shown in FIG. 12 b , FIG. 18 a , and FIG. 18 b , the display substrate may further include a first initial signal line 41 extending along the first direction X. An orthographic projection of the first initial signal line 41 on the substrate 10 overlaps with an orthographic projection of the first data connection line 71 on the substrate 10. Signal interference between the first data connection line 71 and the first initial signal line 41 is minimal, and the overlap of the orthographic projections of the first data connection line 71 and the first initial signal line 41 on the substrate 10 can reduce space on the display substrate.

[0159] In an exemplary embodiment, the pixel driving circuit shown in FIG8 has an 8T1C structure. As shown in FIG8 , the pixel driving circuit may include eight transistors (first to eighth transistors T1 to T8) and one storage capacitor C. The pixel driving circuit is connected to ten signal lines (data signal line DL, first scan signal line S1, second scan signal line S2, third scan signal line S3, fourth scan signal line S4, emission signal line EML, first initial signal line Vinit1, second initial signal line Vinit2, third initial signal line Vinit3, first power line VDD, and second power line VSS).

[0160] As shown in Figure 8, the first electrode of the first transistor T1 is connected to the first initial signal line Vinit1, the second electrode of the first transistor T1 is connected to the third node N3, and the control electrode of the first transistor T1 is connected to the first scan signal line S1; the first electrode of the second transistor T2 is connected to the first node N1, the second electrode of the second transistor T2 is connected to the third node N3, and the control electrode of the second transistor T2 is connected to the fourth scan signal line S4; the first electrode of the third transistor T3 is connected to the second node N2, the second electrode of the third transistor T3 is connected to the third node N3, and the control electrode of the third transistor T3 is connected to the first node N1; the first electrode of the fourth transistor T4 is connected to the data signal line DL, the second electrode of the fourth transistor T4 is connected to the second node N2, and the control electrode of the fourth transistor T4 is connected to the second scan signal line S2; the first electrode of the fifth transistor T5 is connected to the first power supply line VDD The second electrode of the fifth transistor T5 is connected to the second node N2, and the control electrode of the fifth transistor T5 is connected to the light emitting signal line EML; the first electrode of the sixth transistor T6 is connected to the third node N3, the second electrode of the sixth transistor T6 is connected to the fourth node N4, and the control electrode of the sixth transistor T6 is connected to the light emitting signal line EML; the first electrode of the seventh transistor T7 is connected to the second initialization signal line Vinit2, the second electrode of the seventh transistor T7 is connected to the fourth node N4, and the control electrode of the seventh transistor T7 is connected to the third scanning signal line S3; the first electrode of the eighth transistor T8 is connected to the third initialization signal line Vinit3, the second electrode of the eighth transistor T8 is connected to the second node N2, and the control electrode of the eighth transistor T8 is connected to the third scanning signal line S3; the first plate of the storage capacitor C is connected to the first node N1, and the second plate of the storage capacitor C is connected to the first power supply line VDD. The fourth node in the pixel driving circuit shown in FIG8 is connected to the anode of the light emitting device (for example, the light emitting device can be a light emitting diode EL).

[0161] In an exemplary embodiment, the first transistor T1 and the third transistor T3 to the eighth transistor T8 are low-temperature polysilicon transistors, and the second transistor T2 is an oxide transistor.

[0162] In an exemplary embodiment, as shown in Figure 7b, the display substrate may include a display area AA and a binding area 200, and in the second direction Y, the binding area 200 is located on one side of the display area AA; the display area AA may include a first display area AA1 and a second display area AA2, and in the first direction X, the first display area AA1 can be located on both sides of the second display area AA2, and the multiple data signal lines 81 located in the first display area AA1 are respectively electrically connected to the multiple second data connection lines 84 located in the second display area AA2 through the multiple first data connection lines 71, and the multiple data signal lines 81 and the multiple second data connection lines 84 located in the second display area AA2 can be connected to the binding area 200.

[0163] In FIG. 7 b , 10 is a substrate, and 300 is a frame area disposed on the substrate 10 and located around the display area AA.

[0164] In an exemplary embodiment, as shown in FIG7c , in the first direction X, on one side of the second center line, a plurality of data signal lines 81 arranged in the direction from the second display area AA2 to the first display area AA1 in the first display area AA1 are electrically connected in sequence to a plurality of second data connection lines 84 in the direction from the second display area AA2 to the second center line through a plurality of first data connection lines 71 in the direction from the binding area 200 to the display area AA; wherein the second center line is the center line of the display substrate extending along the second direction Y.

[0165] In the embodiment of the present disclosure, the multiple data signal lines 81 located in the first display area AA1 are electrically connected to the multiple second data connection lines 84 located in the second display area AA2 through the multiple first data connection lines 71, and the multiple second data connection lines 84 and the multiple data signal lines 81 located in the second display area AA2 are connected to the binding area 200, so that the data signals of the data signal lines 81 located in the first display area AA1 can be transmitted through the second data connection lines 84 located in the second display area AA2 and the multiple first data connection lines 71 located in the display area AA, and the data signal lines 81 located in the first display area AA1 will not occupy the space of the frame (for example, it will not occupy the space of the binding area 200 of the lower frame), thereby reducing the frame of the display substrate.

[0166] In the embodiment of the present disclosure, as shown in Figure 7c, there is no overlap in the transmission direction (the direction indicated by the arrow) of the data signals provided by the multiple second data connection lines 84 and the multiple first data connection lines 71 to the multiple data signal lines 81 located in the first display area AA1 (that is, there is no overlap in the paths of the data signals provided by the multiple second data connection lines 84 and the multiple first data connection lines 71 to the multiple first data connection lines 71 located in the first display area AA1). This can avoid the signals of the second data connection lines 84 and the signals of the multiple first data connection lines 71 from overlapping and generating parasitic capacitance, resulting in differences in the parasitic capacitance of multiple pixels, and can avoid the phenomenon of poor display effects caused by the difference in parasitic capacitance between the first data connection lines 71 and the second data connection lines 84.

[0167] In an exemplary embodiment, as shown in Figures 18a to 20c, the plurality of first data connection lines 71 may be uniformly arranged along the second direction Y, and the plurality of second data connection lines 84 may be uniformly arranged along the first direction X. In the embodiment of the present disclosure, the plurality of first data connection lines 71 being uniformly arranged along the second direction Y may mean that the plurality of first data connection lines 71 are arranged at equal intervals along the second direction Y, and the plurality of second data connection lines 84 being uniformly arranged along the first direction X may mean that the plurality of second data connection lines 84 are arranged at equal intervals along the first direction X.

[0168] The following is an illustrative explanation through the preparation process of the display substrate. The "patterning process" mentioned in the present disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials or transparent conductive materials, and includes processes such as coating organic materials, mask exposure and development for organic materials. Deposition can be carried out by any one or more of sputtering, evaporation, and chemical vapor deposition, coating can be carried out by any one or more of spraying, spin coating and inkjet printing, and etching can be carried out by any one or more of dry etching and wet etching, and the present disclosure does not limit this. "Thin film" refers to a layer of thin film made by deposition, coating or other processes on a substrate (or base substrate). If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". As used in this disclosure, "A and B are disposed in the same layer" means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer refers to the dimension of the film layer in a direction perpendicular to the display substrate. In exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or that the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0169] In an exemplary embodiment, taking 8 sub-pixels (2 sub-pixel rows and 4 sub-pixel columns) in a display area (AA) as an example, a preparation process of a display substrate may include the following operations.

[0170] (101) Prepare a substrate on a glass carrier. In an exemplary embodiment, the substrate may be a flexible substrate or a rigid substrate. The rigid substrate may include, but is not limited to, one or more of glass and quartz, and the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fiber. In an exemplary embodiment, the flexible substrate may include a first flexible material layer, a first inorganic material layer, an adhesive layer, a second flexible material layer, and a second inorganic material layer stacked together. The first and second flexible material layers may be made of polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film, and the first and second inorganic material layers may be made of silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the substrate's resistance to water and oxygen. The first and second inorganic material layers are also referred to as barrier layers, and the adhesive layer may be made of amorphous silicon (a-Si). In an exemplary embodiment, taking the stacked structure PI1 / Barrier1 / a-si / PI2 / Barrier2 as an example, its preparation process may include: first coating a layer of polyimide on a glass carrier, and forming a first flexible material (PI1) layer after curing; then depositing a barrier film on the first flexible layer to form a first barrier (Barrier1) layer covering the first flexible material layer; then depositing a layer of amorphous silicon film on the first barrier layer to form an amorphous silicon (a-si) layer covering the first barrier layer; then coating the amorphous silicon layer with another layer of polyimide, and forming a second flexible material (PI2) layer after curing; then depositing a barrier film on the second flexible layer to form a second barrier (Barrier2) layer covering the second flexible layer, thereby completing the preparation of the substrate.

[0171] (102) Forming a blocking layer pattern. In an exemplary embodiment, forming the blocking layer pattern may include: depositing a conductive film of the blocking layer on a substrate, patterning the conductive film of the blocking layer through a patterning process, and forming a blocking layer pattern on the substrate, as shown in FIG9 , which is a planar structural diagram of the blocking layer pattern in eight sub-pixels.

[0172] In an exemplary embodiment, the shielding layer pattern of each sub-pixel may include a first shielding structure 11, a second shielding structure 12, a third shielding structure 13, and a shielding block 14. The shielding block 14 may be rectangular in shape, and the corners of the rectangle may be chamfered. The first shielding structure 11 may be in the shape of a strip extending along the first direction X, and the first shielding structure 11 is disposed on one side of the shielding block 14 in the first direction X and is connected to the shielding block 14. The second shielding structure 12 may be in the shape of a strip extending along the second direction Y, and the second shielding structure 12 is disposed on a side of the shielding block 14 in the opposite direction of the second direction Y and is connected to the shielding block 14. The third shielding structure 13 may be in the shape of a broken line extending along the second direction Y, and the third shielding structure 13 is disposed on one side of the shielding block 14 in the second direction Y and is connected to the shielding block 14.

[0173] In an exemplary embodiment, the first shielding structure 11 of each sub-pixel is connected to the shielding block 14 of the adjacent sub-pixel in the first direction X, so that the shielding layers in one sub-pixel row are connected as one, forming an interconnected integrated structure.

[0174] In an exemplary embodiment, the second shielding structure 12 of each sub-pixel is connected to the third shielding structure 13 of the adjacent sub-pixel in the second direction Y, so that the shielding layers in one sub-pixel column are connected as a whole to form an interconnected integrated structure.

[0175] In an exemplary embodiment, the blocking layers in the sub-pixel rows and sub-pixel columns are connected as one, which can ensure that the blocking layers in the display substrate have the same potential, which is beneficial to improving the uniformity of the panel, avoiding poor display of the display substrate, and ensuring the display effect of the display substrate.

[0176] In an exemplary embodiment, the blocking layer of the Nth column and the blocking layer of the N+1th column can be mirror-symmetrical with respect to the first center line, the blocking layer of the N+1th column and the blocking layer of the N+2th column can be mirror-symmetrical with respect to the second center line, and the blocking layer of the N+2th column and the blocking layer of the N+3th column can be mirror-symmetrical with respect to the third center line. The first center line, the second center line and the third center line can respectively be straight lines extending along the second direction Y between adjacent sub-pixel columns. For example, the first center line can be a straight line extending along the second direction Y between the sub-pixels in the Nth column and the N+1th column, the second center line can be a straight line extending along the second direction Y between the sub-pixels in the N+1th column and the N+2th column, and the third center line can be a straight line extending along the second direction Y between the sub-pixels in the N+2th column and the N+3th column.

[0177] In an exemplary embodiment, the shapes of the shielding layers in a plurality of sub-pixel rows may be the same.

[0178] In some exemplary embodiments, the blocking layer pattern may not be provided, that is, the first semiconductor layer pattern described below may be directly formed on the substrate.

[0179] (103) Forming a first semiconductor layer pattern. In an exemplary embodiment, forming the first semiconductor layer pattern may include: sequentially depositing a first insulating film and a first semiconductor film on or on the substrate on which the aforementioned pattern is formed, patterning the first semiconductor film through a patterning process to form a covering shielding layer pattern or a first insulating layer disposed on the substrate, and a first semiconductor layer pattern disposed on the first insulating layer, as shown in FIG10a and FIG10b , FIG10a is a planar structural diagram of eight sub-pixels, and FIG10b is a planar schematic diagram of the first semiconductor layer in FIG10a .

[0180] In an exemplary embodiment, the first semiconductor layer pattern of each sub-pixel may include an active layer 21 of the first transistor T1, an active layer 23 of the third transistor T3 to an active layer 28 of the eighth transistor T8, and the active layer 23 of the third transistor T3 to the active layer 27 of the seventh transistor T7 are an integrated structure connected to each other.

[0181] In an exemplary embodiment, in the first direction X, the active layer 24 of the fourth transistor T4 and the active layer 25 of the fifth transistor T5 are located on the same side of the active layer 23 of the third transistor T3, the active layer 21 of the first transistor T1 and the active layer 26 of the sixth transistor T6 are located on the other side of the active layer 23 of the third transistor T3, and the active layer 28 of the eighth transistor T8 is located between the active layer 25 of the fifth transistor T5 and the active layer 27 of the seventh transistor T7; in the second direction Y, the active layer 24 of the fourth transistor T4 and the active layer 25 of the fifth transistor T5 are located on the active layer 23 of the third transistor T3. The active layer 25 of the fifth transistor T5, the active layer 26 of the sixth transistor T6, and the active layer 27 of the seventh transistor T7 are located on the same side of the active layer 23 of the third transistor T3, the active layer 27 of the seventh transistor T7 is located on a side of the active layer 26 of the sixth transistor T6 away from the active layer 23 of the third transistor T3, the active layer 28 of the eighth transistor T8 is located on a side of the active layer 23 of the third transistor T3 away from the active layer 24 of the fourth transistor T4, and the active layer 21 of the first transistor T1 is located on a side of the active layer 23 of the third transistor T3 away from the active layer 26 of the sixth transistor T6.

[0182] In an exemplary embodiment, the sub-pixel in the Mth row and the Nth column is used as an example for description: in the first direction X, the active layer 24 of the fourth transistor T4 and the active layer 25 of the fifth transistor T5 are located on the side of the active layer 23 of the third transistor T3 away from the sub-pixel in the N+1th column, and the active layer 21 of the first transistor T1 and the active layer 26 of the sixth transistor T6 are located on the side of the active layer 23 of the third transistor T3 away from the sub-pixel in the N-1th column; in the second direction Y, the active layer 24 of the fourth transistor T4 is located on the side of the active layer 23 of the third transistor T3 away from the sub-pixel in the M+1th row, and the active layer 26 of the fifth transistor T6 is located on the side of the active layer 23 of the third transistor T3 away from the sub-pixel in the N-1th column. The active layer 25 of the sixth transistor T5, the active layer 26 of the sixth transistor T6, and the active layer 27 of the seventh transistor T7 are located on a side of the active layer 23 of the third transistor T3 away from the sub-pixels in the M-1th row, the active layer 27 of the seventh transistor T7 is located on a side of the active layer 26 of the sixth transistor T6 away from the active layer 23 of the third transistor T3, the active layer 28 of the eighth transistor T8 is located on a side of the active layer 23 of the third transistor T3 away from the active layer 24 of the fourth transistor T4, and the active layer 21 of the first transistor T1 is located on a side of the active layer 23 of the third transistor T3 away from the active layer 26 of the sixth transistor T6.

[0183] In an exemplary embodiment, the active layer 23 of the third transistor T3 may have an Ω shape, the active layer 21 of the first transistor T1, the active layer 24 of the fourth transistor T4, the active layer 26 of the sixth transistor T6, and the active layer 28 of the eighth transistor T8 may have an I shape, the active layer 25 of the fifth transistor T5 may have a Z shape, and the active layer 27 of the seventh transistor T7 may have an L shape.

[0184] In example embodiments, the active layer of each transistor may include a first region, a second region, and a channel region between the first region and the second region. In an exemplary embodiment, the first region 23-1 of the active layer 23 of the third transistor T3 may serve as the second region 24-2 of the active layer 24 of the fourth transistor T4 and the second region 25-2 of the active layer 25 of the fifth transistor T5. The second region 23-2 of the active layer 23 of the third transistor T3 may serve as the first region 26-1 of the active layer 26 of the sixth transistor T6. The second region 26-2 of the active layer 26 of the sixth transistor T6 may serve as the second region 27-2 of the active layer 27 of the seventh transistor T7. The first region 21-1 and the second region 21-2 of the active layer 21 of the first transistor T1, the first region 24-1 of the active layer 24 of the fourth transistor T4, the first region 25-1 of the active layer 25 of the fifth transistor T5, the first region 27-1 of the active layer 27 of the seventh transistor T7, and the first region 28-1 and the second region 28-2 of the active layer 28 of the eighth transistor T8 may be separately provided.

[0185] In an exemplary embodiment, the orthographic projection of the active layer 23 of the third transistor T3 on the substrate may at least partially overlap with the orthographic projection of the blocking block 14 on the substrate. In an exemplary embodiment, the orthographic projection of the channel region of the active layer 23 of the third transistor T3 on the substrate is located within the range of the orthographic projection of the blocking block 14 on the substrate.

[0186] In an exemplary embodiment, the first region 25-1 of the active layer 25 of the fifth transistor T5 in the Nth column and the first region 25-1 of the active layer 25 of the fifth transistor T5 in the N-1th column are interconnected, and the first region 25-1 of the active layer 25 of the fifth transistor T5 in the N+1th column and the first region 25-1 of the active layer 25 of the fifth transistor T5 in the N+2th column are interconnected. In an exemplary embodiment, since the first region of the active layer of the fifth transistor T5 in each sub-pixel is connected to a first power line to be formed later, by forming an integrated structure in which the first regions of the active layers of the fifth transistors T5 of adjacent sub-pixels are interconnected, the first electrodes of the fifth transistors T5 of adjacent sub-pixels can be ensured to have the same potential, which is beneficial for improving the uniformity of the panel display, avoiding display defects of the display substrate, and ensuring the display quality of the display substrate.

[0187] In an exemplary embodiment, the first semiconductor layer in the Nth column and the first semiconductor layer in the N+1th column may be mirror-symmetrical with respect to the first center line, the first semiconductor layer in the N+1th column and the first semiconductor layer in the N+2th column may be mirror-symmetrical with respect to the second center line, and the first semiconductor layer in the N+2th column and the first semiconductor layer in the N+3th column may be mirror-symmetrical with respect to the third center line.

[0188] In an exemplary embodiment, the first semiconductor layer may be made of polycrystalline silicon (p-Si), meaning that the first transistor T1 and the third transistor T3 through the eighth transistor T8 may be LTPS thin-film transistors. In an exemplary embodiment, patterning the first semiconductor thin film through a patterning process may include: first forming an amorphous silicon (a-Si) thin film on the first insulating film, performing a dehydrogenation treatment on the amorphous silicon thin film, and then crystallizing the dehydrogenated amorphous silicon thin film to form a polycrystalline silicon thin film. Subsequently, patterning the polycrystalline silicon thin film to form a first semiconductor layer pattern.

[0189] (104) Forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern may include: sequentially depositing a second insulating film and a first conductive film on the substrate having the aforementioned pattern formed thereon, patterning the first conductive film through a patterning process to form a second insulating layer covering the first semiconductor layer pattern, and a first conductive layer pattern disposed on the second insulating layer, as shown in FIG11a and FIG11b , where FIG11b is a plan view schematic diagram of the first conductive layer in FIG11a . In an exemplary embodiment, the first conductive layer may be referred to as a first gate metal (GATE1) layer.

[0190] In an exemplary embodiment, the first conductive layer pattern may include at least: a first scanning signal line 31, a second scanning signal line 32, a first electrode 33 of a storage capacitor, a light-emitting control line 34, and a third scanning signal line 35. The main parts of the first scanning signal line 31, the light-emitting control line 34, and the third scanning signal line 35 may extend along the first direction X, and the second scanning signal line 32 may be a folded line structure extending along the first direction X. In the same sub-pixel, the first scanning signal line 31, the second scanning signal line 32, the first electrode 33 of the storage capacitor, the light-emitting control line 34, and the third scanning signal line 35 are arranged along the second direction Y.

[0191] In an exemplary embodiment, in the second direction Y, the second scan signal line 32 and the light emission control line 34 are located on both sides of the first plate 33 of the storage capacitor, the first scan signal line 31 is located on a side of the second scan signal line 32 away from the first plate 33 of the storage capacitor, and the third scan signal line 35 is located on a side of the light emission control line 34 away from the first plate 33 of the storage capacitor. For example, in the second direction, the first scan signal line 31, the second scan signal line 32, the first plate 33 of the storage capacitor, the light emission control line 34, and the third scan signal line 35 are arranged in sequence.

[0192] Take the M-th row and N-th column sub-pixel as an example: in the second direction Y, the second scanning signal line 32 can be located on the side of the first plate 33 of the storage capacitor in this sub-pixel close to the M-1-th row sub-pixel; the light-emitting control line 34 can be located on the side of the first plate 33 of the storage capacitor in this sub-pixel close to the M+1-th row sub-pixel; the first scanning signal line 31 can be located on the side of the second scanning signal line 32 close to the M-1-th row sub-pixel; the third scanning signal line 35 can be located on the side of the light-emitting control line 34 close to the M+1-th row sub-pixel.

[0193] In an exemplary embodiment, the first electrode plate 33 may be located between the light-emission control line 34 and the second scan signal line 32. The first electrode plate 33 may be rectangular, and the corners of the rectangle may be chamfered. The orthographic projection of the first electrode plate 33 on the substrate overlaps with the orthographic projection of the active layer of the third transistor T3 on the substrate. In an exemplary embodiment, the first electrode plate 33 may serve as both a plate of the storage capacitor and a control electrode of the third transistor T3.

[0194] In an exemplary embodiment, a region where the light emission control line 34 (i.e., the light emission signal line EML in FIG8 ) overlaps with the active layer of the fifth transistor T5 may serve as the control electrode of the fifth transistor T5, a region where the light emission control line 34 overlaps with the active layer of the sixth transistor T6 may serve as the control electrode of the sixth transistor T6, a region where the first scan signal line 31 (i.e., the first scan signal line S1 in FIG8 ) overlaps with the active layer of the first transistor T1 may serve as the control electrode of the first transistor T1, a region where the second scan signal line 32 (i.e., the second scan signal line S2 in FIG8 ) overlaps with the active layer of the fourth transistor T4 may serve as the control electrode of the fourth transistor T4, a region where the third scan signal line 35 (i.e., the third scan signal line S3 in FIG8 ) overlaps with the active layer of the seventh transistor T7 may serve as the control electrode of the seventh transistor T7, and a region where the third scan signal line 35 overlaps with the active layer of the eighth transistor T8 may serve as the control electrode of the eighth transistor T8.

[0195] In an exemplary embodiment, the first scanning signal line 31, the third scanning signal line 35, and the light emitting control line 34 can be designed with equal width, or can be designed with unequal width, which not only facilitates the layout of the pixel structure but also reduces the parasitic capacitance between the signal lines.

[0196] In an exemplary embodiment, the second scanning signal line 32 can be a bending structure whose main part extends along the first direction X. The second scanning signal line 32 can include a first bending structure 321 and a second bending structure 322. The first bending structure 321 bends in a direction away from the first electrode 33 of the storage capacitor C, and the orthographic projection of the first bending structure 321 on the substrate 10 does not overlap with the orthographic projection of the channel of the subsequently formed second transistor T2 on the substrate 10, thereby avoiding interference of the signal in the second scanning signal line 32 with the channel of the second transistor T2; the second bending structure 322 bends in a direction close to the first electrode 33 of the storage capacitor C, and the orthographic projection of the second bending structure 322 on the substrate 10 does not overlap with the orthographic projection of the subsequently formed first opening K1 on the substrate 10, thereby avoiding blocking the subsequently formed first opening K1.

[0197] In an exemplary embodiment, after forming the first conductive layer pattern, the first conductive layer can be used as a shield to perform conductorization on the semiconductor layer. The semiconductor layer in the area shielded by the first conductive layer forms the channel region of the first transistor T1 and the third transistor T3 to the eighth transistor T8, and the semiconductor layer in the area not shielded by the first conductive layer is conductorized, that is, the first region and the second region of the active layer 21 of the first transistor T1 and the active layer 23 of the third transistor T3 to the active layer 28 of the eighth transistor T8 are all conductorized.

[0198] (105) Forming a second conductive layer pattern. In an exemplary embodiment, forming the second conductive layer pattern may include: sequentially depositing a third insulating film and a second conductive film on the substrate on which the aforementioned pattern is formed, patterning the second conductive film using a patterning process to form a third insulating layer covering the first conductive layer, and a second conductive layer pattern disposed on the third insulating layer, as shown in FIG12a and FIG12b, FIG12a is a planar structural diagram of eight sub-pixels, and FIG12b is a planar schematic diagram of the second conductive layer in FIG12a. In an exemplary embodiment, the second conductive layer may be referred to as a second gate metal (GATE2) layer.

[0199] In an exemplary embodiment, the second conductive layer pattern includes at least: a first initial signal line 41, a first shielding line 42, and a second plate 43 of a storage capacitor. The main portions of the first initial signal line 41 (i.e., the first initial signal line Vinit1 in FIG8 ) and the first shielding line 42 may extend along the first direction X. The second plate 43 of the storage capacitor serves as another plate of the storage capacitor. In the second direction Y, the first shielding line 42 is located between the first initial signal line 41 and the second plate 43. For example, in the same sub-pixel, the first initial signal line 41, the first shielding line 42, and the second plate 43 of the storage capacitor (i.e., the storage capacitor C in FIG8 ) are arranged sequentially along the second direction Y.

[0200] In an exemplary embodiment, the first shielding line 42 is configured as a shielding layer for the second transistor T2, shielding the channel of the second transistor T2 to ensure the electrical performance of the oxide second transistor T2. In an exemplary embodiment, the first shielding line 42 and the subsequently formed fourth scan signal line 51 can have the same signal. That is, the first shielding line 42 and the subsequently formed fourth scan signal line 51 are connected in parallel and are connected to the same signal source. This allows the first shielding line 42 to serve as the bottom gate electrode (i.e., bottom control electrode) of the second transistor T2, forming a dual-gate structure for the second transistor T2.

[0201] In an exemplary embodiment, the outline of the second electrode plate 43 can be rectangular, and the corners of the rectangle can be chamfered. The orthographic projection of the second electrode plate 43 on the substrate overlaps with the orthographic projection of the first electrode plate 33 on the substrate. The first electrode plate 33 and the second electrode plate 43 constitute the storage capacitor of the pixel driving circuit. An opening 44 is provided on the second electrode plate 43, and the opening 44 can be located in the middle of the second electrode plate 43. The opening 44 can be rectangular, so that the second electrode plate 43 forms a ring structure. The opening 44 exposes the third insulating layer covering the first electrode plate 33, and the orthographic projection of the first electrode plate 33 on the substrate includes the orthographic projection of the opening 44 on the substrate. In an exemplary embodiment, the opening 44 is configured to accommodate a thirteenth via hole formed subsequently. The ninth via hole is located within the opening 44 and exposes the first electrode plate 33, so that the first electrode of the second transistor T2 formed subsequently is connected to the first electrode plate 33.

[0202] (106) Forming a second semiconductor layer pattern. In an exemplary embodiment, forming the second semiconductor layer pattern may include: sequentially depositing a fourth insulating film and a second semiconductor film on the substrate on which the aforementioned pattern is formed, patterning the second semiconductor film through a patterning process to form a fourth insulating layer covering the substrate, and a second semiconductor layer pattern disposed on the fourth insulating layer, as shown in FIG13a and FIG13b, where FIG13a is a planar structural diagram of eight sub-pixels, and FIG13b is a planar schematic diagram of the second semiconductor layer in FIG13a.

[0203] In an exemplary embodiment, the second semiconductor layer pattern in each sub-pixel includes at least an active layer 22 of the second transistor T2 .

[0204] In an exemplary embodiment, the active layer 22 of the second transistor T2 may have an L-shape, and the first region 22 - 1 and the second region 22 - 2 of the active layer 22 of the second transistor T2 may be separately provided.

[0205] In an exemplary embodiment, the second semiconductor layer in the Nth column and the second semiconductor layer in the N+1th column may be mirror-symmetrical with respect to the first center line, the second semiconductor layer in the N+1th column and the second semiconductor layer in the N+2th column may be mirror-symmetrical with respect to the second center line, and the second semiconductor layer in the N+2th column and the second semiconductor layer in the N+3th column may be mirror-symmetrical with respect to the third center line.

[0206] In example embodiments, the shapes of the second semiconductor layers in a plurality of sub-pixel rows may be the same.

[0207] In an exemplary embodiment, within the plane of the display substrate, in the first direction X, the active layer 21 of the first transistor T1 and the active layer 22 of the second transistor T2 are located on the same side of the active layer 23 of the third transistor T3; in the second direction Y, the active layer 22 of the second transistor T2 is located on a side of the active layer 23 of the third transistor T3 away from the active layer 26 of the sixth transistor T6. For example, in the second direction Y, the active layer 22 of the second transistor T2 may be located between the active layer 21 of the first transistor T1 and the active layer 26 of the sixth transistor T6.

[0208] In an exemplary embodiment, the sub-pixel in the Mth row and Nth column is used as an example for description: in the first direction X, the active layer 21 of the first transistor T1, the active layer 22 of the second transistor T2, and the active layer 26 of the sixth transistor T6 are located on a side of the active layer 23 of the third transistor T3 away from the sub-pixel in the N-1th column; in the second direction Y, the active layer 22 of the second transistor T2 is located on a side of the active layer 23 of the third transistor T3 away from the sub-pixel in the M+1th row.

[0209] In an exemplary embodiment, the second semiconductor layer may be made of an oxide, i.e., the second transistor T2 is an oxide thin-film transistor. In an exemplary embodiment, the oxide may be any one or more of the following: indium gallium zinc oxide (InGaZnO), indium gallium zinc oxynitride (InGaZnON), zinc oxide (ZnO), zinc oxynitride (ZnON), zinc tin oxide (ZnSnO), cadmium tin oxide (CdSnO), gallium tin oxide (GaSnO), titanium tin oxide (TiSnO), copper aluminum oxide (CuAlO), strontium copper oxide (SrCuO), lanthanum copper oxysulfide (LaCuOS), gallium nitride (GaN), indium gallium nitride (InGaN), aluminum gallium nitride (AlGaN), and indium gallium aluminum nitride (InGaAlN). In some possible implementations, the second semiconductor thin film may be made of indium gallium zinc oxide (IGZO), which has higher electron mobility than amorphous silicon. Since the leakage current of the IGZO TFT is relatively small, the second transistor T2 is an N-type transistor, which can prevent the first node N1 from leaking during the light-emitting stage.

[0210] (107) Forming a third conductive layer pattern. In an exemplary embodiment, forming the third conductive layer pattern may include: depositing a fifth insulating film and a third conductive film in sequence on the substrate on which the aforementioned pattern is formed, patterning the third conductive film using a patterning process to form a fifth insulating layer covering the second semiconductor layer, and a third conductive layer pattern disposed on the fifth insulating layer, as shown in FIG14a and FIG14b, FIG14a is a planar structural diagram of eight sub-pixels, and FIG14b is a planar schematic diagram of the third conductive layer in FIG14a. In an exemplary embodiment, the third conductive layer may be referred to as a third gate metal (GATE3) layer.

[0211] In an exemplary embodiment, the third conductive layer pattern includes at least: a fourth scanning signal line 51 and a third initial signal line 52 (i.e., the third initial signal line Vinit3 in Figure 8). The main parts of the fourth scanning signal line 51 and the third initial signal line 52 can extend along the first direction X. In the same sub-pixel row, the fourth scanning signal line 51 and the third initial signal line 52 are arranged sequentially along the second direction Y.

[0212] In an exemplary embodiment, a region where the fourth scan signal line 51 (ie, the fourth scan signal line S4 in FIG. 8 ) overlaps with the active layer 22 of the second transistor T2 serves as a control electrode of the second transistor T2 .

[0213] In an exemplary embodiment, the signals of the first shielding line 42 and the fourth scanning signal line 51 can be the same, that is, the two are connected in parallel and connected to the same signal source, so that the first shielding line 42 can serve as the bottom gate electrode (that is, the bottom control electrode) of the second transistor T2, forming a second transistor T2 with a dual-gate structure.

[0214] (108) Forming a sixth insulating layer pattern. In an exemplary embodiment, forming the sixth insulating layer pattern may include: depositing a sixth insulating film on the substrate on which the aforementioned pattern is formed, patterning the sixth insulating film using a patterning process to form a sixth insulating layer covering the third conductive layer, wherein the sixth insulating layer is provided with a plurality of via holes, as shown in FIG15 , which is a planar structural diagram of eight sub-pixels.

[0215] In an exemplary embodiment, the multiple via holes in each sub-pixel include at least: a first via hole V1, a second via hole V2, a third via hole V3, a fourth via hole V4, a fifth via hole V5, a sixth via hole V6, a seventh via hole V7, an eighth via hole V8, a ninth via hole V9, a tenth via hole V10, an eleventh via hole V11, a twelfth via hole V12, a thirteenth via hole V13, a fourteenth via hole V14, a fifteenth via hole V15, and a sixteenth via hole V16.

[0216] In an exemplary embodiment, the orthographic projection of the first via hole V1 on the substrate is located within the orthographic projection of the active layer 21 of the first transistor T1 on the substrate. The sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer, and the second insulating layer within the first via hole V1 are etched away, exposing the surface of the first region 21-1 of the active layer 21 of the first transistor T1. The first via hole V1 is configured to connect the first electrode of the subsequently formed first transistor T1 to the active layer 21 of the first transistor T1 through the via hole.

[0217] In an exemplary embodiment, the orthographic projection of the second via V2 on the substrate is located within the orthographic projection of the active layer 21 of the first transistor T1 on the substrate. The sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer, and the second insulating layer within the second via V2 are etched away, exposing the surface of the second region 21-2 of the active layer 21 of the first transistor T1. The second via V2 is configured to connect the second electrode of the subsequently formed first transistor T1 to the active layer 21 of the first transistor T1 through the via.

[0218] In the exemplary embodiment, the orthographic projection of the third via V3 on the substrate is located within the orthographic projection of the active layer 22 of the second transistor T2 on the substrate. The sixth insulating layer and the fifth insulating layer within the third via V3 are etched away, exposing the surface of the first region 22-1 of the active layer 22 of the second transistor T2. The third via V3 is configured to connect the first electrode of the subsequently formed second transistor T2 to the active layer 22 of the second transistor T2 through the via.

[0219] In the exemplary embodiment, the orthographic projection of the fourth via V4 on the substrate is located within the orthographic projection of the active layer 22 of the second transistor T2 on the substrate. The sixth insulating layer and the fifth insulating layer within the fourth via V4 are etched away, exposing the surface of the second region 22-2 of the active layer 22 of the second transistor T2. The fourth via V4 is configured to connect the second electrode of the subsequently formed second transistor T2 to the active layer 22 of the second transistor T2 through the via.

[0220] In the exemplary embodiment, the orthographic projection of the fifth via V5 on the substrate is located within the orthographic projection of the active layer 24 of the fourth transistor T4 on the substrate. The sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer, and the second insulating layer within the fourth via V4 are etched away, exposing the first region 24-1 of the active layer 24 of the fourth transistor T4. The fifth via V5 is configured to connect the first electrode of the subsequently formed fourth transistor T4 to the active layer 24 of the fourth transistor T4 through the via.

[0221] In an exemplary embodiment, the orthographic projection of the sixth via V6 on the substrate is located within the orthographic projection of the active layer 25 of the fifth transistor T5 on the substrate. The sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer, and the second insulating layer within the sixth via V6 are etched away, exposing the surface of the first region 25-1 of the active layer 25 of the fifth transistor T5. The sixth via V6 is configured to connect the first electrode of the subsequently formed fifth transistor T5 to the active layer 25 of the fifth transistor T5 through the via.

[0222] In an exemplary embodiment, the orthographic projection of the seventh via V7 on the substrate is within the range of the orthographic projection of the active layer 25 of the fifth transistor T5 on the substrate. The sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer, and the second insulating layer within the seventh via V7 are etched away, exposing the surface of the second region 25-2 of the active layer 25 of the fifth transistor T5 (which is also the first region of the active layer 23 of the third transistor T3 and the second region 24-2 of the active layer 24 of the fourth transistor T4). The fifth via V5 is configured to connect the second electrode of the subsequently formed fifth transistor T5 to the active layer 25 of the fifth transistor T5 through the via, connect the first electrode of the subsequently formed third transistor T3 to the active layer 23 of the third transistor T3 through the via, and connect the second electrode of the subsequently formed fourth transistor T4 to the active layer 24 of the fourth transistor T4 through the via.

[0223] In an exemplary embodiment, the orthographic projection of the eighth via V8 on the substrate is located within the orthographic projection of the active layer 26 of the sixth transistor T6 on the substrate. The sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer, and the second insulating layer within the sixth via V6 are etched away, exposing the surface of the first region 26-1 of the active layer 26 of the sixth transistor T6 (which is also the second region of the active layer 23 of the third transistor T3 and the second region of the active layer 27 of the seventh transistor T7). The eighth via V8 is configured to connect the first electrode of the subsequently formed sixth transistor T6 to the active layer 26 of the sixth transistor T6 through the via, connect the second electrode of the subsequently formed third transistor T3 to the active layer 23 of the third transistor T3 through the via, and connect the second electrode of the subsequently formed seventh transistor T7 to the active layer 27 of the seventh transistor T7 through the via.

[0224] In an exemplary embodiment, the orthographic projection of the ninth via V9 on the substrate is located within the orthographic projection of the active layer 26 of the sixth transistor T6 on the substrate. The sixth, fifth, fourth, third, and second insulating layers within the ninth via V9 are etched away, exposing the surface of the second region 26-2 of the active layer 26 of the sixth transistor T6 (also the second region 27-2 of the active layer 27 of the seventh transistor T7). The ninth via V9 is configured to connect the second electrode of the subsequently formed sixth transistor T6 to the active layer 26 of the sixth transistor T6 through the via, and to connect the second electrode of the subsequently formed seventh transistor T7 to the active layer 27 of the seventh transistor T7 through the via.

[0225] In an exemplary embodiment, the orthographic projection of the tenth via V10 on the substrate is located within the orthographic projection of the active layer 27 of the seventh transistor T7 on the substrate. The sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer, and the second insulating layer within the tenth via V10 are etched away, exposing the surface of the first region 27-1 of the active layer 27 of the seventh transistor T7. The tenth via V10 is configured to connect the first electrode of the subsequently formed seventh transistor T7 to the active layer 27 of the seventh transistor T7 through the via.

[0226] In an exemplary embodiment, the orthographic projection of the eleventh via hole V11 on the substrate is located within the orthographic projection of the active layer 28 of the eighth transistor T8 on the substrate. The sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer, and the second insulating layer within the eleventh via hole V11 are etched away, exposing the surface of the first region 28-1 of the active layer 28 of the eighth transistor T8. The eleventh via hole V11 is configured to connect the first electrode of the subsequently formed eighth transistor T8 to the active layer 28 of the eighth transistor T8 through the via hole.

[0227] In an exemplary embodiment, the orthographic projection of the twelfth via V12 on the substrate is located within the range of the orthographic projection of the active layer 28 of the eighth transistor T8 on the substrate. The sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer, and the second insulating layer within the twelfth via V12 are etched away, exposing the surface of the second region 28-2 of the active layer 28 of the eighth transistor T8. The twelfth via V12 is configured to connect the second electrode of the subsequently formed eighth transistor T8 to the active layer 28 of the eighth transistor T8 through the via.

[0228] In the exemplary embodiment, the orthographic projection of the thirteenth via hole V13 on the substrate is within the range of the orthographic projection of the opening 44 on the substrate. The sixth insulating layer, the fifth insulating layer, the fourth insulating layer, and the third insulating layer within the thirteenth via hole V13 are etched away, exposing the surface of the first electrode plate 33. The thirteenth via hole V13 is configured to connect the first electrode of the second transistor T2 formed subsequently to the first electrode plate 33 through the via hole.

[0229] In an exemplary embodiment, the fourteenth via hole V14 is located within the orthographic projection of the second electrode plate 43 on the substrate. The sixth insulating layer, the fifth insulating layer, and the fourth insulating layer within the fourteenth via hole V14 are etched away, exposing the surface of the second electrode plate 43. The fourteenth via hole V14 is configured to connect a subsequently formed fifth connection electrode to the second electrode plate 43 through the via hole. In an exemplary embodiment, a plurality of fourteenth via holes V14 serving as power via holes may be included, and the plurality of fourteenth via holes V14 may be arranged sequentially along the second direction Y or the first direction X to increase the reliability of the connection between the first power connection line and the second electrode plate 43.

[0230] In an exemplary embodiment, the orthographic projection of the fifteenth via hole V15 on the substrate is located within the range of the orthographic projection of the first initial signal line 41 on the substrate. The sixth insulating layer, the fifth insulating layer, and the fourth insulating layer within the fifteenth via hole V15 are etched away, exposing the surface of the first initial signal line 41. The fifteenth via hole V15 is configured to connect the first electrode of the subsequently formed first transistor T1 to the first initial signal line 41 through the via hole.

[0231] In an exemplary embodiment, the orthographic projection of the sixteenth via hole V16 on the substrate is located within the range of the orthographic projection of the third initial signal line 52 on the substrate. The sixth insulating layer, the fifth insulating layer, and the fourth insulating layer within the sixteenth via hole V16 are etched away, exposing the surface of the third initial signal line 52. The sixteenth via hole V16 is configured to connect a subsequently formed eighth connection electrode 68 to the third initial signal line 52 through the via hole.

[0232] (109) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming the fourth conductive layer may include: depositing a fourth conductive film on the substrate having the aforementioned pattern formed thereon, patterning the fourth conductive film using a patterning process, and forming a fourth conductive layer disposed on the sixth insulating layer, as shown in FIG. 16a and FIG. 16b , where FIG. 16a is a planar structural diagram of eight sub-pixels, and FIG. 16b is a planar schematic diagram of the fourth conductive layer in FIG. 16a . In an exemplary embodiment, the fourth conductive layer may be referred to as a first source / drain metal (SD1) layer.

[0233] In an exemplary embodiment, the fourth conductive layer includes at least: a first connecting electrode 61, a second connecting electrode 62, a third connecting electrode 63, a fourth connecting electrode 64, a fifth connecting electrode 65, a sixth connecting electrode 66, a seventh connecting electrode 67, an eighth connecting electrode 68, a second initial signal line 69 (i.e., the second initial signal line Vinit2 in Figure 8), and a second initial signal connecting line 610.

[0234] In an exemplary embodiment, the first connection electrode 61 may be in the shape of a strip with a main portion extending along the first direction X. The first connection electrode 61 is connected to the first region 21-1 of the active layer 21 of the first transistor T1 through a first via hole V1, and is connected to the first initial signal line 41 in the sub-pixels in a sub-pixel row through a fifteenth via hole V15 in the row. In an exemplary embodiment, the first connection electrode 61 may serve as the first electrode of the first transistor T1 and is configured to be connected to the first initial signal line 45 and the active layer 21 of the first transistor T1.

[0235] In an exemplary embodiment, the Nth column and the N+1th column share the same first connection electrode 61, and the N+2th column and the N+3th column share the same first connection electrode 61. In an exemplary embodiment, since the first connection electrode 61 in each sub-pixel is connected to the first initial signal line 41, by forming an interconnected integral structure with adjacent sub-pixels sharing the same first connection electrode 61, it is possible to ensure that the first connection electrodes 61 of adjacent sub-pixels have the same potential, which is beneficial for improving the uniformity of the panel, avoiding display defects on the display substrate, and ensuring the display effect of the display substrate.

[0236] In an exemplary embodiment, the main portion of the second connection electrode 62 extends along the second direction Y. Its first end is connected to the second region 21-2 of the active layer 21 of the first transistor T1 through the second via V2. Its second end is connected to the second region 22-2 of the active layer 22 of the second transistor T2 through the fourth via V4. Furthermore, it is connected to the first region 26-1 of the active layer 26 of the sixth transistor T6 (also the second region 23-2 of the active layer 23 of the third transistor T3) through the eighth via V8. This allows the second electrodes of the first transistor T1, the second transistor T2, the third transistor T3, and the first electrode of the sixth transistor T6 to have the same potential. In an exemplary embodiment, the second connection electrode 62 can function as the second electrode of the first transistor T1, the second electrode of the third transistor T3, and the first electrode of the sixth transistor T6.

[0237] In an exemplary embodiment, one end of the third connection electrode 63 is connected to the first region 22-1 of the active layer 22 of the second transistor T2 through a third via hole V3, and the other end of the third connection electrode 63 is connected to the first electrode plate 33 through a thirteenth via hole V13. In an exemplary embodiment, the third connection electrode 63 can serve as the first electrode of the second transistor T2.

[0238] In an exemplary embodiment, the fourth connection electrode 64 is connected to the first region 24-1 of the active layer 24 of the fourth transistor T4 through the fifth via hole V5. In an exemplary embodiment, the fourth connection electrode 64 may serve as a first electrode of the fourth transistor T4 and be configured to be electrically connected to a subsequently formed data signal line.

[0239] In an exemplary embodiment, the fifth connection electrode 65 is connected to the first region 25-1 of the active layer 25 of the fifth transistor T5 through a sixth via hole V6, and the fifth connection electrode 65 is connected to the second electrode plate 43 through a fourteenth via hole V14. In an exemplary embodiment, the fifth connection electrode 65 can serve as a first electrode of the fifth transistor T5 and is configured to be connected to a first power connection line formed later.

[0240] In an exemplary embodiment, the sixth connection electrode 66 is connected to the second region 26-2 of the active layer 26 of the sixth transistor T6 (also the second region 27-2 of the active layer 27 of the seventh transistor T7) through a ninth via hole V9. In an exemplary embodiment, the sixth connection electrode 66 may serve as the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7. The sixth connection electrode 66 is configured to be connected to an anode connection electrode of a subsequently formed light-emitting element.

[0241] In an exemplary embodiment, one end of the seventh connection electrode 67 is connected to the second region 25-2 of the active layer 25 of the fifth transistor T5 (also the second region 24-2 of the active layer 24 of the fourth transistor T4 and the first region 23-1 of the active layer 23 of the third transistor T3) via a seventh via hole V7, and the other end is connected to the second region 28-2 of the active layer 28 of the eighth transistor T8 via a twelfth via hole V12. In an exemplary embodiment, the seventh connection electrode 67 can serve as the first electrode of the third transistor T3, the second electrode of the fourth transistor T4, the second electrode of the fifth transistor T5, and the second electrode of the eighth transistor T8.

[0242] In an exemplary embodiment, one end of the eighth connection electrode 68 may be connected to the first region 28-1 of the active layer 28 of the eighth transistor T8 through the eleventh via hole V11, and the other end may be connected to the third initial signal line 52 through the sixteenth via hole V16. In an exemplary embodiment, the eighth connection electrode 68 may serve as the first electrode of the eighth transistor T8.

[0243] In an exemplary embodiment, the second initial signal line 69 may be in the shape of a zigzag line, with a main portion extending along the first direction X. The second initial signal line 69 is connected to the first region 27-1 of the active layer 27 of the plurality of seventh transistors T7 in a subpixel row through a plurality of tenth via holes V10 in a subpixel row, thereby writing an initial voltage into the plurality of seventh transistors T7 in a subpixel row. In an exemplary embodiment, since the second initial signal line 69 is connected to the first region 27-1 of the active layer 27 of all the seventh transistors T7 in a subpixel row, the first electrodes of all the seventh transistors T7 in a subpixel row can be ensured to have the same potential, which is beneficial for improving the uniformity of the panel, preventing display defects on the display substrate, and ensuring the display quality of the display substrate. In an exemplary embodiment, the second initial signal line 67 can serve as the first electrode of the seventh transistor T7.

[0244] In an exemplary embodiment, the second initial signal connection line 610 may be in the shape of a zigzag line, with a main portion extending along the second direction Y, and its ends connected to two adjacent second initial signal lines 69. In the second direction Y, the second initial signal line 69 is located between the two adjacent second initial signal lines 69. In an exemplary embodiment, the second initial signal connection line 610 and the second initial signal line 69 may be an integrally formed structure. In an exemplary embodiment, the second initial signal connection line 610 connects multiple second initial signal lines 69 arranged along the second direction Y into an integral structure, so that the multiple second initial signal lines 69 have the same potential, which is beneficial for improving the uniformity of the panel, avoiding display defects on the display substrate, improving low grayscale image quality, and ensuring the display effect of the display substrate. In an exemplary embodiment, the second initial signal connection line 610 can be arranged in odd-numbered sub-pixel columns or even-numbered sub-pixel columns. For example, as shown in Figure 16b, the second initial signal connection line 610 can be arranged in the Nth column and the N+2th column. In an exemplary embodiment, in the first direction X, the spacing between two adjacent second initial signal connection lines 610 can be consistent with the width of the two adjacent sub-pixel columns.

[0245] In an exemplary embodiment, the second initial signal connection line 610 is disposed in an odd-numbered sub-pixel column or an even-numbered sub-pixel column. For example, if the second initial signal connection line 610 is disposed in an odd-numbered sub-pixel column, the even-numbered sub-pixel column may not be provided with the second initial signal connection line 610. Alternatively, if the second initial signal connection line 610 is disposed in an even-numbered sub-pixel column, the odd-numbered sub-pixel column may not be provided with the second initial signal connection line 610. In the first direction X, the distance between the fourth connection electrode 64 and the third connection electrode 63 in the sub-pixel column where the second initial signal connection line 610 is disposed may be greater than the distance between the fourth connection electrode 64 and the third connection electrode 63 in the sub-pixel column where the second initial signal connection line 610 is not disposed.

[0246] (110) Forming a seventh insulating layer and a first planar layer pattern. In an exemplary embodiment, forming the seventh insulating layer and the first planar layer pattern may include: first depositing a seventh insulating film on the substrate on which the aforementioned pattern is formed, then coating the first planar film, patterning the first planar film and the seventh insulating film using a patterning process to form a seventh insulating layer covering the fourth conductive layer pattern and a first planar layer disposed on the seventh insulating layer, wherein a plurality of vias are disposed on the seventh insulating layer and the first planar layer, as shown in FIG17 , which is a planar structural diagram of eight sub-pixels.

[0247] In an exemplary embodiment, the plurality of via holes in each sub-pixel may include at least a seventeenth via hole V17 , an eighteenth via hole V18 , and a nineteenth via hole V19 .

[0248] In an exemplary embodiment, the orthographic projection of the seventeenth via hole V17 on the substrate is located within the range of the orthographic projection of the fourth connection electrode 64 on the substrate. The first planar layer and the seventh insulating layer within the seventeenth via hole V17 are etched away, exposing the surface of the fourth connection electrode 64. The seventeenth via hole V17 is configured to allow a subsequently formed data signal line to be connected to the fourth connection electrode 64 through the via hole.

[0249] In an exemplary embodiment, the orthographic projection of the eighteenth via hole V18 on the substrate is located within the range of the orthographic projection of the sixth connection electrode 66 on the substrate. The first planar layer and the seventh insulating layer within the eighteenth via hole V18 are etched away, exposing the surface of the fifth connection electrode 65. The eighteenth via hole V18 is configured to electrically connect the anode connection electrode of a subsequently formed light-emitting element to the sixth connection electrode 66 through the via hole.

[0250] In an exemplary embodiment, the orthographic projection of the nineteenth via hole V19 on the substrate is located within the range of the orthographic projection of the fifth connection electrode 65 on the substrate. The first planar layer and the seventh insulating layer within the nineteenth via hole V19 are etched away, exposing the surface of the fifth connection electrode 65. The nineteenth via hole V19 is configured to connect a subsequently formed first power connection line to the fifth connection electrode 65 through the via hole.

[0251] In an exemplary embodiment, in the first direction X, the distance between the seventeenth via hole V17 in the sub-pixel column where the second initial signal connection line 610 is set and the third connection electrode 63 is greater than the distance between the seventeenth via hole V17 and the third connection electrode 63 in the sub-pixel column where the second initial signal connection line 610 is not set. On the one hand, the space for accommodating the second initial signal connection line 610 can be increased, and on the other hand, the space of the sub-pixel column where the second initial signal connection line 610 is not set can be saved.

[0252] (111) Forming a fifth conductive layer pattern. In an exemplary embodiment, forming the fifth conductive layer may include: depositing a fifth conductive film on the substrate having the aforementioned pattern formed thereon, and patterning the fifth conductive film using a patterning process to form a fifth conductive layer disposed on the first flat layer, as shown in FIG. 18a and FIG. 18b , where FIG. 18a is a planar structural diagram of eight sub-pixels, and FIG. 18b is a planar schematic diagram of the fifth conductive layer in FIG. 18a . In an exemplary embodiment, the fifth conductive layer may be referred to as a second source / drain metal (SD2) layer.

[0253] In an exemplary embodiment, the fifth conductive layer at least includes: a first data connection line 71 , a data line connection electrode 72 , a first power connection line 73 , and a first anode connection electrode 74 .

[0254] In an exemplary embodiment, the first data connection line 71 may be in the shape of a zigzag line with a main portion extending along the first direction X. The first data connection line 71 is configured to be electrically connected to a subsequently formed data signal line. In an exemplary embodiment, a plurality of first electrode connection blocks 711 may be provided on the first data connection line 71. The first electrode connection blocks 711 at positions electrically connected to the subsequently formed second data connection lines 84 are electrically connected to the second data connection lines 84 (second electrode connection blocks 841) through vias, and no vias are provided at positions not electrically connected to the second data connection lines 84. In the disclosed embodiment, the first electrode connection blocks 711 in the first data connection lines 71 are arranged in a consistent manner in multiple sub-pixels (including a plurality of first electrode connection blocks 711 not connected to the second data connection lines 84 and a first electrode connection block 711 connected to the second data connection lines 84), which can improve the display uniformity of the display substrate.

[0255] In an exemplary embodiment, the orthographic projection of the first data link line 71 on the substrate 10 at least partially overlaps with the orthographic projection of the first initial signal line 41 on the substrate 10, and the signal interference between the first data link line 71 and the first initial signal line 41 is very small. The overlap of the orthographic projections of the first data link line 71 and the first initial signal line 41 on the substrate 10 can save space on the display substrate.

[0256] In an exemplary embodiment, the data line connection electrode 72 may be electrically connected to the fourth connection electrode 64 through the seventeenth via hole V17 , and the data line connection electrode 72 is configured to be electrically connected to a subsequently formed data signal line.

[0257] In an exemplary embodiment, the first power connection line 73 may be in the shape of a zigzag line with a main portion extending along the first direction X. The first power connection line 73 may be connected to the fifth connection electrode 65 through a nineteenth via hole V19. Since the fifth connection electrode 65 is connected to the second electrode plate 43 through the via hole, the first power connection line 73 is connected to the second electrode plate 43, and the power signal is written to the second electrode plate 43. Since the fifth connection electrode 65 is connected to the first region 25-1 of the active layer 25 of the fifth transistor T5 through the via hole, the first power connection line 73 is connected to the first electrode of the fifth transistor T5, and the power signal is written to the fifth transistor T5.

[0258] In an exemplary embodiment, the first anode connection electrode 74 may be connected to the sixth connection electrode 66 through an eighteenth via hole V18. Since the sixth connection electrode 66 is connected to the second region 26-2 of the active layer 26 of the sixth transistor T6 (also the second region 27-2 of the active layer 27 of the seventh transistor T7) through the via hole, the first anode connection electrode 74 is connected to the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7.

[0259] In an exemplary embodiment, the first power connection line 73 may include a plurality of first protrusions 731 and a plurality of second protrusions 732. In the same first power connection line 73, the plurality of first protrusions 731 and the plurality of second protrusions 732 are arranged alternately along the first direction X, and in the second direction Y, the plurality of first protrusions 731 and the plurality of second protrusions 732 are located on both sides of the main body of the first power connection line 73.

[0260] In an exemplary embodiment, by providing a second protrusion 732 on the first power connection line 73, the second protrusion 732 between two adjacent data signal lines 81 can be flush with the first protrusion 731, so that the anode height and flatness of multiple pixels are kept as consistent as possible, that is, the anodes of multiple sub-pixels are kept in the same horizontal plane as much as possible, thereby improving the display uniformity of the display substrate.

[0261] (112) Second planar layer pattern. In an exemplary embodiment, forming the second planar layer pattern may include: coating a second planar film on the substrate on which the aforementioned pattern is formed, patterning the second planar film using a patterning process to form a second planar layer covering the fifth conductive layer pattern, wherein a plurality of vias are provided on the second planar layer, as shown in FIG19a and FIG19b , FIG19a is a planar structural diagram of eight sub-pixels, and FIG19b is a planar structural diagram of sixteen sub-pixels.

[0262] In an exemplary embodiment, the plurality of via holes may include at least a twentieth via hole V20, a twenty-first via hole V21, a twenty-second via hole V22, a twenty-third via hole V23, and a twenty-fourth via hole V24.

[0263] In an exemplary embodiment, the orthographic projection of the twentieth via hole V20 on the substrate is located within the range of the orthographic projection of the first data connection line 71 on the substrate, and the second planar layer within the twentieth via hole V20 is etched away, exposing the surface of the first data connection line 71. The twentieth via hole V20 is configured to allow a subsequently formed second data connection line to be connected to the first data connection line 71 through the via hole.

[0264] In an exemplary embodiment, the orthographic projection of the twenty-first via hole V21 on the substrate is located within the range of the orthographic projection of the data line connection electrode 72 on the substrate. The second planar layer within the twenty-first via hole V21 is etched away, exposing the surface of the data line connection electrode 72. The twenty-first via hole V21 is configured to allow a subsequently formed data signal line to be connected to the data line connection electrode 72 through the via hole.

[0265] In an exemplary embodiment, the orthographic projection of the twenty-second via hole V22 on the substrate is located within the range of the orthographic projection of the first power connection line 73 on the substrate, and the second planar layer within the twenty-second via hole V22 is etched away, exposing the surface of the first power connection line 73. The twenty-second via hole V22 is configured to connect a subsequently formed first power line to the first power connection line 73 through the via hole.

[0266] In an exemplary embodiment, the orthographic projection of the twenty-third via hole V23 on the substrate is located within the range of the orthographic projection of the first anode connecting electrode 74 on the substrate, and the twenty-third via hole V23 is configured to connect the subsequently formed first anode connecting electrode to the first anode connecting electrode 74 through the via hole.

[0267] In an exemplary embodiment, the orthographic projection of the twenty-fourth via hole V24 on the substrate is located within the range of the orthographic projection of the first data connection line 71 on the substrate, and the second planar layer within the twenty-fourth via hole V24 is etched away, exposing the surface of the first data connection line 71. The twenty-fourth via hole V24 is configured to allow a subsequently formed data signal line to be connected to the first data connection line 71 through the via hole.

[0268] (113) Forming a sixth conductive layer pattern. In an exemplary embodiment, forming the sixth conductive layer may include: depositing a sixth conductive film on the substrate on which the aforementioned pattern is formed, patterning the sixth conductive film using a patterning process, and forming a sixth conductive layer disposed on the second flat layer, as shown in Figures 20a to 20c, wherein Figure 20a is a planar structural diagram of eight sub-pixels, Figure 20b is a planar schematic diagram of the sixth conductive layer in Figure 20a, and Figure 20c is a planar structural schematic diagram of sixteen sub-pixels. In an exemplary embodiment, the sixth conductive layer may be referred to as a third source / drain metal (SD3) layer.

[0269] In an exemplary embodiment, the sixth conductive layer includes at least a data signal line 81 (i.e., a data signal line DL in FIG. 8 ), a first power line 82 (i.e., a first power line VDD in FIG. 8 ), a second anode connection electrode 83, and a second data connection line 84. In an exemplary embodiment, the first anode connection electrode 74 and the second anode connection electrode 83 are anode connection electrodes of the light-emitting element.

[0270] In an exemplary embodiment, the data signal line 81 is in the shape of a zigzag line, with the main portion extending along the second direction Y. The data signal line 81 is connected to the data line connection electrode 72 via the twenty-first via hole V21. The data signal line 81 located in the first display area is connected to one of the first data connection lines 71 via the twenty-fourth via hole V24. Because the data line connection electrode 72 is connected to the fourth connection electrode 64 via a via hole, and the fourth connection electrode 64 is connected to the first region 24-1 of the active layer 24 of the fourth transistor T4 via a via hole, the data signal line 81 is connected to the first electrode of the fourth transistor T4, thereby writing the data signal into the fourth transistor T4. In an exemplary embodiment, the first display area may be located on both sides of the second display area in the first direction X.

[0271] In an exemplary embodiment, the portion where the data signal line 81 overlaps the second protrusion 732 may be bent toward the adjacent first power line 82 , thereby making the flatness of the anode at the second position M2 consistent with the flatness of the anode at the first position M1 .

[0272] In an exemplary embodiment, in the same sub-pixel, the second region of the active layer of the fourth transistor T4 and the second region of the active layer of the fifth transistor T5 are interconnected. In the first direction X, the channel region and the first region of the active layer of the fourth transistor T4 are located between the channel region of the active layer of the fifth transistor T5 and the channel region of the active layer of the third transistor T3, so that an accommodating opening K1 is formed between two adjacent fourth transistors T4; in the second direction Y, the portion of the data signal line 81 away from the second protrusion 732 can be bent toward the direction close to the adjacent first power line 82, so that an accommodating opening K1 is formed between the two adjacent data signal lines 81.

[0273] In the exemplary embodiment, the first power line 82 is in the shape of a zigzag line, with its main portion extending along the second direction Y. The first power line 82 is connected to the first power connection line 73 via the twenty-second via hole V22. Since the first power connection line 73 is connected to the fifth connection electrode 65 via the via hole, and the fifth connection electrode 65 is connected to the second electrode plate 43 via the via hole, the first power line 82 is connected to the second electrode plate 43, and the power signal is written to the second electrode plate 43. Since the fifth connection electrode 65 is connected to the first region 25-1 of the active layer 25 of the fifth transistor T5 via the via hole, the first power line 82 is connected to the first electrode of the fifth transistor T5, and the power signal is written to the fifth transistor T5.

[0274] In the exemplary embodiment, the second anode connection electrode 83 is connected to the first anode connection electrode 74 through the twenty-third via hole V23. Since the sixth connection electrode 66 is connected to the second region 26-2 of the active layer 26 of the sixth transistor T6 (also the second region 27-2 of the active layer 27 of the seventh transistor T7) through the via hole, the second anode connection electrode 83 is connected to the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7.

[0275] In an exemplary embodiment, the main portion of the second data connection line 84 extends along the second direction Y, and the second data connection line 84 is connected to the first data connection line 71 through the twentieth via hole V20. In an exemplary embodiment, the second data connection line 84 is disposed between two adjacent columns of sub-pixels. In an exemplary embodiment, a plurality of second data connection lines 84 are respectively connected to a plurality of first data connection lines 71.

[0276] In an exemplary embodiment, a plurality of second electrode connection blocks 841 may be provided on the second data connection line 84. The second electrode connection block 841 at a location electrically connected to the first data connection line 71 is electrically connected to the first data connection line 71 (first electrode connection block 711) by providing a twentieth via hole V20, and no via hole is provided at a location not electrically connected to the first data connection line 71. In the disclosed embodiment, the second electrode connection blocks 841 on the second data connection line 84 are provided in a consistent manner across multiple sub-pixels (including a plurality of second electrode connection blocks 841 not connected to the first data connection line 71 and a plurality of second electrode connection blocks 841 connected to the first data connection line 71), thereby improving display uniformity of the display substrate.

[0277] In an exemplary embodiment, a plurality of first power lines 82 and a plurality of data signal lines 81 are arranged alternately in pairs along a first direction X. A second data connection line 84 is disposed between two adjacent first power lines 82, and the second data connection line 84 is located between two adjacent sub-pixel columns. The orthographic projection of the first protrusion 731 on the substrate at least partially overlaps with the orthographic projections of the two adjacent first power lines 82 on the substrate, and the orthographic projection of the first protrusion 731 on the substrate covers at least a portion of the orthographic projections of the transistor channels located on both sides of the second data connection line 84 on the substrate. The first protrusion 731 shields the transistor channels from interference caused by the signals of the second data connection line 84, thereby protecting the transistor channels in the sub-pixels.

[0278] In an exemplary embodiment, in the first direction X, the two first transistors T1 in two adjacent columns of sub-pixels are located on both sides of the second data connection line 84, and the two second transistors T2 in two adjacent columns of sub-pixels are located on both sides of the second data connection line 84. The orthographic projections of the channels of the first transistors T1 and the second transistors T2 in the two adjacent columns of sub-pixels located on both sides of the second data connection line 84 on the substrate are within the range of the orthographic projection of the first protrusion 731 on the substrate. This prevents the signal of the second data connection line 84 from interfering with the channels of the first transistors T1 and the second transistors T2, thereby effectively protecting the channels of the first transistors T1 and the second transistors T2.

[0279] In an exemplary embodiment, in the first direction X, the two sixth transistors T6 of two adjacent columns of sub-pixels are located on both sides of the second data connection line 84, and the sixth transistors T6 are connected to the first anode connection electrode 74. The positive projection of the channel of the sixth transistor T6 on the substrate is located within the range of the positive projection of the first anode connection electrode 74 on the substrate, so that the first anode connection electrode 74 can shield the signal of the second data connection line 84, preventing the signal of the second data connection line 84 from interfering with the sixth transistor T6, thereby protecting the channel of the sixth transistor T6.

[0280] In an exemplary embodiment, the second data connection line 84 located in the second display area is connected to the first data connection line 71 through the 20th via V20 in the display area, and is connected to the integrated circuit (IC) in the driver chip area in the binding area; the data signal line 81 located in the display area is connected to the data line connection electrode 72 through the 21st via V21 in the display area, and is connected to the integrated circuit (IC) in the driver chip area in the binding area; the data signal line 81 located in the first display area is connected to one of the first data connection lines 71 through the 24th via V24, and the first data connection line 71 is electrically connected to one of the second data connection lines 84 located in the second display area, thereby realizing the provision of data signals by the second data connection line 84 and the first data connection line 71 to the data signal line 81 located in the first display area, which to a certain extent overcomes the technical problem that the data signal line 81 located in the first display area has a large fan-out area width and is difficult to achieve a narrow frame of the display substrate.

[0281] In an exemplary embodiment, as shown in FIG20c, which is a schematic structural diagram of forming the sixth conductive layer on the basis of FIG19b, the data signal line 81 of the N-4th column sub-pixel is electrically connected to the first data connection line 71 between the M-1th row and the Mth row sub-pixel through the twenty-fourth via hole V24, and the second data connection line 84 between the N+2th column sub-pixel and the N+3th column sub-pixel is electrically connected to the first data connection line 71 between the M-1th row and the Mth row sub-pixel through the twentieth via hole V20, thereby realizing the provision of data signals to the data signal line 81 of the N-4th column sub-pixel through the second data connection line 84 between the N+2th column sub-pixel and the N+3th column sub-pixel and the first data connection line 71 between the M-1th row and the Mth row sub-pixel; the N-3th column sub-pixel The data signal line 81 is electrically connected to the first data connection line 71 between the sub-pixels in the M-th row and the M+1-th row through the twenty-fourth via hole V24, and the second data connection line 84 between the sub-pixels in the N+1-th column and the sub-pixels in the N-th column is electrically connected to the first data connection line 71 between the sub-pixels in the M-th row and the M+1-th row through the twentieth via hole V20, thereby providing data signals to the data signal line 81 of the sub-pixels in the N-3-th column through the second data connection line 84 between the sub-pixels in the N+1-th column and the sub-pixels in the N-th column and the first data connection line 71 between the sub-pixels in the M-th row and the M+1-th row; wherein the sub-pixels in the N-3-th column and the sub-pixels in the N-4-th column are located in the first display area AA1, and the sub-pixels in the N+1-th column to the N+3-th column are located in the second display area AA2.

[0282] (114) Third planar layer pattern. In an exemplary embodiment, forming the third planar layer pattern may include: coating a third planar film on the substrate on which the aforementioned pattern is formed, patterning the third planar film using a patterning process to form a third planar layer covering the sixth conductive layer pattern, wherein a plurality of vias are provided on the third planar layer, as shown in FIG21 , which is a planar structural diagram of eight sub-pixels.

[0283] In an exemplary embodiment, the plurality of via holes may include at least a twenty-fifth via hole V25 .

[0284] In an exemplary embodiment, the via holes of each sub-pixel include at least a twenty-fifth via hole V25. The orthographic projection of the twenty-fifth via hole V25 on the substrate is located within the range of the orthographic projection of the second anode connecting electrode 83 on the substrate. The third planar layer within the twenty-fifth via hole V25 is removed, exposing the surface of the second anode connecting electrode 83. The twenty-fifth via hole V25 is configured to electrically connect a subsequently formed anode to the second anode connecting electrode 83 through the via hole.

[0285] At this point, the driving circuit layer is completed on the substrate. In an exemplary embodiment, in a plane perpendicular to the display substrate, the driving circuit layer may include a shielding layer, a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, a fourth conductive layer, a fifth conductive layer, and a sixth conductive layer sequentially disposed on the substrate.

[0286] In an exemplary embodiment, the driving circuit layer may include a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, a fifth insulating layer, a sixth insulating layer, a seventh insulating layer, a first flat layer and a second flat layer, the first insulating layer being arranged between the blocking layer and the first semiconductor layer, the second insulating layer being arranged between the first semiconductor layer and the first conductive layer, the third insulating layer being arranged between the first conductive layer and the second conductive layer, the fourth insulating layer being arranged between the second conductive layer and the second semiconductor layer, the fifth insulating layer being arranged between the second semiconductor layer and the third conductive layer, the sixth insulating layer being arranged between the third conductive layer and the fourth conductive layer, the seventh insulating layer and the first flat layer being arranged between the fourth conductive layer and the fifth conductive layer, and the second flat layer being arranged between the fifth conductive layer and the sixth conductive layer.

[0287] In an exemplary embodiment, after the driving circuit layer is prepared, a light-emitting structure layer is prepared on the driving circuit layer, and the preparation process of the light-emitting structure layer may include the following operations. A third flat layer pattern is formed, and at least an anode via is provided on the third flat layer. An anode pattern (i.e., an anode conductive layer) is formed, and the anode is connected to the anode connection electrode through the anode via. An anode pixel definition layer is formed, and a pixel opening is provided on the pixel definition layer, and the pixel opening exposes the anode. An organic light-emitting layer is formed by an evaporation or inkjet printing process, and a cathode is formed on the organic light-emitting layer. An encapsulation layer is formed, and the encapsulation layer may include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked together. The first encapsulation layer and the third encapsulation layer may be made of inorganic materials, and the second encapsulation layer may be made of organic materials. The second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer to ensure that external water vapor cannot enter the light-emitting structure layer. The steps for forming the anode conductive layer are as follows:

[0288] (115) Forming an anode conductive layer pattern. In an exemplary embodiment, forming the anode conductive layer pattern may include: depositing an anode conductive film on the substrate on which the aforementioned pattern is formed, and patterning the anode conductive film using a patterning process to form an anode conductive layer pattern disposed on the flat layer, as shown in FIG22A and FIG22B , where FIG22B is a planar schematic diagram of the anode conductive layer in FIG22A .

[0289] In an exemplary embodiment, the anode conductive layer pattern may include at least a plurality of anodes 90, and the plurality of anodes 90 may include: a first anode 91 of a red light-emitting unit, a second anode 92 of a blue light-emitting unit, and a third anode 93 of a green light-emitting unit. The area where the first anode 91 is located can form a red light-emitting unit that emits red light, the area where the second anode 92 is located can form a blue light-emitting unit that emits blue light, and the area where the third anode 93 is located can form a green light-emitting unit that emits green light.

[0290] In an exemplary embodiment, the first anode 91, the second anode 92, and the third anode 93 can be connected to the second anode connection electrode 83 in the corresponding sub-pixel through the twenty-fifth via hole V25. Since the second anode connection electrode 83 in the sub-pixel is electrically connected to the first anode connection electrode 74 through the via hole, and the first anode connection electrode 74 is electrically connected to the second electrode of the sixth transistor T6 (also the second electrode of the seventh transistor T7) through the via hole, the first anode 91, the second anode 92, and the third anode 93 can be connected to the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7 through the second anode connection electrode 83, respectively, thereby enabling the pixel driving circuit to drive the light-emitting device to emit light.

[0291] In an exemplary embodiment, the anode 90 may include a main portion 901 and a connecting portion 902. The main portion 901 may be a circular structure. One end of the anode connecting portion 902 is connected to the anode main portion 901, and the other end is electrically connected to the second anode connecting electrode 83 through the twenty-fifth via hole V25. The anode connecting portion 902 may be a strip-shaped structure extending along the first direction X or the second direction Y. The anode connecting portion 902 may be configured to compensate for differences in parasitic capacitance generated by signal routing between multiple sub-pixels. By providing the anode connecting portion 902, the parasitic capacitance of multiple sub-pixels can be kept consistent, thereby improving the display uniformity of the display substrate. In an exemplary embodiment, the anode connecting portion 902 of the anode 90 located on the first protrusion 731 extends along the second direction Y, and the anode connecting portion 902 of the anode 90 located on the second protrusion 732 extends along the first direction X. For example, the anode connecting portion 902 of the first anode 91 and the anode connecting portion 902 of the second anode extend along the second direction Y, and the anode connecting portion 902 of the third anode 93 extends along the first direction X.

[0292] In an exemplary embodiment, the orthographic projections of the main portions 901 of the plurality of anodes 90 on the substrate overlap with the orthographic projections of the first protrusions 731 on the substrate, or overlap with the orthographic projections of the second protrusions 732 on the substrate, thereby ensuring consistent height and flatness of the anodes in the plurality of sub-pixels. For example, the orthographic projections of the main portions 901 of the first anode 91 and the second anode 92 on the substrate overlap with the orthographic projections of the first protrusions 731 on the substrate, and the orthographic projection of the main portion 901 of the third anode 93 on the substrate overlaps with the orthographic projection of the second protrusions 732 on the substrate.

[0293] In an exemplary embodiment, the blocking layer, the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer, the fifth conductive layer, and the sixth conductive layer may be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and may have a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo, Ti / Al / Ti, etc. The first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, the fifth insulating layer, the sixth insulating layer, and the seventh insulating layer may be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may have a single layer, multiple layers, or a composite layer. The first insulating layer can be called a buffer layer, which is used to improve the substrate's resistance to water and oxygen. The second insulating layer, the third insulating layer, the fourth insulating layer and the fifth insulating layer can be called gate insulating (GI) layers. The sixth insulating layer can be called an interlayer insulating (ILD) layer. The seventh insulating layer can be called a passivation (PVX) layer.

[0294] The structure and preparation process shown above in the embodiment of the present disclosure are merely exemplary descriptions. In exemplary implementations, the corresponding structure can be changed and the patterning process can be increased or decreased according to actual needs. The display substrate of the embodiment of the present disclosure can be applied to other display devices with pixel driving circuits, such as quantum dot displays, etc., and the present disclosure does not limit this.

[0295] The present disclosure further provides a display device comprising the display substrate of any of the aforementioned embodiments. The display device may be any product or component with a display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigation system.

[0296] An embodiment of the present disclosure also provides a display device, comprising the above-mentioned display substrate including the first opening. The display device may further include a photosensitive element, and the orthographic projection of the photosensitive element on the base of the display substrate may be within the range of the orthographic projection of the first opening of the display substrate on the base.

[0297] The substrate and display device provided by the embodiments of the present disclosure are characterized in that any column of sub-pixels in the display substrate is electrically connected to one of the data signal lines and one of the first power lines, any first power line is electrically connected to multiple sub-pixels in one column of sub-pixels, at least a portion of the data signal lines are electrically connected to at least a portion of the second data connection lines through at least a portion of the first data connection lines, a second data connection line is provided between two adjacent first power lines, and in the first direction, the second data connection line and the data signal line are arranged on both sides of the first power line, thereby largely avoiding signal interference between the second data connection line and the data signal line, and overcoming the defect of uneven display caused by signal interference.

[0298] The drawings of the embodiments of the present disclosure only involve the structures involved in the embodiments of the present disclosure, and other structures may refer to general designs.

[0299] In the absence of conflict, the embodiments of the present disclosure, i.e., features in the embodiments, can be combined with each other to form new embodiments.

[0300] Although the embodiments disclosed in the present disclosure are as described above, the contents are only embodiments adopted to facilitate understanding of the embodiments of the present disclosure and are not intended to limit the embodiments of the present disclosure. Any person skilled in the art in the field to which the embodiments of the present disclosure belong may make any modifications and changes in the form and details of implementation without departing from the spirit and scope disclosed in the embodiments of the present disclosure, but the scope of patent protection of the embodiments of the present disclosure shall still be based on the scope defined by the attached claims.

Claims

1. A display substrate, comprising: A substrate and a plurality of data signal lines, a plurality of first power lines, a plurality of first data connection lines, a plurality of second data connection lines and a plurality of sub-pixels arranged in an array disposed on the substrate; On a plane parallel to the display substrate, the first data connection line extends along a first direction, the data signal line, the first power line and the second data connection line extend along a second direction, and the first direction intersects the second direction; the first data connection line and the data signal line, the first power line and the second data connection line are located in different conductive layers; Any column of sub-pixels is electrically connected to one of the data signal lines and one of the first power lines, and any first power line is electrically connected to multiple sub-pixels in one column of sub-pixels; at least a portion of the data signal lines are electrically connected to at least a portion of the second data connection lines through at least a portion of the first data connection lines; a second data connection line is provided between two adjacent first power lines, and in the first direction, the second data connection line and the data signal line are arranged on both sides of the first power line.

2. The display substrate according to claim 1, wherein: The sub-pixel includes a plurality of transistors, and the orthographic projections of the plurality of second data connection lines on the substrate do not overlap with the orthographic projections of the channels of the plurality of transistors on the substrate.

3. The display substrate according to claim 2, wherein: The plurality of first data connection lines are disposed between two adjacent sub-pixel rows, and the orthographic projections of the plurality of first data connection lines on the substrate do not overlap with the orthographic projections of the channels of the plurality of transistors on the substrate.

4. The display substrate according to claim 2, wherein: Also included are a plurality of first power connection lines, wherein the main parts of the first power connection lines extend along the first direction, the plurality of first power connection lines are arranged along the second direction, and the plurality of first power connection lines are electrically connected to a plurality of sub-pixels through the plurality of first power connection lines; On a plane perpendicular to the display substrate, orthographic projections of the plurality of first power connection lines on the substrate at least partially overlap with orthographic projections of the plurality of second data connection lines on the substrate.

5. The display substrate according to claim 4, wherein: The first power connection line is electrically connected to a plurality of sub-pixels in one sub-pixel row, and the first power line is electrically connected to a plurality of sub-pixels in a column of sub-pixels through a plurality of first power connection lines.

6. The display substrate according to claim 4, wherein: At least one sub-pixel includes a pixel driving circuit, the pixel driving circuit includes a plurality of transistors, the plurality of transistors include a driving transistor, a first transistor and a second transistor, the first transistor is configured to provide an initialization signal for a gate of the driving transistor, a first electrode of the second transistor is connected to the gate of the driving transistor, and a second electrode of the second transistor is connected to the second electrode of the driving transistor; the plurality of first power lines and the plurality of data signal lines are alternately arranged along the first direction, and two adjacent first power lines are mirror-symmetrical with respect to the second data connection line; the first power connection line includes a plurality of first protrusions, in the second direction, the plurality of first protrusions are located on one side of a main body of the first power connection line, an orthographic projection of the first protrusion on the substrate at least partially overlaps with an orthographic projection of two adjacent first power lines on the substrate, and the orthographic projection of the first protrusion on the substrate covers an orthographic projection of a channel of the first transistor and a channel of the second transistor located on both sides of the second data connection line on the substrate.

7. The display substrate according to claim 6, wherein: The first power connection line further includes a plurality of second protrusions, wherein in the same first power connection line, the plurality of first protrusions and the plurality of second protrusions are alternately arranged along the first direction, and in the second direction, the plurality of first protrusions and the plurality of second protrusions are located on both sides of the main body of the first power connection line; The orthographic projection of the second protrusion on the substrate at least partially overlaps with the orthographic projections of two adjacent data signal lines on the substrate.

8. The display substrate according to claim 7, further comprises a fifth conductive layer, a sixth conductive layer and an anode conductive layer, the first power connection line and the first data connection line are located in the fifth conductive layer, the data signal line, the first power line and the second data connection line are located in the sixth conductive layer, the anode conductive layer is located on the side of the sixth conductive layer away from the substrate, the anode conductive layer comprises a plurality of anodes, and the orthographic projections of the plurality of anodes on the substrate overlap with the orthographic projections of the first protrusions on the substrate, or overlap with the orthographic projections of the second protrusions on the substrate.

9. The display substrate according to claim 6, wherein: The second data connection line is located between two adjacent columns of sub-pixels, and the two adjacent columns of sub-pixels are mirror-symmetric with respect to the second data connection line. In a first direction, two first transistors in two adjacent columns of sub-pixels are located on both sides of the second data connection line, and two second transistors in two adjacent columns of sub-pixels are located on both sides of the second data connection line; in the same sub-pixel, the second electrode of the first transistor is electrically connected to the second electrode of the second transistor.

10. The display substrate according to claim 6, wherein: The multiple transistors also include a sixth transistor, the conductive layer where the first power connection line is located also includes a first anode connection electrode, the second electrode of the sixth transistor is connected to the first anode connection electrode, and in the first direction, the two sixth transistors of two adjacent columns of sub-pixels are located on both sides of the second data connection line, and the orthographic projection of the channel of the sixth transistor on the substrate is located within the range of the orthographic projection of the first anode connection electrode on the substrate.

11. The display substrate according to claim 6, wherein: The multiple transistors also include a fourth transistor, which is configured to provide a data signal to the driving transistor, and the data signal line includes a first part and a second part that are integrally formed, the first part extends along the second direction, the second part is a bent structure, the orthographic projection of the second part on the substrate overlaps with the orthographic projection of the second protrusion on the substrate, the orthographic projection of the channel region and the first region of the fourth transistor on the substrate overlaps with the orthographic projection of the first part on the substrate, and the first part in two adjacent sub-pixels in the first direction forms a first opening.

12. The display substrate according to claim 11, wherein: The middle part of the second part of the data signal line is bent toward a direction close to the first power line adjacent thereto, and a second opening is formed in the middle parts of two second parts adjacent to each other in the first direction.

13. The display substrate according to claim 12, wherein: The two ends of the second portion are bent in a direction away from the first power line adjacent thereto, and the ratio of the distance between the two data signal lines adjacent to each other at the first opening position to the distance between the two data signal lines adjacent to each other at the second opening position is 1.1 to 1.6; A ratio of a distance between two adjacent data signal lines at the first opening position to a distance along the first direction between two adjacent data signal line ends at the first opening position or the second opening position is 1 to 8. 14 . The display substrate according to claim 1 , further comprising a first initial signal line extending along the first direction, wherein an orthographic projection of the first initial signal line on the substrate and an orthographic projection of the first data connection line on the substrate have an overlapping area.

15. The display substrate according to any one of claims 1 to 14, wherein: The display substrate includes a display area and a binding area, and in the second direction, the binding area is located on one side of the display area; the display area includes a first display area and a second display area, and in the first direction, the first display area is located on both sides of the second display area, and a plurality of data signal lines located in the first display area are electrically connected to a plurality of second data connection lines located in the second display area through a plurality of first data connection lines, respectively, and a plurality of data signal lines and a plurality of second data connection lines located in the second display area are connected to the binding area.

16. The display substrate according to claim 15, wherein: In the first direction, a plurality of data signal lines arranged in the direction from the second display area to the first display area and located on one side of the second center line are electrically connected to a plurality of second data connection lines in the direction from the second display area to the second center line through a plurality of first data connection lines in the direction from the binding area to the display area, respectively; wherein the second center line is the center line of the display substrate extending along the second direction.

17. A display device comprising the display substrate according to any one of claims 1 to 16.

18. A display device, comprising the display substrate according to any one of claims 11 to 13, the display device further comprising a photosensitive element, wherein the orthographic projection of the photosensitive element on the base of the display substrate is within the range of the orthographic projection of the first opening of the display substrate on the base.

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