Display substrate and display device

Abstract

The embodiment of the utility model provides a display substrate and a display device. The display substrate comprises a display area and a first frame area, the display area comprises a plurality of sub-pixels and data lines in a plurality of data signal lines, the first frame area comprises a bending area, and in the bending area, in the first direction, data connecting lines of the data signal lines and a plurality of first power supply connecting structures are arranged at intervals. And at least one data connecting line is arranged between two adjacent first power supply connecting structures. According to the technical scheme provided by the embodiment of the invention, the technical problem of display screen splitting caused by abrupt change of the resistance of the signal wiring in the bending area of the display substrate can be avoided.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to, but are not limited to, the field of display technology, and specifically relate to a display substrate and a display device. Background Art

[0002] Organic Light Emitting Diode (OLED) and Quantum-dot Light Emitting Diode (QLED) are active light-emitting display devices with the advantages of self-luminescence, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, bendability and low cost. With the continuous development of display technology, flexible display devices (Flexible Display) using OLED or QLED as light-emitting devices and thin film transistors (TFT) for signal control have become the mainstream products in the current display field.

[0003] Currently, there is a large resistance difference between signal traces on the display substrate, which leads to technical problems in display split-screen. Utility Model Content

[0004] The problem to be solved by the embodiments of the present disclosure is to provide a display substrate and a display device to solve the technical problem of a split screen caused by a large resistance difference between signal lines of an existing display substrate.

[0005] In order to solve the above technical problems, in a first aspect, an embodiment of the present disclosure provides a display substrate, comprising a display area and a first frame area located on one side of the display area, wherein the first frame area is provided with a bending area;

[0006] A plurality of sub-pixels are located in the display area;

[0007] a plurality of data signal lines, located in the display area and the first frame area, and electrically connected to the plurality of sub-pixels, the plurality of data signal lines being configured to provide data signals to the plurality of sub-pixels; the data signal lines comprising data lines and data connection lines, the data lines being located in the display area, the data connection lines being located in the first frame area, and electrically connected to corresponding data lines, and in the same data signal line, at least part of the line segments of the data connection lines being located in the bending area;

[0008] a plurality of first power connection structures, located in the bending area, the plurality of first power connection structures are arranged at intervals along a first direction and extend along a second direction, and are configured to provide a first power signal to the plurality of sub-pixels, the first direction intersecting the second direction;

[0009] In the bending area, along the first direction, the data connection lines of the plurality of data signal lines are arranged at intervals from the plurality of first power connection structures, and at least one data connection line is provided between two adjacent first power connection structures.

[0010] In an exemplary embodiment, in the bending region, along the first direction, the plurality of first power connection structures are arranged at equal intervals.

[0011] In an exemplary embodiment, in the bending area, along the first direction, a plurality of first distances between a plurality of data connection lines are consistent, and the first distance is a distance between two adjacent data connection lines.

[0012] In an exemplary embodiment, in the bending region, along the first direction, the plurality of data connection lines between two adjacent first power connection structures are arranged at equal intervals.

[0013] In an exemplary embodiment, in the bending region, along the first direction, the first distance is greater than or equal to a second distance, and the second distance is the distance between the first power connection structure and an adjacent data connection line.

[0014] In an exemplary embodiment, in the bending zone, along the first direction, a ratio of the first distance to the second distance is greater than or equal to 1.5.

[0015] In an exemplary embodiment, in the bending region, along the first direction, a size of the first power connection structure is consistent with a size of the data connection line.

[0016] In an exemplary embodiment, in a direction perpendicular to the plane where the display substrate is located, the display substrate includes a base and a driving circuit layer arranged on the base, the driving circuit layer includes a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer arranged in sequence on the base, and at least part of the line segments of the data connection line and the multiple first power connection structures are located on the fourth conductive layer.

[0017] In an exemplary embodiment, in a plane parallel to the display substrate, the first frame area further includes a first fan-out area, and in the second direction, the first fan-out area is located between the display area and the bending area; the display substrate further includes a first power connection line, and the data connection line includes a first data connection line and a second data connection line, and in the same data signal line, the data line is electrically connected to the second data connection line through the first data connection line, wherein:

[0018] The first power connection line is located in the first fan-out area, the first power connection line extends along the first direction and is electrically connected to the plurality of first power connection structures, and the plurality of first power connection structures provide first power signals to the plurality of sub-pixels through the first power connection line;

[0019] The first data connection lines are located in the first fan-out area, and among the plurality of the first data connection lines, at least part of them are located in the first conductive layer, and at least part of them are located in the second conductive layer, and the first data connection lines located in the first conductive layer and the first data connection lines located in the second conductive layer are arranged alternately;

[0020] The second data connection line is located in the bending area, in a direction perpendicular to the plane where the display substrate is located, the second data connection line is located in the fourth conductive layer, and at least part of the line segments of the data connection line include the second data connection line.

[0021] In an exemplary embodiment, in a direction perpendicular to the plane where the display substrate is located, the first power connection line is located in the fourth conductive layer, and the first power connection line is directly connected to the multiple first power connection structures; in the same data signal line, the first data connection line is electrically connected to the second data connection line through a via, and the first data connection line is electrically connected to the data line through a via.

[0022] In an exemplary embodiment, in a plane parallel to the display substrate, the first frame area further includes a second fan-out area, and in the second direction, the second fan-out area is located on a side of the bending area away from the display area, the display substrate further includes a first power line, and the data connection line further includes a third data connection line, and in the same data connection line, the first data connection line is electrically connected to the third data connection line through the second data connection line; wherein:

[0023] The first power line is located in the second fan-out area, and the first power line is connected to the plurality of first power connection structures;

[0024] The third data connection lines are located in the second fan-out area. Among the plurality of third data connection lines, at least part is located in the first conductive layer, and at least part is located in the second conductive layer. The third data connection lines located in the first conductive layer and the third data connection lines located in the second conductive layer are arranged alternately.

[0025] In an exemplary embodiment, in a direction perpendicular to the plane of the display substrate, the first power line is located in the fourth conductive layer, and the first power line is directly connected to the multiple first power connection structures; in the same data signal line, the second data connection line is electrically connected to the third data connection line through a via.

[0026] In an exemplary embodiment, in a plane parallel to the display substrate, the first border area also includes a binding area, and in the second direction, the binding area is located on a side of the second fan-out area away from the display area, and the binding area is provided with a first power pad and a driving circuit; the third data connection line is electrically connected to the driving circuit; the first power line extends to the binding area and is electrically connected to the first power pad.

[0027] In a second aspect, the present disclosure further provides a display device, comprising the display substrate described in any of the above embodiments.

[0028] The display substrate and display device provided by the embodiments of the present disclosure include a display area and a first frame area located on one side of the display area, the display area includes a plurality of sub-pixels and a data line among a plurality of data signal lines, the first frame area includes a bending area, in which, along a first direction, data connection lines of a plurality of data signal lines are arranged at intervals with a plurality of first power connection structures, and at least one data connection line is provided between two adjacent first power connection structures. The display substrate provided by the embodiments of the present disclosure can avoid the technical problem of display splitting caused by a sudden change in resistance (large resistance step difference) of a signal routing line in a bending area of ​​the display substrate.

[0029] Other aspects will be apparent upon reading and understanding the drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The accompanying drawings are used to provide a further understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation on the technical solution of the present disclosure. The shapes and sizes of the components in the accompanying drawings do not reflect the actual proportions and are only intended to illustrate the contents of the present disclosure.

[0031] Figure 1 Shown is a schematic structural diagram of a display device;

[0032] Figure 2 Shown is a schematic structural diagram of a display substrate;

[0033] Figure 3 Shown is an enlarged structural schematic diagram of the first frame area;

[0034] Figure 4 The above is a schematic diagram of the structure of a display substrate;

[0035] Figure 5 Shown is a schematic structural diagram of a display substrate;

[0036] Figure 6 Shown is a schematic diagram of a resistance curve of a data signal line;

[0037] Figure 7 Shown is a schematic structural diagram of a display substrate provided in an embodiment of the present disclosure;

[0038] Figure 8a Shown Figure 7 A schematic diagram of an enlarged structure of the M1 position;

[0039] Figure 8b Shown Figure 7 A schematic diagram of an enlarged structure of the M2 position;

[0040] Figure 8c Shown Figure 7 A schematic diagram of an enlarged structure of the M1 position;

[0041] Fig. 9 Shown is a schematic diagram of a display device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0042] The embodiments of the present disclosure will be described in detail below in conjunction with the accompanying drawings. The embodiments of the present disclosure can be implemented in a plurality of different forms. A person of ordinary skill in the art can easily understand the fact that the implementation and content can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments of the present disclosure and the features in the embodiments can be arbitrarily combined with each other.

[0043] In the drawings, the size of the components, the thickness of the layers, or the regions may be exaggerated for the sake of clarity. Therefore, any implementation of the present disclosure is not necessarily limited to the dimensions shown in the drawings, and the shapes and sizes of the components in the drawings do not reflect the true proportions. In addition, the drawings schematically show ideal examples, and any implementation of the present disclosure is not limited to the shapes or values ​​shown in the drawings.

[0044] In the present disclosure, ordinal numbers such as “first”, “second”, and “third” are provided to avoid confusion among constituent elements rather than to limit the number.

[0045] In the present disclosure, for the sake of convenience, the words and phrases indicating the orientation or positional relationship such as "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like are used to illustrate the positional relationship of the constituent elements with reference to the drawings. This is only for the convenience of describing the implementation methods and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation of the present disclosure. The positional relationship of the constituent elements may be appropriately changed according to the orientation of the constituent elements being described. Therefore, it is not limited to the words and phrases described in the text and can be appropriately replaced according to the circumstances.

[0046] In the present disclosure, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements. For ordinary technicians in this field, the meanings of the above terms in the present disclosure can be understood according to the circumstances.

[0047] In the present disclosure, a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (or drain electrode terminal, drain connection region, or drain electrode) and a source electrode (or source electrode terminal, source connection region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In the present disclosure, a channel region refers to a region where current mainly flows.

[0048] In the present disclosure, the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. In the case of using transistors with opposite polarities or when the current direction changes during circuit operation, the functions of the "source electrode" and the "drain electrode" may sometimes be interchanged. Therefore, in the present disclosure, the "source electrode" and the "drain electrode" may be interchanged. In the present disclosure, the control electrode may be a gate.

[0049] In the present disclosure, "electrical connection" includes the situation where the components are connected together through an element having some electrical function. There is no particular limitation on the "element having some electrical function" as long as it can transmit and receive electrical signals between the connected components. The "element having some electrical function" can be, for example, an electrode or wiring, or a switching element such as a transistor, or other functional elements such as a resistor, inductor or capacitor.

[0050] Figure 1The structure diagram of a display device is shown. The display substrate may include a timing controller, a data signal driving circuit, a scanning signal driving circuit, a light emitting signal driving circuit and a pixel array. The timing controller is connected to the data signal driving circuit, the scanning signal driving circuit and the light emitting signal driving circuit respectively. The data signal driving circuit is connected to a plurality of data signal lines (D1 to Dn) respectively. The scanning signal driving circuit is connected to a plurality of scanning signal lines (G1 to Gm) respectively. The light emitting signal driving circuit is connected to a plurality of light emitting signal lines (E1 to Eo) respectively. The pixel array may include a plurality of sub-pixels Pxij, i and j may be natural numbers, at least one sub-pixel Pxij may include a circuit unit and a light emitting device connected to the circuit unit, the circuit unit may include a pixel driving circuit, and the pixel driving circuit may be connected to the scanning signal line, the light emitting signal line and the data signal line (which may be referred to as a data line) respectively. In an exemplary embodiment, the timing controller may provide a grayscale value and a control signal suitable for the specification of the data signal driving circuit to the data signal driving circuit, a clock signal, a scan start signal, etc. suitable for the specification of the scan signal driving circuit to the scan signal driving circuit, and a clock signal, an emission stop signal, etc. suitable for the specification of the light emitting signal driving circuit to the light emitting signal driving circuit. The data signal driving circuit may generate a data voltage to be provided to the data signal lines D1, D2, D3, ... and Dn using the grayscale value and the control signal received from the timing controller. For example, the data signal driving circuit may sample the grayscale value using the clock signal, and apply the data voltage corresponding to the grayscale value to the data signal lines D1 to Dn in units of pixel rows, where n may be a natural number. The scan signal driving circuit may generate a scan signal to be provided to the scan signal lines G1, G2, G3, ... and Gm by receiving a clock signal, a scan start signal, etc. from the timing controller. For example, the scan signal driving circuit may sequentially provide a scan signal having an on-level pulse to the scan signal lines G1 to Gm. For example, the scan signal driving circuit may be constructed in the form of a shift register, and may generate a scan signal in a manner that a scan start signal provided in the form of a conduction level pulse is sequentially transmitted to a next level circuit under the control of a clock signal, and m may be a natural number. The light-emitting signal driving circuit may generate an emission signal to be provided to the light-emitting signal lines E1, E2, E3, ... and Eo by receiving a clock signal, an emission stop signal, etc. from a timing controller. For example, the light-emitting signal driving circuit may sequentially provide an emission signal with a cut-off level pulse to the light-emitting signal lines E1 to Eo. For example, the light-emitting driver may be constructed in the form of a shift register, and may generate an emission signal in a manner that an emission stop signal provided in the form of a cut-off level pulse is sequentially transmitted to a next level circuit under the control of a clock signal, and o may be a natural number.

[0051] Figure 2FIG. 1 is a schematic diagram of the structure of a display panel. Figure 2 As shown, the display panel may include a display area AA and a frame area BB located around the display area AA. In some examples, the peripheral area BB may include: a first frame area (lower frame) B1 and a second frame area (upper frame) B2 arranged relatively in the second direction Y, and a third frame area (left frame) B3 and a fourth frame area (right frame) B4 arranged relatively in the first direction X. The first frame area B1 is connected to the third frame area B3 and the fourth frame area B4, and the second frame area B2 is connected to the third frame area B3 and the fourth frame area B4. In some examples, the display area AA may include a first edge (lower edge) and a second edge (upper edge) arranged relatively in the second direction Y, and a third edge (left edge) and a fourth edge (right edge) arranged relatively in the first direction X. The display area AA may include a plurality of sub-pixels Pxij arranged regularly, and the sub-pixels may include a pixel driving circuit and a light-emitting device, the first frame area B1 may include a binding circuit for connecting a signal line to an external driving device, and the third frame area B3 and the fourth frame area B4 may include a gate driving circuit and a second power line VSS for transmitting a voltage signal to a plurality of sub-pixels.

[0052] Figure 3 The diagram shows a schematic diagram of the planar structure of the first frame region B1. In a plane parallel to the display substrate, the first frame region B1 may include a first fan-out region 11, a bending region 12, a second fan-out region 13, and a binding region 14, which are sequentially arranged in a direction away from the display region AA; wherein the binding region 14 may include a driver chip region 141, a third fan-out region 142, and a binding electrode region 143, which are sequentially arranged in a direction away from the bending region 12 in the second fan-out region 13. The first fan-out region 11 may include a data fan-out line, a first power line, and a second power line VSS. The data fan-out line is located in the middle of the first fan-out region 11 and includes a plurality of data connection lines, which are configured to connect the data line (Data Line) of the display region AA in a fan-out routing manner. The first power line is configured to connect the high voltage power line (VDD) of the display region AA, and the second power line is a low voltage power line (VSS) located in the third frame region B3 and the fourth frame region B4. The bending area 12 may include a composite insulating layer provided with a groove, and is configured to bend the binding area 14 to the back side of the display area AA (eg, Figure 4As shown). The second fan-out area 13 includes a plurality of data connection lines led out in a fan-out routing manner. The driving chip area 141 may be provided with an integrated circuit (IC) 20, which is configured to be connected to a plurality of data connection lines. The binding electrode area 143 includes a plurality of bonding pads, which are configured to be bound and connected to a flexible printed circuit (FPC) 30. In an exemplary embodiment, the integrated circuit (IC) 20 may be bound and connected to the driving chip area 141, and the flexible printed circuit (FPC) 30 may be bound and connected to the binding electrode area 142. In an exemplary embodiment, the integrated circuit 20 (which may be referred to as a data driving circuit or a driving circuit) may generate a driving signal required for driving a sub-pixel, and may provide the driving signal to a sub-pixel Pxij located in the display area AA. For example, the driving signal may be a data signal that controls the luminous brightness of the sub-pixel. In an exemplary embodiment, the binding electrode area 143 may be provided with a pad (PAD) including a plurality of pins (PINs), and the flexible printed circuit 30 may be bound and connected to the pad.

[0053] In an exemplary embodiment, Figure 4 As shown, the bending area 12 can reverse the surface of the binding area 14, that is, the surface of the binding area 14 facing upward can be converted to face downward by bending the bending area 12. In an exemplary embodiment, when the bending area 12 is bent, the binding area 14 can overlap with the display area AA in the thickness direction of the display panel.

[0054] In an exemplary embodiment, for a large-sized display substrate, multiple data driver ICs (which may be referred to as driver ICs, i.e., driver integrated circuits) and multiple FPCs may be provided, and the multiple FPCs are respectively bound and connected to the multiple data driver ICs. For example, four data driver ICs may be provided and respectively bound and connected to four FPCs. The disclosed embodiment is not limited to four ICs and four FPCs. For example, two data driver ICs and two FPCs may be provided. For a small-sized display substrate, one data driver IC or two data driver ICs may be provided. In the disclosed embodiment, the number of data driver ICs and FPCs may be provided according to the size of the display substrate and the requirements of the function, and the disclosed embodiment is not limited thereto.

[0055] In an exemplary embodiment, if Figure 5As shown, it is a schematic diagram of the structure of a display substrate, the display area AA may be provided with a plurality of scan signal lines SL and a data line DL0 among a plurality of data signal lines D (the same data signal line D may include a data line D0 located in the display area AA and a data connection line DL located in the first frame area B1), the plurality of scan signal lines SL may extend along the first direction X and be arranged at intervals along the second direction Y, the plurality of data lines DL0 may extend along the second direction Y and be arranged at intervals along the first direction X, each scan signal line SL may be electrically connected to a plurality of sub-pixels Pxij in a row of sub-pixels, each data line DL0 may be electrically connected to a plurality of sub-pixels in a column of sub-pixels, the second frame area B2 and the third frame area B3 may be provided with a plurality of gate drive circuits GOA (GOA is an abbreviation for array substrate row drive, and its full name in English is Gate Driver on Array) and gate drive circuit signal lines (GOA signal lines), the GOA signal lines may include clock signal lines (for example, they may include CK signal lines, CB signal lines, STV signal lines, etc.), the gate drive circuit GOA is configured to be electrically connected to the corresponding scan signal line SL and provide a scan signal to the corresponding scan signal line SL.The data connection lines DL in the data signal lines D may include a first data connection line DL1, a second data connection line DL2, and a third data connection line DL3. The first fan-out area 11 may include a plurality of first data connection lines DL1 and a first power connection line PL11. The plurality of first data connection lines DL1 may be arranged at intervals along the first direction X. The first power connection line PL11 and the plurality of first data connection lines DL1 are located in different conductive layers. The bending area 12 may include a plurality of second data connection lines DL2, a first power connection structure PL12, and a second power connection structure PL22. The plurality of second data connection lines DL2, the first power connection structure PL12, and the second power connection structure PL22 are arranged at intervals along the first direction X. The second data connection lines DL2, the first power connection structure PL12, and the second power connection structure PL22 in the bending area 12 are usually located in the same conductive layer. Different signal lines need to be arranged at intervals to avoid signal short circuit. The second fan-out area 13 may include The third fan-out area 142 may be provided with a plurality of bonding leads 201, and the binding electrode area 143 may be provided with a plurality of pads, and the plurality of pads may include a first power pad 51, a second power pad 52, a driving pad 53, a first gate driving circuit pad 541, and a second gate driving pad 542. The driving circuit 20 may be electrically connected to the driving pad 53 in the binding electrode area 143 through the binding lead 201, and the plurality of pads may be bound and connected to the flexible circuit board 30, the first power line VDD may be connected to the first power pad connection 51, the second power line VSS may be connected to the second power pad 52, and the driving pad 53 may be electrically connected to the corresponding binding lead 201. In an exemplary embodiment, the data line DL0 , the first data link line DL1 , the second data link line DL2 , and the third data link line DL3 may be connected one-to-one, and the first power line VDD may be electrically connected to the first power link line PL11 through the first power connection structure PL12 .

[0056] In an exemplary embodiment, if Figure 5As shown, the gate drive circuit signal line may include a first gate drive circuit signal line 41 and a second gate drive circuit signal line 42, the first gate drive circuit signal line 41 extends from the third frame area B3 to the first frame area B1, and is connected to the first gate drive pad 541 and the gate drive circuit GOA located in the third frame area B3; the second gate drive circuit signal line 42 extends from the fourth frame area B4 to the first frame area B1, and is connected to the second gate drive pad 542 and the gate drive circuit GOA located in the fourth frame area B4. The gate drive circuit GOA may include a first gate drive circuit GOA1 disposed in the third frame area B3 and a second gate drive circuit GOA2 disposed in the fourth frame area B4, the first gate drive circuit GOA1 is configured to be electrically connected to the first gate drive pad 541 through the first gate drive circuit signal line 41, and the second gate drive circuit GOA2 is configured to be electrically connected to the second gate drive pad 542 through the second gate drive circuit signal line 42.

[0057] In an exemplary embodiment, if Figure 5 As shown, the second data connection line DL2 and the first power connection structure PL12 in the bending area 12 are located in the same conductive layer. In the bending area 12, the size of the second data connection line DL2 is much smaller than that of the first power connection structure PL12. The first power connection structure PL12 is a block structure, resulting in that in the first direction X, the lengths of the two first data connection lines DL1 located on both sides of the first power connection structure PL12 are different. For example, in order to avoid the first power connection structure PL12 in the bending area 12, the routing path of the first data connection line DL12 changes, resulting in the length of the first data connection line DL12 being greater than the length of the first data connection line DL11, and the resistance of the first data connection line DL12 is greater than that of the first data connection line DL11. Figure 6 As shown in FIG. 1 , it is a resistance variation curve of the data signal line D. Figure 6 It can be seen that there are two large resistance mutations (large resistance step difference) in the plurality of data signal lines D, and the mutation positions are located at the data lines corresponding to the first power connection line DL1 on both sides of the first power connection line PL12 ( Figure 6 The two adjacent data signal lines D at positions Z1 and Z2 generate a resistance mutation, and Z1 and Z2 correspond to the positions of the two first power connection structures PL12 in the bending area 12, respectively. The resistance mutation is about 200 ohms (Ω), which can easily cause the problem of split screen. Figure 6 The horizontal axis is the position of the data line DL0 along the first direction X, and the vertical axis is the resistance of the corresponding data line DL0.

[0058] The embodiment of the present disclosure provides a display substrate, which may include a display area and a first frame area located on one side of the display area, wherein the first frame area is provided with a bending area;

[0059] A plurality of sub-pixels are located in the display area;

[0060] a plurality of data signal lines, located in the display area and the first frame area, and electrically connected to the plurality of sub-pixels, the plurality of data signal lines being configured to provide data signals to the plurality of sub-pixels; the data signal lines comprising data lines and data connection lines, the data lines being located in the display area, the data connection lines being located in the first frame area, and electrically connected to corresponding data lines, and in the same data signal line, at least part of the line segments of the data connection lines being located in the bending area;

[0061] a plurality of first power connection structures, located in the bending area, the plurality of first power connection structures are arranged at intervals along a first direction and extend along a second direction, and are configured to provide a first power signal to the plurality of sub-pixels, the first direction intersecting the second direction;

[0062] In the bending area, along the first direction, the data connection lines of the plurality of data signal lines are arranged at intervals from the plurality of first power connection structures, and at least one data connection line is provided between two adjacent first power connection structures.

[0063] The display substrate provided in the embodiment of the present disclosure includes a display area and a first frame area located on one side of the display area, the display area includes a plurality of sub-pixels and a data line of a plurality of data signal lines, the first frame area includes a bending area, in which, along a first direction, data connection lines of a plurality of data signal lines are arranged alternately with a plurality of first power connection structures, and at least one data connection line is provided between two adjacent first power connection structures. The display substrate provided in the embodiment of the present disclosure can avoid the technical problem of display splitting caused by a sudden change in resistance (large resistance step difference) of a signal routing line in a bending area of ​​the display substrate.

[0064] like Figure 7 to Figure 8c As shown, Figure 7 A schematic diagram of the structure of a display substrate provided in an embodiment of the present disclosure is shown in FIG. Figure 8a for Figure 7 A schematic diagram of an enlarged structure of the M1 position in the middle. Figure 8b for Figure 7 A schematic diagram of an enlarged structure of the M2 position in the figure. Figure 8c for Figure 7 Another enlarged structural schematic diagram of the position M1 in the middle, the display substrate may include a display area AA and a first frame area B1 located on one side of the display area AA, and the first frame area B1 is provided with a bending area 12;

[0065] A plurality of sub-pixels Pxij, located in the display area AA;

[0066] A plurality of data signal lines D are located in the display area AA and the first frame area B1 and are electrically connected to the plurality of sub-pixels Pxij. The plurality of data signal lines D are configured to provide data signals to the plurality of sub-pixels Pxij. The data signal lines D may include a data line DL0 and a data connection line DL. The data line DL0 may be located in the display area AA. The data connection line DL may be located in the first frame area B1 and is electrically connected to the corresponding data line DL0. In the same data signal line D, at least part of the line segment of the data connection line DL is located in the bending area 12.

[0067] A plurality of first power connection structures PL12 are located in the bending area 12, the plurality of first power connection structures PL12 are arranged at intervals along the first direction X and extend along the second direction Y, and are configured to provide a first power signal to a plurality of sub-pixels Pxij, and the first direction X intersects with the second direction Y;

[0068] In the bending region 12 , along the first direction X, the data connection lines DL of the plurality of data signal lines D are arranged alternately with the plurality of first power connection structures PL12 , and at least one data connection line DL is disposed between two adjacent first power connection structures PL12 .

[0069] In an exemplary embodiment, if Figure 8a and Figure 8b As shown, two data connection lines DL may be provided between two adjacent first power connection structures PL12, or, as shown in FIG. Figure 8c As shown, four data connection lines DL are arranged between two adjacent first power connection structures PL12. Figures 8a to 8c As shown, for example, the number of the data connection lines DL between two adjacent first power connection structures PL12 may be one, three, or more than three.

[0070] In an exemplary embodiment, in the bending region 12, the first power source provided by the first electrical connection structure PL12 may be a VDD signal, a VSS signal, or an initialization signal, which is used to provide an initialization signal to the transistor in the driving circuit, or to provide a voltage signal such as VGH, VGL, etc. for driving GOA. In an exemplary embodiment, the first power source provided by the first electrical connection structure PL12 may be two constant voltage signals among the VDD signal, the VSS signal, and the initialization signal. In the bending region 12, in the first direction X, the lines providing the initialization signal, VGL, and VGH may be located on both sides of the data connection line DL, and the line providing the VDD signal may be located in the middle.

[0071] In an exemplary embodiment, in the bending region 12 , along the first direction X, a plurality of first distances R1 between a plurality of data link lines DL are consistent, and the first distance R1 is the distance between two adjacent data link lines DL.

[0072] In an exemplary embodiment, the multiple first distances R1 between the multiple data link lines DL are consistent, and may be substantially the same, and may have certain differences within an allowable error range, for example, an error range of 0 microns to 5 microns.

[0073] In an exemplary embodiment, in the bending area 12, the data connection lines DL of the multiple data signal lines D are arranged at intervals with the multiple first power connection structures PL12, and at least one data connection line DL is provided between two adjacent first power connection structures PL12. On the one hand, the consistency of the signal provided by the first power connection structure PL12 can be improved. On the other hand, the first power connection structure PL12 and the data connection lines DL are arranged alternately. The first power connection structure PL2 is not a whole block, but is divided into multiple pieces and is arranged between two adjacent data connection lines DL. This can avoid sudden resistance changes between two adjacent data signal lines D.

[0074] In an exemplary embodiment, in the bending region 12 , along the first direction X, the first distances R1 between the data link lines DL are consistent, which can avoid the problem of large resistance step difference caused by large length difference between two adjacent data signal lines DL.

[0075] In an exemplary embodiment, in the bending area 12, along the first direction X, a plurality of first power connection structures PL12 are arranged at equal intervals, so that the first power signals obtained by the plurality of sub-pixels Pxij are as consistent as possible, thereby improving the display uniformity of the display area.

[0076] In an exemplary embodiment, in the bending area 12, along the first direction X, multiple data connection lines DL between two adjacent first power connection structures PL12 are arranged at equal intervals, which can avoid resistance mutations between two adjacent data signal lines D and effectively reduce the risk of display split screen.

[0077] In an exemplary embodiment, in the bending area 12, along the first direction X, the first distance R1 is greater than or equal to the second distance R2, and the second distance R2 is the distance between the first power connection structure PL12 and the adjacent data connection line. The distance between the two data connection lines DL located on both sides of the first power connection structure PL12 is made as consistent as possible with the distance between the two adjacent data connection lines DL, so that the resistance difference of the data signal line D corresponding to the two data connection lines DL located on both sides of the first power connection structure PL12 is minimized to avoid resistance mutation.

[0078] In an exemplary embodiment, in the bending zone 12 , along the first direction X, a ratio of the first distance R1 to the second distance R2 is greater than or equal to 1.5.

[0079] In an exemplary embodiment, in the bending region 12, along the first direction X, the size L1 of the first power connection structure PL12 is consistent with the size L2 of the data connection line DL, so that the size of the first power connection structure PL12 along the first direction X is not too large, and the data signal lines D corresponding to the two data connection lines DL located on both sides of the first power connection structure PL12 can be prevented from having a sudden change in resistance.

[0080] In an exemplary embodiment, in a direction perpendicular to the plane where the display substrate is located, the display substrate may include a substrate and a driving circuit 20 layer arranged on the substrate, the driving circuit 20 layer may include a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer sequentially arranged on the substrate, at least part of the line segments of multiple data connection lines and multiple first power connection structures PL12 are located in the fourth conductive layer; in an exemplary embodiment, the fourth conductive layer may be referred to as a second source and drain metal layer SD2.

[0081] In an exemplary embodiment, in a plane parallel to the display substrate, the first frame area B1 may further include a first fan-out area 11, and in the second direction Y, the first fan-out area 11 is located between the display area AA and the bending area 12; the display substrate may further include a first power connection line PL11, and the data connection line includes a first data connection line DL1 and a second data connection line DL2, and in the same data signal line, the data line DL0 is electrically connected to the second data connection line DL2 through the first data connection line DL1, wherein:

[0082] A first power connection line PL11, located in the first fan-out area 11, the first power connection line PL11 extends along the first direction X and is electrically connected to a plurality of first power connection structures PL12, and the plurality of first power connection structures PL12 provide a first power signal to a plurality of sub-pixels Pxij through the first power connection line PL11;

[0083] The first data link lines DL1 are located in the first fan-out area 11. Among the plurality of first data link lines DL1, at least a portion is located in the first conductive layer, and at least a portion is located in the second conductive layer. The first data link lines DL1 located in the first conductive layer and the first data link lines DL1 located in the second conductive layer are arranged alternately.

[0084] The second data link line DL2 is located in the bending area 12. In a direction perpendicular to the plane where the display substrate is located, the second data link line DL2 may be located in the fourth conductive layer, and at least part of the line segments of the data link lines may include the second data link line DL2.

[0085] In an exemplary embodiment, the orthographic projection of the first power connection line PL11 on the substrate at least partially overlaps with the orthographic projections of the plurality of first data connection lines DL1 on the substrate, which can save space in the first border area B1. For example, the orthographic projection of the first power connection line PL11 on the substrate can cover the orthographic projections of the plurality of first data connection lines DL1 on the substrate.

[0086] In an exemplary embodiment, in a direction perpendicular to the plane where the display substrate is located, the first power connection line PL11 is located in the fourth conductive layer, and the first power connection line PL11 is directly connected to multiple first power connection structures PL12; in the same data signal line, the first data connection line DL1 is electrically connected to the second data connection line DL2 through a via, and the first data connection line DL1 is electrically connected to the data line DL0 through a via.

[0087] In an exemplary embodiment, in a plane parallel to the display substrate, the first frame area B1 further includes a second fan-out area 13, and in the second direction Y, the second fan-out area 13 is located on a side of the bending area 12 away from the display area AA, the display substrate further includes a first power line VDD, and the data connection line further includes a third data connection line DL3, and in the same data connection line, the first data connection line DL1 is electrically connected to the third data connection line DL3 through the second data connection line DL2; wherein:

[0088] A first power line VDD, located in the second fan-out area 13, and connected to a plurality of first power connection structures PL12;

[0089] The third data link line DL3 is located in the second fan-out area 13. Among the multiple third data link lines DL3, at least part is located in the first conductive layer, at least part is located in the second conductive layer, and the third data link lines DL3 located in the first conductive layer and the third data link lines DL3 located in the second conductive layer are arranged alternately.

[0090] In an exemplary embodiment, in a direction perpendicular to the plane where the display substrate is located, the first power line VDD is located in the fourth conductive layer, and the first power line VDD is directly connected to multiple first power connection structures PL12; in the same data signal line, the second data connection line DL2 and the third data connection line DL3 are electrically connected through vias.

[0091] In an exemplary embodiment, the orthographic projection of the first power line VDD on the substrate at least partially overlaps with the orthographic projections of the plurality of third data link lines DL3 on the substrate, which can save space in the first border area B1.

[0092] In an exemplary embodiment, in a plane parallel to the display substrate, the first border area B1 may further include a binding area 14. In the second direction Y, the binding area 14 is located on a side of the second fan-out area 13 away from the display area AA. The binding area 14 may include a first power pad 51 and a drive circuit 20; the third data link line DL3 is electrically connected to the drive circuit 20; the first power line VDD extends to the binding area 14 and is electrically connected to the first power pad 51.

[0093] In an exemplary embodiment, the display area AA may further be provided with a plurality of scan signal lines SL, which may extend along the first direction X and be arranged at intervals along the second direction Y, and each scan signal line SL may be electrically connected to a plurality of sub-pixels Pxij in a row of sub-pixels.

[0094] In an exemplary embodiment, the second border area B2 and the third border area B3 may be provided with a plurality of gate drive circuits GOA (GOA is an abbreviation for array substrate row drive, and its full English name is Gate Driver on Array) and gate drive circuit signal lines (GOA signal lines). The GOA signal lines may include clock signal lines (for example, may include CK signal lines, CB signal lines, STV signal lines, etc.). The gate drive circuits GOA may be configured to be electrically connected to corresponding scan signal lines SL and provide scan signals to the corresponding scan signal lines SL.

[0095] In an exemplary embodiment, if Figure 7 As shown, the first border area B1 is also provided with a second power line VSS and a second power connection structure PL22. The second power connection structure PL22 is located in the bending area 12. In the first direction X, the second power connection structure PL22 is located on both sides of multiple first power connection structures PL12 and multiple second data connection lines DL2; the second power line VSS is located in the second fan-out area 13 and the binding area 14. In the first direction X, the second power line VSS is located on both sides of the first power line VDD.

[0096] In an exemplary embodiment, the binding area 14 may include a driving chip area 141, a third fan-out area 142 and a binding electrode area 143 which are arranged in sequence along the direction of the second fan-out area 13 away from the bending area 12. The driving chip area 141 may be provided with a driving circuit 20, the third fan-out area 142 may be provided with a plurality of binding leads 201, and the binding electrode area 143 may be provided with a plurality of pads. The plurality of pads may include a first power pad 51, a second power pad 52, a driving pad 53, a first gate driving circuit pad 541, and a second gate driving pad 542. The driving circuit 20 may be electrically connected to the driving pad 53 in the binding electrode area 143 through the binding lead 201, and the plurality of pads may be bound and connected to the flexible circuit board 30. The first power line VDD may be connected to the first power pad connection 51, the second power line VSS may be connected to the second power pad 52, and the driving pad 53 may be electrically connected to the corresponding binding lead 201.

[0097] In an exemplary embodiment, the gate drive circuit signal line may include a first gate drive circuit signal line 41 and a second gate drive circuit signal line 42, the first gate drive circuit signal line 41 extends from the third frame area B3 to the first frame area B1, and is connected to the first gate drive pad 541 and the gate drive circuit GOA located in the third frame area B3; the second gate drive circuit signal line 42 extends from the fourth frame area B4 to the first frame area B1, and is connected to the second gate drive pad 542 and the gate drive circuit GOA located in the fourth frame area B4. The gate drive circuit GOA may include a first gate drive circuit GOA1 disposed in the third frame area B3 and a second gate drive circuit GOA2 disposed in the fourth frame area B4, the first gate drive circuit GOA1 is configured to be electrically connected to the first gate drive pad 541 through the first gate drive circuit signal line 41, and the second gate drive circuit GOA2 is configured to be electrically connected to the second gate drive pad 542 through the second gate drive circuit signal line 42.

[0098] The present disclosure also provides a display device, such as Fig. 9 As shown, the display device may include: a display substrate.

[0099] The display substrate is the display substrate provided by any of the aforementioned embodiments, and the implementation principle and effect are similar, which will not be repeated here.

[0100] In an exemplary embodiment, the display device may be a liquid crystal display device (LCD) or an organic light emitting diode (OLED) or a light emitting diode (LED) display device. The display device may be a liquid crystal panel, electronic paper, OLED panel, active-matrix organic light emitting diode (AMOLED) panel, mobile phone, tablet computer, television, monitor, notebook computer, digital photo frame, navigator, or any other product or component with a display function.

[0101] The display substrate and display device provided by the embodiments of the present disclosure include a display area and a first frame area located on one side of the display area, the display area includes a plurality of sub-pixels and a data line among a plurality of data signal lines, the first frame area includes a bending area, in which, along a first direction, data connection lines of a plurality of data signal lines are arranged at intervals with a plurality of first power connection structures, and at least one data connection line is provided between two adjacent first power connection structures. The display substrate provided by the embodiments of the present disclosure can avoid the technical problem of display splitting caused by a sudden change in resistance (large resistance step difference) of a signal routing line in a bending area of ​​the display substrate.

[0102] The drawings of the embodiments of the present disclosure only involve the structures involved in the embodiments of the present disclosure, and other structures may refer to the general design.

[0103] In the absence of conflict, the embodiments of the present disclosure, that is, the features in the embodiments, can be combined with each other to obtain new embodiments.

[0104] Although the implementation methods disclosed in the embodiments of the present disclosure are as above, the contents described are only implementation methods adopted to facilitate understanding of the embodiments of the present disclosure, and are not used to limit the embodiments of the present disclosure. Any technician in the field to which the embodiments of the present disclosure belong may make any modifications and changes in the form and details of implementation without departing from the spirit and scope disclosed in the embodiments of the present disclosure, but the scope of patent protection of the embodiments of the present disclosure shall still be based on the scope defined by the attached claims.

Claims

1. A display substrate, characterized in that: It includes a display area and a first frame area located on one side of the display area, wherein the first frame area is provided with a bending area; A plurality of sub-pixels are located in the display area; a plurality of data signal lines, located in the display area and the first frame area, and electrically connected to the plurality of sub-pixels, the plurality of data signal lines being configured to provide data signals to the plurality of sub-pixels; the data signal lines comprising data lines and data connection lines, the data lines being located in the display area, the data connection lines being located in the first frame area, and electrically connected to corresponding data lines, and in the same data signal line, at least part of the line segments of the data connection lines being located in the bending area; a plurality of first power connection structures, located in the bending area, the plurality of first power connection structures are arranged at intervals along a first direction and extend along a second direction, and are configured to provide a first power signal to the plurality of sub-pixels, the first direction intersecting the second direction; In the bending area, along the first direction, the data connection lines of the plurality of data signal lines are arranged at intervals from the plurality of first power connection structures, and at least one data connection line is provided between two adjacent first power connection structures.

2. The display substrate according to claim 1, characterized in that: In the bending area, along the first direction, the plurality of first power connection structures are arranged at equal intervals.

3. The display substrate according to claim 1, characterized in that: In the bending area, along the first direction, a plurality of first distances between a plurality of data connection lines are consistent, and the first distance is a distance between two adjacent data connection lines.

4. The display substrate according to claim 1, characterized in that: In the bending area, along the first direction, a plurality of data connection lines between two adjacent first power connection structures are arranged at equal intervals.

5. The display substrate according to claim 3, characterized in that: In the bending area, along the first direction, the first distance is greater than or equal to a second distance, and the second distance is the distance between the first power connection structure and an adjacent data connection line.

6. The display substrate according to claim 5, characterized in that: In the bending area, along the first direction, a ratio of the first distance to the second distance is greater than or equal to 1.

5.

7. The display substrate according to any one of claims 1 to 6, characterized in that: In the bending area, along the first direction, a size of the first power connection structure is consistent with a size of the data connection line.

8. The display substrate according to any one of claims 1 to 6, characterized in that: In a direction perpendicular to the plane where the display substrate is located, the display substrate includes a base and a driving circuit layer arranged on the base, the driving circuit layer includes a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer arranged in sequence on the base, and at least part of the line segments of the data connection line and the multiple first power connection structures are located in the fourth conductive layer.

9. The display substrate according to claim 8, characterized in that: In a plane parallel to the display substrate, the first frame area further includes a first fan-out area, and in the second direction, the first fan-out area is located between the display area and the bending area; the display substrate further includes a first power connection line, and the data connection line includes a first data connection line and a second data connection line. In the same data signal line, the data line is electrically connected to the second data connection line through the first data connection line, wherein: The first power connection line is located in the first fan-out area, the first power connection line extends along the first direction and is electrically connected to the plurality of first power connection structures, and the plurality of first power connection structures provide first power signals to the plurality of sub-pixels through the first power connection line; The first data connection lines are located in the first fan-out area, and among the plurality of the first data connection lines, at least part of them are located in the first conductive layer, and at least part of them are located in the second conductive layer, and the first data connection lines located in the first conductive layer and the first data connection lines located in the second conductive layer are arranged alternately; The second data connection line is located in the bending area, in a direction perpendicular to the plane where the display substrate is located, the second data connection line is located in the fourth conductive layer, and at least part of the line segments of the data connection line include the second data connection line.

10. The display substrate according to claim 9, characterized in that: In a direction perpendicular to the plane where the display substrate is located, the first power connection line is located in the fourth conductive layer, and the first power connection line is directly connected to the multiple first power connection structures; in the same data signal line, the first data connection line is electrically connected to the second data connection line through a via, and the first data connection line is electrically connected to the data line through a via.

11. The display substrate according to claim 9, characterized in that: In a plane parallel to the display substrate, the first frame area further includes a second fan-out area, and in the second direction, the second fan-out area is located on a side of the bending area away from the display area, the display substrate further includes a first power line, and the data connection line further includes a third data connection line, and in the same data connection line, the first data connection line is electrically connected to the third data connection line through the second data connection line; wherein: The first power line is located in the second fan-out area, and the first power line is connected to the plurality of first power connection structures; The third data connection lines are located in the second fan-out area. Among the plurality of third data connection lines, at least part is located in the first conductive layer, and at least part is located in the second conductive layer. The third data connection lines located in the first conductive layer and the third data connection lines located in the second conductive layer are arranged alternately.

12. The display substrate according to claim 11, characterized in that: In a direction perpendicular to the plane where the display substrate is located, the first power line is located in the fourth conductive layer, and the first power line is directly connected to the multiple first power connection structures; in the same data signal line, the second data connection line is electrically connected to the third data connection line through a via.

13. The display substrate according to claim 11, characterized in that: In the plane content parallel to the display substrate, the first border area also includes a binding area. In the second direction, the binding area is located on the side of the second fan-out area away from the display area. The binding area is provided with a first power pad and a drive circuit; the third data connection line is electrically connected to the drive circuit; the first power line extends to the binding area and is electrically connected to the first power pad.

14. A display device, characterized in that: The display substrate comprises the display substrate as claimed in any one of claims 1 to 13.

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