Pixel circuit, display panel comprising pixel circuit and display device

Abstract

A pixel circuit includes a pixel driving circuit (10), a first light emitting element (D1), a second light emitting element (D2), a switching circuit (20), and a reset circuit (30). The pixel driving circuit (10) is connected to the first light-emitting element (D1) to drive the first light-emitting element (D1) to emit light; the switching circuit (20) is configured to electrically connect the second light-emitting element (D2) to the pixel driving circuit (10) in response to the control end thereof receiving a first level signal so as to make the second light-emitting element (D2) emit light, and to disconnect the electrical connection between the second light-emitting element (D2) and the pixel driving circuit (10) in response to the control end (c) receiving a second level signal so as to make the second light-emitting element (D2) emit light. So that the second light-emitting element (D2) is in a non-light-emitting state; the reset circuit (30) is configured to reset the first light-emitting element (D1) and / or the second light-emitting element (D2) under the control of a reset control signal.

Description

Pixel circuit, display panel including the same, and display device Technical Field

[0001] The present application relates to the technical field of electronic circuits, and more specifically, to a pixel circuit, a display panel including the pixel circuit, and a display device. Background Art

[0002] With the development of electronic semiconductor technology and Internet technology, electronic display products have been widely used in people's daily life and work. In addition to the conventional image display function, people also have demands for additional functions or personalized functions of display products. When using display products in public places, there may be a need for the displayed image content to be inappropriate for viewing by others or the displayed content to be kept confidential. For example, when people use mobile phones or flat-panel display devices on public transportation, they do not expect the displayed content to be easily seen by other people next to or nearby. Moreover, this need for confidentiality of displayed content is still growing. Therefore, in some occasions, some anti-peeping measures need to be taken to protect the privacy of the content displayed by the display product. At present, a commonly used measure is to set an anti-peeping film on the display screen of the display product to reduce the display viewing angle.

[0003] Summary of the Invention

[0004] The present application provides a pixel circuit, comprising: a pixel driving circuit, a first light-emitting element, a second light-emitting element, a switching circuit, and a reset circuit. The pixel driving circuit is electrically connected to the first light-emitting element to drive the first light-emitting element to emit light. The switching circuit comprises a first terminal, a second terminal, and a control terminal. The first terminal of the switching circuit is electrically connected to the pixel driving circuit, and the second terminal of the switching circuit is electrically connected to the second light-emitting element. The switching circuit is configured to: electrically connect the second light-emitting element to the pixel driving circuit in response to the control terminal receiving a first level signal, so that the pixel driving circuit drives the second light-emitting element to emit light; and disconnect the second light-emitting element from the pixel driving circuit in response to the control terminal receiving a second level signal, so that the second light-emitting element is in a non-light-emitting state. The reset circuit comprises a reference voltage connection terminal for receiving a first reference voltage and a reset control terminal for receiving a reset control signal. The reset circuit is electrically connected to one of the first terminal and the second terminal of the switching circuit and at least one of the first light-emitting element and the second light-emitting element, and is configured to reset the first light-emitting element and / or the second light-emitting element using the first reference voltage under the control of the reset control signal.

[0005] According to some embodiments of the present application, the switching circuit includes a first transistor, the first end of the switching circuit includes the first pole of the first transistor, the second end of the switching circuit includes the second pole of the first transistor, and the control end of the switching circuit includes the control pole of the first transistor, wherein the first pole of the first transistor is electrically connected to the first pole of the first light-emitting element, the second pole of the first transistor is electrically connected to the first pole of the second light-emitting element, the control pole of the first transistor is configured to receive the first level signal or the second level signal, and the second pole of the first light-emitting element and the second pole of the second light-emitting element are electrically connected to the second reference voltage end.

[0006] According to some embodiments of the present application, the reset circuit includes a second transistor, the first electrode of the second transistor is electrically connected to the first electrode of the second light-emitting element, the second electrode of the second transistor is electrically connected to the reference voltage connection terminal, and the control electrode of the second transistor is electrically connected to the reset control terminal.

[0007] According to some embodiments of the present application, the reset circuit includes a second transistor, the first electrode of the second transistor is electrically connected to the first electrode of the first light-emitting element, the second electrode of the second transistor is electrically connected to the reference voltage connection terminal, and the control electrode of the second transistor is electrically connected to the reset control terminal.

[0008] According to some embodiments of the present application, the reset circuit includes a third transistor and a fourth transistor, the third transistor and the fourth transistor are connected in series between the first pole of the first light-emitting element and the first pole of the second light-emitting element, the second pole of the first light-emitting element and the second pole of the second light-emitting element are electrically connected to the second reference voltage terminal, the first node between the third transistor and the fourth transistor is electrically connected to the reference voltage connection terminal, and the control electrode of the third transistor and the control electrode of the fourth transistor are electrically connected to the reset control terminal.

[0009] According to some embodiments of the present application, the switching circuit includes a fifth transistor, the first end of the switching circuit includes the first pole of the fifth transistor, the second end of the switching circuit includes the second pole of the fifth transistor, and the control end of the switching circuit includes the control pole of the fifth transistor, wherein the pixel driving circuit includes a driving transistor, a sixth transistor and a power supply voltage end for receiving a power supply voltage, the driving transistor and the sixth transistor are connected in series between the power supply voltage end and the first pole of the first light-emitting element, the first pole of the fifth transistor is electrically connected to the first pole or the second pole between the sixth transistor, and the second pole of the fifth transistor is electrically connected to the first pole of the second light-emitting element.

[0010] According to some embodiments of the present application, the pixel driving circuit includes a driving transistor, a sixth transistor, a seventh transistor and a power supply voltage terminal for receiving a power supply voltage, the seventh transistor, the driving transistor, and the sixth transistor are connected in series between the power supply voltage terminal and the first electrode of the first light-emitting element, wherein the pixel driving circuit also includes an eighth transistor, the first electrode of the eighth transistor is electrically connected to a third node between the driving transistor and the seventh transistor, the second electrode of the eighth transistor is electrically connected to a third reference voltage terminal, and the control electrode of the eighth transistor is electrically connected to the reset control terminal.

[0011] According to some embodiments of the present application, the pixel driving circuit also includes a ninth transistor, a tenth transistor, a capacitor and a fourth reference voltage terminal, wherein the capacitor, the ninth transistor and the tenth transistor are connected in series between the power supply voltage terminal and the fourth reference voltage terminal in sequence, and the control electrode of the driving transistor is electrically connected to a fourth node between the capacitor and the ninth transistor, wherein the control electrode of the tenth transistor is electrically connected to the reset control terminal, and the control electrode of the ninth transistor is used to receive a first scanning signal.

[0012] According to some embodiments of the present application, the pixel driving circuit also includes an eleventh transistor and a twelfth transistor, the first electrode and the second electrode of the eleventh transistor being electrically connected to the second node between the driving transistor and the sixth transistor, and the fifth node between the ninth transistor and the tenth transistor, respectively, the first electrode of the twelfth transistor being used to receive a data signal, the second electrode of the twelfth transistor being electrically connected to the third node, and the control electrode of the eleventh transistor and the control electrode of the twelfth transistor being used to receive a second scanning signal.

[0013] According to some embodiments of the present application, the ninth transistor includes a metal oxide thin film transistor, and each of the driving transistor, the sixth transistor, the seventh transistor, the eighth transistor, the tenth transistor, the eleventh transistor and the twelfth transistor includes a low-temperature polysilicon thin film transistor.

[0014] Another embodiment of the present application provides a display panel, comprising: a base substrate; and a plurality of pixel circuits as described in the aforementioned pixel circuit embodiments, wherein the plurality of pixel circuits are arranged in an array on the base substrate to form a pixel circuit array.

[0015] According to some embodiments of the present application, the display panel includes a first reference voltage line located on the base substrate, the first reference voltage line is electrically connected to the reference voltage end to transmit the first reference voltage, wherein two adjacent pixel circuits in the pixel circuit array share the first reference voltage line, and the two adjacent pixel circuits are symmetrically arranged on both sides of the first reference voltage line.

[0016] According to some embodiments of the present application, the first reference voltage line includes a first part and a second part, the first part extends in the column direction of the pixel circuit array, the second part extends in the row direction of the pixel circuit array, the first part and the second part intersect, wherein the two adjacent pixel circuits are symmetrically arranged on both sides of the first part.

[0017] According to some embodiments of the present application, the switching circuit includes a first transistor, the first end of the switching circuit includes the first electrode of the first transistor, the second end of the switching circuit includes the second electrode of the first transistor, the control end of the switching circuit includes the control electrode of the first transistor, the reset circuit includes a second transistor, the first electrode of the second transistor is electrically connected to the first electrode of the first light-emitting element or the second light-emitting element, the second electrode of the second transistor is electrically connected to the reference voltage connection terminal, and the control electrode of the second transistor is electrically connected to the reset control terminal, wherein the pixel driving circuit includes a driving transistor, a sixth transistor, and a power supply voltage terminal for receiving a power supply voltage, the driving transistor and the sixth transistor are connected in series between the power supply voltage terminal and the first electrode of the first light-emitting element, and the display panel further includes a first gate metal layer located on the substrate, wherein the first gate metal layer includes a first gate metal line, a second gate metal line, and a third gate metal line extending along a row direction of the pixel circuit array and spaced apart from each other in a column direction of the pixel circuit array, wherein the first gate metal line includes the gate of the first transistor, the second gate metal line includes the gate of the second transistor, the third gate metal line includes the gate of the sixth transistor, and the first gate metal line is located between the second gate metal line and the third gate metal line.

[0018] According to some embodiments of the present application, the reset circuit includes a third transistor and a fourth transistor, the third transistor and the fourth transistor are connected in series between the first electrode of the first light-emitting element and the first electrode of the second light-emitting element, the second electrode of the first light-emitting element and the second electrode of the second light-emitting element are electrically connected to the second reference voltage terminal, the first node between the third transistor and the fourth transistor is electrically connected to the reference voltage connection terminal, the control electrode of the third transistor and the control electrode of the fourth transistor are electrically connected to the reset control terminal, the switching circuit includes a fifth transistor, the first terminal of the switching circuit includes the first electrode of the fifth transistor, the second terminal of the switching circuit includes the second electrode of the fifth transistor, and the control terminal of the switching circuit includes the control electrode of the fifth transistor, wherein the pixel driving circuit includes a driving transistor, a sixth transistor and a power supply voltage terminal for receiving a power supply voltage, The driving transistor and the sixth transistor are connected in series between the power supply voltage terminal and the first electrode of the first light-emitting element, the first electrode of the fifth transistor is electrically connected to the second node between the driving transistor and the sixth transistor, and the second electrode of the fifth transistor is electrically connected to the first electrode of the second light-emitting element, wherein the display panel also includes: a first gate metal layer located on the base substrate, wherein the first gate metal layer includes a fourth gate metal line, a fifth gate metal line and a sixth gate metal line extending along the row direction of the pixel circuit array and spaced from each other in the column direction of the pixel circuit array, wherein the fourth gate metal line includes the gates of the third transistor and the fourth transistor, the fifth gate metal line includes the gate of the fifth transistor, the sixth gate metal line includes the gate of the sixth transistor, and the fifth gate metal line is located between the fourth gate metal line and the sixth gate metal line.

[0019] According to some embodiments of the present application, the display panel also includes a third gate metal layer, which is located on the side of the second gate metal layer away from the substrate, and includes the top gate of the ninth transistor and a fourth reference voltage line, and the fourth reference voltage line is electrically connected to the fourth reference voltage end to transmit the fourth reference voltage, wherein the display panel also includes a source-drain metal layer located on the side of the third gate metal layer away from the substrate, and the source-drain metal layer includes the first reference voltage line.

[0020] In some embodiments, the display panel further includes a semiconductor layer located on the side of the first gate metal layer facing the base substrate, the semiconductor layer including the active layer, first electrode and second electrode patterns of the first transistor, the second transistor and the sixth transistor, wherein the active layer, first electrode and second electrode patterns of the first transistor and the active layer, first electrode and second electrode patterns of the sixth transistor are interconnected, and the active layer, first electrode and second electrode patterns of the second transistor are separated from the active layer, first electrode and second electrode patterns of the first transistor and the sixth transistor, wherein the display panel further includes a source-drain metal layer located on the side of the first gate metal layer facing away from the base substrate, the source-drain metal layer including the first reference voltage line and the electrode switching line, wherein the electrode switching line electrically connects the active layer, first electrode and second electrode patterns of the second transistor to the active layer, first electrode and second electrode patterns of the sixth transistor.

[0021] According to some embodiments of the present application, the display panel includes a semiconductor layer located on the side of the first gate metal layer facing the substrate, the semiconductor layer includes the first electrode, the second electrode and the active layer of the third transistor and the fourth transistor, wherein the patterns of the first electrode, the second electrode and the active layer of the third transistor and the fourth transistor in the two adjacent pixel circuits are symmetrical about the first part, and the display panel also includes a source-drain metal layer located on the side of the first gate metal layer away from the substrate, the source-drain metal layer includes the first reference voltage line, wherein the source electrodes of the third transistor and the fourth transistor in the two adjacent pixel circuits are electrically connected to the first reference voltage line via the same via located at the connection point between the first part and the second part.

[0022] According to some embodiments of the present application, the display panel further includes: a first light-shielding layer located on the first gate metal layer facing the base substrate, the first light-shielding layer includes a plurality of first light-shielding parts, the first gate metal layer includes the gate of the driving transistor, wherein the positive projection of one of the plurality of first light-shielding parts on the base substrate covers and exceeds the positive projection of the gate of the driving transistor and the active layer on the base substrate.

[0023] According to some embodiments of the present application, the orthographic projection of the top gate of the ninth transistor on the substrate is located within the orthographic projection of the bottom gate of the ninth transistor on the substrate.

[0024] According to some embodiments of the present application, the display panel further includes a pixel definition layer located on the base substrate, wherein the pixel definition layer defines a first light-emitting area of ​​the first light-emitting element and a second light-emitting area of ​​the second light-emitting element, wherein the first light-emitting area and the second light-emitting area are spaced from each other and symmetrically distributed on both sides of a symmetry axis, wherein the symmetry axis intersects with an extension line of the first part.

[0025] Another embodiment of the present application provides a display panel, comprising: a substrate; a pixel circuit as described in the aforementioned pixel circuit embodiment located on the substrate; a pixel definition layer located on the side of the pixel circuit away from the substrate, the pixel definition layer defining a first light-emitting area of ​​the first light-emitting element and a second light-emitting area of ​​the second light-emitting element; and an optical structure located on the side of the pixel definition layer away from the substrate, wherein the optical structure is optically coupled to the first light-emitting area to suppress the propagation of light from the first light-emitting element in a first emission direction that is not perpendicular to the light-emitting surface of the display panel.

[0026] According to some embodiments of the present application, the optical structure includes a light absorbing layer, which at least partially surrounds the first light emitting area, and the orthographic projection of the light absorbing layer on the base substrate does not overlap with the orthographic projection of the second light emitting area on the base substrate.

[0027] According to some embodiments of the present application, the display panel further includes an encapsulation layer located on the side of the pixel definition layer facing away from the base substrate, wherein the optical structure further includes a light-transmitting layer, and the light-absorbing layer includes a first sub-light-absorbing layer and a second sub-light-absorbing layer, the first sub-light-absorbing layer is located on the side of the encapsulation layer facing away from the base substrate, the light-transmitting layer covers the first sub-light-absorbing layer, and the second sub-light-absorbing layer is located on the side of the light-transmitting layer facing away from the base substrate.

[0028] According to some embodiments of the present application, the light-transmitting layer includes a first light-transmitting portion and a second light-transmitting portion, the first light-transmitting portion is located on a side of the first sub-light-absorbing layer away from the substrate, the second light-transmitting portion is located on a side of the first light-transmitting portion away from the substrate, and the second light-transmitting portion covers the first light-transmitting portion, wherein the refractive index of the second light-transmitting portion is higher than the refractive index of the first light-transmitting portion.

[0029] According to some embodiments of the present application, the display panel further includes an encapsulation layer located on the side of the pixel definition layer facing away from the base substrate, the optical structure includes a microlens located on the side of the encapsulation layer facing away from the base substrate, and the microlens is configured to converge light from the first light-emitting element.

[0030] Yet another embodiment of the present application provides a display device, which may include the display panel as described in any of the aforementioned embodiments.

[0031] These and other advantages of the application will be apparent from and elucidated with reference to the embodiments described hereinafter. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The embodiments of the present application will now be described in more detail with reference to the accompanying drawings. It should be understood that the electrical components and layer structures of the display panel shown in the drawings only schematically represent the partial structure of the display panel related to the technical solutions described in the embodiments of the present application and do not necessarily represent the actual product structure.

[0033] FIG1a illustrates a structural block diagram of a pixel circuit according to an embodiment of the present application;

[0034] FIG1 b illustrates a structural block diagram of a pixel circuit according to another embodiment of the present application;

[0035] FIG1c illustrates a structural block diagram of a pixel circuit according to another embodiment of the present application;

[0036] FIG2 a illustrates a structural block diagram of a pixel circuit according to another embodiment of the present application;

[0037] FIG2 b illustrates a structural block diagram of a pixel circuit according to another embodiment of the present application;

[0038] FIG2 c illustrates a structural block diagram of a pixel circuit according to another embodiment of the present application;

[0039] FIG3 illustrates a circuit schematic diagram of a pixel circuit according to an embodiment of the present application;

[0040] FIG4 a illustrates a signal timing diagram when the pixel circuit shown in FIG3 is in a first operating mode;

[0041] FIG4 b illustrates a signal timing diagram when the pixel circuit shown in FIG3 is in the second operating mode;

[0042] FIG5 illustrates a circuit schematic diagram of a pixel circuit according to another embodiment of the present application;

[0043] FIG6 illustrates a signal timing diagram when the pixel circuit shown in FIG5 is in the first operating mode;

[0044] FIG7 illustrates a circuit schematic diagram of a pixel circuit according to another embodiment of the present application;

[0045] FIG8 a illustrates a signal timing diagram when the pixel circuit shown in FIG7 is in the first operating mode;

[0046] FIG8 b illustrates a signal timing diagram when the pixel circuit shown in FIG7 is in the second operating mode;

[0047] FIG9 illustrates a circuit schematic diagram of a pixel circuit according to another embodiment of the present application;

[0048] FIG10 illustrates a top perspective view of a portion of a layer structure of two adjacent pixel circuits in a display panel according to an embodiment of the present application;

[0049] FIG11 illustrates a pattern of a light shielding layer for two adjacent pixel circuits in a display panel according to an embodiment of the present application;

[0050] FIG12 illustrates patterns of semiconductor layers for two adjacent pixel circuits in a display panel according to one embodiment of the present application;

[0051] FIG13 illustrates a pattern of a first gate metal layer for two adjacent pixel circuits in a display panel according to an embodiment of the present application;

[0052] FIG14 illustrates a top perspective view of a semiconductor layer and a first gate metal layer stacked together in two pixel circuits in a display panel according to an embodiment of the present application;

[0053] FIG15 illustrates a pattern of a second gate metal layer for two adjacent pixel circuits in a display panel according to an embodiment of the present application;

[0054] FIG16 illustrates a pattern of metal oxide semiconductor channels for two adjacent pixel circuits in a display panel according to an embodiment of the present application;

[0055] FIG17 illustrates a pattern of a third gate metal layer for two adjacent pixel circuits in a display panel according to an embodiment of the present application;

[0056] 18 illustrates a top perspective view of the second gate metal layer shown in FIG. 15 , the metal oxide semiconductor channel of the ninth transistor shown in FIG. 16 , and the third gate metal layer shown in FIG. 17 stacked together;

[0057] FIG19 illustrates patterns of source and drain metal layers for two adjacent pixel circuits in a display panel according to one embodiment of the present application;

[0058] FIG20 illustrates a partial top perspective view of a semiconductor layer, a first gate metal layer, a second gate metal layer, a metal oxide semiconductor channel of a ninth transistor in a pixel circuit, a third gate metal layer, and a source / drain metal layer in a display panel according to some embodiments of the present application;

[0059] FIG21 illustrates a pattern of a power line metal layer for two adjacent pixel circuits in a display panel according to an embodiment of the present application;

[0060] FIG22 illustrates a pattern of an anode layer for eight adjacent pixel circuits in a display panel according to one embodiment of the present application;

[0061] FIG23 illustrates a pattern of light-emitting areas of light-emitting elements of eight adjacent pixel circuits defined by a pixel definition layer in a display panel according to an embodiment of the present application;

[0062] FIG24 illustrates a top perspective view of a stack of power line metal layers, anode layers, and pixel definition layers for eight adjacent pixel circuits in a display panel according to an embodiment of the present application;

[0063] FIG25 illustrates a top perspective view of a stack of power line metal layers, anode layers, and pixel definition layers for eight adjacent pixel circuits in a display panel according to another embodiment of the present application;

[0064] FIG26 illustrates a top perspective view of a stack of power line metal layers and source / drain metal layers for two adjacent pixel circuits in a display panel according to an embodiment of the present application;

[0065] FIG27 illustrates the locations of some vias based on FIG26;

[0066] FIG28 illustrates a partial cross-sectional view of a display panel according to one embodiment of the present application;

[0067] FIG29 illustrates a partial top perspective view of a single pixel circuit in a display panel corresponding to the portion indicated by the lower left dashed rectangular frame in FIG20 according to another embodiment of the present application;

[0068] FIG30 illustrates a pattern of a light shielding layer for two adjacent pixel circuits in a display panel according to another embodiment of the present application;

[0069] FIG31 illustrates patterns of semiconductor layers for two adjacent pixel circuits in a display panel according to another embodiment of the present application;

[0070] FIG32 illustrates a pattern of a first gate metal layer for two adjacent pixel circuits in a display panel according to another embodiment of the present application;

[0071] FIG33 shows a perspective view of a first gate metal layer and a semiconductor layer stacked together in a pixel circuit of a display panel according to another embodiment of the present application;

[0072] FIG34 illustrates a pattern of a second gate metal layer for two adjacent pixel circuits in a display panel according to another embodiment of the present application;

[0073] FIG35 illustrates a pattern of a third gate metal layer for two adjacent pixel circuits in a display panel according to another embodiment of the present application;

[0074] 36 illustrates a top perspective view of the second gate metal layer shown in FIG 34 , the metal oxide semiconductor channel layer of the ninth transistor, and the third gate metal layer shown in FIG 35 stacked together;

[0075] FIG37 illustrates patterns of source and drain metal layers for two adjacent pixel circuits in a display panel according to another embodiment of the present application;

[0076] FIG38 illustrates a pattern of a power line metal layer for two adjacent pixel circuits in a display panel according to another embodiment of the present application;

[0077] FIG39 schematically shows a top perspective view of the semiconductor layer, the first gate metal layer, the second gate metal layer, the third gate metal layer, the channel layer of the ninth transistor, the source / drain metal layer, and the power line metal layer shown in FIG31 to FIG38 ;

[0078] FIG40 illustrates a pattern of an anode layer and a light-emitting region of a light-emitting element for two adjacent pixel circuits defined by a pixel definition layer in a display panel according to another embodiment of the present application;

[0079] FIG41 illustrates a partial cross-sectional view of a display panel according to another embodiment of the present application, the partial cross-sectional view relating to a first light-emitting region and a second light-emitting region of two light-emitting elements in a single pixel circuit;

[0080] FIG42 illustrates a partial cross-sectional view of a display panel according to another embodiment of the present application, the partial cross-sectional view relating to a first light-emitting region of a first light-emitting element in a single pixel circuit;

[0081] FIG43 illustrates a partial cross-sectional view of a display panel according to yet another embodiment of the present application, the partial cross-sectional view relating to a first light-emitting region of a first light-emitting element in a single pixel circuit;

[0082] FIG44 illustrates a partial cross-sectional view of a display panel according to yet another embodiment of the present application, the partial cross-sectional view relating to a first light-emitting region of a first light-emitting element in a single pixel circuit;

[0083] FIG45 is a schematic diagram illustrating two light-emitting areas of a display panel corresponding to two light-emitting elements in a single pixel circuit in different states in an anti-peeping display mode and a normal display mode, respectively.

[0084] These and other advantages of the application will be apparent from and elucidated with reference to the embodiments described hereinafter. DETAILED DESCRIPTION

[0085] The following description provides specific details of various embodiments of the present application so that those skilled in the art can fully understand and implement the various embodiments of the present application. In some cases, this application does not illustrate or describe in detail some structures or functions well known in the art to avoid these unnecessary descriptions from obscuring the description of the embodiments of the present application. The technical solutions of the present application can be embodied in many different forms and purposes and should not be limited to the embodiments set forth herein. These embodiments are provided to make the technical solutions of the present application clear and complete, but the embodiments do not limit the scope of protection of this patent application.

[0086] Here, first, some of the terms involved in the embodiments of the present application are explained to facilitate understanding by those skilled in the art. The "control electrode" mentioned herein refers to the gate of the transistor for receiving a scan signal. The transistor can be in an on state or an off state under the control of the signal received by its control electrode. The "first electrode of the transistor" mentioned herein refers to one of the two terminals of the transistor other than the control electrode, and the "second electrode of the transistor" refers to the other of the two terminals of the transistor other than the control electrode. That is, the first electrode of the transistor can be one of the source and drain of the transistor, and the second electrode of the transistor can be the other of the source and drain of the transistor. The "first light-emitting element" or "second light-emitting element" mentioned herein refers to an element that can be driven by voltage to emit light. The first light-emitting element or the second light-emitting element can be various diodes such as organic light-emitting diodes. The first electrode of the light-emitting element refers to one of the cathode and the anode, and the second electrode of the light-emitting element refers to the other of the cathode and the anode.

[0087] While both the "display panel" and "display device" mentioned herein have image display capabilities, a display device may include components not present in a display panel. In other words, a display device is a display product that can be delivered directly to users. While a display panel has image display capabilities, it lacks some necessary peripheral components (e.g., a bezel). Therefore, a display panel can be considered part of a display device.

[0088] An embodiment of the present application provides a pixel circuit, comprising: a pixel driver circuit, a first light-emitting element, a second light-emitting element, a switching circuit, and a reset circuit. The pixel driver circuit is electrically connected to the first light-emitting element to drive the first light-emitting element to emit light. The switching circuit comprises a first terminal, a second terminal, and a control terminal. The first terminal of the switching circuit is electrically connected to the pixel driver circuit, and the second terminal of the switching circuit is electrically connected to the second light-emitting element. The switching circuit is configured to: in response to receiving a first level signal at its control terminal, electrically connect the second light-emitting element to the pixel driver circuit so that the pixel driver circuit drives the second light-emitting element to emit light; and in response to receiving a second level signal at its control terminal, disconnect the second light-emitting element from the pixel driver circuit so that the second light-emitting element is in a non-luminous state. The reset circuit comprises a reference voltage connection terminal for receiving a first reference voltage and a reset control terminal for receiving a reset control signal. The reset circuit is electrically connected to one of the first and second terminals of the switching circuit and at least one of the first and second light-emitting elements, and is configured to reset the first or second light-emitting element using the first reference voltage under control of the reset control signal.

[0089] Figures 1a, 1b, and 1c illustrate different examples of the aforementioned pixel circuit. As shown in Figure 1a, the pixel circuit includes a pixel driver circuit 10, a first light-emitting element D1, a second light-emitting element D2, a switching circuit 20, and a reset circuit 30. The pixel driver circuit 10 is electrically connected to the first light-emitting element D1 to drive the first light-emitting element D1 to emit light. The switching circuit 20 includes a first terminal a, a second terminal b, and a control terminal c. The first terminal a of the switching circuit is electrically connected to the pixel driver circuit 10, and the second terminal b of the switching circuit is electrically connected to the second light-emitting element D2. The control terminal c of the switching circuit 20 can receive a corresponding control signal, which can have different levels. When the control terminal c of the switching circuit 20 receives a signal at a first level, the switching circuit 20 electrically connects the second light-emitting element D2 to the pixel driver circuit 10, causing the pixel driver circuit 10 to drive the second light-emitting element D2 to emit light. When the control terminal c of the switching circuit 20 receives a signal at a second level, the switching circuit 20 disconnects the second light-emitting element D2 from the pixel driver circuit 10, causing the second light-emitting element D2 to be in a non-luminous state. In the pixel circuit provided in the embodiment of the present application, the switching circuit 20 does not control or affect the normal emission of the first light-emitting element D1. That is, during normal operation of the pixel circuit, if the control terminal c of the switching circuit 20 receives a first-level signal, both the first light-emitting element D1 and the second light-emitting element D2 are driven to emit light by the pixel driving circuit 10. However, if the control terminal c of the switching circuit 20 receives a second-level signal, the second light-emitting element D2 is disconnected from the pixel driving circuit 10 and enters a non-emitting state. As shown in FIG1a , the reset circuit 30 includes a reference voltage connection terminal Vref1 for receiving a first reference voltage and a reset control terminal rc for receiving a reset control signal. The reset circuit 30 is electrically connected to the first terminal a of the switching circuit 20 and the first light-emitting element D1. The reset circuit 30 is configured to reset the first light-emitting element D1 or the second light-emitting element D2 using the first reference voltage under the control of the reset control signal.

[0090] FIG1b illustrates another example of a pixel circuit. Similar to the example shown in FIG1a , the pixel circuit includes a pixel driver circuit 10, a first light-emitting element D1, a second light-emitting element D2, a switching circuit 20, and a reset circuit 30. Furthermore, the first light-emitting element D1 and the second light-emitting element D2 in the pixel circuit shown in FIG1b operate in the same manner as in the example shown in FIG1a . Specifically, when the pixel circuit 10 is operating normally, if the control terminal c of the switching circuit 20 receives a first-level signal, both the first light-emitting element D1 and the second light-emitting element D2 are driven by the pixel driver circuit 10 to emit light. However, if the control terminal c of the switching circuit 20 receives a second-level signal, the second light-emitting element D2 is disconnected from the pixel driver circuit 10 and enters a non-luminous state. Unlike the example shown in FIG1a , the reset circuit 30 is electrically connected to the second terminal b of the switching circuit 20 and the second light-emitting element D2. The reset circuit 30 can also reset the first light-emitting element D1 or the second light-emitting element D2 under the control of a reset control signal using a first reference voltage received from the reference voltage connection terminal Vref1.

[0091] FIG1c illustrates another example of a pixel circuit. As shown in FIG1c , the pixel circuit includes: a pixel driving circuit 10, a first light-emitting element D1, a second light-emitting element D2, a switching circuit 20, and a reset circuit 30. The pixel driving circuit 10 is electrically connected to the first light-emitting element D1 to drive the first light-emitting element D1 to emit light. The switching circuit 20 includes a first terminal a, a second terminal b, and a control terminal c. The first terminal a of the switching circuit 20 is electrically connected to the pixel driving circuit 10, and the second terminal b of the switching circuit 20 is electrically connected to the second light-emitting element D2. The reset circuit 30 includes a reference voltage connection terminal Vref1 for receiving a first reference voltage and a reset control terminal rc for receiving a reset control signal. The reset circuit 30 is electrically connected to the second terminal b of the switching circuit 20, the first light-emitting element D1, and the second light-emitting element D2. Under the control of the reset control signal, the reset circuit 30 resets the first light-emitting element D1 or the second light-emitting element D2 using the first reference voltage. In this example, the switching circuit 20 electrically connects the second light-emitting element D2 to the pixel driving circuit 10 in response to its control terminal c receiving a first level signal, so that the pixel driving circuit 10 drives the second light-emitting element D2 to emit light, and disconnects the electrical connection between the second light-emitting element D2 and the pixel driving circuit 10 in response to its control terminal c receiving a second level signal, so that the second light-emitting element D2 is in a non-luminous state.

[0092] The inventors of this application are aware of the imperfections of conventional privacy-prevention solutions. For example, privacy films can cause a significant decrease in the brightness of the display screen, and the actual privacy-prevention effect may be positively correlated with the thickness of the privacy film. However, the thicker the privacy film, the more severe the impact on the brightness of the display screen. In addition, privacy films can generally only limit the viewing angle of viewers in the areas on both sides of the display device, and the degree of protection for the privacy of the display screen is limited. Utilizing the pixel circuit provided in the embodiments of this application, for display products that require privacy-prevention functionality, another optical structure can be used to replace the privacy film in conventional privacy-prevention solutions, thereby alleviating or avoiding the aforementioned defects caused by the use of privacy films.

[0093] It can be understood that, based on the connection relationship and function between the switching circuit or reset circuit and other circuits or components in the pixel circuit described above, there may be various specific implementations of the switching circuit or reset circuit. Figures 2a, 2b and 2c show examples of different implementations of the switching circuit and reset circuit. As shown in Figure 2a,

[0094] The switching circuit includes a first transistor T1, a first terminal a of the switching circuit includes a first electrode of the first transistor T1, a second terminal b of the switching circuit includes a second electrode of the first transistor T1, and a control terminal c of the switching circuit includes a control electrode of the first transistor T1. The first electrode of the first transistor T1 is electrically connected to the first electrode (e.g., anode) of the first light-emitting element D1, the second electrode of the first transistor T1 is electrically connected to the first electrode (e.g., anode) of the second light-emitting element D2, the control electrode of the first transistor T1 is configured to receive the aforementioned first level signal or second level signal, and the second electrode (e.g., cathode) of the first light-emitting element D1 and the second electrode (e.g., cathode) of the second light-emitting element D2 are electrically connected to the second reference voltage terminal Vss. Referring next to FIG. 2a , the reset circuit includes a second transistor T2, a first electrode of the second transistor T2 is electrically connected to the first electrode of the second light-emitting element D2, a second electrode of the second transistor T2 is electrically connected to the reference voltage connection terminal Vref1, and the control electrode of the second transistor T2 is electrically connected to the reset control terminal rc. That is, in the example of FIG. 2 a , the first light emitting element D1 and the second light emitting element D2 are connected in parallel to each other via the first transistor T1 , and the second transistor T2 in the reset circuit is electrically connected to the first electrode of the first light emitting element D1 .

[0095] The switching circuit in the pixel circuit shown in FIG2b is the same as that in the example of FIG2a , but the connection method of the second transistor in the reset circuit is different from that in the example of FIG2a . As shown in FIG2b , the reset circuit includes a second transistor T2 , a first electrode of which is electrically connected to the first electrode of the first light-emitting element D1 , a second electrode of which is electrically connected to the reference voltage terminal Vref1 , and a control electrode of which is electrically connected to the reset control terminal rc . As discussed below in more specific embodiments of the pixel circuit, the embodiments of FIG2a and FIG2b have different requirements for setting the control signals for the pixel circuit.

[0096] In the embodiment shown in FIG2 c , the reset circuit includes a third transistor T3 and a fourth transistor T4, which are connected in series between the first electrode of the first light-emitting element D1 and the first electrode of the second light-emitting element D2. The second electrode of the first light-emitting element D1 and the second electrode of the second light-emitting element D2 are electrically connected to the second reference voltage terminal Vss. A first node N1 between the third transistor T3 and the fourth transistor T4 is electrically connected to the reference voltage connection terminal Vref1 to receive the aforementioned first reference voltage. The control electrode of the third transistor T3 and the control electrode of the fourth transistor T4 are electrically connected to the reset control terminal rc. In this embodiment, the switching circuit includes a first transistor T5. The first terminal a of the switching circuit includes the first electrode of the fifth transistor T5, the second terminal b of the switching circuit includes the second electrode of the fifth transistor T5, and the control terminal c of the switching circuit includes the control electrode of the fifth transistor T5. The first electrode of the fifth transistor T5 is electrically connected to the pixel driving circuit 10, and the second electrode b of the fifth transistor T5 is electrically connected to the second light-emitting element D2.

[0097] Next, the specific implementation of the pixel circuit proposed in the embodiment of the present application is further described in detail through other examples.

[0098] FIG3 shows a schematic diagram of a pixel circuit provided according to an embodiment of the present application. As shown in FIG3 , the pixel circuit includes a pixel driving circuit, a reset circuit, a switching circuit, a first light-emitting element D1, and a second light-emitting element D2. The switching circuit includes a first transistor T1, and the reset circuit includes a second transistor T2. The pixel driving circuit includes a driving transistor Td, a sixth transistor T6, a seventh transistor T7, and a power supply voltage terminal VDD for receiving a power supply voltage. The seventh transistor T7, the driving transistor Td, and the sixth transistor T6 are sequentially connected in series between the power supply voltage terminal VDD and the first electrode of the first light-emitting element D1. The pixel driving circuit also includes an eighth transistor T8. The first electrode of the eighth transistor T8 is electrically connected to a third node N3 between the driving transistor Td and the seventh transistor T7. The second electrode of the eighth transistor T8 is electrically connected to a third reference voltage terminal Vref3. The control electrode of the eighth transistor T8 is electrically connected to the reset control terminal.

[0099] Optionally, as shown in Figure 3, in some embodiments, the pixel driving circuit may further include a ninth transistor T9, a tenth transistor T10, a capacitor C and a fourth reference voltage terminal Vref4, the capacitor C, the ninth transistor T9 and the tenth transistor T10 are sequentially connected in series between the power supply voltage terminal VDD and the fourth reference voltage terminal Vref4, the control electrode of the driving transistor Td is electrically connected to a fourth node N4 between the capacitor C and the ninth transistor, the control electrode of the tenth transistor T10 is electrically connected to the reset control terminal, and the control electrode of the ninth transistor T9 is used to receive the first scan signal Gate_N.

[0100] As shown in Figure 3, in some embodiments, the pixel driving circuit may further include an eleventh transistor T11 and a twelfth transistor T12, the first electrode and the second electrode of the eleventh transistor T11 are respectively electrically connected to the second node N2 between the driving transistor Td and the sixth transistor T6, and the fifth node N5 between the ninth transistor T9 and the tenth transistor T10, the first electrode of the twelfth transistor T12 is used to receive the data signal Vdata, the second electrode of the twelfth transistor T12 is electrically connected to the third node N3, and the control electrode of the eleventh transistor T11 and the control electrode of the twelfth transistor T12 are used to receive the second scan signal Gate_P.

[0101] In the example of FIG. 3 , the first light-emitting element D1 and the second light-emitting element D2 may include organic light-emitting diodes (OLEDs). The cathodes of the first light-emitting element D1 and the second light-emitting element D2 are electrically connected to a second reference voltage terminal VSS. The anode of the first light-emitting element D1 is electrically connected to the first electrode of the first transistor T1. The anode of the second light-emitting element D2 is electrically connected to the second electrode of the first transistor T1 and the first electrode of the second transistor T2. The second electrode of the second transistor T2 is electrically connected to a reference voltage terminal Vref1 to receive a first reference voltage. The control electrode of the first transistor T1 is configured to receive a control signal EM2, and the control electrode of the second transistor T2 is configured to receive a reset control signal Re_P. The second reference voltage of the second reference voltage terminal VSS may be a ground voltage of the pixel circuit. The first reference voltage received from the first reference voltage terminal Vref1 may be a constant negative voltage lower than the second reference voltage. When the first transistor T1 and the second transistor T2 are turned on under the control of corresponding control signals, the first reference voltage can reset the anodes of the first light-emitting element D1 and the second light-emitting element D2. In other words, the anodes of the first light-emitting element D1 and the second light-emitting element D2 can form a discharge path through the second transistor T2 and the first reference voltage terminal, which can effectively improve the contrast of the display device when displaying images using this pixel circuit. The control electrode of the eighth transistor T8 is also electrically connected to the reset control terminal of the reset circuit to receive the reset control signal Re_P. The second electrode of the eighth transistor T8 receives a third reference voltage from the third reference voltage terminal Vref3, which can be a constant positive voltage higher than the second reference voltage. Utilizing the third reference voltage and the eighth transistor T8, the potential of the third node N3 can be initialized before the pixel driver circuit drives the first light-emitting element D1 and the second light-emitting element D2 to emit light. This can effectively reduce the threshold voltage drift of the driving transistor Td and promote the stability of the threshold voltage of the driving transistor Td, thereby improving flicker or afterimage phenomena when displaying images in the display device.

[0102] The ninth transistor T9 and the tenth transistor T10, connected in series between the capacitor C and the fourth reference voltage terminal Vref4, can use the fourth reference voltage to initialize the control electrodes of the capacitor C and the driving transistor Td before the pixel driving circuit drives the first light-emitting element D1 and the second light-emitting element D2 to emit light. The control electrode of the tenth transistor T10 is also electrically connected to the reset control terminal of the reset circuit to receive the reset control signal Re_P. Therefore, in the embodiment of Figure 3, the second transistor T2, the eighth transistor T8, and the tenth transistor T10 are controlled by the same signal—the reset control signal Re_P. The control electrodes of the sixth transistor T6 and the seventh transistor T7 are used to receive the control signal EM.

[0103] As can be seen from the previous introduction to the pixel circuit, the pixel circuit proposed in the embodiment of the present application can actually operate in two modes. In the first operating mode, the switching circuit disconnects the electrical connection between the second light-emitting element and the pixel driving circuit, and the pixel driving circuit only drives the first light-emitting element to emit light, and the second light-emitting element is in a non-luminous state. In the second operating mode, the switching circuit electrically connects the second light-emitting element to the pixel driving circuit. At this time, the pixel driving circuit can simultaneously drive the first light-emitting element and the second light-emitting element to emit light. The first operating mode of the pixel circuit shown in Figure 3 is explained below in conjunction with Figures 3 and 4a. Figure 4a schematically shows a timing diagram of various control signals when the pixel circuit shown in Figure 3 is in the first operating mode. As shown in Figure 4a, one frame time for the display device may include a first time period t1, a second time period t2, and a third time period t3. During a first period t1, the reset control signal Re_P is at a low level, the first scan signal Gate_N is at a high level, the second scan signal Gate_P is at a high level, the control signal EM is at a high level, and the control signal EM2 is at a low level. Accordingly, the first transistor T1, the second transistor T2, the eighth transistor T8, the ninth transistor T9, and the tenth transistor T10 are all turned on, and the sixth transistor T6, the seventh transistor T7, the eleventh transistor T11, and the twelfth transistor T12 are all turned off. As a result, the first light-emitting element D1 and the second light-emitting element D2 are both reset by the first reference voltage, causing the anodes of the first light-emitting element D1 and the second light-emitting element D2 to discharge. Furthermore, the third node N3 between the driving transistor Td and the seventh transistor T7 is initialized by the third reference voltage, and the fourth node N4 between the capacitor C and the driving transistor Td is initialized by the fourth reference voltage. Resetting or initializing the anodes of the first light-emitting element D1 and the second light-emitting element D2, the third node N3 between the driving transistor Td and the seventh transistor T7, and the fourth node N4 between the capacitor C and the driving transistor Td can help improve the image display quality of the display device. During the second period t2, the reset control signal Re_P is at a high level, the first scan signal Gate_N is at a high level, the second scan signal Gate_P is at a low level, the control signal EM is at a high level, and the control signal EM2 is at a low level. Accordingly, the first transistor T1, the eleventh transistor T11, the twelfth transistor T12, the ninth transistor T9 and the driving transistor Td are turned on, while the second transistor T2, the eighth transistor T8, the tenth transistor T10, the sixth transistor T6 and the seventh transistor T7 are turned off, and the data signal voltage Vdata is written to the third node N3 via the twelfth transistor T12.During the third period t3, the reset control signal Re_P is at a high level, the first scan signal Gate_N is at a low level, the second scan signal Gate_P is at a high level, the control signal EM is at a low level, and the control signal EM2 is at a high level. Accordingly, the sixth transistor T6, the seventh transistor T7, and the driving transistor Td are turned on, while the first transistor T1, the second transistor T2, the eighth transistor T8, the ninth transistor T9, the tenth transistor T10, the eleventh transistor T11, and the twelfth transistor T12 are all turned off. Therefore, a current path is formed from the power supply voltage terminal VDD through the seventh transistor T7, the driving transistor Td, the sixth transistor, and the first light-emitting element D1 to the second reference voltage terminal VSS. The first light-emitting element D1 emits light, while the second light-emitting element D2 does not emit light because the first transistor T1 is in the off state.

[0104] FIG4 b schematically illustrates a timing diagram of various control signals when the pixel circuit shown in FIG3 is in the second operating mode. As shown in FIG4 b , a frame time for the display device may also include a first period t1, a second period t2, and a third period t3. During the first period t1, the reset control signal Re_P is at a low level, the first scan signal Gate_N is at a high level, the second scan signal Gate_P is at a high level, the control signal EM is at a high level, and the control signal EM2 is at a low level. Accordingly, the first transistor T1, the second transistor T2, the eighth transistor T8, the ninth transistor T9, and the tenth transistor T10 are all turned on, and the sixth transistor T6, the seventh transistor T7, the eleventh transistor T11, and the twelfth transistor T12 are all turned off. Therefore, the first light-emitting element D1 and the second light-emitting element D2 are both reset by the first reference voltage, causing the anodes of the first light-emitting element D1 and the second light-emitting element D2 to discharge. In addition, the third node N3 between the driving transistor Td and the seventh transistor T7 is initialized by the third reference voltage, and the fourth node N4 between the capacitor C and the driving transistor Td is initialized by the fourth reference voltage. During the second period t2, the reset control signal Re_P is at a high level, the first scan signal Gate_N is at a high level, the second scan signal Gate_P is at a low level, the control signal EM is at a high level, and the control signal EM2 is at a low level. Accordingly, the first transistor T1, the eleventh transistor T11, the twelfth transistor T12, the ninth transistor T9 and the driving transistor Td are turned on, while the second transistor T2, the eighth transistor T8, the tenth transistor T10, the sixth transistor T6 and the seventh transistor T7 are turned off, and the data signal voltage Vdata is written to the third node N3 via the twelfth transistor T12. During the third period t3, the reset control signal Re_P is at a high level, the first scan signal Gate_N is at a low level, the second scan signal Gate_P is at a high level, the control signal EM is at a low level, and the control signal EM2 is at a low level. Accordingly, the first transistor T1, the sixth transistor T6, the seventh transistor T7, and the driving transistor Td are turned on, while the second transistor T2, the eighth transistor T8, the ninth transistor T9, the tenth transistor T10, the eleventh transistor T11, and the twelfth transistor T12 are all turned off. Therefore, a first current path is formed from the power supply voltage terminal VDD through the seventh transistor T7, the driving transistor Td, the sixth transistor, and the first light-emitting element D1 to the second reference voltage terminal VSS, and a second current path is formed from the power supply voltage terminal VDD through the seventh transistor T7, the driving transistor Td, the sixth transistor, and the second light-emitting element D2 to the second reference voltage terminal VSS. Therefore, both the first light-emitting element D1 and the second light-emitting element D2 emit light. That is, the difference between the signal timing shown in FIG4b and the signal timing shown in FIG4a lies in the control signal EM2 provided to the control electrode of the first transistor T1.For the pixel circuit shown in FIG3 , in the second operating mode, the control signal EM2 always maintains a low level, and accordingly, the first transistor T1 is always in the on state. Therefore, the pixel driving circuit drives the first light-emitting element D1 and the second light-emitting element D2 to emit light simultaneously.

[0105] In the example of FIG3 , the ninth transistor T9 is a metal oxide thin film transistor, and the first transistor T1, the second transistor T2, the driving transistor Td, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the tenth transistor T10, and the eleventh transistor T11 are all low-temperature polysilicon thin film transistors. Low-temperature polysilicon thin film transistors have the advantages of high electron mobility and fast response speed, while metal oxide thin film transistors have relatively low leakage current. In the embodiment of FIG3 , by providing the metal oxide thin film transistor T9, the stable voltage of the capacitor C can be maintained for a longer time, which provides a good basis for reducing the frame frequency of the displayed image and achieving a power saving effect.

[0106] Figure 5 schematically shows a circuit schematic diagram of a pixel circuit provided according to another embodiment of the present application. Compared with the embodiment shown in Figure 3, the reset circuit in the pixel circuit shown in Figure 5 is connected differently from the other components in the pixel circuit. As shown in Figure 5, the reset circuit includes a second transistor T2, the switching circuit includes a switching transistor T1, the first electrode of the second transistor T2 is connected to the reference voltage terminal Vref1 to receive the first reference voltage, the second electrode of the second transistor T2 is electrically connected to the anode of the first light-emitting element D1, and the second light-emitting element D2 is connected in parallel with the first light-emitting diode D1 via the first transistor T1. The pixel circuit shown in Figure 5 can also operate in the aforementioned first operating mode and second operating mode. Figure 6 schematically shows a timing diagram of various control signals when the pixel circuit shown in Figure 5 is in the first operating mode. The timing diagram of the control signals shown in Figure 6 is basically similar to the timing diagram of the control signals shown in Figure 4a, except that the control signal EM2 provided to the first transistor T1 is different. 5 and 6 , for the pixel circuit shown in FIG5 , when the pixel circuit operates in the first operating mode, the first transistor T1 can be kept in the off state at all times without affecting the resetting of the first light-emitting element D1 by the first reference voltage, nor affecting the normal light emission of the first light-emitting diode D1. Therefore, as shown in FIG6 , the control signal EM2 can be maintained at a constant high level. Compared with the situation shown in FIG4 a where a control signal EM2 with a varying level needs to be provided, the circuit for providing the control signal EM2 can be simplified. The circuit for providing the control signal for the control electrode of each transistor in the pixel circuit is usually provided in the border area of ​​the display device. Therefore, using the pixel circuit shown in FIG5 is beneficial for reducing the area of ​​the border area, thereby facilitating the realization of a narrower border for the display device.

[0107] For the pixel circuit shown in FIG5 , the timing diagram of each control signal when the pixel circuit operates in the second operating mode may be the same as that in FIG4 b , and will not be described in detail here.

[0108] FIG7 illustrates a schematic diagram of a pixel circuit provided according to another embodiment of the present application. As shown in FIG7 , the reset circuit of the pixel circuit includes a third transistor T3 and a fourth transistor T4, wherein the third transistor T3 and the fourth transistor T4 are connected in series between a first electrode (e.g., an anode) of a first light-emitting element D1 and a first electrode (e.g., an anode) of a second light-emitting element D2, wherein a second electrode of the first light-emitting element D1 and a second electrode of the second light-emitting element D2 are electrically connected to a second reference voltage terminal Vss, a first node N1 between the third transistor T3 and the fourth transistor T4 is electrically connected to a reference voltage connection terminal Vref1, and a control electrode of the third transistor T3 and a control electrode of the fourth transistor T4 are electrically connected to a reset control terminal to receive a reset control signal Re_P. The switching circuit of the pixel circuit includes a fifth transistor T5, wherein a first terminal of the switching circuit includes a first electrode of the fifth transistor T5, a second terminal of the switching circuit includes a second electrode of the fifth transistor T5, and a control terminal of the switching circuit includes the control electrode of the fifth transistor T5. The pixel driving circuit includes a driving transistor Td, a sixth transistor T6, and a power supply voltage terminal VDD for receiving a power supply voltage. The driving transistor Td and the sixth transistor T6 are connected in series between the power supply voltage terminal VDD and the first electrode of the first light-emitting element D1. The first electrode of the fifth transistor T5 is electrically connected to the second node N2 between the driving transistor Td and the sixth transistor T6, and the second electrode of the fifth transistor T5 is electrically connected to the first electrode of the second light-emitting element. For example, the first electrode of the fifth transistor can be electrically connected to the first electrode (e.g., the source) of the sixth transistor or the second electrode (e.g., the drain) of the sixth transistor. The pixel driving circuit may further include a seventh transistor T7, which is connected in series between the power supply voltage terminal VDD and the driving transistor Td. The pixel driving circuit may further include an eighth transistor T8, whose first electrode is electrically connected to a third node N3 between the driving transistor Td and the seventh transistor T7, whose second electrode is electrically connected to a third reference voltage terminal Vref3 to receive the third reference voltage, and whose control electrode is electrically connected to a reset control terminal to receive a reset control signal Re_P. The control electrodes of the sixth transistor T6 and the seventh transistor T7 both receive the control signal EM. The control electrode of the fifth transistor T5 receives the control signal EM2.Furthermore, the pixel driving circuit may further include a ninth transistor T9, a tenth transistor T10, a capacitor C, and a fourth reference voltage terminal Vref4, wherein the capacitor C, the ninth transistor T9, and the tenth transistor T10 are sequentially connected in series between the power supply voltage terminal VDD and the fourth reference voltage terminal Vref4, the control electrode of the driving transistor Td is electrically connected to a fourth node N4 between the capacitor C and the ninth transistor, the control electrode of the tenth transistor T10 is electrically connected to the reset control terminal to receive a reset control signal Re_P, and the control electrode of the ninth transistor T9 is used to receive a first scan signal Gate_N. Furthermore, the pixel driving circuit also includes an eleventh transistor T11 and a twelfth transistor T12, the first electrode and the second electrode of the eleventh transistor T11 are respectively electrically connected to the second node N2 between the driving transistor Td and the sixth transistor T6, and the fifth node N5 between the ninth transistor T9 and the tenth transistor T10, the first electrode of the twelfth transistor T12 is used to receive the data signal Vdata, the second electrode of the twelfth transistor T12 is electrically connected to the third node N3, and the control electrode of the eleventh transistor T11 and the control electrode of the twelfth transistor T12 are used to receive the second scan signal Gate_P.

[0109] In the embodiment shown in FIG7 , the ninth transistor T9 is a metal oxide thin film transistor, and the other transistors can all be low-temperature polysilicon thin film transistors. The eighth transistor T8 and the ninth transistor T9 in the pixel circuit shown in FIG7 can achieve similar technical advantages as the eighth transistor and the ninth transistor in the embodiments shown in FIG3 and FIG5 , and will not be further described here.

[0110] The pixel circuit shown in FIG7 can operate in a first operating mode and a second operating mode. In the first operating mode, the pixel driving circuit only drives the first light-emitting element D1 to emit light. In the second operating mode, the pixel driving circuit drives the first light-emitting element D1 and the second light-emitting element 2 to emit light at the same time.

[0111] The following describes the process of the pixel circuit shown in FIG7 in the first operating mode with reference to FIG7 and FIG8a. FIG8a shows a timing diagram of various control signals when the pixel circuit shown in FIG7 is in the first operating mode. As shown in FIG8a, a frame time for the display device may include a first period t1, a second period t2, and a third period t3. During the first period t1, the reset control signal Re_P is at a low level, the first scan signal Gate_N is at a high level, the second scan signal Gate_P is at a high level, the control signal EM and the control signal EM2 are at a high level, and accordingly, the third transistor T3, the fourth transistor T4, the eighth transistor T8, the ninth transistor T9 and the tenth transistor T10 are all turned on, and the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eleventh transistor T11 and the twelfth transistor T12 are all turned off. Therefore, the first light-emitting element D1 and the second light-emitting element D2 are both reset by the first reference voltage provided by the reference voltage terminal Vref1, so that the anodes of the first light-emitting element D1 and the second light-emitting element D2 are discharged, the third node N3 between the driving transistor Td and the seventh transistor T7 is initialized by the third reference voltage, and the fourth node N4 between the capacitor C and the driving transistor Td is initialized by the fourth reference voltage. Resetting or initializing the anodes of the first and second light-emitting elements D1 and D2, the third node N3 between the driving transistor Td and the seventh transistor T7, and the fourth node N4 between the capacitor C and the driving transistor Td can help improve the image quality of the display device. For example, resetting the first and second light-emitting elements D1 and D2 using the first reference voltage can improve the contrast of the image displayed by the display device, and resetting or initializing the third node N3 using the third reference voltage via the eighth transistor T8 can help maintain the stability of the threshold voltage of the driving transistor Td. During the second period t2, the reset control signal Re_P is at a high level, the first scan signal Gate_N is at a high level, the second scan signal Gate_P is at a low level, the control signal EM is at a high level, and the control signal EM2 remains at a high level. Accordingly, the eleventh transistor T11, the twelfth transistor T12, the ninth transistor T9 and the driving transistor Td are turned on, while the third transistor T3, the fourth transistor T4, the fifth transistor T5, the eighth transistor T8, the tenth transistor T10, the sixth transistor T6 and the seventh transistor T7 are turned off, and the data signal voltage Vdata is written to the third node N3 via the twelfth transistor T12.During the third period t3, the reset control signal Re_P is at a high level, the first scan signal Gate_N is at a low level, the second scan signal Gate_P is at a high level, the control signal EM is at a low level, and the control signal EM2 is at a high level. Accordingly, the sixth transistor T6, the seventh transistor T7, and the driving transistor Td are turned on, while the third transistor T3, the fourth transistor T4, the fifth transistor T5, the eighth transistor T8, the ninth transistor T9, the tenth transistor T10, the eleventh transistor T11, and the twelfth transistor T12 are all turned off. Therefore, a current path is formed from the power supply voltage terminal VDD through the seventh transistor T7, the driving transistor Td, the sixth transistor, and the first light-emitting element D1 to the second reference voltage terminal VSS. The first light-emitting element D1 emits light, while the second light-emitting element D2 does not emit light because the fifth transistor T5 is in the off state.

[0112] FIG8 b is a timing diagram of various control signals when the pixel circuit shown in FIG7 is in the second operating mode. As shown in FIG8 b , a frame time for the display device may include a first period t1, a second period t2, and a third period t3. During the first period t1, the reset control signal Re_P is at a low level, the first scan signal Gate_N is at a high level, the second scan signal Gate_P is at a high level, and the control signals EM and EM2 are at a high level. Accordingly, the third transistor T3, the fourth transistor T4, the eighth transistor T8, the ninth transistor T9, and the tenth transistor T10 are all turned on, and the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eleventh transistor T11, and the twelfth transistor T12 are all turned off. Therefore, the first light-emitting element D1 and the second light-emitting element D2 are both reset by the first reference voltage provided by the reference voltage terminal Vref1, causing the anodes of the first light-emitting element D1 and the second light-emitting element D2 to discharge. The third node N3 between the driving transistor Td and the seventh transistor T7 is initialized by the third reference voltage, and the fourth node N4 between the capacitor C and the driving transistor Td is initialized by the fourth reference voltage. Resetting or initializing the anodes of the first and second light-emitting elements D1 and D2, the third node N3 between the driving transistor Td and the seventh transistor T7, and the fourth node N4 between the capacitor C and the driving transistor Td can help improve the image quality of the display device. For example, resetting the first and second light-emitting elements D1 and D2 using the first reference voltage can improve the contrast of the image displayed by the display device, and resetting or initializing the third node N3 using the third reference voltage via the eighth transistor T8 can help maintain the stability of the threshold voltage of the driving transistor Td. During the second period t2, the reset control signal Re_P is at a high level, the first scan signal Gate_N is at a high level, the second scan signal Gate_P is at a low level, the control signal EM is at a high level, and the control signal EM2 remains at a high level. Accordingly, the eleventh transistor T11, the twelfth transistor T12, the ninth transistor T9 and the driving transistor Td are turned on, while the third transistor T3, the fourth transistor T4, the fifth transistor T5, the eighth transistor T8, the tenth transistor T10, the sixth transistor T6 and the seventh transistor T7 are turned off, and the data signal voltage Vdata is written to the third node N3 via the twelfth transistor T12.During the third period t3, the reset control signal Re_P is at a high level, the first scan signal Gate_N is at a low level, the second scan signal Gate_P is at a high level, the control signal EM is at a low level, and the control signal EM2 is at a low level. Accordingly, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the driving transistor Td are turned on, while the third transistor T3, the fourth transistor T4, the eighth transistor T8, the ninth transistor T9, the tenth transistor T10, the eleventh transistor T11, and the twelfth transistor T12 are all turned off. Therefore, a first current path from the power supply voltage terminal VDD through the seventh transistor T7, the driving transistor Td, the sixth transistor T6, and the first light-emitting element D1 to the second reference voltage terminal VSS is formed, and a second current path from the power supply voltage terminal VDD through the seventh transistor T7, the driving transistor Td, the fifth transistor T5, and the second light-emitting element D2 to the second reference voltage terminal VSS is formed. Therefore, the first light-emitting element D1 and the second light-emitting element D2 both emit light. That is, compared to the signal timing diagram shown in FIG8a , the timing of the reset control signal Re_P, the first scan signal Gate_N, the second scan signal Gate_P, and the control signal EM shown in FIG8b is the same as that shown in FIG8a , with the difference being the control signal EM2 shown in FIG8b . During the first period t1 and the second period t2, the control signal EM2 remains at a high level, and therefore the fifth transistor T5 remains off during the first period t1 and the second period t2. However, this does not affect the resetting of the first light-emitting element D1, the second light-emitting element D2, and the third and fourth nodes N3 and N4, or the writing of the data signal voltage Vdata. During the third period t3, the control signal EM2 is at a low level, turning on the fifth transistor T5. At this point, the pixel circuit effectively includes two current conduction paths, thereby causing the first light-emitting element D1 and the second light-emitting element D2 to emit light simultaneously.

[0113] The pixel driving circuit in the pixel circuit provided in each embodiment of the present application is not limited to the specific implementation manner described above with reference to Figures 3, 5 and 7. For example, the ninth transistor T9 (metal oxide thin film transistor) in Figures 3, 5 and 7 can be removed so that the type of transistor in the pixel circuit only includes low-temperature polycrystalline thin film transistors. Alternatively, the schematic diagram of the pixel circuit shown in Figures 3, 5 and 7 can be modified or modified. For example, for the pixel circuit shown in Figure 3, the ninth transistor T9 can be omitted, and the tenth transistor T10, the eleventh transistor T11, the eighth transistor T8, the twelfth transistor T12 and the second transistor T2 can be changed to metal oxide semiconductor transistors, thereby obtaining the schematic diagram of the pixel circuit shown in Figure 9.

[0114] The pixel circuits provided in the embodiments of the present application can be applied to display panels and display devices. Therefore, another embodiment of the present application provides a display panel, which may include a substrate and a plurality of pixel circuits, each of which may be a pixel circuit described in any of the aforementioned embodiments. The plurality of pixel circuits may be arranged in an array on the substrate to form a pixel circuit array.

[0115] In some embodiments, a display panel includes a first reference voltage line located on a base substrate. The first reference voltage line is electrically connected to a reference voltage terminal of a pixel circuit to transmit the aforementioned first reference voltage. Two adjacent pixel circuits in a pixel circuit array share the first reference voltage line, and the two adjacent pixel circuits are symmetrically arranged on either side of the first reference voltage line. Figure 10 schematically illustrates a top perspective view of a portion of the layer structure comprising two adjacent pixel circuits in the pixel circuit array. The first reference voltage line is labeled VL1 in Figure 10. Each pixel circuit may include a multilayer structure located on the base substrate, such as a semiconductor layer, an insulating layer, and various conductive layers. The symmetrical arrangement of the two adjacent pixel circuits on either side of the first reference voltage line means that the patterns of the various layers comprising the two adjacent pixel circuits are arranged symmetrically about the first reference voltage line. Furthermore, the first reference voltage line is shared by the two adjacent pixel circuits, meaning that the first reference voltage line transmits the first reference voltage to both adjacent pixel circuits. This symmetrical layout design allows for a compact arrangement of the components of each pixel circuit on the base substrate, saving component layout space on the base substrate, and facilitating improved resolution and smaller display devices.

[0116] Next, the structure of the display panel including the pixel circuit provided in the embodiment of the present application is further explained through more specific examples.

[0117] In some embodiments, the first reference voltage line includes a first portion and a second portion, wherein the first portion extends in the column direction of the pixel circuit array, and the second portion extends in the row direction of the pixel circuit array, and the first portion and the second portion intersect, wherein two adjacent pixel circuits are symmetrically arranged on either side of the first portion. For example, FIG10 illustrates a first portion P1 and a second portion P2 of a first reference voltage line VL1, wherein the first portion P1 extends in the column direction of the pixel circuit array, and the second portion P2 extends in the row direction of the pixel circuit array and passes through one end of the first portion P1. In FIG10, the first portion P1 and the second portion P2 intersect at point C. In some embodiments, the first portion and the second portion of the first reference voltage line in each pixel circuit in the pixel circuit array intersect with each other, such that the first reference voltage lines in the display panel as a whole form a grid-like structure.

[0118] The partial top perspective view shown in FIG10 may correspond to the pixel circuit shown in FIG3 . FIG10 schematically illustrates the approximate positions of the first transistor T1, the second transistor T2, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, the eleventh transistor T11, and the driving transistor Td in the pixel circuit shown in FIG3 . The patterns on either side of the first portion P1 of the first reference voltage line VL1 in FIG12 represent the layout of the partial layer structures of two adjacent pixel circuits, respectively. The partial layer structures of the two adjacent pixel circuits are symmetrical about the first portion P1 of the first reference voltage line VL1 . Reference numeral T10′ in FIG10 represents the partial pattern of the tenth transistor in another pixel circuit adjacent to the pixel circuit to the left of the first portion P1 in a direction consistent with the extension direction of the first portion P1.

[0119] Taking the pixel circuit shown in FIG3 as an example, some main layer structures included in the pixel circuit are separately described in an illustrative manner.

[0120] In some embodiments, the display panel includes a light shielding layer located on a base substrate, and the light shielding layer can be formed of an opaque metal material. The light shielding layer can include a plurality of light shielding blocks and a light shielding strip connecting the light shielding blocks as a whole. Each light shielding block can correspond to a pixel circuit, and the light shielding blocks are electrically connected to each other via the light shielding strip and have the same potential when the display panel is in operation. Figure 11 shows an example of a partial pattern of the light shielding layer. The pattern of the light shielding layer shown in Figure 11 can be used for two pixel circuits adjacent in the row direction in the pixel circuit array. As shown in Figure 11, the light shielding layer can include a first light shielding block BL1 and a second light shielding block BL2. The light shielding layer can shield the pixel circuit from a portion of light that may enter the display panel from the back side opposite to the display surface of the display panel. In particular, the first light shielding block BL1 and the second light shielding block BL2 can respectively shield a portion of light for the driving transistors in the two adjacent pixel circuits, thereby facilitating the stabilization of the performance of the driving transistor Td in the pixel circuit.

[0121] Figure 12 schematically illustrates a partial top view of a semiconductor layer located on a substrate. The semiconductor layer shown in Figure 12 is for the two adjacent pixel circuits in the pixel circuit array. The semiconductor layer can be located on the side of the light shielding layer facing away from the substrate. As can be seen in Figure 12, the semiconductor layers of the two adjacent pixel circuits also exhibit a symmetrical arrangement, with the axis of symmetry (indicated by the dashed line in Figure 12) actually being the first portion P1 of the aforementioned first reference voltage line VL1. The semiconductor layer shown in Figure 12 may include the active layer, first electrode, and second electrode (source and drain) of each transistor in the pixel circuit shown in Figure 3. Figure 12 also uses reference numerals T1, T2, and Td to indicate the approximate locations of the active layers of each transistor in the pixel circuit shown in Figure 3. As can be seen in Figure 12, at least the active layers of the first transistor T1, the second transistor T2, and the sixth transistor T6 are interconnected to form a single unit. The patterns of the semiconductor layers on either side of the dashed line in Figure 12 are symmetrical about the dashed line, respectively representing the active layer, first electrode, and second electrode of each transistor in the two adjacent pixel circuits in a first direction perpendicular to the dashed line. Reference mark T10 in Figure 12 indicates the position of the active layer of the tenth transistor in the pixel circuit on the left side of the dotted line, and reference mark T10′ indicates a portion of the pattern of the active layer, first electrode and second electrode of the tenth transistor in another pixel circuit adjacent to the pixel circuit on the left side of the dotted line in a direction consistent with the dotted line.

[0122] As described above, the switching circuit in the pixel circuit may include a first transistor T1, the first end of the switching circuit includes the first electrode of the first transistor, the second end of the switching circuit includes the second electrode of the first transistor, the control end of the switching circuit includes the control electrode of the first transistor, the reset circuit includes a second transistor T2, the first electrode of the second transistor T2 is electrically connected to the first electrode of the first light-emitting element or the second light-emitting element, the second electrode of the second transistor T2 is electrically connected to the reference voltage connection terminal, and the control electrode of the second transistor T2 is electrically connected to the reset control terminal rc, wherein the pixel driving circuit includes a driving transistor Td, a sixth transistor T6 and a power supply voltage terminal VDD for receiving a power supply voltage, and the driving transistor Td and the sixth transistor T6 are connected in series between the power supply voltage terminal VDD and the first electrode of the first light-emitting element D1. In some embodiments, the display panel further includes a first gate metal layer located on the substrate, the first gate metal layer including a first gate metal line, a second gate metal line, and a third gate metal line extending along the row direction of the pixel circuit array and spaced apart from each other in the column direction of the pixel circuit array, wherein the first gate metal line includes the gate of the first transistor T1, the second gate metal line includes the gate of the second transistor T2, and the third gate metal line includes the gate of the sixth transistor T6, and the first gate metal line is located between the second gate metal line and the third gate metal line. Figure 13 shows a partial top view of the first gate metal layer, and the pattern of the first gate metal layer shown in Figure 13 corresponds to the first gate metal layer in the two adjacent pixel circuits described above. The first gate metal layer includes a first gate metal line GL1, a second gate metal line GL2, and a third gate metal line GL3, which are spaced apart from each other in the column direction of the pixel circuit array and extend along the row direction of the pixel circuit array. The first gate metal line GL1 may include the gate of the first transistor T1 in the pixel circuit shown in FIG3 , the second gate metal line GL2 may include the gate of the second transistor T2 in FIG3 , and the third gate metal line GL3 may include the gate of the sixth transistor T6 in the pixel circuit shown in FIG3 . By designing the layout of the pattern of the first gate metal layer, the layout space occupied by the reset circuit and switching circuit in the pixel circuit on the substrate can be reduced, which helps to reduce the area occupied by a single pixel circuit on the substrate. It can be understood that the first gate metal line GL1, the second gate metal line GL2, and the third gate metal line GL3 may each include a gate connection line electrically connected to the gate of the corresponding transistor.In some embodiments, the first gate metal line GL1 further includes a gate connection line electrically connected to the gate of the first transistor T1, the second gate metal line GL2 further includes the gate of the eighth transistor T8 and the gate of the tenth transistor T10 in the pixel circuit shown in FIG3 , and the corresponding gate connection line, and the third gate metal line GL3 further includes the gate of the seventh transistor T7 in the pixel circuit shown in FIG3 and the corresponding gate connection line. In the embodiment shown in FIG13 , the first gate metal layer further includes a fourth gate metal line GL4, which includes the gates of the eleventh transistor T11 and the twelfth transistor T12 in FIG3 , and the corresponding gate connection line. As can be seen from FIG13 , the first gate metal layers of two adjacent pixel circuits also present a symmetrical arrangement, and the axis of symmetry (shown by the dotted line in FIG13 ) is actually the aforementioned first reference voltage line VL1.

[0123] As previously described, in some embodiments, the pixel driving circuit further includes a ninth transistor T9, a tenth transistor T10, a capacitor C, and a fourth reference voltage terminal Vref4, wherein the capacitor C, the ninth transistor T9, and the tenth transistor T10 are sequentially connected in series between the power supply voltage terminal VDD and the fourth reference voltage terminal Vref4, the control electrode of the driving transistor Td is electrically connected to a fourth node N4 between the capacitor C and the ninth transistor, the control electrode of the tenth transistor T10 is electrically connected to the reset control terminal, and the control electrode of the ninth transistor T9 is configured to receive a first scanning signal. The first gate metal layer may further include gates of the driving transistors. For example, FIG13 illustrates gates GB1 and GB2 of the driving transistors Td used in the two adjacent pixel circuits described above.

[0124] Figure 14 shows a perspective view of the first gate metal layer and semiconductor layer in the pixel circuit after being superimposed together. Figure 14 includes the first gate metal line GL1, the second gate metal line GL2, the third gate metal line GL3, the fourth gate metal line GL4, the gates GB1 and GB2 shown in Figure 13. GL2′ in Figure 14 represents the second gate metal line in the first gate metal layer of the pixel circuit adjacent to the pixel circuit in Figure 14 in the direction of extension of the aforementioned symmetry axis. Figure 14 similarly shows the approximate positions of the first transistor T1, the second transistor T2, the driving transistor Td, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the tenth transistor T10, the eleventh transistor T11, and the twelfth transistor T12 in the pixel circuit shown in Figure 3. T10′ represents the approximate position of the tenth transistor in another pixel circuit adjacent to the pixel circuit on the left side of the symmetry axis in a direction consistent with the extension direction of the symmetry axis. As shown in FIG14 , the semiconductor layers of the seventh transistor T7 and the twelfth transistor T12 (i.e., the active layer, the first electrode, and the second electrode of the transistor) are connected to each other. FIG14 also shows a node of the semiconductor layer corresponding to the third node N3 in FIG3 . FIG14 also shows two connection nodes CD1 and CD2 in the semiconductor layer of the pixel circuit, which are electrically connected to the first light-emitting element D1 and the second light-emitting element D2 in the pixel circuit shown in FIG3 , respectively.

[0125] In some embodiments, the display panel may further include a second gate metal layer located on a side of the first gate metal layer facing away from the base substrate. FIG15 shows a pattern of the second gate metal layer for the two adjacent pixel circuits described above. As shown in FIG15 , the second gate metal layer includes capacitor electrode blocks CB1 and CB2 and bottom gates BG1 and BG2 of the ninth transistor T9. The orthographic projection of the capacitor electrode block CB1 or CB2 on the base substrate and the orthographic projection of the gate GB1 or GB2 of the driving transistor on the base substrate at least partially overlap to form the aforementioned capacitor C. The capacitor electrode blocks CB1 and CB2 include openings penetrating the capacitor electrode blocks, as shown by O1 or O2 in FIG15 . The orthographic projection of the opening O1 or O2 on the base substrate is located within the orthographic projection of the gate GB1 or GB2 of the driving transistor on the base substrate. In this embodiment, the ninth transistor T9 is a dual-gate metal oxide thin film transistor. The bottom gate of the ninth transistor T9 and the capacitor electrode block can be obtained by patterning the same metal layer to form the pattern of the second gate metal layer as shown in FIG15 . The opening in the capacitor electrode block can facilitate the gate of the driving transistor to be electrically connected to other components in the pixel circuit (for example, the ninth transistor T9 shown in Figure 3) through the opening. It can be understood that the display panel also includes an insulating layer between the first gate metal layer and the second gate metal layer and in the above-mentioned opening. For the sake of simplicity, it is not described in detail here. The second gate metal layer shown in Figure 15 also includes a third reference voltage line VL3 for electrically connecting to the third reference voltage terminal Vref3 in Figure 3 to transmit a third reference voltage. As can be seen from Figure 15, the second gate metal layers of the two adjacent pixel circuits also present a symmetrical arrangement, and the axis of symmetry (as shown by the dotted line in Figure 15) is actually the aforementioned first reference voltage line VL1.

[0126] In some embodiments, the display panel further includes a third gate metal layer, the third gate metal layer including the top gate of the ninth transistor T9 and a fourth reference voltage line, the fourth reference voltage line being electrically connected to the fourth reference voltage terminal Vref4 in the pixel circuit to transmit the fourth reference voltage. The top gate and bottom gate of the ninth transistor T9 may be located on opposite sides of the metal oxide semiconductor channel, respectively. FIG16 illustrates the pattern of the metal oxide semiconductor channel of the ninth transistor T9 in two adjacent pixel circuits, and FIG17 illustrates the third gate metal layer in the two adjacent pixel circuits. The third gate metal layer includes the top gates TG1 and TG2 of the ninth transistor T9 in the two adjacent pixel circuits and the fourth reference voltage line VL4. As can be seen from FIG17, the patterns of the third gate metal layers of the two adjacent pixel circuits also present a symmetrical arrangement, with the axis of symmetry (shown by the dotted line in FIG17 ) actually being the aforementioned first reference voltage line VL1.

[0127] According to some embodiments of the present application, the orthographic projection of the fourth reference voltage line VL4 in the third gate metal layer on the substrate can at least partially overlap with the orthographic projection of the first gate metal line GL1 or the third gate metal line GL3 in the first gate metal layer on the substrate. This can improve the light transmittance of the display panel and enhance the image quality of the display panel. Although the first gate metal line GL1 or the third gate metal line GL3 can transmit the light emission control signal EM to the gate of the sixth transistor and the gate of the seventh transistor, the fourth reference voltage line VL4 is used to transmit a fourth reference voltage having a constant voltage. Therefore, the fourth reference voltage line VL4 has a smaller impact on the light emission control signal line that transmits the control signal EM.

[0128] Figure 18 illustrates a top perspective view of the superposition of the second gate metal layer shown in Figure 15, the metal oxide semiconductor channel of the ninth transistor shown in Figure 16, and the third gate metal layer shown in Figure 17. The approximate position of the ninth transistor in the pixel circuit shown in Figure 3 is shown as T9 in Figure 18.

[0129] According to some embodiments of the present application, the display panel further includes a source-drain metal layer located on the side of the third gate metal layer facing away from the substrate, the source-drain metal layer including the first reference voltage line mentioned in the aforementioned embodiments, and the first electrode or the second electrode (i.e., the source or the drain) of the second transistor T2 in the two adjacent pixel circuits is electrically connected to the first reference voltage line via a first via located at the intersection of the first part P1 and the second part P2 of the first reference voltage line. Figure 19 illustrates a partial top view of the source-drain metal layer in a display panel according to an embodiment of the present application. As mentioned above, the first electrode and the second electrode (source or drain) of the other transistors except the ninth transistor T9 in the pixel circuit shown in Figure 3 are located in the aforementioned semiconductor layer, and the above-mentioned first via can pass through the insulating layer provided between the semiconductor layer and the source-drain metal layer, and the position of the first via can correspond to the intersection C of the first part P1 and the second part P2 of the first reference voltage line (as shown in Figure 19). That is, the two second transistors T2 included in the two adjacent pixel circuits shown in Figure 3 are both electrically connected to the first reference voltage line via the above-mentioned first via, thereby reducing the complexity of the component layout in all pixel circuits of the display panel and saving the space occupied by the pixel circuit on the substrate. In addition to the first reference voltage line, the source-drain metal layer also includes multiple source-drain connection lines. These source-drain connection lines are used to electrically connect the first electrode or the second electrode of each transistor in the various transistors shown in Figure 3 to other transistors or electrical components. For example, Figure 19 illustrates multiple connection pads pad1, pad2, pad3, pad4 and pad5, and multiple connection lines NL1, NL2, NL3 and NL4. Referring to Figures 3 and 19, the connection pad pad1 is used to electrically connect the ninth transistor T9 and the tenth transistor T10, the connection pad pad2 is electrically connected to the twelfth transistor T12 for receiving the data signal voltage, the connection pads pad3 and pad4 serve as transfer connection pads, respectively realizing the electrical connection between the first light-emitting element D1 and the second light-emitting element D2 and the corresponding transistors, and the connection pad pad5 is electrically connected to the eighth transistor T8 to receive the third reference voltage. The connection lines NL1, NL2, NL3, and NL4 in FIG19 respectively represent the connection line for the fourth node N4 in FIG3 , the connection line for the power supply voltage terminal VDD, the connection line for the third node N3, and the connection line for the fourth reference voltage terminal vref4. As can be seen from FIG19 , the patterns of the source and drain metal layers of two adjacent pixel circuits also present a symmetrical arrangement. In this embodiment, the axis of symmetry is the first portion P1 of the first reference voltage line.

[0130] Figure 20 illustrates a partial top perspective view of a semiconductor layer, a first gate metal layer, a second gate metal layer, a metal oxide semiconductor channel of a ninth transistor in a pixel circuit, a third gate metal layer, and a source / drain metal layer stacked together in a display panel according to some embodiments of the present application. Compared to Figure 10 , Figure 20 does not illustrate the light shielding layer on the base substrate of the display panel. However, Figure 20 illustrates the approximate position of the tenth transistor T10 in the pixel circuit shown in Figure 3 .

[0131] According to some embodiments of the present application, the display panel further includes a power line metal layer, the power line metal layer including a power line electrically connected to a power supply voltage terminal VDD of a pixel circuit to transmit a power supply voltage. The power line includes a first conductive block, which is shared by two adjacent pixel circuits in the pixel circuit array. The orthographic projection of the first conductive block on the substrate overlaps and exceeds the orthographic projections of the top gate and active layer of the ninth transistor T9 in the two adjacent pixel circuits, as well as the orthographic projections of the gate and active layer of the drive transistor Td on the substrate. FIG21 illustrates an example of a pattern of a power line metal layer for two adjacent pixel circuits. As shown in FIG21 , the power line includes a first conductive block PC, which is shared by the two adjacent pixel circuits. Furthermore, the orthographic projection of the first conductive block PC on the substrate overlaps and exceeds the orthographic projections of the top gate and active layer of the ninth transistor T9 in the two adjacent pixel circuits, as well as the orthographic projections of the gate and active layer of the drive transistor Td on the substrate. Thus, in addition to transmitting the power supply voltage to two adjacent pixel circuits, the first conductive block PC in the power line can also serve to shield at least the ninth transistor T9 and the driving transistor Td from light. Specifically, the first conductive block PC in the power line can partially block external light that may enter the display panel from the display surface and reach the ninth transistor T9 and the driving transistor Td. Because the threshold voltage of the metal oxide thin film transistor T9 is sensitive to light, and changes in the threshold voltage of the driving transistor Td significantly affect the brightness uniformity of the image displayed by the display panel, the first conductive block PC helps stabilize the threshold voltages of the metal oxide thin film transistor T9 and the driving transistor Td, thereby improving the quality of the image displayed by the display panel. As shown in Figure 21, the power line metal layer may also include data lines d1 and d2 electrically connected to the twelfth transistor T12 in Figure 3. The data lines d1 and d2 respectively transmit the data signal voltage Vdata to the two adjacent pixel circuits. In some embodiments, the orthographic projection of the top gate of the ninth transistor on the substrate is located within the orthographic projection of the bottom gate of the ninth transistor on the substrate. 21 also illustrates connection pads pd1 and pd2 electrically connected to the anodes of the first and second light-emitting elements D1 and D2, respectively, shown in FIG3 .

[0132] As mentioned above, the first light-emitting element and the second light-emitting element can be organic electroluminescent diodes (OLEDs), and Figures 22 and 23 respectively illustrate a portion of the pattern of the anode layer of the first light-emitting element and the second light-emitting element included in the display panel and a portion of the pattern of the light-emitting area of ​​each light-emitting element defined by the pixel definition layer. Figure 22 shows the anodes of sixteen light-emitting elements. These sixteen light-emitting elements can be divided into eight pairs of light-emitting elements, each pair of light-emitting elements corresponding to a pixel circuit, and each pair of light-emitting elements can include the first light-emitting element and the second light-emitting element in a single pixel circuit. The anodes of these light-emitting elements are also shown in Figure 22 with labels D1 and D2, respectively. According to an embodiment of the present application, the display panel also includes a pixel definition layer for defining the light-emitting areas of the first light-emitting element and the second light-emitting element in the pixel circuit. Figure 23 schematically shows sixteen light-emitting areas corresponding to the sixteen light-emitting elements shown in Figure 22, defined by the pixel definition layer.

[0133] Figure 24 illustrates a top perspective view of the pixel definition layer, anode layer, and the aforementioned power line metal layer stacked together in a display panel. Figure 24 shows the power line metal layer for eight pixel circuits and the anode layer and pixel definition layer located on the side of the power line metal layer facing away from the substrate. Since each pixel circuit includes two light-emitting elements, the eight pixel circuits involve a total of sixteen light-emitting elements. According to some embodiments of the present application, the light-emitting elements in different pixel circuits in the display panel can emit light of different colors, for example, red, green, and blue, and accordingly, the display area of ​​the display panel includes a red pixel area, a green pixel area, and a blue pixel area. According to an embodiment of the present application, the first light-emitting element and the second light-emitting element included in the same pixel circuit emit light of the same color, and each first light-emitting element or each second light-emitting element can correspond to a separate light-emitting area. As shown in Figure 24, each pixel circuit can correspond to two separate light-emitting areas, for example, red light-emitting areas R1, R2, green light-emitting areas G1, G2, and blue light-emitting areas B1, B2. The first light-emitting element D1 and the second light-emitting element D2 in the pixel circuit shown in FIG3 may correspond to red light-emitting regions R1 and R2, or green light-emitting regions G1 and G2, and blue light-emitting regions B1 and B2, respectively. As shown in FIG24 , the first light-emitting region (e.g., red light-emitting region R1) and the second light-emitting region (e.g., red light-emitting region R2) of the first light-emitting element defined by the pixel definition layer are spaced apart and symmetrically distributed on either side of an axis of symmetry, which (as indicated by the dashed line S in FIG24 ) intersects with the extension of the first portion P1 of the first reference voltage line. The arrangement of light-emitting regions of different colors shown in FIG24 can improve the uniformity of light emission in the display panel and help improve the aperture ratio of each light-emitting region. FIG24 also shows data lines d1 and d2 in the power line metal layer for transmitting data signal voltages. In the embodiment of FIG21 , the area of ​​the blue light-emitting region is larger than that of the red light-emitting region, which in turn is larger than that of the green light-emitting region. That is, the blue light-emitting region has the largest area, while the green light-emitting region has the smallest area. However, in FIG24 , the two light-emitting elements in the same pixel circuit have light-emitting regions of substantially the same area. That is, the red light emitting regions R1 and R2 shown in FIG. 24 have the same area, the green light emitting regions G1 and G2 have the same area, and the blue light emitting regions B1 and B2 have the same area.

[0134] Figure 25 illustrates a top perspective view of the pixel definition layer, the anode layer and the aforementioned power line metal layer of the display panel according to another embodiment of the present application stacked together. The difference between Figure 25 and Figure 24 is that the areas of the light-emitting regions of the two light-emitting elements in a single pixel circuit are different. For example, the area of ​​the first light-emitting region (for example, the red light-emitting region R1) of the first light-emitting element is larger than the area of ​​the second light-emitting region (for example, the red light-emitting region R2) of the second light-emitting element. In some embodiments, the area of ​​the first light-emitting region of the first light-emitting element is twice the area of ​​the second light-emitting region of the second light-emitting element. In Figure 25, the area of ​​the green light-emitting region G1 is twice the area of ​​the green light-emitting region G2, the area of ​​the red light-emitting region R1 is twice the area of ​​the green light-emitting region R2, and the area of ​​the blue light-emitting region B1 is twice the area of ​​the blue light-emitting region B2. When the area of ​​the first light-emitting region of the first light-emitting element is larger than the area of ​​the second light-emitting region of the second light-emitting element, it is beneficial to reduce the difference in service life between the first light-emitting element and the second light-emitting element.

[0135] FIG26 shows a top perspective view of source / drain metal layers and power line metal layers stacked together for two adjacent pixel circuits in a display panel according to some embodiments of the present application.

[0136] According to an embodiment of the present application, the aforementioned light shielding layer, semiconductor layer, first gate metal layer, second gate metal layer, metal oxide semiconductor channel layer, third gate metal layer, source and drain metal layer, power line metal layer, anode layer and pixel definition layer can be arranged in sequence on the substrate. Moreover, it can be understood that the display panel may also include necessary insulating layers between the above-mentioned layer structures arranged in sequence and other layer structures required for the normal operation of the pixel circuit. For example, the pixel circuit also includes a cathode layer for each light-emitting element. For the sake of brevity, other layer structures such as insulating layers are not described here. Different conductive layers in the display panel can be electrically connected to each other via vias. For example, based on Figure 26, Figure 27 illustrates the location of some vias. The vias shown in black rectangular boxes in Figure 27 include vias (for example, vias VO1 and VO2) that electrically connect part of the pattern of the source and drain metal layer to part of the pattern in the power line metal layer, and vias (for example, vias VO3) that electrically connect part of the pattern in the power line metal layer to the anode of the light-emitting element. The vias represented by black solid dots in Figure 27 include vias that electrically connect a partial pattern of the source-drain metal layer and a partial pattern of other conductive layers (for example, a second gate layer, a semiconductor layer, or a hook layer of the ninth transistor) located between the source-drain metal layer and the substrate, for example, via VO4 in Figure 27.

[0137] In order to more clearly understand the relationship between some of the layer structures included in the display panel, in particular the relationship between the aforementioned first gate metal layer, the second gate metal layer and the third gate metal layer. Figure 28 schematically illustrates a partial cross-sectional view of the display panel. As shown in Figure 28, the display panel includes a substrate SB and various layer structures arranged on the substrate. BL1 in Figure 28 represents the first light shielding block in the aforementioned light shielding layer. The aforementioned semiconductor layer includes the active layer, source and drain of other transistors except the ninth transistor shown in Figure 3. The semiconductor layer of the driving transistor Td is a low-temperature polycrystalline silicon semiconductor layer, represented by Poly in Figure 28. The aforementioned first gate metal layer includes the gate GB1 of the driving transistor, the aforementioned second gate metal layer includes the bottom gate BG1 of the ninth transistor, and the aforementioned third gate metal layer includes the top gate TG1 of the ninth transistor. The aforementioned source-drain metal layer includes a source connection line SD1 electrically connected to the source of the driving transistor, and the aforementioned power line metal layer includes a metal connection line SD2 connected to the source connection line SD1. In FIG28 , the channel layer (i.e., active layer) of the ninth transistor is represented by IGZO. The pixel definition layer and the anode of the light-emitting element are represented by PDL and AND, respectively. As can be understood from FIG28 , the light shielding layer, the semiconductor layer, the first gate metal layer, the second gate metal layer, the third gate metal layer, the source and drain metal layer, the power line metal layer, the anode layer, and the pixel definition layer are sequentially arranged on the substrate in a direction perpendicular to the substrate SB, and necessary interlayer insulating layers may be included between the above-mentioned layer structures.

[0138] As previously described with reference to FIG11 , the light shielding layer can shield the pixel circuit from a portion of light that may enter the display panel from the back surface opposite the display surface of the display panel. In some embodiments, the light shielding layer includes a first light shielding block BL1 and a second light shielding block BL2. The orthographic projection of the first light shielding block BL1 or the second light shielding block BL2 on the base substrate covers the orthographic projection of the active layer and gate of the driving transistor in the two adjacent pixel circuits on the base substrate, as shown in FIG28 . Thus, the first light shielding block BL1 and the second light shielding block BL2 can respectively shield a portion of light for the driving transistors in the two adjacent pixel circuits, thereby facilitating the stabilization of the threshold voltage of the driving transistor Td in the pixel circuit and improving the brightness uniformity of the image displayed on the display panel.

[0139] 10 to 28 may be considered as examples of layouts of spatial structures and planar patterns of some layers of a display panel in the case where the display panel includes the pixel circuit shown in FIG. 3 .

[0140] In the case where the display panel includes a pixel circuit as shown in Figure 5, adjacent pixel circuits in the display panel may also have a symmetrical layout as described with reference to the above embodiment. That is, a plurality of pixel circuits as shown in Figure 5 may form a pixel circuit array in the display panel, and the display panel includes a first reference voltage line located on a substrate, and the first reference voltage line is electrically connected to the reference voltage terminal of the pixel circuit to transmit the aforementioned first reference voltage. Two adjacent pixel circuits in the pixel circuit array share the first reference voltage line, and the two adjacent pixel circuits are symmetrically arranged on both sides of the first reference voltage line. Based on such a symmetrical layout design, the constituent elements of each pixel circuit can be compactly arranged on the substrate, saving the element layout space on the substrate, which is conducive to improving the resolution of the display device and realizing a small-sized display device.

[0141] However, for the pixel circuit shown in Figure 5, the pattern of some layer structures in the display panel may be different from the embodiment described with reference to Figures 10 to 28. According to some embodiments of the present application, the display panel further includes a semiconductor layer located on the side of the first gate metal layer facing the base substrate, the semiconductor layer including the active layer, first electrode and second electrode patterns of the first transistor, the second transistor and the sixth transistor, the active layer, first electrode and second electrode patterns of the first transistor and the active layer, first electrode and second electrode patterns of the sixth transistor are interconnected, the active layer, first electrode and second electrode patterns of the second transistor are separated from the active layer, first electrode and second electrode patterns of the first transistor and the sixth transistor, the display panel further includes a source-drain metal layer located on the side of the first gate metal layer facing away from the base substrate, the source-drain metal layer including the first reference voltage line and an electrode connection line, wherein the electrode connection line electrically connects the active layer, first electrode and second electrode patterns of the second transistor to the active layer, first electrode and second electrode patterns of the sixth transistor. That is, in this embodiment, at least the semiconductor layer and source-drain metal layer of the display panel are different from the embodiment described with reference to Figures 10 to 28. This embodiment will be described in detail below with reference to FIG. 29 and FIG. 20 .

[0142] FIG29 can be viewed as a partial top perspective view of a single pixel circuit in a display panel corresponding to the portion indicated by the dotted rectangular box in the lower left corner of FIG20 . With respect to the portions of the single pixel circuit other than those indicated by the dotted rectangular box, the pixel circuit in this embodiment can have the same structure and layout as the pixel circuit shown in FIG20 . In FIG29 , the active layer, first and second electrode patterns of the first transistor T1, the active layer, first and second electrode patterns of the sixth transistor T6, and the active layer, first and second electrode patterns of the second transistor T2 in the semiconductor layer are indicated by the shaded portions with diagonal lines. As shown in FIG29 , the active layer, first and second electrode patterns of the first transistor T1 and the active layer, first and second electrode patterns of the sixth transistor T6 are interconnected, while the active layer, first and second electrode patterns of the second transistor T2 are separated from the active layer, first and second electrode patterns of the first and sixth transistors T1 and T6. In other words, the semiconductor layer of the second transistor T2 is independent of the semiconductor layers of the first and sixth transistors T1 and T6. In this case, the source / drain metal layer of the display panel includes, in addition to the aforementioned first reference voltage line, an electrode connection line CNL, which electrically connects the active layer, first electrode, and second electrode patterns of the second transistor T2 to the active layer, first electrode, and second electrode patterns of the sixth transistor T6. Therefore, as shown in FIG29 , viewed in the row direction of the pixel circuit array, the second transistor T2 can be considered to be located between the first transistor T1 of the pixel circuit and the tenth transistor T10′ in the pixel circuit adjacent to the pixel circuit in the column direction of the pixel circuit array. As previously described, for the pixel circuit shown in FIG5 , when the pixel circuit operates in the first operating mode, the first reference voltage can be used to reset the first light-emitting element D1 only via the second transistor T2. In this case, the first transistor T1 can be kept in the off state without affecting the resetting of the first light-emitting element D1 by the first reference voltage or the normal emission of the first light-emitting diode D1. The control signal provided to the gate of the first transistor T1 can maintain a constant level in the first operating mode. The semiconductor layer of the second transistor T2 is independent of the semiconductor layers of the other transistors, thereby enhancing the physical isolation between the second transistor T2 and the other transistors. The presence of the electrode connection line CNL ensures electrical connection between the second transistor T2 and the sixth transistor T6 (similarly, the first light-emitting element D1), and fully utilizes the spatial gaps between different conductive layers on the substrate, facilitating the compact arrangement of the components of each pixel circuit on the substrate, saving component layout space on the substrate, thereby facilitating improved display resolution and the realization of a small-sized display device. In addition, the second transistor T2 is farther away from the gate of the first transistor T1, which helps reduce the impact of parasitic capacitance on the first transistor.

[0143] Taking the pixel circuit shown in FIG. 7 as an example, some main layer structures included in the pixel circuit are briefly described below by way of example.

[0144] Figures 30 to 39 schematically illustrate some layer structures in a display panel including the pixel circuit shown in Figure 7. Similar to the aforementioned embodiment, the display panel may include a light shielding layer, a semiconductor layer, a first gate metal layer, a second gate metal layer, a third gate metal layer, a source / drain metal layer, a power line metal layer, an anode layer, and a pixel definition layer, which are sequentially arranged on the substrate in a direction perpendicular to the substrate. A pixel circuit array is formed on the substrate of the display panel including a plurality of pixel circuits as shown in Figure 7. Two adjacent pixel circuits in the pixel circuit array share a first reference voltage line for transmitting the above-mentioned first reference voltage. Figures 30 to 39 illustrate the pattern of the layer structure of the above-mentioned two adjacent pixel circuits in the pixel circuit array. The layer structure patterns shown in Figures 30 to 39 have similar symmetry to the embodiments described above with reference to Figures 10 to 28, i.e., the pattern of each layer structure of the two adjacent pixel circuits is symmetrical about the first reference voltage line.

[0145] Figure 30 illustrates the pattern of the light-shielding layer for two adjacent pixel circuits in a display panel. The pattern of the light-shielding layer shown in Figure 30 is similar to the pattern of the light-shielding layer shown in Figure 11. The light-shielding layer includes a first light-shielding block BL1 and a second light-shielding block BL2. The first light-shielding block BL1 and the second light-shielding block BL2 can respectively block part of the light for the active layer of the driving transistor Td in the two adjacent pixel circuits, thereby facilitating the stabilization of the performance of the driving transistor Td in the pixel circuit.

[0146] FIG31 illustrates the pattern of the semiconductor layers of transistors other than the ninth transistor T9 in FIG7 in two adjacent pixel circuits. The semiconductor layer includes a first electrode (e.g., source or drain), a second electrode (e.g., source or drain), and a control electrode (e.g., gate) for each transistor. Specifically, FIG31 illustrates the semiconductor layers AL3 and AL4 for the third and fourth transistors T3 and T4 shown in FIG7 . The semiconductor layers AL3 and AL4 of the third and fourth transistors T3 and T4 in two adjacent pixel circuits in the row direction of the pixel circuit array are symmetrical about a first reference voltage line (as shown by the dashed line in FIG31 ). Furthermore, the semiconductor layers AL3 and AL4 of the third and fourth transistors T3 and T4 in the two adjacent pixel circuits are electrically connected to the same node CO1. For example, the second electrode of the third transistor T3 and the first electrode of the fourth transistor T4 in the two adjacent pixel circuits are connected to the node CO1. This node CO1 is electrically connected to the first reference voltage line in the source / drain metal layer as described below, so that the first reference voltage line transmits the first reference voltage to the third and fourth transistors T3 and T4 in the two adjacent pixel circuits. Because the first reference voltage line in the source / drain metal layer and the semiconductor layer are located in different layers, they need to be electrically connected to each other via a via that penetrates other layers between the source / drain metal layer and the semiconductor layer. The location of this via corresponds to node CO1. However, the sources of the third transistor T3 and the fourth transistor T4 in two adjacent pixel circuits are electrically connected to the first reference voltage line via the same via. In other words, the four transistors (two third transistors T3 and two fourth transistors T4) in two adjacent pixel circuits share a first reference voltage line, and the four crystal patterns are connected to the first reference voltage line via the same via. This saves space on the substrate occupied by the various components of the pixel circuit, which helps improve the pixel resolution of the display panel.

[0147] The partial pattern of the first gate metal layer shown in FIG32 is substantially the same as the pattern of the first gate metal layer shown in FIG13 . The first gate metal layer includes a fifth gate metal line GL5, a sixth gate metal line GL6, a seventh gate metal line GL7, and an eighth gate metal line GL8, extending along the row direction of the pixel circuit array and spaced apart in the column direction of the pixel circuit array, as well as gates GB1 and GB2. The fifth gate metal line includes the gate of the fifth transistor T5 in the pixel circuit shown in FIG7 . The sixth gate metal line GL6 includes the gates of the third transistor T3, the fourth transistor T4, and the eighth transistor T8 in the pixel circuit shown in FIG7 . The seventh gate metal line includes the gates of the sixth transistor T6 and the seventh transistor T7, and the fifth gate metal line is located between the sixth and seventh gate metal lines. The pattern of the first gate metal layer shown in FIG32 corresponds to the first gate metal layer in two adjacent pixel circuits shown in FIG7 . By designing the layout of the first gate metal layer in this manner, the layout space occupied by the reset circuit and switching circuit in the pixel circuit can be reduced on the substrate, thereby reducing the area occupied by a single pixel circuit on the substrate. It is understood that the fifth gate metal line GL5, the sixth gate metal line GL6, and the seventh gate metal line GL7 may each include a gate connection line electrically connected to the gate of the corresponding transistor. In the embodiment shown in FIG32, the fourth gate metal line GL4 includes the gates of the eleventh transistor T11 and the twelfth transistor T12 and the corresponding gate connection lines as shown in FIG7.

[0148] Figure 33 shows a perspective view of the first gate metal layer and semiconductor layer in a pixel circuit superimposed together. Figure 33 includes the fifth gate metal line GL5, the sixth gate metal line GL6, the seventh gate metal line GL7, and the eighth gate metal line GL8, as well as the gate electrodes GB1 and GB2 shown in Figure 32. GL6′ in Figure 33 represents a second gate metal line in the first gate metal layer of a pixel circuit adjacent to the pixel circuit in Figure 33 in the direction of extension of the aforementioned axis of symmetry. Figure 33 similarly shows the approximate positions of the third transistor T3, the fourth transistor T4, the driving transistor Td, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the tenth transistor T10, the eleventh transistor T11, and the twelfth transistor T12 in the pixel circuit shown in Figure 7. T10′ represents the approximate position of the tenth transistor in another pixel circuit adjacent to the pixel circuit on the left side of the axis of symmetry in a direction consistent with the direction of extension of the axis of symmetry. As shown in FIG33 , the semiconductor layers of the seventh transistor T7 and the twelfth transistor T12 (i.e., the active layers, first electrodes, and second electrodes of the transistors) are interconnected. FIG14 also shows a node of the semiconductor layer corresponding to the third node N3 in FIG3 . FIG33 also shows two connection nodes CD1 and CD2 in the semiconductor layer of the pixel circuit, which are electrically connected to the first light-emitting element D1 and the second light-emitting element D2 in the pixel circuit shown in FIG7 , respectively.

[0149] Similarly, the display panel includes a second gate metal layer located on a side of the first gate metal layer facing away from the substrate. The pattern of the second gate metal layers of the two adjacent pixel circuits shown in FIG34 is similar to the pattern of the second gate metal layer shown in FIG15. The ninth transistor T9 in FIG7 is a dual-gate thin-film transistor. As shown in FIG34, the second gate metal layer includes capacitor electrode blocks CB1 and CB2 and bottom gates BG1 and BG2 of the ninth transistor T9. The orthographic projection of the capacitor electrode block CB1 or CB2 on the substrate substrate and the orthographic projection of the gate GB1 or GB2 of the driver transistor on the substrate substrate at least partially overlap to form the capacitor C in FIG7. The capacitor electrode blocks CB1 and CB2 include openings penetrating the capacitor electrode blocks, as shown by O1 or O2 in FIG34. The orthographic projection of the opening O1 or O2 on the substrate substrate is located within the orthographic projection of the gate GB1 or GB2 of the driver transistor on the substrate substrate. The second gate metal layer shown in FIG34 also includes a third reference voltage line VL3 for electrically connecting to the third reference voltage terminal Vref3 in FIG7 to transmit a third reference voltage.

[0150] FIG35 illustrates a third gate metal layer in a display panel. The third gate metal layer includes the top gate of a ninth transistor T9 and a fourth reference voltage line. The fourth reference voltage line is electrically connected to a fourth reference voltage terminal Vref4 in the pixel circuit to transmit a fourth reference voltage. The display panel also includes a pattern of a metal oxide semiconductor channel of the ninth transistor T9. The top gate and bottom gate of the ninth transistor T9 may be located on opposite sides of the metal oxide semiconductor channel.

[0151] Figure 36 illustrates a top perspective view of the second gate metal layer shown in Figure 34, the metal oxide semiconductor channel layer of the ninth transistor, and the third gate metal layer shown in Figure 35 stacked together. The approximate position of the ninth transistor in the pixel circuit shown in Figure 7 is shown as T9 in Figure 36.

[0152] As previously described, the display panel includes a semiconductor layer located on the side of the first gate metal layer facing the substrate, the semiconductor layer including the first electrode, second electrode, and active layer of the third and fourth transistors in the pixel circuit shown in FIG7 . The patterns of the first electrode, second electrode, and active layer of the third and fourth transistors in two adjacent pixel circuits are symmetrical about the first portion of the first reference voltage line. The display panel also includes a source / drain metal layer located on the side of the first gate metal layer facing away from the substrate, the source / drain metal layer including the first reference voltage line, and the sources of the third and fourth transistors in the two adjacent pixel circuits are electrically connected to the first reference voltage line via the same via located at the junction of the first portion and the second portion. FIG37 illustrates the source / drain metal layer located on the side of the third gate metal layer facing away from the substrate, the source / drain metal layer including the first reference voltage line, the first reference voltage line including a first portion P1 and a second portion P2, and the first electrode or second electrode (i.e., source or drain) of the second transistor T2 in the two adjacent pixel circuits being electrically connected to the first reference voltage line via a second via located at the intersection of the first portion P1 and the second portion P2 of the first reference voltage line. The second via hole can pass through the insulating layer provided between the semiconductor layer and the source / drain metal layer. The position of the second via hole can correspond to the intersection C of the first portion P1 and the second portion P2 of the first reference voltage line (as shown in FIG37 ) and the node CO1 shown in FIG31 . In other words, the third transistor and the fourth transistor included in the two adjacent pixel circuits are electrically connected to the first reference voltage line via the above-mentioned second via hole. This can reduce the complexity of the component layout in all pixel circuits of the display panel and save the space occupied by the pixel circuit on the substrate. In addition to the first reference voltage line, the source / drain metal layer also includes a plurality of source / drain connection lines. These source / drain connection lines are used to realize the electrical connection between the first electrode or the second electrode of each transistor in each transistor shown in FIG7 and other transistors or electrical components. As can be seen from FIG37 , the patterns of the source / drain metal layers of the two adjacent pixel circuits also present a symmetrical arrangement. In this embodiment, the axis of symmetry is the first portion P1 of the first reference voltage line.

[0153] Figure 38 shows a partial pattern of the power line metal layer on the side of the source and drain metal layer facing away from the base substrate. This pattern is essentially similar to the power line metal layer shown in Figure 21 and includes power lines and data lines. As shown in Figure 38 , the power line includes a first conductive block PC, which is shared by two adjacent pixel circuits. Furthermore, the orthographic projection of the first conductive block PC on the base substrate overlaps and extends beyond the orthographic projections of the top gate and active layer of the ninth transistor T9 in the two adjacent pixel circuits, as well as the orthographic projections of the gate and active layer of the drive transistor Td on the base substrate. Thus, in addition to transmitting the power supply voltage to the two adjacent pixel circuits, the first conductive block PC in the power line also serves to shield at least the ninth transistor T9 and the drive transistor Td from light. As shown in Figure 38 , data lines d1 and d2 transmit the data signal voltage Vdata to the two adjacent pixel circuits, respectively.

[0154] Figure 39 schematically illustrates a top perspective view of the semiconductor layer, first gate metal layer, second gate metal layer, third gate metal layer, channel layer of the ninth transistor, source / drain metal layer, and power line metal layer shown in Figures 31 to 38 . Figure 39 also illustrates the approximate locations of the third transistor T3, fourth transistor T4, fifth transistor T5, sixth transistor T6, seventh transistor T7, drive transistor Td, eighth transistor T8, ninth transistor T9, tenth transistor T10, eleventh transistor T11, and twelfth transistor T12 shown in Figure 7 . In this document, the position of a transistor described with respect to the planar layout of various components and wires in the pixel circuit of a display panel refers to the approximate position of the transistor's gate on the planar layout of the corresponding components and wires. As shown in Figure 39 , according to some embodiments of the present application, the orthographic projection of the fourth reference voltage line VL4 in the third gate metal layer on the substrate can at least partially overlap with the orthographic projection of the seventh gate metal line GL7 on the substrate. This can improve the light transmittance of the display panel and enhance the image quality of the display panel. Although the seventh gate metal line GL7 can transmit the light-emitting control signal to the gates of the sixth transistor T6 and the seventh transistor T7, the fourth reference voltage line VL4 is used to transmit the fourth reference voltage having a constant voltage, so the fourth reference voltage line VL4 has little effect on the light-emitting control signal line that transmits the control signal EM. In addition, the fifth transistor T5 can be electrically connected to the source or drain of the sixth transistor T6. When the fifth transistor T5 is electrically connected to the drain of the sixth transistor T6 (i.e., the drain of the sixth transistor is electrically connected to the second node N2), the connection line between the fifth transistor T5 and the sixth transistor T6 may not cross the fourth reference voltage line VL4 that is electrically connected to the fourth reference voltage terminal Vref4, thereby reducing coupling between different signal lines.

[0155] According to another embodiment of the present application, the fourth reference voltage line in the third gate metal layer can be arranged in another position. As shown in FIG39 , the fourth reference voltage line VL4′, shown as a dashed line, is arranged in a curved form in the gap between adjacent conductive lines. Specifically, in a row direction parallel to the pixel circuit array, the fourth reference voltage line extends approximately between the fifth gate metal line GL5 and the sixth gate metal line GL6. The fourth reference voltage line VL4′ is electrically connected to the tenth transistor T10′ through a via VH1. This facilitates the compact arrangement of the components of each pixel circuit on the substrate, saving component layout space on the substrate.

[0156] Figure 40 illustrates the anodes of two adjacent pixel circuits of a display panel and the light-emitting areas defined by the pixel definition layer. The anodes of the first light-emitting element D1 and the second light-emitting element D2 in each pixel circuit are shown in the solid rectangular area in Figure 40, and the light-emitting area defined by the pixel definition layer is shown in the dashed rectangular area shown in Figure 40. The anodes of the light-emitting elements in the pixel circuits are electrically connected to the corresponding source-drain connection lines in the source-drain metal layer via a conductor pattern and vias.

[0157] As shown in Figure 40, the first light-emitting area of ​​the first light-emitting element and the second light-emitting area of ​​the second light-emitting element defined by the pixel definition layer are spaced apart from each other and symmetrically distributed on both sides of the symmetry axis, and the symmetry axis (as shown by the dotted line S1 in Figure 40) intersects with the extension line of the first part of the first reference voltage line (as shown by the dotted line S2 in Figure 40).

[0158] Figures 41 to 44 illustrate partial schematic diagrams of display panels provided according to further embodiments of the present application. In these embodiments, the display panel includes: a substrate, a pixel circuit as described in any of the aforementioned pixel circuit embodiments herein, arranged on the substrate, a pixel definition layer located on a side of the pixel circuit facing away from the substrate, and an optical structure located on a side of the pixel definition layer facing away from the substrate, the pixel definition layer defining a first light-emitting region of the first light-emitting element and a second light-emitting region of the second light-emitting element, the optical structure being optically coupled to the first light-emitting region to suppress propagation of light from the first light-emitting element in a first emission direction that is not perpendicular to the light-emitting surface of the display panel.

[0159] As previously mentioned, using the pixel circuit provided in the embodiments of the present application, for display products that require privacy protection, alternative optical structures can be used to replace the privacy film in conventional privacy protection solutions, thereby alleviating or avoiding the aforementioned defects caused by the use of privacy films. The aforementioned optical structure, which is optically coupled to the first light-emitting region corresponding to the first light-emitting element in the pixel circuit, can replace the privacy film in conventional privacy protection solutions, thereby enabling the display panel to have privacy protection. For example, when the pixel circuit in the display panel operates in the first operating mode, the pixel driving circuit in the pixel circuit only drives the first light-emitting element to emit light, and the second light-emitting element is in a non-light-emitting state. The optical structure optically coupled to the first light-emitting area corresponding to the first light-emitting element in the pixel circuit can suppress the propagation of light from the first light-emitting element in a first emission direction that is not perpendicular to the light-emitting surface of the display panel. That is, if the vertical direction perpendicular to the light-emitting surface of the display panel is used as the reference direction, the light whose emission direction intersects with the reference direction to form a larger angle (that is, light with a larger emission angle) is suppressed by the optical structure. Therefore, if the viewer deviates from the front of the light-emitting surface of the display panel, for example, viewers on both sides of the display panel will not be able to see the displayed picture clearly, while users whose viewing direction is consistent with the above-mentioned reference direction or has a smaller deviation will not be affected by the display picture of the display panel. At this time, the display panel can be regarded as being in a narrow viewing angle display mode. When the pixel circuit in the display panel operates in the second operating mode, the pixel driving circuit can simultaneously drive the first light-emitting element and the second light-emitting element to emit light, and the propagation of light emitted by the second light-emitting element in each pixel circuit will not be affected by the optical structure. At this time, the display panel can be regarded as being in a wide-viewing angle display mode, and viewers directly in front of and around the display panel can clearly see the displayed image.

[0160] The optical structure of the display panel is illustrated below with reference to Figures 41 to 44. In Figures 41 to 44, for simplicity, the base substrate and the pixel circuit located on the base substrate are collectively labeled PS. As shown in Figure 41, the optical structure includes a light absorbing layer BM, which at least partially surrounds a first light emitting area corresponding to a first light emitting element, and the orthographic projection of the light absorbing layer on the base substrate does not overlap with the orthographic projection of the second light emitting area corresponding to a second light emitting element on the base substrate. As a result, light emitted from the first light emitting element with a direction consistent with the above-mentioned reference direction (for example, light ray L0 in Figure 41) or light with a smaller emission angle can be emitted normally from the display panel, while light with a larger emission angle (for example, light rays L1 and L2 as shown in Figure 41) is absorbed or blocked by the light absorbing layer BM, and the light emitted by the second light emitting element is less affected or unaffected by the light absorbing layer BM. Therefore, the operating state of the display panel can be switched between the wide-viewing angle display mode and the narrow-viewing angle display mode described above. That is, the display panel can operate in both the anti-peeping display mode and the normal display mode. Moreover, the implementation of the display panel's anti-peeping function can avoid the defects caused by the anti-peeping film in conventional anti-peeping solutions. In some embodiments, the display panel includes an encapsulation layer TFE, which can cover the pixel definition layer PDL. The light absorption layer BM can be located on the side of the encapsulation layer TFT facing away from the base substrate, as shown in Figure 41.

[0161] For the sake of simplicity, Figures 42 to 44 only show partial cross-sectional views of the first light-emitting region corresponding to the first light-emitting element in the display panel, while omitting cross-sectional views of the second light-emitting region corresponding to the second light-emitting element. As shown in Figure 42, the display panel also includes a light-transmitting layer OC, and the light-absorbing layer includes a first sub-light-absorbing layer BM1 and a second sub-light-absorbing layer BM2. The first sub-light-absorbing layer BM1 is located on the side of the encapsulation layer TFT facing away from the base substrate. The light-transmitting layer OC covers the first sub-light-absorbing layer BM1, and the second sub-light-absorbing layer BM2 is located on the side of the light-transmitting layer OC facing away from the base substrate. For the embodiment shown in Figure 42, the thickness requirements for individual sub-light-absorbing layers can be reduced, thereby facilitating the production of the sub-light-absorbing layers. The first sub-light-absorbing layer and the second sub-light-absorbing layer can be made of black light-absorbing material. The specific materials of the light-absorbing layer (sub-light-absorbing layer) and the light-transmitting layer are not limited herein. The dotted line in Figure 42 indicates that light emitted from the first light-emitting element with a larger emission angle is absorbed or blocked by the first sub-light-absorbing layer or the second sub-light-absorbing layer, while light with a smaller emission angle can be emitted normally from the light-emitting surface of the display panel.

[0162] In the embodiment of FIG43 , the light-transmitting layer includes a first light-transmitting portion OC1 and a second light-transmitting portion OC2. The first light-transmitting portion OC1 is located on the side of the first light-absorbing sub-layer BM1 facing away from the substrate, and the second light-transmitting portion OC2 is located on the side of the first light-transmitting portion OC1 facing away from the substrate. The second light-transmitting portion overlaps the first light-transmitting portion, and the refractive index of the second light-transmitting portion OC2 is higher than that of the first light-transmitting portion OC1. In FIG43 , the first light-transmitting portion OC1 is illustrated with a slashed hatching pattern. As shown in FIG43 , because the refractive index of the second light-transmitting portion OC2 is higher than that of the first light-transmitting portion OC1, at least a portion of light emitted from the first light-emitting element at a larger emission angle (e.g., light L3 or L4 in FIG43 ) may be totally reflected at the interface between the first light-transmitting portion OC1 and the second light-transmitting portion OC2. The reflected light then propagates in a direction toward a smaller emission angle, such as light L3′ or L4′ in FIG43 . Therefore, the embodiment shown in FIG43 can further enhance the anti-peeping effect of the display panel and increase the brightness of the image viewed by viewers directly in front of the display panel. As shown in FIG43 , in some embodiments, the orthographic projection of the first light-transmitting portion OC1 on the base substrate can completely cover the orthographic projection of the first light-absorbing sub-layer BM1 on the base substrate, and the orthographic projection of the second light-absorbing sub-layer BM2 on the base substrate does not exceed the orthographic projection of the first light-absorbing sub-layer BM1 on the base substrate.

[0163] FIG44 shows a partial cross-sectional view of a display panel according to another embodiment of the present application. As shown in FIG44 , the display panel includes a pixel definition layer (PDL) located on a base substrate and an encapsulation layer (TFE) located on a side of the pixel definition layer facing away from the base substrate. The pixel definition layer defines a first light-emitting region of a first light-emitting element and a second light-emitting region of a second light-emitting element ( FIG44 only shows the pixel definition layer defining the first light-emitting region). The optical structure includes a microlens (LEN) located on a side of the encapsulation layer (TFE) facing away from the base substrate. The microlens is configured to converge light from the first light-emitting element. The microlens (LEN) may include a micro-convex lens, whose orthographic projection on the base substrate may overlap and extend beyond the orthographic projection of the first light-emitting region on the base substrate. The microlens (LEN) may converge light emitted from the first light-emitting element, thereby converting light with a larger emission angle into light with a smaller emission angle, thereby achieving an anti-peeping effect for the display panel.

[0164] Figure 45 illustrates schematic diagrams of two light-emitting areas of a display panel corresponding to two light-emitting elements in a single pixel circuit in different states, respectively, in anti-peeping display mode and normal display mode. The two light-emitting areas corresponding to the two light-emitting elements in a single pixel circuit (i.e., the first and second light-emitting elements described above) are labeled A1 and A2, respectively. The left diagram in Figure 45 shows the states of the two light-emitting areas A1 and A2 when the display panel is in anti-peeping display mode, while the right diagram in Figure 45 shows the states of the two light-emitting areas A1 and A2 when the display panel is in normal display mode. The optical structure described in the aforementioned embodiment is provided in light-emitting area A1, while the optical structure described in the aforementioned embodiment is not provided in light-emitting area A2. As shown in the left diagram in Figure 45, light-emitting area A1 is in an emitting state, but no light is emitted from light-emitting area A2 because the second light-emitting element corresponding to light-emitting area A2 is in a non-emitting state. However, the light emitted at a larger emission angle by the first light-emitting element corresponding to the light-emitting area is suppressed or blocked by the optical structure, making it difficult for viewers near the display panel to clearly see the display content of the display panel, thereby achieving an anti-peeping effect. As shown in the right figure in Figure 45, the luminous area A1 and the luminous area A2 are both in a luminous state, and the light emitted from the luminous area A2 is not blocked or restricted by the optical structure. The viewing effect of viewers directly in front of and around the display panel is not affected by the optical structure, and the display panel is in a normal display mode.

[0165] Another embodiment of the present application provides a display device, which may include the display panel described in any of the aforementioned embodiments regarding display panels. The display device may be any electronic device with an image display function, such as a mobile phone or a tablet computer.

[0166] It is understood that in the accompanying drawings, the size or thickness of some elements or structures may be exaggerated for the sake of clarity. Therefore, the implementation of any embodiment of the present application is not necessarily limited to the dimensions shown in the drawings, and the shapes and sizes of the components in the drawings do not reflect the true proportions of the dimensions of the various elements in the actual product. In this article, for convenience, the use of words and phrases such as "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", and "outside" to indicate the orientation or positional relationship to illustrate the positional relationship of the constituent elements with reference to the accompanying drawings is only for the convenience of describing the implementation methods and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. The positional relationship of the constituent elements can be appropriately changed according to the direction of the constituent elements being described. Therefore, it is not limited to the words and phrases described in the text and can be appropriately replaced according to the circumstances.

[0167] The phrase "and / or" as used in the specification and claims should be understood to mean "either one or both" of the elements so combined, i.e., elements that are presented connected in some cases and separately in other cases. Multiple elements listed with "and / or" should be interpreted in the same manner, i.e., "one or more" of the elements so combined. In addition to the elements specifically indicated by the "and / or" clause, other elements may optionally be present, whether related or unrelated to the specifically identified elements. Thus, as a non-limiting example, a reference to "A and / or B" when used in conjunction with open language such as "comprising" refers to A only (optionally including elements in addition to B) in one embodiment; to B only (optionally including elements in addition to A) in another embodiment; and to both A and B (optionally including other elements) in yet another embodiment.

[0168] In this document, unless otherwise specified or limited, the terms "connected," "connected," and "electrically connected" should be understood broadly. For example, they can refer to fixed connections, removable connections, or integral connections; they can refer to direct connections, indirect connections through intermediate components, or internal connections between two components. Those skilled in the art will understand the meanings of these terms in this application based on the specific circumstances.

[0169] In this article, a transistor refers to an element that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between the drain electrode, and current can flow through the drain electrode, the channel region, and the source electrode. In this article, the first electrode can be the drain electrode, the second electrode can be the source electrode, or the first electrode can be the source electrode, and the second electrode can be the drain electrode. In this article, "electrically connected" includes a situation where the components are connected together through an element having some electrical function. In this article, "film" and "layer" can be interchangeable. For example, "conductive layer" can sometimes be replaced by "conductive film". Similarly, "insulating film" can sometimes be replaced by "insulating layer".

[0170] In the description of this specification, the description with reference to the terms "one embodiment", "another embodiment", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment are included in at least one embodiment of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in a suitable manner in any one or more embodiments or examples. In addition, those skilled in the art can combine the different embodiments or examples described in this specification and the features of different embodiments or examples, unless they are contradictory. In addition, it should be noted that in this specification, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated.

[0171] The above descriptions are merely some specific implementations of the embodiments of the present application, but the scope of protection of the present application is not limited thereto. Any person skilled in the art who can easily conceive of changes or substitutions within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A pixel circuit, comprising: a pixel driving circuit, a first light emitting element, a second light emitting element, a switching circuit and a reset circuit, The pixel driving circuit is electrically connected to the first light emitting element to drive the first light emitting element to emit light, the switching circuit comprises a first end, a second end and a control end, the first end of the switching circuit is electrically connected to the pixel driving circuit, the second end of the switching circuit is electrically connected to the second light emitting element, and the switching circuit is configured as follows: In response to the control terminal receiving a first level signal, the second light emitting element is electrically connected to the pixel driving circuit, so that the pixel driving circuit drives the second light emitting element to emit light, and In response to the control terminal receiving a second level signal, the electrical connection between the second light emitting element and the pixel driving circuit is disconnected, so that the second light emitting element is in a non-light emitting state. The reset circuit includes a reference voltage connection terminal for receiving a first reference voltage and a reset control terminal for receiving a reset control signal. The reset circuit is electrically connected to one of the first terminal and the second terminal of the switching circuit, and at least one of the first light-emitting element and the second light-emitting element, and is configured to reset the first light-emitting element and / or the second light-emitting element using the first reference voltage under the control of the reset control signal.

2. The pixel circuit according to claim 1, wherein the switching circuit comprises a first transistor, the first end of the switching circuit comprises a first electrode of the first transistor, the second end of the switching circuit comprises a second electrode of the first transistor, and the control end of the switching circuit comprises a control electrode of the first transistor, The first electrode of the first transistor is electrically connected to the first electrode of the first light-emitting element, the second electrode of the first transistor is electrically connected to the first electrode of the second light-emitting element, the control electrode of the first transistor is configured to receive the first level signal or the second level signal, and the second electrode of the first light-emitting element and the second electrode of the second light-emitting element are electrically connected to a second reference voltage terminal.

3. The pixel circuit according to claim 2, wherein the reset circuit comprises a second transistor, a first electrode of the second transistor is electrically connected to a first electrode of the second light-emitting element, a second electrode of the second transistor is electrically connected to the reference voltage connection terminal, and a control electrode of the second transistor is electrically connected to the reset control terminal.

4. The pixel circuit according to claim 2, wherein the reset circuit comprises a second transistor, a first electrode of the second transistor is electrically connected to the first electrode of the first light-emitting element, a second electrode of the second transistor is electrically connected to the reference voltage connection terminal, and a control electrode of the second transistor is electrically connected to the reset control terminal.

5. The pixel circuit according to claim 1, wherein the reset circuit comprises a third transistor and a fourth transistor, the third transistor and the fourth transistor are connected in series between the first electrode of the first light-emitting element and the first electrode of the second light-emitting element, the second electrode of the first light-emitting element and the second electrode of the second light-emitting element are electrically connected to a second reference voltage terminal, a first node between the third transistor and the fourth transistor is electrically connected to the reference voltage connection terminal, and a control electrode of the third transistor and a control electrode of the fourth transistor are electrically connected to the reset control terminal.

6. A pixel circuit according to claim 5, wherein the switching circuit includes a fifth transistor, the first end of the switching circuit includes the first electrode of the fifth transistor, the second end of the switching circuit includes the second electrode of the fifth transistor, and the control end of the switching circuit includes the control electrode of the fifth transistor, wherein the pixel driving circuit includes a driving transistor, a sixth transistor and a power supply voltage end for receiving a power supply voltage, the driving transistor and the sixth transistor are connected in series between the power supply voltage end and the first electrode of the first light-emitting element, the first electrode of the fifth transistor is electrically connected to the first electrode or the second electrode of the sixth transistor, and the second electrode of the fifth transistor is electrically connected to the first electrode of the second light-emitting element.

7. A pixel circuit according to any one of claims 1-6, wherein the pixel driving circuit comprises a driving transistor, a sixth transistor, a seventh transistor and a power supply voltage terminal for receiving a power supply voltage, the seventh transistor, the driving transistor and the sixth transistor are connected in series in sequence between the power supply voltage terminal and the first electrode of the first light-emitting element, wherein the pixel driving circuit further comprises an eighth transistor, the first electrode of the eighth transistor is electrically connected to a third node between the driving transistor and the seventh transistor, the second electrode of the eighth transistor is electrically connected to a third reference voltage terminal, and the control electrode of the eighth transistor is electrically connected to the reset control terminal.

8. The pixel circuit according to claim 7, wherein the pixel driving circuit further comprises a ninth transistor, a tenth transistor, a capacitor and a fourth reference voltage terminal, wherein the capacitor, the ninth transistor and the tenth transistor are sequentially connected in series between the power supply voltage terminal and the fourth reference voltage terminal, the control electrode of the driving transistor is electrically connected to a fourth node between the capacitor and the ninth transistor, wherein the control electrode of the tenth transistor is electrically connected to the reset control terminal, and the control electrode of the ninth transistor is used to receive a first scanning signal.

9. The pixel circuit according to claim 8, wherein the pixel driving circuit further comprises an eleventh transistor and a twelfth transistor, the first electrode and the second electrode of the eleventh transistor being electrically connected to the second node between the driving transistor and the sixth transistor, and the fifth node between the ninth transistor and the tenth transistor, respectively, the first electrode of the twelfth transistor being used to receive a data signal, the second electrode of the twelfth transistor being electrically connected to the third node, and the control electrode of the eleventh transistor and the control electrode of the twelfth transistor being used to receive a second scanning signal.

10. The pixel circuit according to claim 9, wherein the ninth transistor comprises a metal oxide thin film transistor, and each of the driving transistor, the sixth transistor, the seventh transistor, the eighth transistor, the tenth transistor, the eleventh transistor, and the twelfth transistor comprises a low temperature polysilicon thin film transistor.

11. A display panel, comprising: substrate substrate; as well as A plurality of pixel circuits as claimed in claim 1, A plurality of the pixel circuits are arranged in an array on the substrate to form a pixel circuit array.

12. The display panel according to claim 11, wherein the display panel comprises a first reference voltage line located on the base substrate, the first reference voltage line is electrically connected to the reference voltage terminal to transmit the first reference voltage, wherein two adjacent pixel circuits in the pixel circuit array share the first reference voltage line, and the two adjacent pixel circuits are symmetrically arranged on both sides of the first reference voltage line.

13. The display panel according to claim 12, wherein the first reference voltage line comprises a first portion and a second portion, the first portion extends in a column direction of the pixel circuit array, the second portion extends in a row direction of the pixel circuit array, the first portion intersects with the second portion, and the two adjacent pixel circuits are symmetrically arranged on both sides of the first portion.

14. The display panel according to claim 13, wherein the switching circuit comprises a first transistor, the first end of the switching circuit comprises a first electrode of the first transistor, the second end of the switching circuit comprises a second electrode of the first transistor, the control end of the switching circuit comprises a control electrode of the first transistor, the reset circuit comprises a second transistor, the first electrode of the second transistor is electrically connected to the first electrode of the first light-emitting element or the second light-emitting element, the second electrode of the second transistor is electrically connected to the reference voltage connection end, and the control electrode of the second transistor is electrically connected to the reset control end, wherein the pixel driving circuit comprises a driving transistor, a sixth transistor and a power supply voltage end for receiving a power supply voltage, the driving transistor and the sixth transistor are connected in series between the power supply voltage end and the first electrode of the first light-emitting element, The display panel further comprises a first gate metal layer located on the base substrate, wherein the first gate metal layer comprises a first gate metal line, a second gate metal line and a third gate metal line extending along a row direction of the pixel circuit array and spaced apart from each other in a column direction of the pixel circuit array, wherein the first gate metal line comprises a gate of the first transistor, the second gate metal line comprises a gate of the second transistor, the third gate metal line comprises a gate of the sixth transistor, and the first gate metal line is located between the second gate metal line and the third gate metal line.

15. The display panel according to claim 13, wherein the reset circuit comprises a third transistor and a fourth transistor, the third transistor and the fourth transistor are connected in series between the first electrode of the first light-emitting element and the first electrode of the second light-emitting element, the second electrode of the first light-emitting element and the second electrode of the second light-emitting element are electrically connected to a second reference voltage terminal, a first node between the third transistor and the fourth transistor is electrically connected to the reference voltage connection terminal, a control electrode of the third transistor and a control electrode of the fourth transistor are electrically connected to the reset control terminal, the switching circuit comprises a fifth transistor, a first terminal of the switching circuit comprises a first electrode of the fifth transistor, a second terminal of the switching circuit comprises a second electrode of the fifth transistor, and a control terminal of the switching circuit comprises a control electrode of the fifth transistor, The pixel driving circuit includes a driving transistor, a sixth transistor and a power supply voltage terminal for receiving a power supply voltage, the driving transistor and the sixth transistor are connected in series between the power supply voltage terminal and the first electrode of the first light-emitting element, the first electrode of the fifth transistor is electrically connected to a second node between the driving transistor and the sixth transistor, and the second electrode of the fifth transistor is electrically connected to the first electrode of the second light-emitting element. The display panel further comprises: A first gate metal layer is located on the substrate, wherein the first gate metal layer includes a plurality of layers extending along the row direction of the pixel circuit array and extending along the row direction of the pixel circuit array. A fourth gate metal line, a fifth gate metal line and a sixth gate metal line are spaced apart from each other in a column direction of a pixel circuit array, wherein the fourth gate metal line includes the gates of the third transistor and the fourth transistor, the fifth gate metal line includes the gate of the fifth transistor, the sixth gate metal line includes the gate of the sixth transistor, and the fifth gate metal line is located between the fourth gate metal line and the sixth gate metal line.

16. The display panel according to claim 15, wherein the display panel further comprises a third gate metal layer, wherein the third gate metal layer is located on a side of the second gate metal layer away from the substrate, and comprises a top gate of the ninth transistor and a fourth reference voltage line, wherein the fourth reference voltage line is electrically connected to the fourth reference voltage terminal to transmit the fourth reference voltage, wherein the display panel further comprises a source-drain metal layer located on a side of the third gate metal layer away from the substrate, and the source-drain metal layer comprises the first reference voltage line.

17. A display panel according to claim 14, wherein the display panel further comprises a semiconductor layer located on the side of the first gate metal layer facing the base substrate, the semiconductor layer comprising the active layer, first pole and second pole patterns of the first transistor, the second transistor and the sixth transistor, wherein the active layer, first pole and second pole patterns of the first transistor and the active layer, first pole and second pole patterns of the sixth transistor are connected to each other, and the active layer, first pole and second pole patterns of the second transistor are separated from the active layer, first pole and second pole patterns of the first transistor and the sixth transistor, wherein the display panel further comprises a source-drain metal layer located on the side of the first gate metal layer away from the base substrate, the source-drain metal layer comprising the first reference voltage line and an electrode switching line, wherein the electrode switching line electrically connects the active layer, first pole and second pole patterns of the second transistor to the active layer, first pole and second pole patterns of the sixth transistor.

18. The display panel according to claim 15, wherein the display panel comprises a semiconductor layer located on a side of the first gate metal layer facing the substrate, the semiconductor layer comprises a first electrode, a second electrode and an active layer of the third transistor and the fourth transistor, wherein patterns of the first electrode, the second electrode and the active layer of the third transistor and the fourth transistor in two adjacent pixel circuits are symmetrical about the first part, the display panel further comprises a source-drain metal layer located on a side of the first gate metal layer facing away from the substrate, the source-drain metal layer comprises the first reference voltage line, The sources of the third transistor and the fourth transistor in the two adjacent pixel circuits are electrically connected to the first reference voltage line via a same via hole located at a connection point between the first portion and the second portion.

19. The display panel according to claim 14 or 15, wherein the display panel further comprises: A first light-shielding layer is located on the first gate metal layer and faces the base substrate, the first light-shielding layer includes a plurality of first light-shielding portions, the first gate metal layer includes the gate of the driving transistor, wherein the orthographic projection of one of the plurality of first light-shielding portions on the base substrate covers and exceeds the orthographic projection of the gate of the driving transistor and the active layer on the base substrate.

20. A display panel, comprising: substrate substrate; The pixel circuit according to claim 1 is located on the substrate; A pixel definition layer located on a side of the pixel circuit away from the base substrate, wherein the pixel definition layer defines a first light emitting region of the first light emitting element and a second light emitting region of the second light emitting element; as well as an optical structure located on a side of the pixel definition layer away from the substrate, The optical structure is optically coupled to the first light emitting area to suppress propagation of light from the first light emitting element in a first emission direction that is not perpendicular to a light emitting surface of the display panel.

21. A display panel according to 20, wherein the optical structure comprises a light absorbing layer, the light absorbing layer at least partially surrounds the first light emitting area, and the orthographic projection of the light absorbing layer on the base substrate does not overlap with the orthographic projection of the second light emitting area on the base substrate.

22. The display panel according to claim 21, wherein the display panel further comprises an encapsulation layer located on a side of the pixel definition layer away from the base substrate, wherein the optical structure further comprises a light-transmitting layer, the light-absorbing layer comprises a first sub-light-absorbing layer and a second sub-light-absorbing layer, the first sub-light-absorbing layer is located on a side of the encapsulation layer away from the base substrate, the light-transmitting layer covers the first sub-light-absorbing layer, and the second sub-light-absorbing layer is located on a side of the light-transmitting layer away from the base substrate.

23. The display panel according to claim 22, wherein the light-transmitting layer comprises a first light-transmitting portion and a second light-transmitting portion, the first light-transmitting portion is located on a side of the first sub-light-absorbing layer away from the base substrate, the second light-transmitting portion is located on a side of the first light-transmitting portion away from the base substrate, the second light-transmitting portion covers the first light-transmitting portion, and a refractive index of the second light-transmitting portion is higher than a refractive index of the first light-transmitting portion.

24. A display panel according to claim 20, wherein the display panel further comprises an encapsulation layer located on a side of the pixel definition layer away from the base substrate, the optical structure comprises a microlens located on a side of the encapsulation layer away from the base substrate, and the microlens is configured to converge light from the first light-emitting element.

25. A display device comprising the display panel according to claim 11 or claim 20.

Images