Memories, memory cell arrays, and cascaded adders that support in-memory computation

Abstract

The embodiments of the present application provide a memory, a memory array and a cascade adder supporting in-memory calculations, including: a memory cell array and a read-write unit and a bit line shared by the memory cells on the same column in the memory cell array. Among them, a column of memory cells is divided into multiple groups, and the same bit line shared by a column of memory cells is provided with a switching circuit corresponding to each of the multiple groups of memory cells, so that the switching circuit can control the on or off state of a group of memory cells. Then, when data is read and written to a target memory cell with a target address in the memory, the switching circuit corresponding to the target group memory cell containing the target memory cell is closed to turn on the memory cells in the target group memory cells, and the switching circuits corresponding to the other groups of memory cells are disconnected to put the other memory cells in the off state. It can be seen that when reading and writing data, the disconnection of some memory cells in the memory cell array can obviously reduce the power consumption of the memory.

Description

Technical Field

[0001] The present application relates to the field of memory, and in particular to a memory supporting in-memory computing, a storage cell array, and a cascade adder. Background Art

[0002] With the rapid development of cloud computing and artificial intelligence, the current data processing demand is growing at an unprecedented scale. This growth has put forward higher requirements on the host's computing resources, such as memory and central processing unit (CPU).

[0003] In practice, the memory in the host can be modified to achieve in-memory computing (IMC). Since in-memory computing is to perform calculation operations directly in the storage unit of the memory without transferring data from the storage unit to the processing unit for calculation, it can reduce the time required for data transmission, thereby improving the data processing performance of the host.

[0004] On this basis, while using memory to implement in-memory computing, how to reduce the power consumption of memory becomes an urgent problem to be solved. Summary of the invention

[0005] In view of this, various aspects of the present application provide a memory, a storage cell array, and a cascade adder that support in-memory computing, so as to improve data processing efficiency while reducing the power consumption of the processor.

[0006] The embodiment of the present application provides a memory supporting in-memory computing, comprising: an electrically connected control circuit and a memory cell array, and a data read / write unit and a bit line shared by a column of memory cells in the memory cell array;

[0007] There is an electrical connection between the data read / write unit shared by the column of memory cells and the bit line, and a plurality of switch circuits are arranged on the bit line shared by the column of memory cells; the column of memory cells includes a plurality of groups of memory cells, and the switch states of the memory cells in different groups are respectively controlled by different switch circuits; any memory cell in the memory cell array is electrically connected to the word line corresponding to the any memory cell;

[0008] The control circuit is used to control the switch circuit corresponding to the first storage unit with the first address to close according to the read / write signal including the first address, so that a group of storage units including the first storage unit is in a conducting state; control other switch circuits to open, so that other groups of storage units not including the first storage unit are in a disconnected state; and set the word line electrically connected to the first storage unit to a high level according to the read / write signal;

[0009] The data reading and writing unit is used to receive the data to be read and written in the reading and writing signal;

[0010] A common bit line of a column of memory cells including the first memory cell is used to respond to the read / write signal according to the level value of the bit line when the word line is set to a high level, so as to read and write the first memory cell according to the data to be read and written.

[0011] The embodiment of the present application provides a memory supporting in-memory computing, comprising: an electrically connected control circuit and a memory cell array, a data read-write unit shared by a column of memory cells in the memory cell array, and a cascade adder electrically connected to the memory cell array; a weight value is stored in any memory cell;

[0012] The control circuit is used to output a calculation signal including a plurality of addresses, wherein the plurality of addresses include a first address, a second address, a third address and a fourth address;

[0013] According to the calculation signal, the switch circuit is controlled to be closed, so that the first storage unit with the first address and the second storage unit with the second address are in a conducting state, so that the third storage unit with the third address and the fourth storage unit with the fourth address are in a conducting state; the switch circuit is controlled to be opened, so that at least one group of storage units not including the first storage unit to the fourth storage unit is in a disconnected state, wherein the first storage unit to the fourth storage unit are respectively included in the same group or different groups of storage units;

[0014] A first-stage adder in the cascade adder is used to query a weighted summation result of the first value to be calculated and the second value to be calculated in a lookup table according to the weight value in the first storage unit, the weight value in the second storage unit, and the first value to be calculated and the second value to be calculated in the calculation signal, wherein the value to be calculated in the calculation signal and the weight value in the storage unit are binary data, and the lookup table includes a weighted summation result obtained by combining different values ​​to be calculated and different weight values ​​in the storage unit;

[0015] Another first-stage adder in the cascade adder is used to query a weighted sum result of the third value to be calculated and the fourth value to be calculated in a lookup table according to the weight value in the third storage unit, the weight value in the fourth storage unit, and the third value to be calculated and the fourth value to be calculated in the calculation signal;

[0016] The second-stage adder in the cascade adder is used to calculate the weighted summation results output by different first-stage adders.

[0017] The embodiment of the present application provides a memory cell array, wherein a column of memory cells in the memory cell array shares a data read / write unit and a bit line; any memory cell in the memory cell array is electrically connected to a word line corresponding to the any memory cell;

[0018] There is an electrical connection between the data read / write unit shared by the column of memory cells and the bit line, and a plurality of switch circuits are arranged on the bit line shared by the column of memory cells; the column of memory cells includes a plurality of groups of memory cells, and the switch states of the memory cells in different groups are respectively controlled by different switch circuits;

[0019] The control circuit is used to control the switch circuit corresponding to the first storage unit with the first address to close according to the read / write signal including the first address, so that a group of storage units including the first storage unit is in a conducting state; control other switch circuits to open, so that other groups of storage units not including the first storage unit are in a disconnected state; and set the word line electrically connected to the first storage unit to a high level according to the read / write signal;

[0020] The data reading and writing unit is used to receive the data to be read and written in the reading and writing signal;

[0021] A common bit line of a column of memory cells including the first memory cell is used to respond to the read / write signal according to the level value of the bit line when the word line is set to a high level, so as to read and write the first memory cell according to the data to be read and written.

[0022] The embodiment of the present application provides a cascade adder, comprising: a first-stage adder and a second-stage adder, wherein the second-stage adder comprises a zero-value detection circuit, an OR gate, and an adder unit;

[0023] Any first-stage adder, used to output a calculation result in response to a calculation signal;

[0024] The zero value detection circuit is used to determine whether the weighted summation results output by different first-stage adders contain a zero value;

[0025] If the weighted summation results outputted by the different first-stage adders contain a zero value, a high-level OR gate enable signal is outputted, and a low-level adder enable signal is outputted;

[0026] If the weighted summation results output by different first-stage adders do not contain a zero value, a low-level OR gate enable signal is output, and a high-level adder enable signal is output;

[0027] The OR gate is used to perform an OR logic operation on the non-zero weighted summation results in the different first-stage adders after being activated by a high-level OR gate enable signal;

[0028] The adder unit is used to sum the weighted summation results output by the different first-stage adders after being activated by a high-level adder enable signal.

[0029] The memory supporting in-memory computing provided by the embodiment of the present application includes: an electrically connected control circuit and a memory cell array, and a data read-write unit and a bit line shared by a column of memory cells in the memory cell array. Among them, there is also an electrical connection between the shared data read-write unit and the bit line. And a plurality of switch circuits can be provided on the bit line shared by a column of memory cells. A column of memory cells can be divided into a plurality of groups, and the switch states of the memory cells in different groups are respectively controlled by different switch circuits. The switch circuit is used to control the switch state of a group of memory cells; any memory cell in the memory cell array is electrically connected to the word line corresponding to any memory cell.

[0030] For a memory having the above structure, when a read / write signal is generated for a memory cell having a certain address in a memory cell array, the control circuit can generate a read / write signal including the address to control the switch circuit of the memory cell to close, so that a group of memory cells including the memory cell is in a conducting state. At the same time, the control circuit can also control the switch circuits of other groups of memory cells in the memory cell array to be disconnected, so that the memory cells in other groups are in a disconnected state.

[0031] That is to say, the memory provided in the embodiment of the present application can perform more precise control on the switch state of the memory cell by grouping the memory cells and setting corresponding switch circuits for the memory cells in different groups. When reading and writing data, the memory cell related to the read and write signal is in the on state, while the other memory cells are in the off state. Compared with all the memory cells being on, this can obviously reduce the power consumption of the memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0033] Figure 1a A schematic diagram of the structure of a memory supporting in-memory computing provided in an embodiment of the present application;

[0034] Figure 1b for Figure 1a Schematic diagram of the data reading and writing process of the memory shown;

[0035] Figure 2 A schematic diagram of the structure of another memory supporting in-memory computing provided in an embodiment of the present application;

[0036] Figure 3 A schematic diagram of the structure of another memory supporting in-memory computing provided in an embodiment of the present application;

[0037] Figure 4 A schematic diagram of the structure of another memory supporting in-memory computing provided in an embodiment of the present application;

[0038] Figure 5a A schematic diagram of the structure of a cache unit in a memory supporting in-memory computing provided in an embodiment of the present application;

[0039] Figure 5b A schematic diagram of the structure of a cascade adder in a memory supporting in-memory computing provided in an embodiment of the present application;

[0040] Figure 6 A schematic diagram of the structure of a storage cell array provided in an embodiment of the present application;

[0041] Figure 7 A schematic diagram of the structure of a cascade adder provided in an embodiment of the present application;

[0042] Figure 8 A schematic diagram of the structure of another memory supporting in-memory computing provided in an embodiment of the present application. DETAILED DESCRIPTION

[0043] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0044] The terms used in the embodiments of the present application are only for the purpose of describing specific embodiments, and are not intended to limit the present application. The singular forms of "a", "said", and "the" used in the embodiments of the present application and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings, and "multiple" generally includes at least two, but does not exclude the inclusion of at least one.

[0045] It should be understood that the term "and / or" used in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0046] As used herein, the words "if" and "if" may be interpreted as "at the time of" or "when" or "in response to determining" or "in response to identifying", depending on the context. Similarly, the phrases "if it is determined" or "if (stated condition or event) is identified" may be interpreted as "when determining" or "in response to determining" or "when identifying (stated condition or event)" or "in response to identifying (stated condition or event)", depending on the context.

[0047] It should be noted that, in the case where the embodiments of the present application involve user information, the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in the embodiments of the present application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data need to comply with the relevant laws, regulations and standards of the relevant countries and regions, and provide corresponding operation entrances for users to choose to authorize or refuse.

[0048] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a product or system including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such a product or system. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the product or system including the elements.

[0049] Some embodiments of the present application may be described in detail below in conjunction with the accompanying drawings. In the case where there is no conflict between the embodiments, the following embodiments and the features in the embodiments may be combined with each other. In addition, the step sequence in the following method embodiments is only an example and not a strict limitation.

[0050] A memory supporting in-memory computing provided by an embodiment of the present application may include a memory cell array, and there is an electrical connection between different memory cells in the memory cell array and their corresponding word lines (Word Line, WL for short). A column of memory cells in the memory cell array may also share a bit line and also share a data read and write unit. The shared bit line is also a global bit line (Global Bit Line, GBL for short), and there is also an electrical connection between the data read and write units of the bit line shared by a column of memory cells. At the same time, a column of memory cells may also be divided into a plurality of memory cell sub-arrays, and a memory cell sub-array may include a plurality of groups of memory cells, wherein the memory cells in a memory cell sub-array share a local bit line (Local Bit Line, LBL for short), and a plurality of switch circuits may also be provided on the global bit line and the local bit line shared by a column of memory cells, and a switch circuit is used to control the switch state of each memory cell of at least one group of memory cells in a memory cell sub-array. Optionally, a common method is that a switch is used to control the switch state of a memory cell in a group of memory cells.

[0051] Figure 1a A schematic diagram of the structure of a memory supporting in-memory computing provided in an embodiment of the present application. Figure 1a As shown, assuming that the size of the memory cell array in the memory is 3N*M, the number of memory cells in a column is 3N, and the 3N memory cells can constitute a memory cell subarray, then a column of memory cells can be divided into 3 groups, and a group contains N memory cells, and the memory cells in the 3 groups are numbered 1...N, N+1...2N, 2N+1...3N respectively. Three switch circuits are set on the bit line shared by each memory cell in the column of memory cells, which can be respectively called switch circuit 1~switch circuit 3, and the three switch circuits are used to separate the three groups of memory cells. A switch circuit is responsible for controlling the switch state of N memory cells in a group of memory cells. Among them, there is no size relationship between M and N.

[0052] It needs to be explained that: Figure 1a It only illustrates a size of a memory cell array, and the present application does not limit the size of the memory cell array, the number of memory cell groups, the number of memory cells contained in a group of memory cells, and the number of memory cells controlled by a switch circuit.

[0053] It should be noted that the following embodiments of the present application all take a column of memory cells including a memory cell sub-array as an example to illustrate the working process of the memory.

[0054] Based on the above introduction to each part of the memory, the data reading and writing process of the memory can be described as follows:

[0055] The control circuit in the memory can generate a read / write signal including a first address. Furthermore, the control circuit can respond to the read / write signal to control the switch circuit corresponding to the first storage unit with the first address to close, so that a group of storage units including the first storage unit are all in a conducting state. The control circuit can also control the switch circuits corresponding to other groups of storage units in the storage unit array that do not include the first storage unit to be disconnected, so that the storage units in the other groups of storage units are all in a disconnected state. At the same time, the control circuit can set the word line electrically connected to the first storage unit to a high level.

[0056] At the same time, the read / write signal generated by the control circuit can be input into the data read / write unit, so that the data read / write unit can obtain the data to be read / written in the read / write signal. And when the word line is at a high level, the global bit line shared by a column of storage cells including the first storage cell can respond to the read / write signal according to its own level value, thereby reading and writing the data of the first storage cell according to the data to be read / written in the read / write signal.

[0057] The above data reading and writing process can also be combined with Figure 1b Understand. Figure 1b As shown, assuming that the first storage unit is the storage unit numbered N in the first group of storage units, the control circuit can control the switch circuit 1 to be closed, and the switch circuit 2 to the switch circuit 3 to be disconnected, so that the storage units numbered 1 to N in the 3N storage units are in the on state, and the storage units numbered N+1 to 3N are in the off state. And the word line of the storage unit numbered N is set to a high level, and the bit line can read and write data according to its own level value.

[0058] Optionally, the global bit line can read and write data according to the level value of its positive and negative electrodes. The high and low level values ​​of the positive electrode of the bit line can be defined by the Global Bit Line Positive (GBLP) signal, and the high and low level values ​​of the negative electrode of the bit line can be defined by the Global Bit Line Negative (GBLN) signal.

[0059] Then, when the read / write signal is specifically a data write signal, when the positive electrode of the global bit line connected to the first storage unit is charged to a high level, that is, the GBLP signal is at a high level, and the negative electrode is charged to a low level, that is, the GBLN signal is at a low level, then the global bit line can write a first binary value into the first storage unit, such as 1. When the positive electrode of the global bit line connected to the first storage unit is charged to a low level, that is, the GBLP signal is at a low level, and the negative electrode is charged to a high level, that is, the GBLN signal is at a high level, then the global bit line can write a second binary value into the first storage unit, such as 0.

[0060] Optionally, when the read / write signal is specifically a data read signal, when the positive electrode of the global bit line connected to the first storage unit is at a high level, that is, the GBLP signal is at a high level, and the negative electrode is at a low level, that is, the GBLN signal is at a low level, then the global bit line can read a first binary value from the first storage unit, such as 1. When the positive electrode of the global bit line connected to the first storage unit is at a low level, that is, the GBLP signal is at a low level, and the negative electrode is at a high level, that is, the GBLN signal is at a high level, then the global bit line can read a second binary value from the first storage unit, such as 0.

[0061] In this embodiment, when the data read / write unit generates a read / write signal to a memory cell with a certain address in the memory cell array, the control circuit can control the switch circuit corresponding to the memory cell to close, so that a group of memory cells including the memory cell is in a conducting state. At the same time, the control circuit can also control the switch circuits of other groups of memory cells in the memory cell array to open, so that the memory cells in other groups are in a disconnected state.

[0062] That is to say, the memory provided in this embodiment can control the switch state of the memory cell more finely by grouping the memory cells and setting corresponding switch circuits for the memory cells in different groups. When reading and writing data, the memory cell related to the read and write signal is in the on state, while the other memory cells are in the off state. Compared with all the memory cells being on, this can obviously reduce the power consumption of the memory.

[0063] Figure 2 A schematic diagram of the structure of another memory supporting in-memory computing provided in an embodiment of the present application. Figure 1a Based on the embodiment shown, the memory may optionally further include a precharge circuit and a power supply for the memory cell array. The precharge circuit is used to charge the positive and negative electrodes of the bit lines to corresponding level values ​​to write data into the memory cells.

[0064] Specifically, in one case, the precharge circuit can charge the positive electrode of the global bit line connected to the first storage unit to a high level, and charge the negative electrode of the bit line to a low level, so that the bit line can write a first binary value into the storage unit, such as writing 1. In another case, the precharge circuit can also charge the positive electrode of the global bit line connected to the first storage unit to a low level, and charge the negative electrode of the bit line to a high level, so that the bit line can write a second binary value into the first storage unit, such as writing 0.

[0065] In this embodiment, the precharge circuit in the memory can charge the positive and negative electrodes of the global bit line so that the positive and negative electrodes of the bit line have corresponding level values ​​to achieve data writing. In addition, the contents not described in detail in this embodiment and the technical effects that can be achieved can be referred to the description of the above embodiments, and will not be repeated here.

[0066] Figure 3 A schematic diagram of the structure of another memory supporting in-memory computing provided in an embodiment of the present application. Figure 2 The circuit structure of each component included in the memory in the illustrated embodiment is described in detail. Figure 3 The present invention is a specific circuit diagram of a column of memory cells and a switch circuit on the column of memory cells.

[0067] Alternatively, if Figure 3 As shown, any memory cell in the memory cell array may include: a first N-type field effect transistor, a second N-type field effect transistor and a latch. The N-type field effect transistor is also an N-type metal oxide semiconductor (Negative channel Metal Oxide Semiconductor, referred to as NMOS). Optionally, the latch may be composed of two inverters. Among them, the connection relationship between the devices in the memory cell can be described as:

[0068] The gate electrodes (G electrodes) of the first N-type field effect transistor and the second N-type field effect transistor are respectively connected to a word line connected to any storage unit.

[0069] The source (S pole) of the first N-type field effect transistor is connected to the negative pole of the bit line connected to any memory cell, and the source (S pole) of the second N-type field effect transistor is connected to the positive pole of the local bit line connected to any memory cell.

[0070] The drain (D pole) of the first N-type field effect transistor is connected to the positive output end of the latch, and the drain (D pole) of the second N-type field effect transistor is connected to the negative output end of the latch.

[0071] Alternatively, if Figure 3 As shown, any switch circuit in the memory may include: a third N-type field effect transistor and a fourth N-type field effect transistor. The connection relationship between the components in the switch circuit can be described as:

[0072] The gate electrodes (G electrodes) of the third N-type field effect transistor and the fourth N-type field effect transistor are connected to each other.

[0073] The drain (D pole) and source (S pole) of the third N-type field effect transistor and the fourth N-type field effect transistor are respectively connected to a global bit line or a local bit line connected to any memory cell.

[0074] More specifically, a switch circuit is deployed between two groups of memory cells in a memory cell subarray, and the drain (D pole) and source (S pole) of the third N-type field effect transistor and the fourth N-type field effect transistor in the switch circuit are respectively connected to the local bit lines of the memory cells.

[0075] A switch circuit is deployed between a first group of memory cells in a memory cell subarray, wherein the drain (D pole) and source (S pole) of the third N-type field effect transistor and the fourth N-type field effect transistor in the switch circuit are connected to the global bit lines corresponding to the first group of memory cells.

[0076] Alternatively, if Figure 3 As shown, the pre-charging circuit may include: a first P-type field effect transistor and a second P-type field effect transistor. The P-type field effect transistor is also a P-type metal oxide semiconductor (Positive channel Metal Oxide Semiconductor, referred to as PMOS). Among them, the connection relationship between the components in the pre-charging circuit can be described as:

[0077] The gates (G poles) of the first P-type field effect transistor and the second P-type field effect transistor are connected. The source (S pole) of the first P-type field effect transistor is connected to the negative pole of the local bit line, and the source (S pole) of the second P-type field effect transistor is connected to the positive pole of the local bit line. The drains (D poles) of the first P-type field effect transistor and the second P-type field effect transistor are respectively connected to the power supply (VDDC).

[0078] In this embodiment, the storage unit, the switch circuit and the pre-charge circuit in the memory may have Figure 3 The structure shown can realize data reading and reduce the power consumption of the memory. In addition, the contents not described in detail in this embodiment and the technical effects that can be achieved can be referred to the description of the above embodiments, and will not be repeated here.

[0079] Figure 4 A schematic diagram of the structure of another memory supporting in-memory computing provided in an embodiment of the present application. Figure 2 Based on the memory shown, optionally, as Figure 4 As shown, the memory may further include a cascade adder electrically connected to the memory cell array.

[0080] In this embodiment, the introduction of the cascade adder enables the memory to realize data calculation while realizing data reading and writing. Optionally, in this embodiment, the storage unit of the memory stores weight values, and the data calculation process of the memory can occur during the training or use of the neural network model. The cascade adder may include multiple first-level adders and multiple second-level adders. Any adder in the first-level adder may be an adder with multiple input terminals, which is used to perform weighted summation of multiple values ​​to be calculated and multiple weight values, and any adder in the second-level adder may be an adder with multiple input terminals, which is used to calculate multiple numerical values. Optionally, any first-level adder may be an adder with two input terminals, which is used to perform weighted summation of multiple values ​​to be calculated and multiple weight values. Any second-level adder may also be an adder with two input terminals, which is used to calculate two numerical values.

[0081] The process of data calculation in the memory can be described as:

[0082] The control unit may input and the control unit may output a calculation signal including a plurality of addresses.

[0083] Wherein, when the first-stage adder has two input terminals, the multiple addresses may specifically include a first address, a second address, a third address and a fourth address. The first storage unit with the first address and the second storage unit with the second address may be located in the same group or in different groups, and the third storage unit with the third address and the fourth storage unit with the fourth address may also be located in the same group or in different groups.

[0084] Afterwards, the control circuit can control the opening and closing of the switch circuit so that the first storage unit to the fourth storage unit are all in the on state.

[0085] Furthermore, one of the first-stage adders in the cascade adder can query the weighted sum of the first value to be calculated and the second value to be calculated in the lookup table according to the weight value in the first storage unit, the weight value in the second storage unit, and the first value to be calculated and the second value to be calculated in the calculation signal. Another first-stage adder in the cascade adder is used to query the weighted sum of the third value to be calculated and the third value to be calculated in the lookup table according to the weight value in the third storage unit, the weight value in the fourth storage unit, and the third value to be calculated and the fourth value to be calculated in the calculation signal.

[0086] Wherein, the value to be calculated in the calculation signal and the weight value in the storage unit are binary data. The lookup table includes a plurality of weighted summation results obtained by combining different values ​​to be calculated and different weight values ​​in the storage unit. Optionally, the value to be calculated in the calculation signal can be 1-bit binary data, and the weight value can be 4-bit binary data, then the weighted summation result queried through the lookup table is 5-bit binary data.

[0087] For the table lookup calculation process of the first-stage adder, for example, when the value to be calculated is 1-bit binary data, that is, the value to be calculated can be 1 or 0, the first count value in the calculation signal is represented by IN0, and the second count value is represented by IN1. For a first-stage adder with two input terminals, the weight value in the first storage unit is represented by W0, and the weight value stored in the second storage unit is represented by W1, where W0 can be 0 or A, and W1 can be 0 or B.

[0088] Then the lookup table used by a first-stage adder can be shown in Table 1 below:

[0089] Table 1:

[0090]

[0091] Similarly, when the value to be calculated is 1-bit binary data, that is, the value to be calculated can be 1 or 0, the third count value in the calculation signal is represented by IN2, and the fourth count value is represented by IN3. For another first-stage adder with two input terminals, the weight value stored in the third storage unit is represented by W2, and the weight value stored in the fourth storage unit is represented by W3, where W2 can be 0 or C, and W3 can be 0 or D.

[0092] Then the lookup table used by another first-stage adder can be shown in Table 2 below:

[0093] Table 2:

[0094]

[0095] After the first-stage addition is completed, the second-stage adder in the cascade adder may be further used to calculate, that is, sum, the weighted summation results outputted by the different first-stage adders.

[0096] Optionally, after the second-stage adder, the cascade adder may further include adders of subsequent levels. For example, the third-stage adder and the fourth-stage adder, and so on. The third-stage adder may further sum the summed results of the respective outputs of the second-stage adders. The fourth-stage adder may further sum the summed results of the respective outputs of the third-stage adders. Optionally, assuming that any one-stage adder in the cascade adder has two input terminals, the number of adders in the latter stage is half the number of adders in the previous stage. For example, there are 4N storage unit groups, each of which contains M storage units, then the number of first-stage adders in the cascade adder may be 2N, the number of second-stage adders may be N, and so on, and the number of stages of the cascade adder may be K = 2 + log2 (N).

[0097] Finally, the calculation result output by the last adder in the cascade adder is the calculation result of the calculation signal.

[0098] It needs to be explained that: Figure 1a The data reading and writing process described in the embodiment and the data calculation process described in the embodiment can be two independent processes. Figure 1a The first storage unit mentioned in the illustrated embodiment and the first to fourth storage units mentioned in this embodiment may be different storage units.

[0099] In this embodiment, the memory can use a multi-stage adder to implement data calculation, and the first-stage addition operation is implemented by table lookup rather than direct calculation. Compared with direct calculation, table lookup has a faster speed, so the speed of the first-stage addition operation can be increased, thereby also increasing the overall calculation speed of the memory. And when performing data calculation, the control circuit can also control the closure of the corresponding switch circuit, so that at least one group of storage cells to which the storage cells participating in the calculation in the storage cell array belong is in a conducting state, and the remaining storage cells are in a disconnected state, thereby reducing the power consumption of the memory.

[0100] In addition, the contents not described in detail in this embodiment and the technical effects that can be achieved can be found in the description of the above-mentioned related embodiments and will not be repeated here.

[0101] Alternatively, if Figure 4As shown, the memory may also include a cache unit (Load / Store Unit, LSU for short) connected to a column of storage cells, and the cache unit and the column of storage cells are electrically connected to the same bit line. When performing data calculation, the control circuit may set the bit lines connected to the first storage unit to the fourth storage unit to a high level according to the calculation signal, and after the bit lines connected to the storage units are set to a high level, the control unit may read the weight values ​​stored in the first storage unit to the fourth storage unit into the cache unit. Among them, a column of storage cells corresponds to a cache unit.

[0102] Alternatively, if Figure 4 As shown, the second-stage adder may specifically include a zero value detection circuit, an OR gate, an adder unit, and a selector. Optionally, in the cascade adder, except for the first-stage adder, the second-stage adder and the adders of the subsequent layers may have the same structure. The working process of the second-stage adder may be described in detail below.

[0103] The zero value detection circuit can determine whether the weighted summation results output by different first-stage adders contain a zero value. Generally speaking, the zero value detection circuit determines whether the weighted summation results output by two first-stage adders contain a zero value. The weighted summation results output by the two first-stage adders are the inputs of the second-stage adder.

[0104] In one case, if the weighted summation results output by different first-stage adders contain a zero value, the zero-value detection circuit outputs a high-level OR gate enable signal and a low-level adder enable signal. At this time, the high-level OR gate enable signal can activate the OR gate, thereby performing an OR logic operation on the weighted summation results that are not zero in different first-stage adders to output the logic operation result. At the same time, although the adder unit is not activated, the adder unit can output a value.

[0105] In another case, if the weighted summation results output by different first-stage adders do not contain zero values, the zero-value detection circuit outputs a low-level OR gate enable signal and outputs a high-level adder enable signal. At this time, the high-level adder enable signal can activate the adder unit, thereby summing the weighted summation results output by different first-stage adders to output the summation result. At the same time, although the NOT gate is not activated, the NOT gate can output a value.

[0106] Since the value output by the unactivated adder unit or OR gate is an abnormal value that can be identified by a selector, when the OR gate is activated, the selector outputs the logical operation result of the OR gate output; when the adder unit is activated, the selector outputs the summation result of the adder unit output.

[0107] In this embodiment, a zero value detection circuit and an OR gate are introduced. When a zero value exists in the weighted summation result output by the first-stage adder, no calculation is required, and the non-zero weighted summation result can be directly used as the output of the second-stage adder, thereby improving the calculation efficiency of the memory. When a zero value does not exist in the weighted summation result output by the first-stage adder, calculation is required.

[0108] In summary, for the memory provided by the above embodiments of the present application, on the one hand, the storage cells in the memory are grouped so that the switch circuit can perform more precise control on the switch state of the storage cell. Then, when data is read and written, the storage cells related to the read and write signals are in the on state, while other storage cells are in the off state, thereby reducing the power consumption of the memory. On the other hand, the first-level addition operation can be implemented by table lookup, thereby improving the calculation speed of the first-level addition. When the detection result output by the zero value detection circuit is "the weighted sum result is not zero", the second-level adder can directly output the result without calculation, thereby improving the calculation speed of the second-level addition. It can be seen that the use of the memory provided by the present application can improve the speed of different-level calculations in different ways, and can also improve the overall calculation speed of the memory.

[0109] Figure 5a A schematic diagram of the structure of a cache unit in a memory supporting in-memory computing provided in an embodiment of the present application. Figure 5b The structural diagram of the cascade adder in the memory supporting in-memory computing provided by the embodiment of the present application is as follows: Figure 3 Based on the circuit diagram shown in FIG. Figure 4 The circuit structure of each component included in the memory in the illustrated embodiment is described in detail.

[0110] Alternatively, if Figure 5a As shown, the cache unit electrically connected to a column of memory cells in the memory cell array may include: two three-input NAND gates and two two-input NAND gates.

[0111] Wherein, a first input terminal of any three-input NAND gate is connected to a bit line shared by the column of storage cells.

[0112] The second input terminal of any three-input NAND gate is connected to the output terminal of another three-input NAND gate.

[0113] The first input terminal of any two-input NAND gate is connected to the output of any three-input NAND gate.

[0114] The second input terminal of any two-input NAND gate is connected to the output terminal of the other two-input NAND gate.

[0115] Alternatively, if Figure 5bAs shown, the zero-value detection circuit in the second-stage adder may include: a plurality of first-stage NOR gates and a second-stage NOR gate.

[0116] Among them, any first-stage NOR gate is used to input the weighted summation result output by any first-stage adder; and perform a NOR logic operation on the weighted summation result.

[0117] The second-level NOR gate is used to perform NOR logic operation on the output results of different first-level NOR gates. If the NOR logic operation result is a zero value, a high-level OR gate enable signal is output and a low-level adder enable signal is output. If the NOR logic operation result is a non-zero value, a low-level OR gate enable signal is output and a high-level adder enable signal is output.

[0118] Alternatively, if Figure 5b As shown, the OR gate in the second-stage adder can also be electrically connected to an N-type field effect transistor and a P-type field effect transistor respectively.

[0119] The drain of the N-type field effect transistor is connected to the OR gate, and the source of the N-type field effect transistor is grounded. The drain of the P-type field effect transistor is connected to the OR gate, and the source of the P-type field effect transistor is connected to the power supply, wherein the power supply can be Figure 2 or Figure 4 The power supply of the memory cell array shown in FIG. The gates of the N-type field effect transistor and the P-type field effect transistor are respectively connected to the second-stage NOR gate in the zero value detection circuit.

[0120] The high-level OR gate enable signal output by the second-stage NOR gate can be applied to the gates of the P-type field effect transistor and the N-type field effect transistor to turn on the P-type field effect transistor and the N-type field effect transistor electrically connected to the OR gate. At this time, the OR gate can perform an OR logic operation on the weighted calculation results output by different first-stage adders.

[0121] Alternatively, if Figure 5b As shown, the adder unit in the second-stage adder can also be electrically connected to an N-type field effect transistor and a P-type field effect transistor respectively.

[0122] The drain of the N-type field effect tube is connected to the adder unit, and the source of the N-type field effect tube is grounded. The drain of the P-type field effect tube is connected to the adder unit, and the source of the P-type field effect tube is connected to the power supply, wherein the power supply can be Figure 2 or Figure 4 The power supply of the memory cell array shown in FIG. The gates of the N-type field effect transistor and the P-type field effect transistor are respectively connected to the second-stage NOR gate in the zero value detection circuit.

[0123] The high-level adder enable signal output by the second-stage NOR gate can be applied to the gates of the P-type field effect transistor and the N-type field effect transistor to turn on the P-type field effect transistor and the N-type field effect transistor electrically connected to the adder unit. At this time, the adder unit can sum the weighted calculation results output by different first-stage adders.

[0124] Alternatively, if Figure 5b As shown, different input terminals of the selector are electrically connected to the output terminals of the adder unit and the OR gate respectively.

[0125] In this embodiment, the circuit structure of the cache unit and the second-stage adder in the memory can be as follows: Figure 5b As shown, this structure can improve the calculation speed of data.

[0126] In addition, for other contents not described in detail in this embodiment and the beneficial effects that can be achieved, please refer to the relevant descriptions in the above embodiments, which will not be repeated here.

[0127] Figure 6 A schematic diagram of the structure of a storage cell array provided in an embodiment of the present application.

[0128] like Figure 6 As shown, a column of memory cells in a memory cell array shares a data read / write unit and a bit line, and any memory cell in the memory cell array is electrically connected to a word line corresponding to any memory cell; and there is also an electrical connection between the data read / write units of the bit line shared by a column of memory cells. At the same time, a column of memory cells can also be divided into multiple memory cell sub-arrays, and a memory cell sub-array can include multiple groups of memory cells, wherein the memory cells in a memory cell sub-array share a local bit line, and multiple switch circuits can be arranged on the global bit line and the local bit line shared by a column of memory cells, and a switch circuit is used to control the switch state of each memory cell of at least one group of memory cells in a memory cell sub-array.

[0129] The control circuit can control the switch circuit corresponding to the first storage unit with the first address to close according to the read-write signal containing the first address, so that a group of storage units containing the first storage unit is in a conductive state. The control circuit can also control other switch circuits to be disconnected, so that other groups of storage units that do not contain the first storage unit are in a disconnected state. The control circuit can also set the word line electrically connected to the first storage unit to a high level according to the read-write signal. At the same time, the read-write signal generated by the control circuit can be input into the data read-write unit, so that the data read-write unit obtains the data to be read and written in the read-write signal. And the global bit line can respond to the read-write signal according to the level value of the global bit line when the word line is set to a high level, so as to read and write the first storage unit according to the data to be read and written.

[0130] In addition, when performing calculations, the control circuit can also control the switch circuit corresponding to the storage unit related to the calculation signal to be closed, and control the switch circuit corresponding to the storage unit not related to the calculation signal to be opened.

[0131] In this embodiment, by grouping the storage cells and respectively setting corresponding switch circuits for the storage cells of different groups, the switch state of the storage cells can be more finely controlled. When reading or writing data or calculating data, the control circuit can control the switch circuit corresponding to the storage cell related to the read / write signal or the calculation signal to close, so that a group of storage cells including the storage cell is in a conducting state. At the same time, the control circuit can also control the switch circuits of other groups of storage cells in the storage cell array to be disconnected, so that the storage cells in other groups are in a disconnected state. Compared with all storage cells being turned on, this can obviously reduce the power consumption of the memory.

[0132] In addition, the process of using this storage cell array to read, write and calculate data can refer to the description in the above-mentioned related embodiments, which will not be repeated here.

[0133] Figure 7 A schematic diagram of the structure of a cascade adder provided in an embodiment of the present application. Figure 7 As shown, the cascade adder may include a first-stage adder and a second-stage adder. The second-stage adder may specifically include a zero-value detection circuit, an OR gate, and an adder unit.

[0134] Wherein, any first-stage adder is used to output a calculation result in response to a calculation signal.

[0135] The zero value detection circuit is used to determine whether the calculation results output by different first-stage adders respectively as inputs of the second-stage adder contain a zero value.

[0136] In one case, if the calculation results output by different first-stage adders contain a zero value, a high-level OR gate enable signal is output and a low-level adder enable signal is output. At this time, the OR gate is activated by the high-level NOR gate enable signal, thereby performing an OR logic operation on the calculation results that are not zero in different first-stage adders.

[0137] In another case, if the calculation results output by different first-stage adders do not contain a zero value, a low-level OR gate enable signal is output and a high-level adder enable signal is output. At this time, the adder unit can be activated by the high-level adder enable signal to sum the calculation results output by different first-stage adders.

[0138] In this embodiment, the memory can use a multi-stage adder to realize data calculation. The first-stage addition operation is realized by table lookup rather than direct calculation. Compared with direct calculation, table lookup has a faster speed, so the speed of the first-stage addition operation can be improved, thereby also improving the overall calculation speed of the memory. In addition, a zero value detection circuit and an OR gate are introduced. When there is a zero value in the weighted summation result output by the first-stage adder, there is no need to calculate, and the non-zero weighted summation result can be directly used as the output of the second-stage adder, thereby improving the speed of the second-stage addition operation of the memory. At the same time, when performing data calculation, the control circuit can also control the closure of the corresponding switch circuit, so that at least one group of storage cells to which the storage cells participating in the calculation in the storage cell array belong is in a conducting state, and the remaining storage cells are in a disconnected state, thereby reducing the power consumption of the memory.

[0139] In addition, for the contents not described in detail in this embodiment and the beneficial effects that can be achieved, please refer to the relevant descriptions in the above embodiments, and will not be repeated here.

[0140] Figure 8 A schematic diagram of the structure of another memory supporting in-memory computing provided in an embodiment of the present application. Figure 8 As shown, the memory may include: an electrically connected control circuit and a memory cell array, a data read / write unit shared by a column of memory cells in the memory cell array, and a cascade adder electrically connected to the memory cell array; a weight value is stored in any memory cell. The cascade adder in this embodiment may be connected to Figure 6 The provided cascade adders have the same structure.

[0141] The control circuit is used to output a calculation signal containing multiple addresses, where the multiple addresses include a first address, a second address, a third address and a fourth address.

[0142] Then, according to the calculation signal, the switch circuit is controlled to be closed so that the first storage unit with the first address and the second storage unit with the second address are in the on state, so that the third storage unit with the third address and the fourth storage unit with the fourth address are in the on state; the switch circuit is controlled to be opened so that at least one group of storage units that does not include the first storage unit to the fourth storage unit is in the off state; wherein the first storage unit to the fourth storage unit are respectively included in the same group or different groups of storage units.

[0143] A first-stage adder in a cascade adder is used to query a weighted summation result of a first value to be calculated and a second value to be calculated in a lookup table according to a weight value in a first storage unit, a weight value in a second storage unit, and a first value to be calculated and a second value to be calculated in a calculation signal; wherein the value to be calculated in the calculation signal and the weight value in the storage unit are binary data, and the lookup table includes a weighted summation result obtained by combining different values ​​to be calculated and different weight values ​​in the storage unit.

[0144] Another first-stage adder in the cascade adder is used to query the weighted sum of the third value to be calculated and the fourth value to be calculated in the lookup table according to the weight value in the third storage unit, the weight value in the fourth storage unit, and the third value to be calculated and the fourth value to be calculated in the calculation signal.

[0145] The second-stage adder in the cascade adder is used to calculate the weighted summation results of the outputs of different first-stage adders.

[0146] For the contents not described in detail in this embodiment and the beneficial effects that can be achieved, please refer to the relevant descriptions in the above embodiments, and will not be repeated here.

[0147] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A memory supporting in-memory computing, characterized in that: include: An electrically connected control circuit and a memory cell array, and a data read / write unit and a bit line shared by a column of memory cells in the memory cell array; There is an electrical connection between the data read / write unit shared by the column of memory cells and the bit line, and a plurality of switch circuits are arranged on the bit line shared by the column of memory cells; the column of memory cells includes a plurality of groups of memory cells, and the switch states of the memory cells in different groups are respectively controlled by different switch circuits; any memory cell in the memory cell array is electrically connected to the word line corresponding to the any memory cell; The control circuit is used to control the switch circuit corresponding to the first storage unit with the first address to close according to the read / write signal including the first address, so that a group of storage units including the first storage unit is in a conducting state; control other switch circuits to open, so that other groups of storage units not including the first storage unit are in a disconnected state; and set the word line electrically connected to the first storage unit to a high level according to the read / write signal; The data reading and writing unit is used to receive the data to be read and written in the reading and writing signal; A common bit line of a column of memory cells including the first memory cell is used to respond to the read / write signal according to the level value of the bit line when the word line is set to a high level, so as to read and write the first memory cell according to the data to be read and written.

2. The memory according to claim 1, characterized in that: Any one of the storage units comprises: a first N-type field effect transistor, a second N-type field effect transistor and a latch; The gates of the first N-type field effect transistor and the second N-type field effect transistor are respectively connected to the word line connected to any one of the storage units; The source of the first N-type field effect transistor is connected to the negative electrode of the bit line connected to any one of the memory cells; The source of the second N-type field effect transistor is connected to the positive electrode of the bit line connected to any one of the memory cells; The drain of the first N-type field effect transistor is connected to the positive output terminal of the latch; The drain of the second N-type field effect transistor is connected to the reverse output terminal of the latch.

3. The memory according to claim 1, characterized in that: The switch circuit for controlling the switch state of any of the storage units comprises: a third N-type field effect transistor and a fourth N-type field effect transistor; The gates of the third N-type field effect transistor and the fourth N-type field effect transistor are respectively connected; The drain and source of each of the third N-type field effect transistor and the fourth N-type field effect transistor are respectively connected to the bit line connected to any one of the storage units.

4. The memory according to claim 1, characterized in that: The memory further comprises: a precharge circuit for charging the positive electrode of the bit line to a high level and charging the negative electrode of the bit line to a low level, so as to write a first binary value in the first storage unit through the bit line; Alternatively, the positive electrode of the bit line is charged to a low level, and the negative electrode of the bit line is charged to a high level, so that the second binary value is written into the first memory cell through the bit line.

5. The memory according to claim 4, characterized in that: The memory also includes: a power supply of the memory cell array; the pre-charging circuit includes: a first P-type field effect transistor and a second P-type field effect transistor; The gates of the first P-type field effect transistor and the second P-type field effect transistor are respectively connected; The source of the first P-type field effect transistor is connected to the negative electrode of the bit line; The source of the second P-type field effect transistor is connected to the positive electrode of the bit line; The drains of the first P-type field effect transistor and the second P-type field effect transistor are respectively connected to the power supply.

6. The memory according to claim 1, characterized in that: The memory also includes a cascade adder electrically connected to the memory cell array, and a weight value is stored in any memory cell; The control circuit is used to output a calculation signal including a plurality of addresses, wherein the plurality of addresses include a first address, a second address, a third address and a fourth address; According to the calculation signal, the switch circuit is controlled to be closed, so that the first storage unit with the first address and the second storage unit with the second address are in a conducting state, so that the third storage unit with the third address and the fourth storage unit with the fourth address are in a conducting state; the switch circuit is controlled to be opened, so that at least one group of storage units not including the first storage unit to the fourth storage unit is in a disconnected state, wherein the first storage unit to the fourth storage unit are respectively included in the same group or different groups of storage units; A first-stage adder in the cascade adder is used to query a weighted summation result of the first value to be calculated and the second value to be calculated in a lookup table according to the weight value in the first storage unit, the weight value in the second storage unit, and the first value to be calculated and the second value to be calculated in the calculation signal, wherein the value to be calculated in the calculation signal and the weight value in the storage unit are binary data, and the lookup table includes a weighted summation result obtained by combining different values ​​to be calculated and different weight values ​​in the storage unit; Another first-stage adder in the cascade adder is used to query a weighted sum result of the third value to be calculated and the fourth value to be calculated in a lookup table according to the weight value in the third storage unit, the weight value in the fourth storage unit, and the third value to be calculated and the fourth value to be calculated in the calculation signal; The second-stage adder in the cascade adder is used to calculate the weighted summation results output by different first-stage adders.

7. The memory according to claim 6, characterized in that: The memory further comprises: a cache unit connected to the column of storage cells, the cache unit and the column of storage cells being electrically connected to the same bit line; The control circuit is used to set the word lines connected to the first storage unit to the fourth storage unit to a high level according to the calculation signal; The bit lines electrically connected from the first storage unit to the fourth storage unit are used to read the weight values ​​in the first storage unit to the fourth storage unit into the cache unit.

8. The memory according to claim 7, characterized in that: The cache unit includes two three-input NAND gates and two two-input NAND gates; A first input terminal of any three-input NAND gate is connected to a bit line; The second input terminal of any three-input NAND gate is connected to the output terminal of another three-input NAND gate; A first input terminal of any two-input NAND gate is connected to an output of any three-input NAND gate; The second input terminal of any two-input NAND gate is connected to the output terminal of the other two-input NAND gate.

9. The memory according to claim 6, characterized in that: The second-stage adder includes a zero-value detection circuit, an OR gate, and an adder unit; The zero value detection circuit is used to determine whether the weighted summation results output by different first-stage adders contain a zero value; If the weighted summation results outputted by the different first-stage adders contain a zero value, a high-level OR gate enable signal is outputted, and a low-level adder enable signal is outputted; If the weighted summation results output by different first-stage adders do not contain a zero value, a low-level OR gate enable signal is output, and a high-level adder enable signal is output; The OR gate is used to perform an OR logic operation on the non-zero weighted summation results in the different first-stage adders after being activated by a high-level OR gate enable signal; The adder unit is used to sum the weighted summation results output by the different first-stage adders after being activated by a high-level adder enable signal.

10. The memory according to claim 9, characterized in that: The zero value detection circuit comprises a first-stage NOR gate and a second-stage NOR gate; Any first-stage NOR gate is used to input the weighted summation result output by any first-stage adder; and perform a NOR logic operation on the weighted summation result; The second-stage NOR gate is used to perform a NOR logic operation on the output results of different first-stage NOR gates; if the NOR logic operation result is a zero value, a high-level OR gate enable signal is output, and a low-level adder enable signal is output; If the result of the NOR logic operation is a non-zero value, a low-level OR gate enable signal is output, and a high-level adder enable signal is output.

11. The memory according to claim 10, characterized in that: The second-stage adder further includes: an N-type field effect transistor and a P-type field effect transistor electrically connected to the OR gate; The drain of the N-type field effect tube is connected to the OR gate, and the source of the N-type field effect tube is grounded; The drain of the P-type field effect tube is connected to the OR gate, and the source of the P-type field effect tube is connected to the power supply; The gates of the N-type field effect transistor and the P-type field effect transistor are respectively connected to the second-stage NOR gate in the zero value detection circuit; The high-level OR gate enable signal output by the second-stage NOR gate is applied to the gates of the P-type field effect transistor and the N-type field effect transistor, so that the P-type field effect transistor and the N-type field effect transistor are turned on; The OR gate is used to perform an OR logic operation on the weighted calculation results output by the different first-stage adders.

12. The memory according to claim 10, characterized in that: The second-stage adder also includes an N-type field effect transistor and a P-type field effect transistor electrically connected to the adder unit; The drain of the N-type field effect tube is connected to the adder unit, and the source of the N-type field effect tube is grounded; The drain of the P-type field effect tube is connected to the adder unit, and the source of the P-type field effect tube is connected to the power supply; The gates of the N-type field effect transistor and the P-type field effect transistor are respectively connected to the second-stage NOR gate in the zero value detection circuit; The high-level adder enable signal output by the second-stage NOR gate is applied to the gates of the P-type field effect transistor and the N-type field effect transistor, so that the P-type field effect transistor and the N-type field effect transistor are turned on; The adder unit is used to sum the weighted calculation results output by the different first-stage adders.

13. The memory according to claim 10, characterized in that: The second-stage adder further comprises: a selector, different input ends of the selector being electrically connected to the adder unit and the output end of the OR gate respectively; The selector is used to output the output result of the OR gate or the adder unit.

14. A memory supporting storage computing, characterized in that: It includes an electrically connected control circuit and a memory cell array, a data read-write unit shared by a column of memory cells in the memory cell array, and a cascade adder electrically connected to the memory cell array; any memory cell stores a weight value; The control circuit is used to output a calculation signal including a plurality of addresses, wherein the plurality of addresses include a first address, a second address, a third address and a fourth address; According to the calculation signal, the switch circuit is controlled to be closed, so that the first storage unit with the first address and the second storage unit with the second address are in a conducting state, so that the third storage unit with the third address and the fourth storage unit with the fourth address are in a conducting state; the switch circuit is controlled to be opened, so that at least one group of storage units not including the first storage unit to the fourth storage unit is in a disconnected state, wherein the first storage unit to the fourth storage unit are respectively included in the same group or different groups of storage units; A first-stage adder in the cascade adder is used to query a weighted summation result of the first value to be calculated and the second value to be calculated in a lookup table according to the weight value in the first storage unit, the weight value in the second storage unit, and the first value to be calculated and the second value to be calculated in the calculation signal, wherein the value to be calculated in the calculation signal and the weight value in the storage unit are binary data, and the lookup table includes a weighted summation result obtained by combining different values ​​to be calculated and different weight values ​​in the storage unit; Another first-stage adder in the cascade adder is used to query a weighted sum result of the third value to be calculated and the fourth value to be calculated in a lookup table according to the weight value in the third storage unit, the weight value in the fourth storage unit, and the third value to be calculated and the fourth value to be calculated in the calculation signal; The second-stage adder in the cascade adder is used to calculate the weighted summation results output by different first-stage adders.

15. A memory cell array, characterized in that: A column of memory cells in the memory cell array shares a data read / write unit and a bit line; any memory cell in the memory cell array is electrically connected to a word line corresponding to the any memory cell; There is an electrical connection between the data read / write unit shared by the column of memory cells and the bit line, and a plurality of switch circuits are arranged on the bit line shared by the column of memory cells; the column of memory cells includes a plurality of groups of memory cells, and the switch states of the memory cells in different groups are respectively controlled by different switch circuits; a control circuit, configured to control a switch circuit corresponding to a first storage unit having the first address to close according to a read / write signal including the first address, so that a group of storage units including the first storage unit is in a conducting state; control other switch circuits to open, so that other groups of storage units not including the first storage unit are in a disconnected state; and set a word line electrically connected to the first storage unit to a high level according to the read / write signal; The data reading and writing unit is used to receive the data to be read and written in the reading and writing signal; A common bit line of a column of memory cells including the first memory cell is used to respond to the read / write signal according to the level value of the bit line when the word line is set to a high level, so as to read and write the first memory cell according to the data to be read and written.

16. A cascade adder, characterized in that: include: A first-stage adder and a second-stage adder, wherein the second-stage adder comprises a zero-value detection circuit, an OR gate and an adder unit; Any first-stage adder, used to output a calculation result in response to a calculation signal; The zero value detection circuit is used to determine whether the weighted summation results output by different first-stage adders contain a zero value; If the weighted summation results outputted by the different first-stage adders contain a zero value, a high-level OR gate enable signal is outputted, and a low-level adder enable signal is outputted; If the weighted summation results output by different first-stage adders do not contain a zero value, a low-level OR gate enable signal is output, and a high-level adder enable signal is output; The OR gate is used to perform an OR logic operation on the non-zero weighted summation results in the different first-stage adders after being activated by a high-level OR gate enable signal; The adder unit is used to sum the weighted summation results output by the different first-stage adders after being activated by a high-level adder enable signal.

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