Hardware Network Card and Logical Circuit Module Configuration Method for Virtual Machine Programs

Abstract

The present application provides a method for configuring a hardware network card and a logic circuit module for a virtual machine program, which relates to the technical field of virtual machines. The hardware network card includes: one or more virtual machine program logic circuit modules, at least one network interface, and at least one general connection interface to form a hardware network card for a virtual machine program; the network interface sends the received network packet to the corresponding virtual machine program logic circuit module; the virtual machine program logic circuit module processes the network packet; when the network packet of the virtual machine program logic circuit module needs to be transmitted to the host, it is sent to the host through the general connection interface. This hardware network card enables adjustment in the way of unloading the virtual machine hardware of the host according to the requirements of individual virtual machine program functions, which is relatively flexible and applicable to various scenarios.

Description

Technical Field

[0001] This application relates to the technical field of virtual machines, and in particular, to a hardware network card and a configuration method for a logic circuit module for a virtual machine program. Background Art

[0002] A virtual machine is a computer program or system that simulates the hardware operating environment of a physical computer through software, enabling multiple operating systems to run simultaneously on the same hardware network card. Virtual machines have functions such as cross-platform operation, application program isolation, and rapid deployment. Therefore, the configuration of virtual machine programs is of great significance for the data processing function of hardware network cards.

[0003] In related technologies, some network device platforms can already adjust virtual machine programs on hardware to complete subsequent data processing such as network packet encapsulation. However, in related technologies, the unified adjustment of virtual machine programs is too rigid and not applicable to multiple scenarios. Summary of the Invention

[0004] The hardware network card and the configuration method for a logic circuit module for a virtual machine program provided by the embodiments of this application are used to achieve the effect of flexible adjustment of virtual machine programs to be applicable to multiple scenarios.

[0005] In a first aspect, the embodiments of this application provide a hardware network card for a virtual machine program, including: one or more virtual machine program logic circuit modules, at least one network interface, and at least one general connection interface;

[0006] Among them, the one or more virtual machine program logic circuit modules are respectively communicatively connected to the network interface;

[0007] The network interface is used to receive or send network packets;

[0008] The one or more virtual machine program logic circuit modules are respectively communicatively connected to the general connection interface;

[0009] The general connection interface is communicatively connected to a host; one or more virtual machines are included in the host, and the virtual machine program logic circuit module is configured according to the virtual machine programs of each virtual machine;

[0010] The network interface sends the received network packet to the corresponding virtual machine program logic circuit module;

[0011] The virtual machine program logic circuit module processes the network packet;

[0012] When the network packet of the virtual machine program logic circuit module needs to be transmitted to the host, it is sent to the host through the general connection interface.

[0013] In a possible implementation, it further includes: a local memory end and one or more virtual machine program key-value query circuit modules; wherein, the local memory end is communicatively connected to the one or more virtual machine program key-value query circuit modules respectively; each virtual machine program key-value query circuit module is communicatively connected to a corresponding virtual machine program logic circuit module; the network interface sends the received network packet to the corresponding virtual machine program logic circuit module; the virtual machine program logic circuit module processes the network packet; the virtual machine program logic circuit module sends the network packet to the corresponding virtual machine program key-value query circuit module; the virtual machine program key-value query circuit module sends the network packet to the local memory end; the local memory end stores the network packet; when the virtual machine program logic circuit module needs to transfer the network packet to the host, it accesses the local memory end through the corresponding virtual machine program key-value query circuit module to send the network packet to the host through the general connection interface.

[0014] In a possible implementation, it further includes: one or more energy detectors, wherein each energy detector is configured in a corresponding virtual machine program logic circuit module; each energy detector obtains the measured throughput of the corresponding virtual machine program logic circuit module for network packets within a preset time; determines the total throughput according to each measured throughput, and determines whether the total throughput is less than the throughput threshold; if the total throughput is less than the throughput threshold, continue to supplement additional virtual machine program logic circuit modules; if the total throughput is not less than the preset throughput, stop supplementing additional virtual machine program logic circuit modules.

[0015] In a second aspect, an embodiment of the present application provides a method for configuring a virtual machine program logic circuit module, which is used to configure the virtual machine program logic circuit module in the hardware network card as described in the first aspect; the method includes: obtaining the code of the virtual machine program of any virtual machine of the host; converting the code of the virtual machine program into the bytecode of the virtual machine program according to a virtual machine compiler; parsing the bytecode of the virtual machine program by a bytecode parser to obtain the circuit code of the virtual machine program; converting the circuit code of the virtual machine program into the virtual machine program logic circuit module according to a field programmable gate array.

[0016] In a possible implementation manner, the parsing of the bytecode of the virtual machine program by the bytecode parser to obtain the circuit code of the virtual machine program includes: parsing the bytecode of the virtual machine program by the bytecode parser to determine the instruction units required by the bytecode of the virtual machine program; determining the circuit code of the virtual machine program according to the instruction units. In a possible implementation manner, where the instruction units include instructions and instruction execution functions, and the circuit code of the virtual machine program includes instruction decoding circuit code and instruction execution circuit code; correspondingly, the parsing of the bytecode of the virtual machine program by the bytecode parser to determine the instruction units required by the bytecode of the virtual machine program includes: parsing the bytecode of the virtual machine program by the bytecode parser to determine the instructions and instruction execution functions required by the bytecode of the virtual machine program; correspondingly, the determining of the circuit code of the virtual machine program according to the instruction units includes: determining the instruction decoding circuit code of the virtual machine program according to the instructions; determining the instruction execution circuit code of the virtual machine program according to the instruction execution functions.

[0017] In a possible implementation manner, the converting of the circuit code of the virtual machine program into the virtual machine program logic circuit module according to the field programmable gate array includes: converting the instruction decoding circuit code and the instruction execution circuit code of the virtual machine program into the virtual machine program logic circuit module according to the field programmable gate array.

[0018] In a possible implementation manner, where the virtual machine compiler includes a compilation front end and a compilation back end; correspondingly, the converting of the code of the virtual machine program into the bytecode of the virtual machine program according to the virtual machine compiler includes: converting the code of the virtual machine program into the bytecode of the virtual machine program according to the compilation front end, the compilation back end and preset parameters.

[0019] In a possible implementation manner, the circuit code of the virtual machine program is a preset hardware language or configuration file.

[0020] In a possible implementation manner, the hardware network card further includes: one or more virtual machine program key value query circuit modules; the method includes: obtaining one or more stored key value pairs of pre-generated virtual machine programs; converting the one or more stored key value pairs of pre-generated virtual machine programs into corresponding one or more virtual machine program key value query circuit modules according to the field programmable gate array.

[0021] In a possible implementation, the generation process of the storage key-value pair of the virtual machine program includes: obtaining any storage key; and declaring the storage key according to a preset language program to obtain the storage key-value pair of the virtual machine program.

[0022] In a possible implementation, after converting the storage key-value pairs of the one or more pre-generated virtual machine programs into the corresponding one or more virtual machine program key-value query circuit modules according to the field programmable gate array, it further includes: the host sending an initial storage key to the general connection interface; the general connection interface sending the initial storage key to the one or more virtual machine program key-value query circuit modules to initialize the one or more virtual machine program key-value query circuit modules.

[0023] In a third aspect, an embodiment of the present application provides an electronic device, including: a memory and a processor;

[0024] The memory stores computer execution instructions;

[0025] The processor executes the computer execution instructions stored in the memory, so that the processor executes the above second aspect and / or various possible implementations of the second aspect.

[0026] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, in which computer execution instructions are stored, and when the computer execution instructions are executed by a processor, they are used to implement the above second aspect and / or various possible implementations of the second aspect.

[0027] In a fifth aspect, an embodiment of the present application provides a computer program product, including a computer program, and when the computer program is executed by a processor, it implements the above second aspect and / or various possible implementations of the second aspect.

[0028] The method for configuring the hardware network card and logic circuit module for the virtual machine program provided by the embodiment of the present application forms a hardware network card for the virtual machine program through one or more virtual machine program logic circuit modules, at least one network interface, and at least one general connection interface; the network interface sends the received network packet to the corresponding virtual machine program logic circuit module; the virtual machine program logic circuit module processes the network packet; when the network packet of the virtual machine program logic circuit module needs to be transmitted to the host, it is sent to the host through the general connection interface, so that it can be adjusted in the way of unloading the virtual machine hardware of the host according to the requirements of individual virtual machine program functions, which is relatively flexible and applicable to multiple scenarios. Description of the Drawings

[0029] The accompanying drawings herein are incorporated into and constitute a part of this specification, showing embodiments consistent with the present application, and are used together with the specification to explain the principles of the present application.

[0030] Figure 1 Structural schematic of the hardware network card for the virtual machine program provided by the embodiment of the present application Figure 1 ;

[0031] Figure 2 Flowchart of the method for configuring the logic circuit module of the virtual machine program provided by the embodiment of the present application;

[0032] Figure 3 Structural schematic of the hardware network card for the virtual machine program provided by the embodiment of the present application Figure 2 ;

[0033] Figure 4 Flowchart of the method for configuring the key-value query circuit module of the virtual machine program provided by the embodiment of the present application;

[0034] Figure 5 Structural schematic of the hardware network card for the virtual machine program provided by the embodiment of the present application Figure 3 ;

[0035] Figure 6 Structural schematic diagram of the device for configuring the logic circuit module of the virtual machine program provided by the embodiment of the present application;

[0036] Figure 7 Structural schematic diagram of the electronic device provided by the embodiment of the present application.

[0037] Through the above accompanying drawings, specific embodiments of the present application have been shown, and there will be more detailed descriptions hereinafter. These drawings and written descriptions are not intended to limit the scope of the concept of the present application in any way, but to illustrate the concept of the present application to those skilled in the art by referring to specific embodiments. Detailed implementation manners

[0038] Here, the exemplary embodiments will be described in detail, and the examples are shown in the accompanying drawings. When the following description refers to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementation manners described in the following exemplary embodiments do not represent all implementation manners consistent with the present application. On the contrary, they are merely examples of the devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0039] A virtual machine is a simulated version of a physical computer that uses software to simulate the hardware operating environment of a physical computer, enabling multiple operating systems to run simultaneously on the same hardware network card. Virtual machines have functions such as cross-platform operation, application isolation, and rapid deployment. Therefore, the configuration of virtual machine programs is of great significance to the data processing function of the hardware network card.

[0040] In related technologies, some network device platforms can already adjust virtual machine programs on hardware to complete subsequent data processing such as network packet encapsulation. However, in related technologies, the unified adjustment of virtual machine programs is too rigid and not applicable to multiple scenarios.

[0041] To solve the above technical problems, the embodiments of this application propose the following technical concept: The inventor considered a hardware network card for virtual machine programs constructed by one or more virtual machine program logic circuit modules, at least one network interface, and at least one general connection interface. Based on the network interface, the received network packets are sent to the corresponding virtual machine program logic circuit module so that the virtual machine program logic circuit module processes the network packets. And when the network packets of the virtual machine program logic circuit module need to be transmitted to the host, they are sent to the host using the above general connection interface, enabling adjustment in the way of unloading the virtual machine hardware of the host according to the requirements of individual virtual machine program functions, which is relatively flexible and applicable to multiple scenarios.

[0042] The following uses specific embodiments to elaborate in detail on the technical solutions of this application and how the technical solutions of this application solve the above technical problems. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of this application will be described below with reference to the accompanying drawings.

[0043] Figure 1 Structural schematic of the hardware network card for virtual machine programs provided by the embodiments of this application Figure 1 。

[0044] As Figure 1 , the hardware network card for virtual machine programs includes: one or more virtual machine program logic circuit modules 101, at least one network interface 102, and at least one general connection interface 103.

[0045] Among them, one or more virtual machine program logic circuit modules 101 are respectively communicatively connected to the network interface 102.

[0046] In this embodiment, the virtual machine is an eBPF virtual machine, and it can also be other virtual machines.

[0047] Among them, eBPF is an extended Berkeley packet filter.

[0048] In this embodiment, the virtual machine program logic circuit module 101 is an eBPF RISC circuit.

[0049] Among them, eBPF RISC is a reduced instruction set computer of the extended Berkeley packet filter.

[0050] In this embodiment, the network interface 102 is a Network Interface.

[0051] The network interface 102 is used to receive or send network packets.

[0052] One or more virtual machine program logic circuit modules 101 are respectively communicatively connected to the general connection interface 103.

[0053] In this embodiment, the general connection interface 103 is a PCIe Interface.

[0054] The general connection interface 103 is communicatively connected to the host 20; among them, the host 20 includes one or more virtual machines, and the virtual machine program logic circuit module 101 is obtained according to the virtual machine programs of each virtual machine.

[0055] In this embodiment, the current number of instructions of the virtual machine is ≥ 100. In the hardware circuit design, the more instructions there are, the larger the area of the "instruction decoder" and the "arithmetic logic unit" circuit logic, and the slower the circuit speed (clock). However, most virtual machine programs do not use all 100 instructions. According to observations, most only use the most common 30% of the instructions.

[0056] The network interface 102 sends the received network packet to the corresponding virtual machine program logic circuit module 101.

[0057] The virtual machine program logic circuit module 101 processes the network packet.

[0058] In this embodiment, processing the network packet includes: packet loss processing of the network packet, transfer processing after modifying the address of the network packet, original path transfer processing of the network packet, and other processing.

[0059] When the network packet of the virtual machine program logic circuit module 101 needs to be transmitted to the host 20, it is sent to the host 20 through the general connection interface 103.

[0060] The hardware network card for virtual machine programs provided in this embodiment forms a hardware network card for virtual machine programs through one or more virtual machine program logic circuit modules, at least one network interface, and at least one general connection interface; the network interface sends the received network packets to the corresponding virtual machine program logic circuit module; the virtual machine program logic circuit module processes the network packets; when the network packets of the virtual machine program logic circuit module need to be transmitted to the host, they are sent to the host through the general connection interface, enabling adjustment in the way of unloading the virtual machine hardware of the host according to the requirements of individual virtual machine program functions, which is relatively flexible and applicable to various scenarios.

[0061] Figure 2 The flowchart of the configuration method for the virtual machine program logic circuit module provided in the embodiment of this application, and the execution subject of this embodiment can be Figure 1 The hardware network card for virtual machine programs in the embodiment shown, and there is no special limitation here in this embodiment. As Figure 2 shown, this method includes:

[0062] S201: Obtain the code of the virtual machine program of any virtual machine of the host.

[0063] In this embodiment, the code of the virtual machine program can be C language code or other codes.

[0064] Among them, the virtual machine can be an eBPF virtual machine.

[0065] Among them, the virtual machine program can be an eBPF virtual machine program.

[0066] S202: Convert the code of the virtual machine program into bytecode of the virtual machine program according to the virtual machine compiler.

[0067] In this embodiment, the virtual machine compiler includes a compilation front end and a compilation back end; correspondingly, step S202 specifically includes: converting the code of the virtual machine program into bytecode of the virtual machine program according to the compilation front end, the compilation back end, and preset parameters.

[0068] In this embodiment, the compilation front end is clang; the compilation back end is LLVM; the preset parameter is -targetbpf.

[0069] Among them, clang is a lightweight compiler for C language, C++, and Objective-C languages; LLVM is a framework system for building compilers.

[0070] In this embodiment, the bytecode of the virtual machine program is eBPF bytecode.

[0071] Among them, the eBPF bytecode is the bytecode of the extended Berkeley Packet Filter.

[0072] Exemplarily, any eBPF bytecode is as follows:

[0073] { 0x28, 0, 0, 0x0000000c}, { 0x15, 0, 3, 0x00000800}, { 0x30, 0, 0,0x00000017}, { 0x15, 0, 1, 0x00000011}, { 0x6, 0, 0, 0x00040000}, { 0x6, 0,0, 0x00000000}

[0074] Among them, {0x15, 0, 3, 0x00000800} is the opcode (0x15 instruction), dst_reg (r0), src_reg (r3), offset / immediate (0x00000800)

[0075] S203: Parse the bytecode of the virtual machine program according to the bytecode parser to obtain the circuit code of the virtual machine program.

[0076] In this embodiment, the circuit code of the virtual machine program is a preset hardware language or configuration file.

[0077] Among them, the preset hardware language can be any one of Verilog, VHDL or SystemVerilog RTL, or it can be other hardware languages.

[0078] Specifically, step S203 specifically includes:

[0079] S2031: Parse the bytecode of the virtual machine program according to the bytecode parser to determine the instruction units required by the bytecode of the virtual machine program.

[0080] In this embodiment, the instruction unit includes an instruction and an instruction execution function; correspondingly, step S2031 is specifically: Parse the bytecode of the virtual machine program according to the bytecode parser to determine the instruction and the instruction execution function required by the bytecode of the virtual machine program.

[0081] In this embodiment, the bytecode parser is a bytecode parser.

[0082] Among them, the bytecode parser can be implemented in any software language, for example: C language, Java or other software languages.

[0083] In addition, according to step S2031, the corresponding register can also be determined.

[0084] S2032: Determine the circuit code of the virtual machine program according to the instruction unit.

[0085] In this embodiment, the circuit code of the virtual machine program includes instruction decoding circuit code and instruction execution circuit code; correspondingly, step S2032 specifically includes:

[0086] S20321: Determine the instruction decoding circuit code of the virtual machine program according to the instruction.

[0087] Specifically, the instruction is fetched through an Instruction Fetch action, and an Instruction Decode action is performed according to the instruction to determine the instruction decoding circuit code of the virtual machine program.

[0088] S20322: Determine the instruction execution circuit code of the virtual machine program according to the instruction execution function.

[0089] S204: Convert the circuit code of the virtual machine program into a virtual machine program logic circuit module according to the field programmable gate array.

[0090] Specifically, step S204 is specifically: according to the field programmable gate array, convert the instruction decoding circuit code and the instruction execution circuit code of the virtual machine program into a virtual machine program logic circuit module.

[0091] In this embodiment, the field programmable gate array is an FPGA.

[0092] Specifically, an Execution action is performed according to the field programmable gate array to convert the instruction decoding circuit code and the instruction execution circuit code of the virtual machine program into a virtual machine program logic circuit module.

[0093] Exemplarily, the arithmetic logic unit in the instruction can be addition, subtraction, left shift, right shift, NOT, AND, OR, and other arithmetic logics.

[0094] In addition, the virtual machine program logic circuit module can also perform Memory Read / Write actions and Write Back actions.

[0095] The method for configuring the virtual machine program logic circuit module provided in this embodiment obtains the code of the virtual machine program of any virtual machine of the host; converts the code of the virtual machine program into the bytecode of the virtual machine program according to the virtual machine compiler; parses the bytecode of the virtual machine program according to the bytecode parser to obtain the circuit code of the virtual machine program; and converts the circuit code of the virtual machine program into the virtual machine program logic circuit module according to the field programmable gate array. By parsing the bytecode of the virtual machine program with the bytecode parser to determine the virtual machine program logic circuit module, subsequent adjustments can be made according to the requirements of individual virtual machine program functions, which is relatively flexible and applicable to various scenarios.

[0096] In addition, parse the bytecode of the virtual machine program according to the bytecode parser to determine the instruction units required by the bytecode of the virtual machine program; determine the circuit code of the virtual machine program according to the instruction units, so that a virtual machine program logic circuit module with optimized area and speed can be obtained to achieve virtual machine hardware acceleration.

[0097] Figure 3 The structure diagram of the hardware network card for the virtual machine program provided in the embodiment of the present application Figure 2 。In Figure 1 Based on the embodiment of, the hardware network card for the virtual machine program further includes: a local memory end 104 and one or more virtual machine program key-value query circuit modules 105;

[0098] Among them, the local memory end 104 is communicatively connected to one or more virtual machine program key-value query circuit modules 105 respectively.

[0099] In this embodiment, the virtual machine program key-value query circuit module 105 is a KVS BPF Map circuit.

[0100] Among them, the BPF Map uses the memory of the host 20 to store BPF Map data.

[0101] Among them, the KVS BPF Map circuit converts the software BPF Map into high-speed hardware, and the Map access speed can be increased by 10 to 20 times.

[0102] Among them, KVS is a special type of computer storage applied to some very high-speed search programs.

[0103] Among them, the BPF Map stores key-value pairs.

[0104] Each virtual machine program key-value query circuit module 105 is communicatively connected to the corresponding virtual machine program logic circuit module 101.

[0105] In this embodiment, the discussion about the virtual machine program logic circuit module 101 has been described in Figure 1 the corresponding embodiment and will not be elaborated here.

[0106] The network interface 102 sends the received network packet to the corresponding virtual machine program logic circuit module 101.

[0107] In this embodiment, the discussion about the network interface 102 has been described in Figure 1 the corresponding embodiment and will not be elaborated here.

[0108] The virtual machine program logic circuit module 101 processes the network packet.

[0109] In this embodiment, the discussion about processing the network packet has been described in Figure 1 the corresponding embodiment and will not be elaborated here.

[0110] The virtual machine program logic circuit module 101 sends the network packet to the corresponding virtual machine program key-value query circuit module 105.

[0111] The virtual machine program key-value query circuit module 105 sends the network packet to the local memory end 104.

[0112] The local memory end 104 stores the network packet.

[0113] When the virtual machine program logic circuit module 101 needs to transfer the network packet to the host 20, it accesses the local memory end 104 through the corresponding virtual machine program key-value query circuit module 105, so as to send the network packet to the host 20 through the general connection interface 103.

[0114] The hardware network card for the virtual machine program provided in this embodiment adds a local memory end and one or more virtual machine program key-value query circuit modules; the received network packet is sent to the corresponding virtual machine program logic circuit module through the network interface; the virtual machine program logic circuit module processes the network packet; the virtual machine program logic circuit module sends the network packet to the corresponding virtual machine program key-value query circuit module, and the virtual machine program key-value query circuit module sends the network packet to the local memory end; the local memory end stores the network packet; when the virtual machine program logic circuit module needs to transfer the network packet to the host, it accesses the local memory end through the corresponding virtual machine program key-value query circuit module, so as to send the network packet to the host through the general connection interface. By adding the local memory end and the virtual machine program key-value query circuit module, the read and write speed of the hardware network card is improved.

[0115] Figure 4The flowchart of the method for configuring the virtual machine program key-value query circuit module provided by the embodiment of the present application. The execution subject of this embodiment may be Figure 3 the hardware network card for the virtual machine program in the embodiment shown, and there is no special limitation here in this embodiment. As Figure 4 shown, the method includes:

[0116] S301: Obtain one or more pre-generated storage key-value pairs of the virtual machine program.

[0117] In this embodiment, the generation process of the storage key-value pair of the virtual machine program specifically includes:

[0118] S3011: Obtain any storage key.

[0119] S3012: Declare the storage key according to the preset language program to obtain the storage key-value pair of the virtual machine program.

[0120] In this embodiment, the preset language program may be a C language program or other language programs.

[0121] Specifically, declare the storage key in the form of Key / Value according to the C language program to obtain the storage key-value pair of the virtual machine program.

[0122] Exemplarily, Key / Value is "port0" / 3003, "port2" / 1234. It means using the key "port0" to determine the corresponding value to obtain 3003, that is, it means that port0 of the network interface is 3003 at this time.

[0123] Among them, the storage key-value pair of the virtual machine program can be embodied in the Struct structure.

[0124] S302: Convert one or more pre-generated storage key-value pairs of the virtual machine program into corresponding one or more virtual machine program key-value query circuit modules according to the field programmable gate array.

[0125] In this embodiment, after step S302, steps a to b are further included:

[0126] Step a: The host sends the initial storage key to the general connection interface.

[0127] Step b: The general connection interface sends the initial storage key to one or more virtual machine program key-value query circuit modules to initialize one or more virtual machine program key-value query circuit modules.

[0128] In addition, according to a preset period, through a general connection interface, the stored key values for update can be sent to one or more virtual machine program key value query circuit modules, so that the one or more virtual machine program key value query circuit modules can complete the update.

[0129] Among them, the preset period can be 1 day, 1 week or other periods.

[0130] The method for configuring the virtual machine program key value query circuit module provided in this embodiment obtains one or more stored key value pairs of pre-generated virtual machine programs; according to the field programmable gate array, the one or more stored key value pairs of pre-generated virtual machine programs are converted into corresponding one or more virtual machine program key value query circuit modules, laying a foundation for improving the reading and writing speed of the subsequent hardware network card.

[0131] Figure 5 The structural schematic diagram of the hardware network card for the virtual machine program provided by the embodiment of the present application Figure 3 , on the basis of the embodiment of Figure 1 , the hardware network card for the virtual machine program further includes: one or more energy detectors, and each energy detector is configured in the corresponding virtual machine program logic circuit module 101.

[0132] Each energy detector obtains the measured throughput of the network packets by the corresponding virtual machine program logic circuit module 101 within a preset time.

[0133] In this embodiment, the preset time can be any time among 1 day, 2 days or 3 days, or other times.

[0134] In this embodiment, the throughput is "throughput".

[0135] Determine the total throughput according to each measured throughput, and judge whether the total throughput is less than the throughput threshold.

[0136] In this embodiment, the throughput threshold is "Threshold", which can be set to any value among 0.9, 2.0 or 3.0, or determined as other values.

[0137] If the total throughput is less than the throughput threshold, continue to supplement additional virtual machine program logic circuit modules; if the total throughput is not less than the preset throughput, stop supplementing additional virtual machine program logic circuit modules.

[0138] In addition, if the total throughput is not less than the preset throughput, stop supplementing additional virtual machine program logic circuit modules, and replace with a new hardware network card and continue to supplement additional virtual machine program logic circuit modules.

[0139] The hardware network card for the virtual machine program provided in this embodiment adds one or more energy measurement detectors, and each energy measurement detector is configured in the corresponding virtual machine program logic circuit module; through each energy measurement detector, the measurement throughput of the network packet by the corresponding virtual machine program logic circuit module within a preset time is obtained; the total throughput is determined according to each measurement throughput, and it is judged whether the total throughput is less than the throughput threshold; if the total throughput is less than the throughput threshold, additional virtual machine program logic circuit modules are continuously added; if the total throughput is not less than the preset throughput, adding additional virtual machine program logic circuit modules is stopped, so that the operation of the hardware network card can be regularly controlled to ensure the efficient operation of the hardware network card.

[0140] Figure 6 FIG. is a schematic structural diagram of a virtual machine program logic circuit module configuration device provided by an embodiment of the present application. As Figure 6 shown, the virtual machine program logic circuit module configuration device provided in this embodiment includes: a first acquisition module 601, a first conversion module 602, an analysis module 603, and a conversion module 604.

[0141] The first acquisition module 601 is used to acquire the code of the virtual machine program of any virtual machine of the host.

[0142] The first conversion module 602 is used to convert the code of the virtual machine program into the bytecode of the virtual machine program according to the virtual machine compiler.

[0143] The analysis module 603 is used to analyze the bytecode of the virtual machine program according to the bytecode parser to obtain the circuit code of the virtual machine program.

[0144] The conversion module 604 is used to convert the circuit code of the virtual machine program into the virtual machine program logic circuit module according to the field programmable gate array.

[0145] In a possible design, the analysis module 603 specifically includes:

[0146] An analysis unit is used to analyze the bytecode of the virtual machine program according to the bytecode parser to determine the instruction unit required by the bytecode of the virtual machine program.

[0147] A determination unit is used to determine the circuit code of the virtual machine program according to the instruction unit.

[0148] In a possible design, the instruction unit includes instructions and instruction execution functions, and the circuit code of the virtual machine program includes instruction decoding circuit code and instruction execution circuit code; correspondingly, the parsing unit is specifically configured to: parse the bytecode of the virtual machine program according to the bytecode parser to determine the instructions and instruction execution functions required by the bytecode of the virtual machine program;

[0149] Correspondingly, the determining unit specifically includes:

[0150] The first determining unit is configured to determine the instruction decoding circuit code of the virtual machine program according to the instructions;

[0151] The second determining unit is configured to determine the instruction execution circuit code of the virtual machine program according to the instruction execution function.

[0152] In a possible design, the conversion module 604 is specifically configured to: convert the instruction decoding circuit code and the instruction execution circuit code of the virtual machine program into the virtual machine program logic circuit module according to the field programmable gate array.

[0153] In a possible design, the virtual machine compiler includes a compilation front end and a compilation back end; correspondingly, the first conversion module 602 is specifically configured to: convert the code of the virtual machine program into the bytecode of the virtual machine program according to the compilation program front end, the compilation program back end, and preset parameters.

[0154] In a possible design, the circuit code of the virtual machine program is a preset hardware language or configuration file.

[0155] In a possible design, the hardware network card further includes: one or more virtual machine program key value query circuit modules; the device further includes:

[0156] The second obtaining module is configured to obtain one or more storage key value pairs of pre-generated virtual machine programs;

[0157] The second conversion module is configured to convert the one or more storage key value pairs of pre-generated virtual machine programs into corresponding one or more virtual machine program key value query circuit modules according to the field programmable gate array.

[0158] In a possible design, the device further includes:

[0159] The third obtaining module is configured to obtain any storage key value;

[0160] The announcing module is configured to announce the storage key value according to a preset language program to obtain a storage key value pair of the virtual machine program.

[0161] In a possible design, the device further includes:

[0162] A first sending module, for the host, to send an initial stored key value to a general connection interface;

[0163] A second sending module, for the general connection interface, to send the initial stored key value to one or more virtual machine program key value query circuit modules, so that the one or more virtual machine program key value query circuit modules complete initialization.

[0164] The virtual machine program logic circuit module configuration device provided in this embodiment can execute the method provided in the above method embodiment, and its implementation principle and technical effect are similar, which will not be elaborated here in this embodiment.

[0165] Figure 7 It is a schematic structural diagram of an electronic device provided by this application. As Figure 7 shown, the electronic device provided in this embodiment includes: at least one processor 701 and a memory 702. Optionally, the device further includes a communication component 703. Among them, the processor 701, the memory 702, and the communication component 703 are connected through a bus.

[0166] In a specific implementation process, at least one processor 701 executes computer execution instructions stored in the memory 702, so that at least one processor 701 executes the above method.

[0167] The specific implementation process of the processor 701 can refer to the above method embodiment, and its implementation principle and technical effect are similar, which will not be elaborated here in this embodiment.

[0168] In the above embodiment, it should be understood that the processor may be a central processing unit (Central Processing Unit, abbreviated as: CPU), and may also be other general-purpose processors, digital signal processors (Digital Signal Processor, abbreviated as: DSP), application specific integrated circuits (Application Specific Integrated Circuit, abbreviated as: ASIC), etc. The general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc. The steps of the method disclosed in combination with the application can be directly implemented by a hardware processor or implemented by a combination of hardware and software modules in the processor.

[0169] The memory may include a high-speed memory (Random Access Memory, RAM), and may also include a non-volatile memory (Non-volatile Memory, NVM), such as at least one disk memory.

[0170] The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, an Extended Industry Standard Architecture (EISA) bus, etc. The bus can be divided into an address bus, a data bus, a control bus, etc. For the sake of convenience in representation, the buses in the accompanying drawings of this application are not limited to only one bus or one type of bus.

[0171] The embodiments of this application also provide a computer program product, including a computer program, which implements the above method when executed by a processor.

[0172] The embodiments of this application also provide a computer-readable storage medium, in which computer-executable instructions are stored, and when the processor executes the computer-executable instructions, the above method is implemented.

[0173] The above-mentioned readable storage medium can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as a static random access memory (SRAM), an electrically erasable programmable read-only memory (EEPROM), an erasable programmable read-only memory (EPROM), a programmable read-only memory (PROM), a read-only memory (ROM), a magnetic memory, a flash memory, a magnetic disk or an optical disk. The readable storage medium can be any available medium that can be accessed by a general-purpose or special-purpose computer.

[0174] An exemplary readable storage medium is coupled to the processor, enabling the processor to read information from the readable storage medium and write information to the readable storage medium. Of course, the readable storage medium can also be a component of the processor. The processor and the readable storage medium can be located in an Application Specific Integrated Circuit (ASIC). Of course, the processor and the readable storage medium can also exist as discrete components in a device.

[0175] The division of units is only a logical function division. In actual implementation, there can be other division methods. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed coupling or direct coupling or communication connection to each other can be through some interfaces, and the indirect coupling or communication connection of devices or units can be in electrical, mechanical or other forms.

[0176] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed over multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0177] In addition, the functional units in the various embodiments of the present application may be integrated in a processing unit, may exist separately as individual physical units, or two or more units may be integrated in one unit.

[0178] If the function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, in essence, or the part that contributes to the prior art, or a part of this technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods in the various embodiments of the present application. The aforementioned storage medium includes: USB flash drives, mobile hard disks, read-only memories (ROMs), random access memories (RAMs), magnetic disks, or optical discs, etc., which can store program codes.

[0179] Those of ordinary skill in the art can understand that all or part of the steps of implementing the above method embodiments can be completed by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When the program is executed, it executes the steps including the above method embodiments; and the aforementioned storage medium includes: ROMs, RAMs, magnetic disks, or optical discs, etc., which can store program codes.

[0180] Finally, it should be noted that: After considering the specification and practicing the application disclosed herein, those skilled in the art will readily think of other implementation schemes of the present application. The present application aims to cover any variations, uses, or adaptive changes of the present application. These variations, uses, or adaptive changes follow the general principles of the present application and include the common general knowledge or conventional technical means in the technical field not disclosed in the present application. It is not limited to the precise structures described above and shown in the drawings, and various modifications and changes can be made without departing from its scope. The scope of the present application is only limited by the appended claims.

Claims

1. A hardware network card for a virtual machine program, characterized in that: include: One or more virtual machine program logic circuit modules, at least one network interface and at least one universal connection interface; Wherein, the one or more virtual machine program logic circuit modules are respectively communicatively connected with the network interface; The network interface is used to receive or send network packets; The one or more virtual machine program logic circuit modules are respectively communicatively connected to the universal connection interface; The universal connection interface is communicatively connected with a host; wherein the host includes one or more virtual machines, the virtual machine program logic circuit module is generated by converting the circuit code of the virtual machine program according to a field programmable gate array, and the circuit code of the virtual machine program is obtained by obtaining the code of the virtual machine program of any virtual machine of the host, converting the code of the virtual machine program into the bytecode of the virtual machine program according to a virtual machine compiler, and parsing the bytecode of the virtual machine program according to a bytecode parser; The network interface sends the received network packet to the corresponding virtual machine program logic circuit module; The virtual machine program logic circuit module processes the network packet; When the network packet of the virtual machine program logic circuit module needs to be transmitted to the host, it is sent to the host through the universal connection interface.

2. The hardware network card according to claim 1, characterized in that: Also includes: A local memory terminal and one or more virtual machine program key value query circuit modules; Wherein, the local memory end is respectively connected to the one or more virtual machine program key value query circuit modules for communication; Each virtual machine program key value query circuit module is communicatively connected with the corresponding virtual machine program logic circuit module; The network interface sends the received network packet to the corresponding virtual machine program logic circuit module; The virtual machine program logic circuit module processes the network packet; The virtual machine program logic circuit module sends the network packet to the corresponding virtual machine program key value query circuit module; The virtual machine program key value query circuit module sends the network packet to the local memory end; The local memory end stores the network packets; When the virtual machine program logic circuit module needs to transmit the network packet to the host, the local memory end is accessed through the corresponding virtual machine program key value query circuit module to send the network packet to the host through the universal connection interface.

3. The hardware network card according to claim 1 or 2, characterized in that: Also includes: One or more performance measurement devices, wherein each performance measurement device is configured in a corresponding virtual machine program logic circuit module; Each efficiency meter obtains the measured throughput of the network packets by the corresponding virtual machine program logic circuit module within a preset time; Determine a total throughput according to each measured throughput, and determine whether the total throughput is less than a throughput threshold; If the total throughput is less than the throughput threshold, continue to add additional virtual machine program logic circuit modules; If the total throughput is not less than the preset throughput, the replenishment of additional virtual machine program logic circuit modules is stopped.

4. A method for configuring a virtual machine program logic circuit module, characterized in that: Used to configure the virtual machine program logic circuit module in the hardware network card as claimed in claim 1; the method comprises: Obtain the code of a virtual machine program of any virtual machine of the host; Converting the code of the virtual machine program into the bytecode of the virtual machine program according to the virtual machine compiler; Parsing the bytecode of the virtual machine program according to the bytecode parser to obtain the circuit code of the virtual machine program; The circuit code of the virtual machine program is converted into the virtual machine program logic circuit module according to the field programmable gate array.

5. The method according to claim 4, characterized in that The step of parsing the bytecode of the virtual machine program according to the bytecode parser to obtain the circuit code of the virtual machine program includes: Parsing the bytecode of the virtual machine program according to the bytecode parser to determine the instruction unit required by the bytecode of the virtual machine program; The circuit code of the virtual machine program is determined according to the instruction unit.

6. The method according to claim 5, characterized in that The instruction unit includes instructions and instruction execution functions, and the circuit code of the virtual machine program includes instruction decoding circuit code and instruction execution circuit code; Accordingly, parsing the bytecode of the virtual machine program according to the bytecode parser to determine the instruction unit required by the bytecode of the virtual machine program includes: Parsing the bytecode of the virtual machine program according to the bytecode parser to determine the instructions and instruction execution functions required by the bytecode of the virtual machine program; Accordingly, the determining the circuit code of the virtual machine program according to the instruction unit includes: Determine the instruction decoding circuit code of the virtual machine program according to the instruction; The instruction execution circuit code of the virtual machine program is determined according to the instruction execution function.

7. The method according to claim 6, characterized in that The converting the circuit code of the virtual machine program into the virtual machine program logic circuit module according to the field programmable gate array includes: According to the field programmable gate array, the instruction decoding circuit code and the instruction execution circuit code of the virtual machine program are converted into the virtual machine program logic circuit module.

8. The method according to claim 4, characterized in that The virtual machine compiler includes a compilation front end and a compilation back end; Accordingly, converting the code of the virtual machine program into the bytecode of the virtual machine program according to the virtual machine compiler includes: The code of the virtual machine program is converted into the bytecode of the virtual machine program according to the compiler front end, the compiler back end and preset parameters.

9. The method according to any one of claims 4 to 8, characterized in that: The circuit code of the virtual machine program is a preset hardware language or a configuration file.

10. The method according to claim 4, characterized in that The hardware network card also includes: one or more virtual machine program key value query circuit modules; The method comprises: Obtaining storage key-value pairs of one or more pre-generated virtual machine programs; The one or more pre-generated storage key-value pairs of the virtual machine programs are converted into corresponding one or more virtual machine program key-value query circuit modules according to the field programmable gate array.

11. The method according to claim 10, characterized in that The process of generating the storage key-value pair of the virtual machine program includes: Get any storage key value; The storage key value is declared according to a preset language program to obtain a storage key value pair of the virtual machine program.

12. The method according to claim 10 or 11, characterized in that: After converting the one or more pre-generated virtual machine program storage key-value pairs into corresponding one or more virtual machine program key-value query circuit modules according to the field programmable gate array, the method further includes: The host sends the initial storage key value to the universal connection interface; The universal connection interface sends the initial storage key value to one or more virtual machine program key value query circuit modules, so that the one or more virtual machine program key value query circuit modules complete initialization.

13. An electronic device, characterized in that: include: Memory and processor; The memory stores computer-executable instructions; The processor executes the computer-executable instructions stored in the memory to implement the virtual machine program logic circuit module configuration method according to any one of claims 4 to 11.

14. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer-executable instructions, which, when executed by a processor, are used to implement the virtual machine program logic circuit module configuration method according to any one of claims 4 to 11.

15. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the method for configuring a virtual machine program logic circuit module is implemented as described in any one of claims 4 to 11.

Images