A method, device, equipment and storage medium for scheduling computing resources

Abstract

The present application provides a scheduling method, apparatus, device and storage medium for computing resources. When a CPU core receives an interrupt request, it uses a preset user-mode instruction to obtain read and write permissions for a first memory area in a shared memory area, reads and executes a switching function from the first memory area, and schedules the computing resources of the CPU core from a first user-mode process to a target user-mode process. When the CPU core executes any user-mode process, it only has read and write permissions for a second memory area occupied by the user-mode process in the shared memory area. Since any user-mode process can only read and write the memory space occupied by itself, and the process of switching the user-mode process executed by the CPU core is all in the user-mode mode of the operating system, there is no need to enter the kernel mode of the operating system. This can reduce the computing resource overhead of process switching while ensuring process isolation, thereby improving the utilization of CPU computing resources.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a method, apparatus, device, and storage medium for scheduling computing resources. Background Art

[0002] In order to save CPU computing resources, the main method currently used is to allocate and manage CPU computing resources through a scheduler based on application performance information.

[0003] However, this scheduling method still suffers from low CPU computing resource utilization when processing short tasks with an average service time of 1-2 microseconds, such as the distributed cache system Memcached and the remote dictionary service Redis, as well as densely placed applications.

[0004] The fundamental reason is that traditional operating systems rely on standard operating system processes to run applications. When scheduling CPU computing resources between two applications, it is necessary to switch between the user state and kernel state of the operating system multiple times. However, this switching process between user state and kernel state itself consumes a certain amount of CPU computing resources, resulting in a reduction in the CPU computing resources actually used to execute applications, which in turn leads to low CPU computing resource utilization. Summary of the Invention

[0005] In view of this, the present application provides a method, apparatus, device and storage medium for scheduling computing resources to address the deficiencies in the related art.

[0006] In a first aspect of the present application, a method for scheduling computing resources is provided, which is applied to a CPU core and includes:

[0007] When an interrupt request is received, the user-mode instruction is used to obtain read and write permissions for a first memory area in the shared memory area, where a switching function for switching the user-mode process executed by the CPU core is pre-set;

[0008] The switching function is read and executed from the first memory area to schedule the computing resources of the CPU core from the first user state process to the target user state process, wherein the first user state process is the user state process executed by the CPU core when receiving the interrupt request, and when the CPU core executes any user state process, it only has read and write permissions to the second memory area occupied by the user state process in the shared memory area.

[0009] According to one embodiment of the present application, reading and executing the switching function from the first memory area includes:

[0010] Switching the running stack from the running stack of the first user state process to the running stack during user state runtime;

[0011] Reading an entry address of the switching function from a preset designated location in the shared memory area;

[0012] Jump to the entry address to read and execute the switching function.

[0013] According to an embodiment of the present application, each user state process is started by an operating system process associated with the user state process, and multiple operating system processes share the shared memory area.

[0014] According to one embodiment of the present application, the shared memory area is pre-divided into N memory areas, and the CPU core is configured with a first register containing N permission identifiers, the N permission identifiers correspond one-to-one to the N memory areas, and each permission identifier is used to represent the access rights of the CPU core to the memory area corresponding to the permission identifier.

[0015] According to an embodiment of the present application, obtaining read and write permissions for a first memory area in a shared memory area by using a preset user mode instruction includes:

[0016] Using a preset user mode instruction, the permission identifier corresponding to the first memory area in the first register is modified to a first value, where the first value indicates that the CPU core has read and write permissions for the first memory area.

[0017] According to one embodiment of the present application, after scheduling the computing resources of the CPU core from the first user state process to the target user state process, the method further includes a permission restoration step, wherein the permission restoration step includes:

[0018] Using the number of the CPU core as an offset address, obtaining, from a third memory area preset in the shared memory area, the values ​​of the N permission identifiers when the CPU core executes the target user state process, wherein the third memory area is used to record the values ​​of the N permission identifiers in the first register of each CPU core when the CPU core executes the current user state process;

[0019] Using the obtained values ​​of the N permission identifiers of the CPU core when executing the target user state process, the values ​​of the N permission identifiers in the first register of the CPU core are updated so that the CPU core only has read and write permissions for the second memory area occupied by the target user state process in the shared memory area.

[0020] According to one embodiment of the present application, after updating the values ​​of the N permission identifiers in the first register of the CPU core, the method further includes:

[0021] Using the number of the CPU core as an offset address, again obtaining from the third memory area the values ​​of the N permission identifiers when the CPU core executes the target user mode process;

[0022] Determine whether the values ​​of the N permission identifiers obtained again when the CPU core executes the target user mode process are the same as the values ​​of the N permission identifiers in the first register of the CPU core after the update;

[0023] If different, repeat the permission recovery step.

[0024] In a second aspect of the present application, a computing resource scheduling device is provided, which is applied to a CPU core and includes:

[0025] a privilege escalation unit, configured to, upon receiving an interrupt request, obtain read and write permissions for a first memory area in the shared memory area using a preset user-mode instruction, wherein the first memory area is pre-set with a switching function for switching a user-mode process executed by a CPU core;

[0026] A scheduling unit is used to read and execute the switching function from the first memory area to schedule the computing resources of the CPU core from the first user state process to the target user state process, wherein the first user state process is the user state process executed by the CPU core when receiving the interrupt request, and when the CPU core executes any user state process, it only has read and write permissions for the second memory area occupied by the user state process in the shared memory area.

[0027] In a third aspect of the present application, an electronic device is provided, comprising a processor and a memory, wherein the memory stores machine-executable instructions that can be executed by the processor, and the processor is used to execute the machine-executable instructions to implement the steps of the method proposed in the above embodiment.

[0028] In a fourth aspect of the present application, a machine-readable storage medium is provided, wherein the machine-readable storage medium stores machine-executable instructions, and when the machine-executable instructions are executed by a processor, the steps of the method proposed in the above embodiment are implemented.

[0029] In a fifth aspect of the present application, a computer program product is provided, comprising a computer program / instruction, which implements the steps of the method proposed in the above embodiment when executed by a processor.

[0030] It can be seen from the above technical solution that, when an interrupt request is received, the read and write permissions of the first memory area in the shared memory area are obtained by using a pre-set user-state instruction, and the switching function is read and executed from the first memory area to schedule the computing resources of the CPU core from the first user-state process to the target user-state process, wherein the first user-state process is the user-state process executed by the CPU core when the interrupt request is received. When the CPU core executes any user-state process, it only has the read and write permissions of the second memory area occupied by the user-state process in the shared memory area. Since any user-state process can only read and write the memory space occupied by itself, it cannot read and write the memory space occupied by other user-state processes, and the process of switching the user-state process executed by the CPU core is all in the user-state mode of the operating system, there is no need to enter the kernel mode of the operating system, thereby reducing the computing resource overhead of process switching while ensuring process isolation and improving the CPU computing resource utilization.

[0031] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 This is a flow chart of a method for scheduling computing resources provided in an embodiment of the present application;

[0033] Figure 2 is a schematic diagram of a shared memory space layout provided in an embodiment of the present application;

[0034] Figure 3 This is a schematic diagram of the structure of a user-mode process provided by an embodiment of the present application;

[0035] Figure 4 This is a flow chart of a method for scheduling computing resources provided in an embodiment of the present application;

[0036] Figure 5 This is a schematic diagram of the structure of a scheduling device for computing resources provided in an embodiment of the present application;

[0037] Figure 6 It is a schematic diagram of the hardware structure of an electronic device shown in an exemplary embodiment of the present application. DETAILED DESCRIPTION

[0038] Exemplary embodiments will be described in detail herein, with examples illustrated in the accompanying drawings. In the following description, when referring to the drawings, identical numerals in different figures represent identical or similar elements, unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.

[0039] The terms used in this application are for the purpose of describing particular embodiments only and are not intended to limit this application. As used in this application and the appended claims, the singular forms "a," "an," "the," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0040] In order to enable those skilled in the art to better understand the technical solutions provided by the embodiments of the present application, and to make the above-mentioned purposes, features and advantages of the embodiments of the present application more obvious and easy to understand, the technical solutions in the embodiments of the present application are further described in detail below with reference to the accompanying drawings.

[0041] Currently, 100-200Gbps networks have been widely adopted by mainstream cloud service providers, and some DPUs

[0042] (Data Processing Unit) can even achieve up to 400Gbps connection with a latency of less than 1 microsecond. Storage manufacturers are also constantly exploring the performance limit. New products such as Optane memory and SSDs that support memory semantics can easily achieve more than one million IOPS.

[0043] (Input / Output Operations Per Second, the number of read and write operations per second.) However, CPU performance has stagnated relatively, and the slowdown of Moore's Law has become a major bottleneck.

[0044] In order to save CPU computing resources, the current methods mainly include kernel bypass technology, integration of multiple application workloads and user-mode scheduler.

[0045] Among them, the user-mode scheduler method allocates and manages CPU computing resources through a scheduler based on application performance information. However, this method can only improve efficiency to a certain extent. When processing short tasks with an average service time of 1-2 microseconds, such as the distributed cache system Memcached and the remote dictionary service Redis, and when densely placing applications, this scheduling method still suffers from low CPU computing resource utilization. The root cause is that traditional operating systems rely on standard operating system processes to run applications. When scheduling CPU computing resources between two applications, it is necessary to frequently switch between the operating system's user mode and kernel mode. This switching process consumes CPU computing resources, resulting in a reduction in the CPU computing resources actually used to execute applications, thereby reducing overall CPU computing resource utilization.

[0046] In view of this, an embodiment of the present application discloses a method for scheduling computing resources to address the deficiencies in related technologies.

[0047] like Figure 1 As shown, Figure 1 : is a flow chart of a method for scheduling computing resources provided in an embodiment of the present application. The method for scheduling computing resources may include the following steps:

[0048] S101: When an interrupt request is received, a pre-set user mode instruction is used to obtain read and write permissions of a first memory area in a shared memory area, where a switching function for switching user mode processes executed by a CPU core is pre-set.

[0049] S102: Read and execute the switching function from the first memory area to schedule the computing resources of the CPU core from the first user state process to the target user state process, wherein the first user state process is the user state process executed by the CPU core when receiving the interrupt request, and when the CPU core executes any user state process, it only has read and write permissions to the second memory area occupied by the user state process in the shared memory area.

[0050] In an embodiment of the present application, for a pre-configured shared memory area, memory access control is implemented in the shared memory area.

[0051] The shared memory area includes at least a first memory area and a second memory area. Among them, the second memory area is the memory area occupied by the user-state process. Each user-state process occupies a second memory area in the shared memory area and only has read and write permissions for the second memory area occupied by itself, and does not have read and write permissions for other memory areas in the shared memory area. Therefore, when the CPU core is executing any user-state process, it only has read and write permissions for the second memory area occupied by the user-state process in the shared memory area, and does not have read and write permissions for other memory areas (such as the first memory area) in the shared memory area.

[0052] It should be noted that the user-state process in the embodiment of the present application is in the user-state mode of the operating system, and can complete the creation, isolation, scheduling and destruction of the process without entering the kernel-state mode of the operating system.

[0053] A switching function for switching the user-mode process executed by the CPU core is pre-set in the first memory area. When the CPU core receives an interrupt request, it can use the pre-set user-mode instruction to obtain the read and write permissions of the first memory area in the shared memory area to ensure that the CPU core can obtain and execute the switching function to realize switching between different user-mode processes.

[0054] like Figure 2 As shown, Figure 2 This is a schematic diagram of a shared memory space layout provided by an embodiment of the present application. The shared memory area includes a user-state process area and a privileged area. The user-state process area is composed of multiple second memory areas. Each second memory area is a memory area occupied by a user-state process. The user-state process uses the second memory area occupied by itself to store its code, data, stack and other segments. The user-state process only has read and write permissions for the second memory area occupied by itself, and does not have read and write permissions for other memory areas in the shared memory area. The other memory areas here include the second memory area occupied by the user-state process and the privileged area.

[0055] The privileged area is the first memory area. The runtime is a set of common libraries and common functions that support the execution of user programs. They are responsible for handling a series of functions related to program scheduling, thread management, process management, etc. Common functions can exist in the kernel state of the operating system or in the user state. In an embodiment of the present application, the privileged area is the memory area occupied by the user state runtime. In this privileged area, the user state runtime exists in the form of code, and these codes contain pre-set switching functions for switching the user state process executed by the CPU core. When the CPU core receives an interrupt request, it can use the pre-set user state instructions to obtain read and write permissions for the privileged area to ensure that the CPU core can obtain and execute the switching function contained in the user state runtime to realize switching between different user state processes.

[0056] In an embodiment of the present application, by implementing memory access control in the shared memory area, the CPU core has read and write permissions to the first memory area only when it needs to execute a switching function to switch the user-state process executed by itself. When executing other codes, such as executing the code of any user-state process, the CPU core only has read and write permissions to the second memory area occupied by the user-state process in the shared memory area, and does not have read and write permissions to the first memory area, thereby achieving support for the user-state process executed by the CPU core in the user-state switching of the operating system while ensuring isolation between user-state processes.

[0057] S101 and S102 will be described in detail below.

[0058] S101: When an interrupt request is received, a pre-set user mode instruction is used to obtain read and write permissions of a first memory area in a shared memory area, where a switching function for switching user mode processes executed by a CPU core is pre-set.

[0059] In an embodiment of the present application, after receiving an interrupt request, the CPU core will execute a set of preset user-mode instructions to obtain read and write permissions for the first memory area in the shared memory area.

[0060] The CPU core obtains the read and write permissions for the first memory area, which means that the CPU core enters the privileged mode. In the privileged mode, the CPU core has read and write permissions for the switching function pre-set in the first memory area for switching the user mode process executed by the CPU core.

[0061] In some embodiments, the CPU core may receive an interrupt request from hardware (eg, a hardware timer, a controller, etc.) or software (eg, a software timer, a scheduler, etc.).

[0062] For example, a pre-set user-mode instruction refers to a non-privileged instruction defined in advance to handle a specific type of interrupt request. A non-privileged instruction means that the instruction can be executed without entering the kernel state of the operating system, that is, the non-privileged instruction can be executed in the user-mode of the operating system without switching to the kernel state of the operating system.

[0063] In an embodiment of the present application, a user-state process is a process that can be created, isolated, scheduled, and destroyed in the user-state mode of the operating system without entering the kernel-state mode of the operating system.

[0064] In some embodiments, each user state process is started by an operating system process associated with the user state process, and multiple operating system processes share the shared memory area.

[0065] like Figure 3 As shown, Figure 3 This is a schematic diagram of the structure of a user-mode process provided in an embodiment of the present application.

[0066] Specifically, an operating system may include multiple operating system processes, for example, including operating system process 1, operating system process 1, ..., and operating system process M. Shared memory is a communication mechanism between multiple operating system processes. A shared memory region is a block of physical memory that multiple operating system processes can share. A preconfigured scheduler generates and executes scheduling decisions. The address mapping of a shared memory region is identical in all participating operating system processes. That is, any data in the shared memory region can be accessed from the same address across multiple shared operating system processes.

[0067] For each operating system process among multiple operating system processes, a pre-configured manager can be used to create and initialize a user state process associated with the operating system process. For example, the manager can be used to create and initialize the user state process 1 associated with operating system process 1, and the manager can be used to create and initialize the user state process M associated with operating system process M.

[0068] Each user state process is started by an operating system process associated with the user state process. Multiple threads can be created in the operating system process and assigned to the CPU to run application tasks.

[0069] Each user-state process only has read and write permissions for the second memory area it occupies in the shared memory area, and does not have read and write permissions for other memory areas in the shared memory area. For example, user-state process 1 only has read and write permissions for the user-state process 1 memory area it occupies in the shared memory area, and user-state process M only has read and write permissions for the user-state process M memory area it occupies in the shared memory area.

[0070] The executable files and libraries of each user-mode process are loaded into the second memory area occupied by itself in the shared memory area. Different applications can run in different user-mode processes. For example, application 1 runs in user-mode process 1, application M runs in user-mode process M, and so on.

[0071] Each user-state process may have multiple CPU cores for executing the user-state process. For example, CPU cores 1 , 2 , and 3 are used to execute user-state process 1 , and CPU cores i, . . . , and k are used to execute user-state process M.

[0072] In some embodiments, each page table entry in the operating system may contain multiple reserved bits for expansion or specific purposes. The K-bit reserved space in each page table entry may be used to divide the shared memory area into two K A unique code can be assigned to each memory area, for example, the unique codes are 0-15.

[0073] It should be noted that 2 K A memory area may include multiple second memory areas respectively occupied by different user-mode processes, a first memory area, and an unused memory area.

[0074] Exemplarily, the value of K may be determined according to the hardware implementation of the CPU. For example, K may be 4 or 5.

[0075] For example, the number of user-mode processes can be 2 K -3.

[0076] In some embodiments, the shared memory area is pre-divided into N memory areas, and each CPU core is configured with a first register containing N permission identifiers. The N permission identifiers correspond one-to-one to the N memory areas, and each permission identifier is used to represent the CPU core's access rights to the memory area corresponding to the permission identifier.

[0077] For example, the shared memory area is pre-divided into 16 memory areas, each memory area is configured with a unique code, 0-15, and the CPU core is configured with a first register containing 16 two-bit permission identifiers.

[0078] Assuming that the code of the memory area occupied by the user-mode process executed by the CPU core in the shared memory area is 3, the 16 two-bit permission identifiers in the first register of the CPU core can be as shown in Table 1.

[0079] Table 1

[0080]

[0081] In the table, the two-bit permission identifier can be 00, 01, 10 and 11, among which, when the two-bit permission identifier is 00, it can indicate that the CPU core does not have read permission and write permission to the first memory area; when the two-bit permission identifier is 01, it can indicate that the CPU core only has read permission to the first memory area; when the two-bit permission identifier is 10, it can indicate that the CPU core only has write permission to the first memory area; when the two-bit permission identifier is 11, it can indicate that the CPU core has both read permission and write permission to the first memory area.

[0082] In some embodiments, obtaining read and write permissions for a first memory area in a shared memory area using a preset user mode instruction includes:

[0083] Using a preset user mode instruction, the permission identifier corresponding to the first memory area in the first register is modified to a first value, where the first value indicates that the CPU core has read and write permissions for the first memory area.

[0084] For example, when the CPU core receives an interrupt request, the code of the memory area occupied by the user mode process executed by it in the shared memory area is 3, then the 16 two-bit permission identifiers in the first register of the CPU core can be as shown in Table 1.

[0085] Assume that the code of the first memory area is 15, and the first value of the two-bit permission identifier is "11", indicating that the CPU core has both read permission and write permission for the corresponding memory area.

[0086] Then, a preset user mode instruction can be used to modify the permission identifier corresponding to code 15 in the first register of the CPU core to "11". The 16 two-bit permission identifiers in the first register of the CPU core after modification can be shown in Table 2.

[0087] Table 2

[0088]

[0089] In some embodiments, upon receiving an interrupt request, the CPU core may also use a pre-set user mode instruction to modify all permission identifiers in its first register to the first value. That is, the CPU core may obtain read and write permissions for all memory areas in the shared memory area, including the first memory area.

[0090] S102: Read and execute the switching function from the first memory area to schedule the computing resources of the CPU core from the first user state process to the target user state process, wherein the first user state process is the user state process executed by the CPU core when receiving the interrupt request, and when the CPU core executes any user state process, it only has read and write permissions to the second memory area occupied by the user state process in the shared memory area.

[0091] After the CPU core obtains the read and write permissions of the first memory area in the shared memory area through S101, it enters the privileged mode. In the privileged mode, the CPU core can read and execute a pre-set switching function for switching the user-mode process executed by the CPU core from the first memory area to schedule the CPU core to execute the target user-mode process.

[0092] In some embodiments, when the CPU core receives an interrupt request, the user state process executed by the CPU core is the first user state process. At this time, the running stack used by the CPU core is the running stack of the first user state process.

[0093] The running stack is switched from the running stack of the first user state process to the running stack of the user state runtime; the entry address of the switching function is read from a preset designated position in the shared memory area; and the switching function is read and executed by jumping to the entry address.

[0094] In some embodiments, the scheduler may send an interrupt request to the CPU core, and the CPU core may receive the interrupt request from the scheduler.

[0095] The scheduler can obtain the performance parameters of the applications running in each user-mode process and determine the target user-mode process to be executed by a CPU core based on these performance parameters. In addition, the scheduler will also record the CPU core number and the corresponding target user-mode process information as an entry in a pre-set mapping table.

[0096] The switching function pre-set in the first memory area includes a first parameter, which is used to indicate the number of the CPU core executing the switching function. The value of the first parameter changes dynamically based on the CPU core currently executing the switching function. For example, when the CPU core executing the switching function is numbered 3, the value of the first parameter is 3, and when the CPU core executing the switching function is numbered 4, the value of the first parameter changes to 4.

[0097] During the execution of the switching function, the CPU core will obtain the target user state process from a preset mapping table according to the value of the first parameter included in the switching function.

[0098] In some embodiments, the shared memory area also includes a pre-set third memory area, which is used to record the values ​​of N permission identifiers in the first register of each CPU core when the CPU core executes the current user-mode process, using the CPU core number as the offset address.

[0099] After scheduling the computing resources of the CPU core from the first user state process to the target user state process, a permission restoration step is further included, and the permission restoration step includes:

[0100] Using the CPU core number as an offset address, obtain the values ​​of N permission identifiers in the first register of the CPU core when executing the target user mode process from a third memory area preset in the shared memory area;

[0101] Using the obtained values ​​of the N permission identifiers in the first register of the CPU core when executing the target user state process, the current values ​​of the N permission identifiers in the first register of the CPU core are updated so that the CPU core only has read and write permissions for the second memory area occupied by the target user state process in the shared memory area.

[0102] In this embodiment, after the computing resources of the CPU core are scheduled from the first user state process to the target user state process, the CPU core is restored from the privileged mode to the non-privileged mode through the permission recovery step, and the access permission control of the shared memory area is used to ensure that the CPU core enters the privileged mode only when executing the switching function pre-set in the first memory area for switching the user state process executed by the CPU core, and is in non-privileged mode when executing other codes.

[0103] In some embodiments, after updating the current values ​​of the N permission identifiers in the first register of the CPU core using the obtained values ​​of the N permission identifiers in the first register when the CPU core executes the target user state process, the values ​​of the N permission identifiers in the first register of the CPU core when the CPU core executes the target user state process may be obtained again from the third memory area using the CPU core number as an offset address;

[0104] Determine whether the values ​​of the N permission identifiers in the first register of the CPU core obtained again when executing the target user state process are the same as the values ​​of the N permission identifiers in the first register of the CPU core after the update;

[0105] If they are different, repeat the above permission recovery steps.

[0106] In this embodiment, the values ​​of N permission identifiers in the first register of the CPU core when executing the target user-mode process are obtained again from the third memory area and compared with the updated values ​​to avoid the situation where the CPU core cannot be restored from privileged mode to non-privileged mode due to malicious attacks.

[0107] In an embodiment of the present application, when an interrupt request is received, the read and write permissions of the first memory area in the shared memory area are obtained by using a pre-set user-state instruction, and the switching function is read and executed from the first memory area to schedule the computing resources of the CPU core from the first user-state process to the target user-state process, wherein the first user-state process is the user-state process executed by the CPU core when the interrupt request is received. When the CPU core executes any user-state process, it only has the read and write permissions of the second memory area occupied by the user-state process in the shared memory area. Since any user-state process can only read and write the memory space occupied by itself, it cannot read and write the memory space occupied by other user-state processes, and the process of switching the user-state process executed by the CPU core is all in the user-state mode of the operating system, there is no need to enter the kernel mode of the operating system, thereby reducing the computing resource overhead of process switching while ensuring process isolation and improving the CPU computing resource utilization.

[0108] like Figure 4 As shown, Figure 4 This is a schematic diagram of a method for scheduling computing resources provided in an embodiment of the present application.

[0109] For the pre-configured shared memory area, memory access control is implemented in the shared memory area. The shared memory area includes the user state process area and the privileged area, wherein the user state process area is composed of multiple second memory areas, each second memory area is a memory area occupied by a user state process, and the user state process only has the read and write permissions of the second memory area occupied by itself, and does not have the read and write permissions of other memory areas in the shared memory area. For example, Figure 4 In the figure, user state process 1 only has read and write permissions for the memory area occupied by user state process 1, and does not have read and write permissions for other memory areas (memory areas with dotted lines) in the shared memory area.

[0110] The privileged area is the memory area occupied by the user-mode runtime. In this privileged area, the user-mode runtime exists in the form of code, which contains pre-set switching functions for switching the user-mode process executed by the CPU core.

[0111] By implementing memory access control in the shared memory area, the CPU core has read and write permissions to the first memory area only when it needs to execute a switching function to switch the user-state process it is executing. When executing other codes, such as the code of any user-state process, the CPU core only has read and write permissions to the second memory area occupied by the user-state process in the shared memory area, and does not have read and write permissions to the first memory area. This ensures that the user-state processes executed by the CPU core in the user-state switching of the operating system are supported while ensuring isolation between the user-state processes.

[0112] The scheduler can obtain the performance parameters of the applications running in each user-mode process and determine the target user-mode process to be executed by a CPU core based on these performance parameters. In addition, the scheduler will also record the CPU core number and the corresponding target user-mode process information as an entry in a pre-set mapping table.

[0113] After determining the target user-mode process to be switched to execution by the CPU core, the scheduler sends a user-mode interrupt (interrupt request) to the CPU core.

[0114] The user state process executed by the CPU core when receiving an interrupt request is the first user state process. Figure 4 In the example, user process 1 is the first user process. When the CPU core executes a user process, it has read and write permissions only for the second memory area occupied by the user process in the shared memory area, and does not have read and write permissions for other memory areas in the shared memory area.

[0115] When an interrupt request is received, the CPU core saves the execution state at the time of the interrupt and jumps to the call gate to start execution, thereby enhancing the privileges of the CPU core and putting the CPU core into privileged mode.

[0116] Specifically, a call gate can include the following steps:

[0117] 1. The CPU core uses a preset user mode instruction to rewrite the values ​​of N permission identifiers in the first register, so that the CPU core has read and write permissions for N memory areas, thereby entering the privileged mode.

[0118] The shared memory area is pre-divided into N memory areas. The CPU core is configured with a first register containing N permission identifiers. The N permission identifiers correspond one-to-one to the N memory areas. Each permission identifier is used to represent the CPU core's access rights to the memory area corresponding to the permission identifier.

[0119] In privileged mode, the CPU core has read and write permissions to N memory areas. Under normal circumstances, user-mode processes can only read and write to the memory areas occupied by themselves, and cannot read or write to memory areas not occupied by themselves.

[0120] The CPU core enters the privileged mode only when executing a switching function preset in the first memory area for switching the user mode process executed by the CPU core, and is in the non-privileged mode when executing other codes.

[0121] 2. Switch the running stack of the first user state process to the running stack of the user state runtime.

[0122] 3. Read the entry address of the switching function from the pre-set specified location in the shared memory area.

[0123] 4. Jump to the entry address, read and execute the switching function, and return after execution.

[0124] The preset switching function includes a first parameter, which is used to indicate the number of the CPU core that executes the switching function. The value of the first parameter changes dynamically according to the CPU core that currently executes the switching function.

[0125] During the execution of the switching function, the CPU core will obtain the target user state process from a preset mapping table according to the value of the first parameter included in the switching function, and switch the execution state to the target user state process. Figure 4 In the example, CPU core 3 is used to execute user state process 1 when receiving an interrupt request, and after executing the switching function, CPU core 3 is used to execute user state process 2.

[0126] 5. Switch the running stack of the user-mode runtime to the running stack of the target user-mode process.

[0127] 6. Using the CPU core number as the offset address, obtain the values ​​of N permission identifiers in the first register of the CPU core when executing the target user mode process from a third memory area preset in the shared memory area.

[0128] The shared memory area also includes a pre-set third memory area, namely Figure 4 The "communication pipe" memory area in the CPU core memory is used to record the values ​​of N permission identifiers in the first register of each CPU core when the CPU core executes the current user mode process, using the CPU core number as the offset address.

[0129] 7. Using the obtained values ​​of the N permission identifiers in the first register of the CPU core when executing the target user state process, update the current values ​​of the N permission identifiers in the first register of the CPU core, so that the CPU core only has read and write permissions for the second memory area occupied by the target user state process in the shared memory area.

[0130] The CPU core is restored from privileged mode to non-privileged mode through the permission recovery step. Through the access permission control of the shared memory area, it is ensured that the CPU core enters the privileged mode only when executing the switching function pre-set in the first memory area for switching the user mode process executed by the CPU core, and is in non-privileged mode when executing other codes.

[0131] 8. Using the CPU core number as the offset address, obtain the values ​​of the N permission identifiers in the first register of the CPU core when executing the target user mode process from the third memory area again.

[0132] 9. Determine whether the values ​​of the N permission identifiers in the first register of the CPU core obtained again when executing the target user mode process are the same as the values ​​of the N permission identifiers in the first register of the CPU core after the update;

[0133] If they are the same, return from the call gate;

[0134] If they are different, return to step 6.

[0135] By again obtaining the values ​​of the N permission identifiers in the first register of the CPU core when executing the target user-mode process from the third memory area and comparing them with the updated values, the situation in which the CPU core cannot be restored from privileged mode to non-privileged mode due to malicious attacks can be avoided.

[0136] In an embodiment of the present application, when an interrupt request is received, the read and write permissions of the first memory area in the shared memory area are obtained by using a pre-set user-state instruction, and the switching function is read and executed from the first memory area to schedule the computing resources of the CPU core from the first user-state process to the target user-state process, wherein the first user-state process is the user-state process executed by the CPU core when the interrupt request is received. When the CPU core executes any user-state process, it only has the read and write permissions of the second memory area occupied by the user-state process in the shared memory area. Since any user-state process can only read and write the memory space occupied by itself, it cannot read and write the memory space occupied by other user-state processes, and the process of switching the user-state process executed by the CPU core is all in the user-state mode of the operating system, there is no need to enter the kernel mode of the operating system, thereby reducing the computing resource overhead of process switching while ensuring process isolation and improving the CPU computing resource utilization.

[0137] The above content describes the method provided by this application. The following describes the device provided by this application:

[0138] See Figure 5 , Figure 5 A schematic diagram of the structure of a scheduling device for computing resources provided in an embodiment of the present application.

[0139] like Figure 5 As shown, the device may include:

[0140] The privilege escalation unit 510 is configured to, upon receiving an interrupt request, obtain read and write permissions for a first memory area in the shared memory area using a preset user-mode instruction, wherein the first memory area is pre-set with a switching function for switching a user-mode process executed by a CPU core;

[0141] The scheduling unit 520 is used to read and execute the switching function from the first memory area to schedule the computing resources of the CPU core from the first user state process to the target user state process, wherein the first user state process is the user state process executed by the CPU core when receiving the interrupt request, and when the CPU core executes any user state process, it only has read and write permissions for the second memory area occupied by the user state process in the shared memory area.

[0142] In some embodiments, the scheduling unit 520 is specifically configured to:

[0143] Switching the running stack from the running stack of the first user state process to the running stack during user state runtime;

[0144] Reading an entry address of the switching function from a preset designated location in the shared memory area;

[0145] Jump to the entry address to read and execute the switching function.

[0146] In some embodiments, each user state process is started by an operating system process associated with the user state process, and multiple operating system processes share the shared memory area.

[0147] In some embodiments, the shared memory area is pre-divided into N memory areas, and the CPU core is configured with a first register containing N permission identifiers, the N permission identifiers correspond one-to-one to the N memory areas, and each permission identifier is used to represent the CPU core's access rights to the memory area corresponding to the permission identifier.

[0148] In some embodiments, the privilege escalation unit 510 is specifically configured to:

[0149] Using a preset user mode instruction, the permission identifier corresponding to the first memory area in the first register is modified to a first value, where the first value indicates that the CPU core has read and write permissions for the first memory area.

[0150] In some embodiments, the apparatus further includes a permission restoration unit configured to perform a permission restoration step, wherein the permission restoration step includes:

[0151] Using the number of the CPU core as an offset address, obtaining, from a third memory area preset in the shared memory area, the values ​​of the N permission identifiers when the CPU core executes the target user state process, wherein the third memory area is used to record the values ​​of the N permission identifiers in the first register of each CPU core when the CPU core executes the current user state process;

[0152] Using the obtained values ​​of the N permission identifiers of the CPU core when executing the target user state process, the values ​​of the N permission identifiers in the first register of the CPU core are updated so that the CPU core only has read and write permissions for the second memory area occupied by the target user state process in the shared memory area.

[0153] In some embodiments, the permission recovery unit is further configured to:

[0154] Using the number of the CPU core as an offset address, again obtaining from the third memory area the values ​​of the N permission identifiers when the CPU core executes the target user mode process;

[0155] Determine whether the values ​​of the N permission identifiers obtained again when the CPU core executes the target user mode process are the same as the values ​​of the N permission identifiers in the first register of the CPU core after the update;

[0156] If different, repeat the permission recovery step.

[0157] The implementation process of the functions and effects of each unit in the above-mentioned device is specifically described in the implementation process of the corresponding steps in the above-mentioned method, and will not be repeated here.

[0158] The embodiment of the present application also provides a hardware structure. Figure 6 , Figure 6 This is a structural diagram of an electronic device provided in an embodiment of the present application. Figure 6 As shown, the hardware structure may include: a processor and a machine-readable storage medium, the machine-readable storage medium storing machine-executable instructions that can be executed by the processor; the processor is used to execute the machine-executable instructions to implement the method disclosed in the above example of this application.

[0159] Based on the same application concept as the above method, an embodiment of the present application also provides a machine-readable storage medium, on which a number of computer instructions are stored. When the computer instructions are executed by a processor, the method disclosed in the above example of the present application can be implemented.

[0160] Exemplarily, the machine-readable storage medium may be any electronic, magnetic, optical, or other physical storage device that may contain or store information, such as executable instructions, data, and the like. For example, the machine-readable storage medium may be: RAM (Random Access Memory), volatile memory, non-volatile memory, flash memory, a storage drive (such as a hard disk drive), a solid-state drive, any type of storage disk (such as a CD, DVD, etc.), or similar storage media, or a combination thereof.

[0161] It should be noted that, in this document, relational terms such as target and objective are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article or device comprising the element.

[0162] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A method for scheduling computing resources, applied to a CPU core, characterized in that: The method comprises: When an interrupt request is received, the user-mode instruction is used to obtain read and write permissions for a first memory area in the shared memory area, where a switching function for switching the user-mode process executed by the CPU core is pre-set; The switching function is read and executed from the first memory area to schedule the computing resources of the CPU core from the first user state process to the target user state process, wherein the first user state process is the user state process executed by the CPU core when receiving the interrupt request, and when the CPU core executes any user state process, it only has read and write permissions to the second memory area occupied by the user state process in the shared memory area.

2. The method according to claim 1, characterized in that The step of reading and executing the switching function from the first memory area includes: Switching the running stack from the running stack of the first user state process to the running stack during user state runtime; Reading an entry address of the switching function from a preset designated location in the shared memory area; Jump to the entry address to read and execute the switching function.

3. The method according to claim 1, characterized in that Each user state process is started by an operating system process associated with the user state process, and multiple operating system processes share the shared memory area.

4. The method according to claim 1, wherein The shared memory area is pre-divided into N memory areas, and the CPU core is configured with a first register containing N permission identifiers, the N permission identifiers correspond one-to-one to the N memory areas, and each permission identifier is used to represent the access rights of the CPU core to the memory area corresponding to the permission identifier.

5. The method according to claim 4, characterized in that The method of obtaining the read and write permissions of the first memory area in the shared memory area by using a preset user state instruction includes: Using a preset user mode instruction, the permission identifier corresponding to the first memory area in the first register is modified to a first value, where the first value indicates that the CPU core has read and write permissions for the first memory area.

6. The method according to claim 4, characterized in that After scheduling the computing resources of the CPU core from the first user state process to the target user state process, the method further includes a permission restoration step, the permission restoration step including: Using the number of the CPU core as an offset address, obtaining, from a third memory area preset in the shared memory area, the values ​​of the N permission identifiers when the CPU core executes the target user state process, wherein the third memory area is used to record the values ​​of the N permission identifiers in the first register of each CPU core when the CPU core executes the current user state process; Using the obtained values ​​of the N permission identifiers of the CPU core when executing the target user state process, the values ​​of the N permission identifiers in the first register of the CPU core are updated so that the CPU core only has read and write permissions for the second memory area occupied by the target user state process in the shared memory area.

7. The method according to claim 6, characterized in that After updating the values ​​of the N permission identifiers in the first register of the CPU core, the method further includes: Using the number of the CPU core as an offset address, again obtaining from the third memory area the values ​​of the N permission identifiers when the CPU core executes the target user mode process; Determine whether the values ​​of the N permission identifiers obtained again when the CPU core executes the target user mode process are the same as the values ​​of the N permission identifiers in the first register of the CPU core after the update; If different, repeat the permission recovery step.

8. A computing resource scheduling device, applied to a CPU core, characterized in that: The device comprises: a privilege escalation unit, configured to, upon receiving an interrupt request, obtain read and write permissions for a first memory area in the shared memory area using a preset user-mode instruction, wherein the first memory area is pre-set with a switching function for switching a user-mode process executed by a CPU core; A scheduling unit is used to read and execute the switching function from the first memory area to schedule the computing resources of the CPU core from the first user state process to the target user state process, wherein the first user state process is the user state process executed by the CPU core when receiving the interrupt request, and when the CPU core executes any user state process, it only has read and write permissions for the second memory area occupied by the user state process in the shared memory area.

9. An electronic device, characterized in that: The system comprises a processor and a memory, wherein the memory stores machine-executable instructions that can be executed by the processor, and the processor is configured to execute the machine-executable instructions to implement the method according to any one of claims 1 to 7.

10. A machine-readable storage medium, characterized in that The machine-readable storage medium stores machine-executable instructions, and when the machine-executable instructions are executed by a processor, the method according to any one of claims 1 to 7 is implemented.

11. A computer program product comprising a computer program / instructions, characterized in that When the computer program / instructions are executed by a processor, the steps of the method according to any one of claims 1 to 7 are implemented.

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