Error correction decoding method, device, electronic device and computer readable storage medium

Abstract

The embodiments of the present invention provide an error correction decoding method, device, electronic device and computer-readable storage medium. The method includes: obtaining pMLC data; reading target valid bit data from the pMLC data; decoding the target valid bit data based on a preset error correction engine; in the case of decoding failure, combining and encoding the target valid bit data, the first valid bit data and the second valid bit data to obtain threshold distribution level information; based on the error correction engine, identifying the offset scenario of the threshold voltage distribution of the pMLC data according to the threshold distribution level information; in the case of identifying that the offset scenario of the threshold voltage distribution of the pMLC data is a right-biased scenario, bit flipping the data in the target level storage unit corresponding to the target valid bit data. According to the solution of the embodiment of the present invention, the error correction decoding capability can be improved.

Description

Technical Field

[0001] The present invention relates to the field of data processing technology, and in particular to an error correction decoding method, device, electronic equipment and computer-readable storage medium. Background Art

[0002] NAND Flash can be divided into SLC (single-layer cell, each cell stores 1 bit of data), MLC (multi-layer cell, each cell stores 2 bits of data), TLC (three-layer cell, each cell stores 3 bits of data) and QLC (four-layer cell, each cell stores 4 bits of data) according to the number of bits of data stored in the storage cell. TLC or QLC type NAND Flash can also program TLC / QLC type storage cells into MLC-like storage cells through special programming methods, which is called pMLC (pseudo Multi-Level Cell) in the industry.

[0003] In the prior art, decoding of pMLC data generally can only rely on the error correction engine to decode and correct the least significant bit (LSB) and the most significant bit (MSB) data in the pMLC separately. At this time, the upper limit of the decoding capability depends on the error correction capability of the error correction engine. Once the number of error bits in the LSB and MSB data exceeds the upper limit of the error correction capability of the error correction engine, data loss will occur. Summary of the invention

[0004] The present invention aims to solve at least one of the technical problems existing in the prior art.

[0005] To this end, the present invention proposes an error correction decoding method, which can improve the error correction decoding capability.

[0006] The present invention also provides a device applying the error correction decoding method.

[0007] The present invention also provides an electronic device using the error correction decoding method.

[0008] The present invention also provides a computer-readable storage medium applying the above error correction decoding method.

[0009] The error correction decoding method according to the first aspect of the present invention includes:

[0010] Acquire pseudo multi-level cell pMLC data, wherein the pMLC data includes target valid bit data, first valid bit data and second valid bit data;

[0011] Reading the target valid bit data from the pMLC data;

[0012] Decoding the target valid bit data based on a preset error correction engine;

[0013] In case of decoding failure, the first valid bit data and the second valid bit data are read; and the target valid bit data, the first valid bit data and the second valid bit data are combined and coded to obtain threshold distribution level information;

[0014] Based on the error correction engine, an offset scenario of the threshold voltage distribution of the pMLC data is identified and processed according to the threshold distribution level information;

[0015] When it is identified that the offset scenario of the threshold voltage distribution of the pMLC data is a right-skewed scenario, a bit flipping process is performed on the data in the target level storage unit corresponding to the target valid bit data.

[0016] According to some embodiments of the present invention, in the case of a decoding failure, reading the first valid bit data and the second valid bit data; and performing combined encoding processing on the target valid bit data, the first valid bit data and the second valid bit data to obtain threshold distribution level information includes:

[0017] In the case where the error correction engine fails to decode the target valid bit data, reading the first valid bit data and the second valid bit data from the pMLC data based on a preset read threshold voltage;

[0018] Combining and encoding the target valid bit data, the first valid bit data and the second valid bit data in bitwise order to obtain a storage unit value;

[0019] The threshold distribution level information is determined according to the storage unit value.

[0020] According to some embodiments of the present invention, the identifying and processing the offset scenario of the threshold voltage distribution of the pMLC data based on the threshold distribution level information by the error correction engine includes:

[0021] determining a first target threshold voltage and a second target threshold voltage from the threshold distribution level information;

[0022] An identification process is performed on the number of storage cells of the first target threshold voltage and the number of storage cells of the second target threshold voltage to determine an offset scenario of the threshold voltage distribution of the pMLC data.

[0023] According to some embodiments of the present invention, when the target valid bit data is the least significant bit data, performing bit flipping processing on the data in the target level storage unit corresponding to the target valid bit data includes:

[0024] Determine a first right-biased direction level storage unit and a second right-biased direction level storage unit according to the least significant bit data, wherein the target level storage unit includes the first right-biased direction level storage unit and the second right-biased direction level storage unit;

[0025] Bit flipping is performed on the data in the first right-biased pointing level storage unit and the second right-biased pointing level storage unit.

[0026] According to some embodiments of the present invention, when the target valid bit data is the most significant bit data, performing bit flipping processing on the data in the target level storage unit corresponding to the target valid bit data includes:

[0027] Determine a third right-biased pointing level storage unit and a fourth right-biased pointing level storage unit according to the most significant bit data, wherein the target level storage unit includes the third right-biased pointing level storage unit and the fourth right-biased pointing level storage unit;

[0028] The data in the third right-biased pointing level storage unit and the fourth right-biased pointing level storage unit are subjected to bit flipping processing.

[0029] According to some embodiments of the present invention, when it is identified that the offset scenario of the threshold voltage distribution of the pMLC data is a right-skewed scenario, after performing bit flipping processing on the data in the target level storage unit corresponding to the target valid bit data, the method further includes:

[0030] The data in the target level storage unit after bit flipping is decoded based on the error correction engine.

[0031] According to some embodiments of the present invention, the decoding process on the target valid bit data based on a preset error correction engine includes:

[0032] The target valid bit data is subjected to LDPC or BCH decoding processing based on the error correction engine.

[0033] According to the second aspect of the present invention, the error correction decoding device comprises:

[0034] A first processing unit, configured to obtain pseudo multi-level cell pMLC data, wherein the pMLC data includes target valid bit data, first valid bit data, and second valid bit data;

[0035] A second processing unit, configured to read the target valid bit data from the pMLC data;

[0036] A third processing unit, configured to perform decoding processing on the target valid bit data based on a preset error correction engine;

[0037] a fourth processing unit, configured to read the first valid bit data and the second valid bit data in case of a decoding failure; and perform combined encoding processing on the target valid bit data, the first valid bit data and the second valid bit data to obtain threshold distribution level information;

[0038] A fifth processing unit, configured to identify and process an offset scenario of a threshold voltage distribution of the pMLC data based on the threshold distribution level information by the error correction engine;

[0039] The sixth processing unit is configured to perform bit flipping processing on the data in the target level storage unit corresponding to the target valid bit data when it is identified that the offset scenario of the threshold voltage distribution of the pMLC data is a right-skewed scenario.

[0040] An electronic device according to an embodiment of the third aspect of the present invention includes: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the error correction decoding method as described above when executing the computer program.

[0041] According to a computer-readable storage medium of an embodiment of the fourth aspect of the present invention, the computer-readable storage medium stores computer-executable instructions, and the computer-executable instructions, when executed by a control processor, implement the error correction decoding method as described above.

[0042] According to the error correction decoding method of the embodiment of the present invention, at least the following beneficial effects are achieved: in the process of error correction decoding, firstly, pMLC data is obtained, wherein the pMLC data includes target valid bit data, first valid bit data and second valid bit data; then, the target valid bit data is read from the pMLC data; then, the target valid bit data is decoded based on a preset error correction engine; in the case of decoding failure, the first valid bit data and the second valid bit data are read; and the target valid bit data, the first valid bit data and the second valid bit data are combined and encoded, so as to obtain threshold distribution level information; then, based on the error correction engine, the offset scenario of the threshold voltage distribution of the pMLC data is identified according to the threshold distribution level information; in the case of identifying that the offset scenario of the threshold voltage distribution of the pMLC data is a right-biased scenario, the data in the target level storage unit corresponding to the target valid bit data is bit flipped. Through the above technical solution, in the process of error correction decoding, the threshold voltage distribution information of each bit of the valid data is obtained in combination with the threshold voltage distribution characteristics of the pMLC data after programming, the decoding capability of the error correction engine is increased, and the error correction decoding capability is improved to reduce the situation of error correction engine decoding failure.

[0043] Other features and advantages of the present invention will be described in the following description, and partly become apparent from the description, or understood by practicing the present invention. The purpose and other advantages of the present invention can be realized and obtained by the structures particularly pointed out in the description, claims and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] The accompanying drawings are used to provide further understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation on the technical solution of the present disclosure.

[0045] Figure 1 It is a schematic diagram of the principle of converting TLC to pMLC provided by one embodiment of the present invention;

[0046] Figure 2 is a flow chart of an error correction decoding method provided by an embodiment of the present invention;

[0047] Figure 3 yes Figure 1 Sub-flow chart of step S400 in;

[0048] Figure 4 yes Figure 1 Sub-flow chart of step S500 in;

[0049] Figure 5 yes Figure 1 Sub-flow chart of step S600 in;

[0050] Figure 6 yes Figure 1 Another sub-flowchart of step S600 in;

[0051] Figure 7 is a flow chart of an error correction decoding method provided by another embodiment of the present invention;

[0052] Figure 8 yes Figure 1 Sub-flow chart of step S300 in;

[0053] Fig. 9 is a schematic diagram of the structure of an error correction decoding device provided by an embodiment of the present invention;

[0054] Fig.10 It is a schematic diagram of the structure of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0055] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0056] In the description of the present invention, "several" means one or more, "more" means more than two, "greater than", "less than", "exceed" etc. are understood as not including the number itself, and "above", "below", "within" etc. are understood as including the number itself. If there is a description of "first" or "second", it is only used for the purpose of distinguishing the technical features, and cannot be understood as indicating or implying the relative importance or implicitly indicating the number of the indicated technical features or implicitly indicating the order of the indicated technical features.

[0057] In the description of the present invention, unless otherwise clearly defined, terms such as setting, installing, connecting, etc. should be understood in a broad sense, and technicians in the relevant technical field can reasonably determine the specific meanings of the above terms in the present invention based on the specific content of the technical solution.

[0058] The present invention provides an error correction decoding method, device, electronic device and computer-readable storage medium, the method comprising: in the process of error correction decoding, firstly obtaining pMLC data, wherein the pMLC data comprises target valid bit data, first valid bit data and second valid bit data; then reading the target valid bit data from the pMLC data; then decoding the target valid bit data based on a preset error correction engine; in case of decoding failure, reading the first valid bit data and the second valid bit data; and combining and encoding the target valid bit data, the first valid bit data and the second valid bit data, so as to obtain threshold distribution level information; then identifying and processing the offset scenario of the threshold voltage distribution of the pMLC data based on the error correction engine according to the threshold distribution level information; in case the offset scenario of the threshold voltage distribution of the pMLC data is identified as a right-biased scenario, bit flipping processing is performed on the data in the target level storage unit corresponding to the target valid bit data. Through the above technical solution, during the error correction decoding process, the threshold voltage distribution information of each bit of valid data is obtained in combination with the threshold voltage distribution characteristics of the programmed pMLC data, thereby increasing the decoding capability of the error correction engine and improving the error correction decoding capability to reduce the number of decoding failures of the error correction engine.

[0059] The embodiments of the present invention are further described below in conjunction with the accompanying drawings.

[0060] like Figure 1 As shown, Figure 1This is a schematic diagram of the principle of converting TLC to pMLC. Taking the TLC type storage unit as an example, its 3-bit storage unit is named the least significant bit (LSB), the center significant bit (CSB) and the most significant bit (MSB). The LSB data that should be written in accordance with the NAND Flash requirements is bit-by-bit XORed with the MSB data, and the XORed data replaces the original CSB data. Then the above LSB data, MSB data and the replaced CSB data are written to the NAND Flash. At this time, pMLC data can be achieved. At this time, LSB and MSB are valid data, and CSB is invalid data. On this basis, CSB data will not be able to store valid user data, while LSB and MSB data can store valid user data. The threshold voltage distribution of pMLC data in NAND Flash is similar to that of MLC data. Error bits may be generated after experiencing some stress scenarios. However, the threshold voltage distribution characteristic of pMLC data after programming is that there is at least one TLC Level threshold interval between the threshold distribution of each Level. Therefore, taking the same or type of pMLC data as an example, the LSB and MSB data have a larger left-biased safety area, and the right-biased safety area is similar to the original TLC type threshold distribution voltage, as shown in the figure. At present, the decoding of pMLC data can generally only rely on the error correction engine to decode and correct the LSB and MSB data in pMLC separately. At this time, the upper limit of the decoding capability depends on the error correction capability of the error correction engine. However, the present invention proposes a method for combining CSB data with another valid data to significantly improve the error correction capability of LSB data and MSB data in some scenarios in view of the programming characteristics of pMLC. The present invention utilizes the programming characteristics of NAND Flash pMLC, combined with the decoding function design of the error correction engine hardware, to improve the final error correction capability and greatly reduce the phenomenon of data error correction decoding failure.

[0061] like Figure 2 As shown, a flowchart of an error correction decoding method provided by an embodiment of the present invention. The method includes but is not limited to step S100, step S200, step S300, step S400, step S500 and step S600:

[0062] Step S100, obtaining pseudo multi-level cell pMLC data, wherein the pMLC data includes target valid bit data, first valid bit data and second valid bit data;

[0063] Step S200, reading target valid bit data from pMLC data;

[0064] Step S300, decoding the target valid bit data based on a preset error correction engine;

[0065] Step S400, in case of decoding failure, reading the first valid bit data and the second valid bit data; and performing combined encoding processing on the target valid bit data, the first valid bit data and the second valid bit data to obtain threshold distribution level information;

[0066] Step S500, based on the error correction engine, the offset scenario of the threshold voltage distribution of the pMLC data is identified and processed according to the threshold distribution level information;

[0067] Step S600 , when it is identified that the shift scenario of the threshold voltage distribution of the pMLC data is a right-skewed scenario, bit flipping processing is performed on the data in the target level storage unit corresponding to the target valid bit data.

[0068] It should be noted that, in the process of error correction decoding, firstly, pMLC data is obtained, wherein the pMLC data includes target valid bit data, first valid bit data and second valid bit data; then, the target valid bit data is read from the pMLC data; then, the target valid bit data is decoded based on a preset error correction engine; in the case of decoding failure, the first valid bit data and the second valid bit data are read; and the target valid bit data, the first valid bit data and the second valid bit data are combined and encoded, so as to obtain threshold distribution level information; then, based on the error correction engine, the offset scenario of the threshold voltage distribution of the pMLC data is identified and processed according to the threshold distribution level information; in the case of identifying that the offset scenario of the threshold voltage distribution of the pMLC data is a right-biased scenario, the data in the target level storage unit corresponding to the target valid bit data is bit-flipped. Through the above technical solution, in the process of error correction decoding, the threshold voltage distribution information of each bit of the valid data is obtained in combination with the threshold voltage distribution characteristics of the pMLC data after programming, the decoding capability of the error correction engine is increased, and the error correction decoding capability is improved to reduce the situation of error correction engine decoding failure.

[0069] It is worth noting that in the process of obtaining the target valid bit data in the pMLC data, when the target valid bit data is the least significant bit LSB data, the first valid bit data can be the middle significant bit CSB data, and the second valid bit data can be the most significant bit MSB data; when the target valid bit data is the MSB data, the first valid bit data can be the LSB data, and the second valid bit data can be the CSB data.

[0070] It is worth noting that in the embodiment of the present invention, when the error correction decoding capability of the error correction engine is lower than the number of error bits of the target valid bit data, the error correction engine will not be able to correctly decode the target valid bit data, resulting in decoding failure.

[0071] In some embodiments of the present invention, reference Figure 1 , taking the conversion of TLC data type to pMLC data type as an example, when error correction decoding is performed on the LSB data or MSB data of pMLC, if the decoding fails, the default read threshold voltage can be used to read the other two types of data. For example, when the decoding engine fails to decode the LSB data, the default read threshold voltage is used to read the CSB data and the MSB data. The three data groups are encoded in bit combination, and the combined encoding represents the value of the TLC storage unit and also represents the threshold distribution level of the storage unit in the NAND Flash. Therefore, after the above processing, the error correction engine can know the threshold distribution level (Erase level->G level) of each bit of the LSB data, and then the error correction engine identifies the error scene. If the LSB data error scene is in the right-biased scene, it is determined that the bit of the LSB data at the (MSB-CSB-LSB, the subsequent description also describes the combination encoding in this order) 110, 011 level is flipped. The error correction engine flips the bits at 110 (A level) and 011 (E level) and decodes again. In addition, the decoding process of the MSB data of pMLC is similar, except that for the MSB data, the levels of bit flipping that can be recognized by the error correction engine through the threshold distribution level are 000 (C level) and 101 (G level).

[0072] In addition, in one embodiment, if Figure 3 As shown, in the event of a decoding failure, the first valid bit data and the second valid bit data are read; and the target valid bit data, the first valid bit data and the second valid bit data are combined and encoded to obtain the threshold distribution level information, which may include but is not limited to step S410, step S420 and step S430.

[0073] Step S410, when the error correction engine fails to decode the target valid bit data, reading the first valid bit data and the second valid bit data from the pMLC data based on a preset read threshold voltage;

[0074] Step S420, performing bit combination encoding on the target valid bit data, the first valid bit data and the second valid bit data to obtain a storage unit value;

[0075] Step S430, determining threshold distribution level information according to the storage unit value.

[0076] It should be noted that in the process of combining and encoding the target valid bit data, the first valid bit data and the second valid bit data to obtain the threshold distribution level information, first, when the error correction engine fails to decode the target valid bit data, the first valid bit data and the second valid bit data are read from the pMLC data based on the preset read threshold voltage; then, the target valid bit data, the first valid bit data and the second valid bit data are bit-combined and encoded to obtain the storage cell value; finally, the threshold distribution level information can be determined according to the storage cell value, in preparation for the subsequent improvement of the decoding capability of the error correction engine.

[0077] It is worth noting that when the target valid bit data is LSB data, the MSB data and CSB data can be read from the pMLC data. When the target valid bit data is MSB data, the LSB data and CSB data can be read from the pMLC data.

[0078] For example, when the decoding engine fails to decode the LSB data, the default read threshold voltage is used to read the CSB data and the MSB data. The three data groups are encoded by bit combination, and the combined code represents the value of the TLC storage unit and also represents the threshold distribution level of the storage unit in the NAND Flash, so as to prepare for the subsequent improvement of the error correction capability of the decoding engine.

[0079] In addition, in one embodiment, if Figure 4 As shown, the error correction engine identifies and processes the offset scenario of the threshold voltage distribution of the pMLC data according to the threshold distribution level information, which may include but is not limited to step S510 and step S520.

[0080] Step S510, determining a first target threshold voltage and a second target threshold voltage from the threshold distribution level information;

[0081] Step S520 , identifying the number of memory cells of the first target threshold voltage and the number of memory cells of the second target threshold voltage to determine a shift scenario of the threshold voltage distribution of the pMLC data.

[0082] It should be noted that in the process of identifying and processing the offset scenario of the threshold voltage distribution of the pMLC data based on the error engine according to the threshold distribution level information, the first target threshold voltage and the second target threshold voltage are first determined from the threshold distribution level information; then the number of storage cells of the first target threshold voltage and the number of storage cells of the second target threshold voltage are identified and processed to determine the offset scenario of the threshold voltage distribution of the pMLC data, in preparation for subsequent data flipping.

[0083] In addition, in one embodiment, if Figure 5 As shown, when the target valid bit data is the least significant bit, bit flipping processing is performed on the data in the target level storage unit corresponding to the target valid bit data, which may include but is not limited to step S610 and step S620.

[0084] Step S610, determining a first right-biased pointing level storage unit and a second right-biased pointing level storage unit according to the least significant bit, wherein the target level storage unit includes the first right-biased pointing level storage unit and the second right-biased pointing level storage unit;

[0085] Step S620, performing bit flipping processing on the data in the first right-biased pointing level storage unit and the second right-biased pointing level storage unit.

[0086] It should be noted that, when the target valid bit data is LSB data, the first right-biased level storage unit and the second right-biased level storage unit will be determined from the pMLC data, wherein the target level storage unit includes the first right-biased level storage unit and the second right-biased level storage unit; then the data in the first right-biased level storage unit and the second right-biased level storage unit can be bit-flipped. For example, when the target valid bit data is LSB data, the data in 110 (A level) and 011 (E level) can be flipped.

[0087] In addition, in one embodiment, if Figure 6 As shown, when the target valid bit data is the most significant bit, bit flipping processing is performed on the data in the target level storage unit corresponding to the target valid bit data, which may include but is not limited to step S630 and step S640.

[0088] Step S630, determining a third right-biased pointing level storage unit and a fourth right-biased pointing level storage unit according to the most significant bit, wherein the target level storage unit includes the third right-biased pointing level storage unit and the fourth right-biased pointing level storage unit;

[0089] Step S640: performing bit flipping processing on the data in the third right-biased pointing level storage unit and the fourth right-biased pointing level storage unit.

[0090] It should be noted that, when the target valid bit data is MSB data, the third right-biased level storage unit and the fourth right-biased level storage unit will be determined from the pMLC data, wherein the target level storage unit includes the third right-biased level storage unit and the fourth right-biased level storage unit; then the data in the third right-biased level storage unit and the fourth right-biased level storage unit can be bit-flipped. For example, when the target valid bit data is MSB data, the data in 000 (C level) and 101 (G level) can be flipped.

[0091] For example, taking the LSB data type of pMLC as an example, its reading voltage is A level and E level. When a decoding error occurs in the LSB data, it means that there is a bit flip in the LSB data, which is manifested in the NAND Flash as a shift in the threshold voltage distribution of the storage cell. For example, the storage cell that should be at the Erase level shifts to the A level, and the storage cell at the D level shifts to the E level. At this time, the storage cell with this shift is manifested as a bit flip. Combined with the programming characteristics of pMLC NAND Flash, Figure 1 It can be seen that when the following conditions are met at the same time, the overall extreme left deviation of the storage cell threshold voltage may also cause the LSB data decoding failure: 1) There are a certain number X of storage cells at the B level that are offset to the Erase level, and a certain number Y of storage cells at the F level that are offset to the D / B level; 2) The value of X+Y is greater than the decoding capability of the error correction engine. The above scenario can be identified by judging the number of storage cells at the Erase level and G level threshold voltages in this scenario. But in general, the probability of pMLC NAND Flash generating an erroneous bit due to the extreme left deviation of the overall threshold voltage distribution is very low. Therefore, when the LSB data fails to be decoded, if the extreme left deviation scenario is excluded by using the above extreme left deviation scenario recognition algorithm, it can be basically determined that the scenario of the LSB data decoding error is a data error scenario caused by the right deviation of the overall threshold voltage distribution. Based on this, when a bit in the LSB data is at A / E level, it can be considered that it is almost 100% offset from the Erase / D level; at this time, the error correction engine can flip the bits in the A and E level storage units, and then decode the flipped data to correct the remaining error bits. The above principle also applies to the MSB data type of pMLC.

[0092] In addition, in one embodiment, if Figure 7As shown, when it is identified that the offset scenario of the threshold voltage distribution of the pMLC data is a right-skewed scenario, after bit flipping is performed on the data in the target level storage unit corresponding to the target valid bit data, the process may also include but is not limited to step S710.

[0093] Step S710: decoding the data in the target level storage unit after bit flipping based on the error correction engine.

[0094] It should be noted that when it is identified that the offset scenario of the threshold voltage distribution of the pMLC data is a right-skewed scenario, after bit-flipping the data in the target level storage unit corresponding to the target valid bit data, the data in the target level storage unit after the bit flipping can be decoded based on the error correction engine, thereby obtaining the correct decoding result.

[0095] In addition, in one embodiment, if Figure 8 As shown, decoding processing is performed on the target valid bit data based on a preset error correction engine, which may include but is not limited to step 310.

[0096] Step 310: Perform LDPC or BCH decoding processing on the target valid bit data based on the error correction engine.

[0097] It should be noted that in the process of decoding the target valid bit data based on the preset error correction engine, the target valid bit data can be subjected to LDPC or BCH decoding based on the error correction engine. Among them, low-density parity-check code decoding (LDPC code) is a linear block code, and its check matrix is ​​sparse, that is, most of the elements in the matrix are 0, and only a few elements are 1. This sparsity makes the LDPC code have a lower complexity when decoding. BCH code (Bose-Chaudhui-Hocquenghem code) is a powerful error correction code, which belongs to linear block code and is particularly suitable for correcting multiple random errors.

[0098] like Fig. 9 As shown, in some embodiments of the present invention, an embodiment of the present invention further provides an error correction decoding device 10, including:

[0099] A first processing unit 100 is used to obtain pseudo multi-level cell pMLC data, wherein the pMLC data includes target valid bit data, first valid bit data and second valid bit data;

[0100] The second processing unit 200 is used to read target valid bit data from the pMLC data;

[0101] The third processing unit 300 is used to decode the target valid bit data based on a preset error correction engine;

[0102] The fourth processing unit 400 is used to read the first valid bit data and the second valid bit data in case of decoding failure; and perform combined encoding processing on the target valid bit data, the first valid bit data and the second valid bit data to obtain threshold distribution level information;

[0103] A fifth processing unit 500 is used to identify and process the offset scenario of the threshold voltage distribution of the pMLC data based on the threshold distribution level information based on the error correction engine;

[0104] The sixth processing unit 600 is configured to perform bit flipping processing on data in a target level storage unit corresponding to target valid bit data when it is identified that the offset scenario of the threshold voltage distribution of the pMLC data is a right-skewed scenario.

[0105] It is worth noting that the specific implementation of the error correction decoding device 10 in the embodiment of the present invention is basically the same as the specific implementation of the above-mentioned error correction decoding method, and will not be repeated here.

[0106] In some embodiments of the present invention, Fig.10 As shown, an embodiment of the present invention further provides an electronic device 700, including: a memory 720, a processor 710, and a computer program stored in the memory 720 and executable on the processor 710. When the processor 710 executes the computer program, the error correction decoding method in the above embodiment is implemented, for example, the above described Figure 2 Steps S100 to S600 of the method, Figure 3 Steps S410 to S430 of the method, Figure 4 Steps S510 to S520 of the method, Figure 5 Steps S610 to S620 of the method, Figure 6 Steps S630 to S640 of the method, Figure 7 In the method step S710 and Figure 8 Method step S310 in .

[0107] In some embodiments of the present invention, an embodiment of the present invention further provides a computer-readable storage medium, which stores computer-executable instructions. The computer-executable instructions are executed by a processor or a controller, for example, by a processor in the above-mentioned device embodiment, so that the above-mentioned processor can execute the error correction decoding method in the above-mentioned embodiment, for example, execute the above-mentioned Figure 2 Steps S100 to S600 of the method, Figure 3 Steps S410 to S430 of the method, Figure 4 Steps S510 to S520 of the method, Figure 5Steps S610 to S620 of the method, Figure 6 Steps S630 to S640 of the method, Figure 7 In step S710 of the method and Figure 8 Method step S310 in .

[0108] It will be appreciated by those skilled in the art that all or some of the steps and systems in the methods disclosed above may be implemented as software, firmware, hardware, and appropriate combinations thereof. Some or all physical components may be implemented as software executed by a processor, such as a central processing unit, a digital signal processor, or a microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or non-transitory medium) and a communication medium (or transient medium). As known to those skilled in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disk (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and can be accessed by a computer. Furthermore, it is well known to those skilled in the art that communication media typically embodies computer readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

[0109] The above is a specific description of the preferred implementation of the present invention, but the present invention is not limited to the above-mentioned implementation mode. Technical personnel familiar with the field can also make various equivalent deformations or substitutions without violating the spirit of the present invention. These equivalent deformations or substitutions are all included in the scope defined by the claims of the present invention.

Claims

1. An error correction decoding method, characterized in that: include: Acquire pseudo multi-level cell pMLC data, wherein the pMLC data includes target valid bit data, first valid bit data and second valid bit data; Reading the target valid bit data from the pMLC data; Decoding the target valid bit data based on a preset error correction engine; In case of decoding failure, the first valid bit data and the second valid bit data are read; and the target valid bit data, the first valid bit data and the second valid bit data are combined and coded to obtain threshold distribution level information; Based on the error correction engine, an offset scenario of the threshold voltage distribution of the pMLC data is identified and processed according to the threshold distribution level information; When it is identified that the offset scenario of the threshold voltage distribution of the pMLC data is a right-skewed scenario, bit flipping processing is performed on the data in the target level storage unit corresponding to the target valid bit data; Wherein, in the case of decoding failure, the first valid bit data and the second valid bit data are read; and the target valid bit data, the first valid bit data and the second valid bit data are combined and coded to obtain threshold distribution level information, including: In the case where the error correction engine fails to decode the target valid bit data, reading the first valid bit data and the second valid bit data from the pMLC data based on a preset read threshold voltage; Combining and encoding the target valid bit data, the first valid bit data and the second valid bit data in bitwise order to obtain a storage unit value; determining the threshold distribution level information according to the storage unit value; When the target valid bit data is the least significant bit data, performing bit flipping processing on the data in the target level storage unit corresponding to the target valid bit data includes: Determine a first right-biased direction level storage unit and a second right-biased direction level storage unit according to the least significant bit data, wherein the target level storage unit includes the first right-biased direction level storage unit and the second right-biased direction level storage unit; Bit flipping is performed on the data in the first right-biased pointing level storage unit and the second right-biased pointing level storage unit.

2. The error correction decoding method according to claim 1, characterized in that: The identifying and processing the offset scenario of the threshold voltage distribution of the pMLC data based on the error correction engine according to the threshold distribution level information includes: determining a first target threshold voltage and a second target threshold voltage from the threshold distribution level information; An identification process is performed on the number of storage cells of the first target threshold voltage and the number of storage cells of the second target threshold voltage to determine an offset scenario of the threshold voltage distribution of the pMLC data.

3. The error correction decoding method according to claim 1, characterized in that: When the target valid bit data is the most significant bit data, performing bit flipping processing on the data in the target level storage unit corresponding to the target valid bit data includes: Determine a third right-biased pointing level storage unit and a fourth right-biased pointing level storage unit according to the most significant bit data, wherein the target level storage unit includes the third right-biased pointing level storage unit and the fourth right-biased pointing level storage unit; The data in the third right-biased pointing level storage unit and the fourth right-biased pointing level storage unit are subjected to bit flipping processing.

4. The error correction decoding method according to claim 1, characterized in that: In the case where it is identified that the offset scenario of the threshold voltage distribution of the pMLC data is a right-skewed scenario, after bit flipping the data in the target level storage unit corresponding to the target valid bit data, the method further includes: The data in the target level storage unit after bit flipping is decoded based on the error correction engine.

5. The error correction decoding method according to claim 1, characterized in that: The decoding process of the target valid bit data based on the preset error correction engine includes: The target valid bit data is subjected to LDPC or BCH decoding processing based on the error correction engine.

6. An error correction decoding device, characterized in that: include: A first processing unit, configured to obtain pseudo multi-level cell pMLC data, wherein the pMLC data includes target valid bit data, first valid bit data, and second valid bit data; A second processing unit, configured to read the target valid bit data from the pMLC data; A third processing unit, configured to perform decoding processing on the target valid bit data based on a preset error correction engine; a fourth processing unit, configured to read the first valid bit data and the second valid bit data in case of a decoding failure; and perform combined encoding processing on the target valid bit data, the first valid bit data and the second valid bit data to obtain threshold distribution level information; A fifth processing unit, configured to identify and process an offset scenario of a threshold voltage distribution of the pMLC data based on the threshold distribution level information by the error correction engine; a sixth processing unit, configured to perform bit flipping processing on data in a target level storage unit corresponding to the target valid bit data when it is identified that the offset scenario of the threshold voltage distribution of the pMLC data is a right-skewed scenario; Wherein, in the case of decoding failure, the first valid bit data and the second valid bit data are read; and the target valid bit data, the first valid bit data and the second valid bit data are combined and coded to obtain threshold distribution level information, including: In the case where the error correction engine fails to decode the target valid bit data, reading the first valid bit data and the second valid bit data from the pMLC data based on a preset read threshold voltage; Combining and encoding the target valid bit data, the first valid bit data and the second valid bit data in bitwise order to obtain a storage unit value; determining the threshold distribution level information according to the storage unit value; When the target valid bit data is the least significant bit data, performing bit flipping processing on the data in the target level storage unit corresponding to the target valid bit data includes: Determine a first right-biased direction level storage unit and a second right-biased direction level storage unit according to the least significant bit data, wherein the target level storage unit includes the first right-biased direction level storage unit and the second right-biased direction level storage unit; Bit flipping is performed on the data in the first right-biased pointing level storage unit and the second right-biased pointing level storage unit.

7. An electronic device, characterized in that: include: A memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the error correction decoding method according to any one of claims 1 to 5 when executing the computer program.

8. A computer-readable storage medium storing computer-executable instructions, characterized in that: When the computer executable instructions are executed by the control processor, the error correction decoding method according to any one of claims 1 to 5 is implemented.

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