A reliable data transmission method based on SPI interface

Abstract

The present invention discloses a reliable data transmission method based on an SPI interface, belonging to the field of data communication technology. The method comprises: the SPI interface comprises a master end and a slave end, the slave end being provided with a slave transmission queue, and when there is slave data to be sent to the master end, the slave end writes the slave data into the slave transmission queue; the method further comprises: the master end periodically sending master data to the slave end in accordance with a transmission data frame format; the slave end providing data feedback to the master end for each master data sent by the master end, and determining whether valid data is fed back to the master end by combining the master data sent by the master end and whether there is slave data in the slave transmission queue; wherein the slave end provides data feedback to the master end in accordance with a received data frame format. The present invention can improve the reliability of master-slave data transmission of the SPI interface.

Description

Technical Field

[0001] The present invention relates to the technical field of data communication, and in particular to a reliable data transmission method based on an SPI interface. Background Art

[0002] The Serial Peripheral Interface (SPI) is a high-speed, full-duplex, synchronous communication bus used for serial communication between an MCU and various peripheral devices. The SPI interface operates in master-slave mode, using a standard four-wire connection between the master and slave terminals.

[0003] In related technologies, the master initiates data transmission and reception, and only receives data from a slave after it has sent data to the master. If the slave has no data to send to the master, the master cannot determine whether the data is valid when it receives it, resulting in unreliable data transmission. Summary of the Invention

[0004] The present invention provides a reliable data transmission method based on the SPI interface, which can solve the problem of unreliable data transmission in related technologies. The technical solution is as follows:

[0005] In one aspect, a reliable data transmission method based on an SPI interface is provided. The SPI interface includes a master end and a slave end. The slave end is provided with a slave transmission queue. When there is slave data to be sent to the master end, the slave end writes the slave data into the slave transmission queue. The method further includes:

[0006] The master end periodically sends master control data to the slave end in accordance with the data frame format;

[0007] The slave end provides data feedback to the master end for each master data sent by the master end, and determines whether valid data is fed back to the master end by combining the master data sent by the master end and whether there is slave data in the slave sending queue; wherein, the slave end feeds back data to the master end in accordance with the received data frame format.

[0008] On the other hand, a reliable data transmission device based on an SPI interface is provided, wherein the SPI interface includes a master end and a slave end, wherein the slave end is provided with a slave transmission queue, and when there is slave data to be sent to the master end, the slave end writes the slave data into the slave transmission queue; the device includes:

[0009] The first processing unit located at the master end is used for the master end to periodically send master control data to the slave end in accordance with the data transmission frame format;

[0010] The second processing unit located at the slave end is used for the slave end to provide data feedback to the master end for each master data sent by the master end, and to determine whether valid data is fed back to the master end by combining the master data sent by the master end and whether the slave data exists in the slave sending queue; wherein the slave end feeds back data to the master end in accordance with the received data frame format.

[0011] On the other hand, a computer device is provided, comprising a memory and a processor, wherein the memory is used to store a computer program, and the processor is used to execute the computer program stored in the memory to implement the steps of the above-mentioned reliable data transmission method based on the SPI interface.

[0012] On the other hand, a computer-readable storage medium is provided, wherein a computer program is stored in the storage medium. When the computer program is executed by a processor, the steps of the above-mentioned reliable data transmission method based on the SPI interface are implemented.

[0013] On the other hand, a computer program product is provided, comprising a computer program, wherein when the computer program is executed by a processor, the steps of the above-mentioned reliable data transmission method based on the SPI interface are implemented.

[0014] The technical solution provided by the present invention can at least bring the following beneficial effects:

[0015] Regardless of whether the master has valid data to send, it will periodically send master data to the slave, and the data is sent in accordance with the data frame format, ensuring that the slave can send and receive data immediately. The data frame format enables the slave to confirm whether the master has sent valid data. In addition, the slave is provided with a slave sending queue. As long as the slave has slave data that needs to be sent to the master, the slave data will first be written into the slave sending queue. When the master sends master data to the slave in the next cycle, it will determine whether to feed back valid data to the master based on whether there is slave data in the master data and the slave sending queue. It can be seen that this solution, by designing the data frame format for sending data and the data frame format for receiving data, enables the slave to determine whether the master data is valid and whether to feed back data, and the master can also determine whether there is valid data in the feedback data, thereby ensuring the reliability of data transmission. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0017] Figure 1 This is a flow chart of a reliable data transmission method based on an SPI interface provided by one embodiment of the present invention;

[0018] Figure 2 This is a schematic diagram of a master-slave connection in an SPI interface provided by one embodiment of the present invention;

[0019] Figure 3 1 is a schematic diagram comparing the sending data frame format and the receiving data frame format provided by one embodiment of the present invention;

[0020] Figure 4 This is a hardware architecture diagram of a computer device provided by one embodiment of the present invention. DETAILED DESCRIPTION

[0021] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0022] Please refer to Figure 1 An embodiment of the present invention provides a reliable data transmission method based on an SPI interface. The SPI interface includes a master end and a slave end. The slave end is provided with a slave transmission queue. When the slave end has slave data to be sent to the master end, the slave data is written into the slave transmission queue. The method further includes:

[0023] Step 100: The master terminal periodically sends master control data to the slave terminal in accordance with the data frame format;

[0024] In step 102, the slave end provides data feedback to the master end for each master data sent by the master end, and determines whether valid data is fed back to the master end by combining the master data sent by the master end and whether there is slave data in the slave sending queue; wherein, the slave end provides data feedback to the master end in accordance with the received data frame format.

[0025] In an embodiment of the present invention, the master terminal periodically sends master control data to the slave terminal regardless of whether it has valid data to send, and the data is sent in accordance with the data transmission frame format, ensuring that the slave terminal can send and receive data immediately. The data transmission frame format enables the slave terminal to confirm whether the master terminal has sent valid data. In addition, the slave terminal is provided with a slave transmission queue. As long as the slave terminal has slave control data that needs to be sent to the master terminal, the slave control data is first written into the slave transmission queue. When the master terminal sends master control data to the slave terminal in the next cycle, it determines whether to feed back valid data to the master terminal based on whether there is slave control data in the master control data and the slave transmission queue. It can be seen that this solution, by designing the data transmission frame format and the data reception frame format, enables the slave terminal to determine whether the master control data is valid and whether to feed back data, and the master terminal can also determine whether there is valid data in the feedback data, thereby ensuring the reliability of data transmission.

[0026] Please refer to Figure 2 The master end of the SPI interface is located in the processor system, and the slave end is located in the external device. The processor system and the external device are connected through the SPI interface. The master end and the slave end are connected by 4 standard lines, namely mosi, miso, clk and gate lines. The master end performs periodic queries according to the period T. Assuming that the period T is n nanoseconds, n is a positive integer, a data query is performed every n nanoseconds. Each time a query is made, the master data is sent to the slave end. If valid data is received, it is used for data processing in the processor system. In addition to the slave send queue, the slave end can also include a slave receive queue. Every time the master data sent by the master end is received, if the master data is valid, the master data is written to the slave receive queue. If there is slave data sent to the master end, the slave data is written to the slave send queue. The master data in the slave receive queue can be used for data processing in the external device.

[0027] In order to improve data transmission reliability, the embodiment of the present invention designs a sending data frame format and a receiving data frame format, which are described below.

[0028] Because data transmission and reception on a standard SPI interface are synchronized under clock control, the master can grasp both transmitted and received data information from the first clock, while the slave can only grasp X bits of information after receiving X bits of data. Based on this X bits of information, the slave can then determine whether to send data and what data to send. Based on this, in an embodiment of the present invention, and pursuant to the aforementioned characteristics of the SPI interface, the transmit data frame format and the receive data frame format are asymmetric; the data frame length required by the receive data frame format is shorter than the data frame length required by the transmit data frame format by a set number of bits. This set number of bits is left blank starting from the start bit of the receive data frame format, allowing the slave to utilize this blanked-out set number of bits to perform information discrimination and data processing on the master data.

[0029] For example, the first X bits in the receive data frame format are undefined bits, and X bits are the sum of the length of the command bit and the padding bit. The X bits left blank in the receive data frame format are used to perform information identification and data processing on the transmitted master data. Where X is a positive integer. Taking the command bit occupying 2 bits and the padding bit occupying 2 bits as an example, then X bits are 4 bits. For the master, the receive data frame is 4 bits shorter than the transmit data frame. The first two blank bits of the receive data frame are used by the slave to identify the information bits, and the remaining two blank bits are used for the clock cycle for the slave to perform the identification and processing. This ensures that the slave has effective time and space for command reception and processing at the protocol level. With the support of the slave receive queue and the slave transmit queue, the slave can not only actively send master data to the master, but also respond to the master's commands in real time.

[0030] Please refer to Figure 3 , is a schematic diagram comparing the sending data frame format and the receiving data frame format. The sending data frame format includes at least the following data frames starting from the start bit: a command bit, a padding bit, and a sending data bit; the number of bits occupied by the command bit and the padding bit is the set number of bits; Figure 3 In the example, the setting bit number is 4 bits, and the command bit and padding bit occupy 2 bits respectively.

[0031] The received data frame format includes at least the following data frames in sequence after leaving the set number of bits from the start bit: a received identification bit and a received data bit.

[0032] Among them, the command bit in the sending data frame format is used to indicate whether the master control data sent this time is valid and whether the feedback data from the slave control end is received this time; the fill bit is used to provide the parsing waiting time for the slave control end; the sending data bit is used to fill the master control data to be sent; the receiving identification bit is used to indicate whether the feedback data this time is valid data; the receiving data bit is used to fill the slave control data required for feedback.

[0033] Then, the master end periodically sends the master control data to the slave end according to the data frame format, which may specifically include:

[0034] The master end periodically queries the SPI interface to determine the content of each data frame in the master data sent to the slave end this time;

[0035] When it is determined that data needs to be sent to the slave end but not received, the command bit in the master data sent to the slave end is used to indicate that only sending and not receiving is required and the sent data is valid, and the data to be sent is filled into the send data bit;

[0036] When it is determined that data does not need to be sent to the slave end but needs to be received, the command bit in the master data sent to the slave end this time is used to indicate that only data is received and sending data is invalid;

[0037] When it is determined that data needs to be sent to the slave end and data needs to be received, the command bit in the master data sent to the slave end is used to indicate that both sending and receiving are performed simultaneously and that the sent data is valid, and the data to be sent is filled into the send data bit;

[0038] Accordingly, the determining whether valid data is fed back to the master end by combining the master data sent by the master end and whether slave data exists in the slave sending queue may specifically include:

[0039] When the slave receives the command bit in the master data sent by the master, which indicates that only sending and not receiving is allowed, and the sent data is valid, the slave parses the data from the send data bit of the master data, and the receive flag in the feedback data indicates that the data fed back this time is invalid data.

[0040] When the slave end receives the master data sent by the master end and the command bit is used to indicate that only reception is required and the data to be sent is invalid, it determines whether there is slave data in the slave send queue. If so, it takes the slave data from the slave send queue and fills it into the receive data bit of the feedback data, and the receive flag bit in the feedback data is used to indicate that the data fed back this time is valid data; if not, the receive flag bit in the feedback data is used to indicate that the data fed back this time is invalid data;

[0041] When the slave end receives the command bit in the master control data sent by the master control end, which is used to indicate simultaneous transmission and reception and the transmitted data is valid, the slave end parses the data from the transmitted data bit in the master control data and determines whether there is slave control data in the slave control transmit queue. If so, the slave control data is taken out from the slave control transmit queue and filled into the received data bit of the feedback data, and the received identification bit in the feedback data is used to indicate that the data fed back this time is valid data; if not, the received identification bit in the feedback data is used to indicate that the data fed back this time is invalid data.

[0042] Furthermore, in addition to the above-mentioned data frame, in one embodiment of the present invention, the data frame format for transmission may further include: a master address bit and a master check bit. In one implementation, the master address bit may be located between the padding bit and the transmission data bit, and the master check bit may be located after the transmission data bit.

[0043] The master address bit indicates the destination address of the master data. When the SPI interface has multiple slaves, the master address bit is written to the target slave address. When multiple slaves receive master data from the master, they use the master address bit in the data to determine whether it is intended for them. The master check bit is used by the slaves to verify the master data.

[0044] Similarly, in addition to the above data frame, in one embodiment of the present invention, the receiving data frame format may further include: a slave address bit and a slave check bit. In one implementation, the slave address bit may be located before the receiving identifier, and the slave check bit may be located after the receiving data bit.

[0045] The slave address bit indicates the destination address of the feedback data. If the SPI interface has multiple masters, the target master's address is written into the slave address bit. When multiple masters receive feedback data from a slave, they use the slave address bit in the feedback data to determine whether it is intended for them. The slave check bit is used by the master to verify the feedback data.

[0046] In the embodiment of the present invention, since 8 bits constitute a byte, in order to facilitate data processing, the total length of the master control data and the feedback data may be an integer multiple of 8.

[0047] In one embodiment, in the data frame format, the command bit occupies 2 bits of the data frame length, the padding bit occupies 2 bits of the data frame length, the master address bit occupies 3 bits of the data frame length, the transmitted data bit occupies M bits, where M is a positive integer, and the master check bit can be 8kbits, where k is a positive integer.

[0048] Correspondingly, in the receive data frame format, after leaving 4 bits from the start bit, the slave address bit occupies 3 bits of the data frame length, the receive identification bit occupies 1 bit of the data frame length, the receive data bit occupies M bits, where M is a positive integer, and the slave check bit can be 8kbits, where k is a positive integer.

[0049] In order to make the total length of the master control data and feedback data an integer multiple of 8, the sending data frame format may also include an undefined bit, which is used to supplement the data length and occupies 1 bit of the data frame length; the receiving data frame format may also include an undefined bit, and the undefined bit in the receiving data frame format is used to leave the start bit empty for a set number of bits, that is, the undefined bit occupies 4 bits of the data frame length.

[0050] Taking the bit occupied by each bit in the above embodiment as an example, the setting of the command bit in the data transmission frame format is described.

[0051] When the command bit is 01, it is used to indicate that only sending is not allowed and the sent data is valid;

[0052] When the command bit is 10, it is used to indicate that only receiving and sending data is invalid;

[0053] When the command bit is 11, it is used to indicate simultaneous transmission and reception and the transmitted data is valid;

[0054] When the command bit is 00, it means that the field is not defined and the sent data is invalid.

[0055] As can be seen, regardless of whether the master has data to send or receive, it will periodically query the SPI interface to determine whether it has data to send or receive. Regardless of whether there is a need, it will send master data to the slave. When there is no data to send or receive, the command bit can be set to 00 to send master data.

[0056] It should be noted that, no matter whether there is data to be sent or not, the total length of the master data sent by the master end to the slave end is L.

[0057] Taking the occupied bits in the above embodiment as an example, the setting of the receiving identification bit in the received data frame format is described.

[0058] When the receive flag is 1, it indicates that the feedback data is valid.

[0059] When the receive flag is 0, it indicates that the feedback data is invalid.

[0060] As can be seen, as long as the slave has slave data to send to the master, it will write the slave data into the slave send queue. When receiving master data from the master, if the command bit of the master data indicates that feedback data can be received, the slave data in the slave send queue is filled into the feedback data as valid data, and the reception flag is indicated as valid data. Otherwise, the slave data in the slave send queue is not filled into the feedback data. In this way, the slave can provide data feedback according to the actual situation, ensuring the effectiveness of data transmission between the master and the slave.

[0061] It should be noted that, no matter whether the feedback data is filled with valid data to be sent, the total length of the data fed back from the control end to the master end is L.

[0062] In one embodiment of the present invention, to ensure timely processing of data after transmission and to avoid confusion, a slave receiving queue is further provided on the slave end. After parsing the data from the transmit data bit of the master data sent from the master end, the process may further include writing the parsed data into the slave receiving queue. Thus, when data exists in the slave receiving queue, the data can be processed sequentially according to the order in which the data was placed in the slave receiving queue.

[0063] In one embodiment of the present invention, in order to avoid queue data overflow, the length of the slave control sending queue and the length of the slave control receiving queue are both N, and N satisfies the following relationship:

[0064]

[0065] Among them, L is the total length of the master data and feedback data, T is the period of the master end querying the SPI interface, and S is the sending rate of the master end.

[0066] In the embodiment of the present invention, the delay time of the periodic query n nanoseconds can be set to a time granularity according to the real-time requirement, so as to ensure the real-time performance of sending and receiving data from the control end.

[0067] An embodiment of the present invention provides a reliable data transmission device based on an SPI interface, wherein the SPI interface includes a master end and a slave end, wherein the slave end is provided with a slave transmission queue. When there is slave data to be transmitted to the master end, the slave end writes the slave data into the slave transmission queue. The device includes:

[0068] The first processing unit located at the master end is used for the master end to periodically send master control data to the slave end in accordance with the data transmission frame format;

[0069] The second processing unit located at the slave end is used for the slave end to provide data feedback to the master end for each master data sent by the master end, and to determine whether valid data is fed back to the master end by combining the master data sent by the master end and whether the slave data exists in the slave sending queue; wherein the slave end feeds back data to the master end in accordance with the received data frame format.

[0070] In one embodiment of the present invention, the sending data frame format and the receiving data frame format are asymmetric;

[0071] The data frame length required by the received data frame format is shorter by a set number of bits than the data frame length required by the sent data frame format. The set number of bits is left empty starting from the start bit of the received data frame format, and is used by the control end to realize information discrimination and data processing of the master control data by utilizing the left empty set number of bits.

[0072] In one embodiment of the present invention, the data transmission frame format includes at least the following data frames in sequence starting from the start bit: a command bit, a padding bit, and a transmission data bit; the number of bits occupied by the command bit and the padding bit is the set number of bits;

[0073] The received data frame format includes at least the following data frames in sequence after the set number of bits is left out from the start bit: a received identification bit and a received data bit;

[0074] When the master control end periodically sends the master control data to the slave control end according to the data frame format, the method specifically includes:

[0075] The master end periodically queries the SPI interface to determine the content of each data frame in the master data sent to the slave end this time;

[0076] When it is determined that data needs to be sent to the slave end but not received, the command bit in the master data sent to the slave end is used to indicate that only sending and not receiving is required and the sent data is valid, and the data to be sent is filled into the send data bit;

[0077] When it is determined that data does not need to be sent to the slave end but needs to be received, the command bit in the master data sent to the slave end this time is used to indicate that only data is received and sending data is invalid;

[0078] When it is determined that data needs to be sent to the slave end and data needs to be received, the command bit in the master data sent to the slave end is used to indicate that both sending and receiving are performed simultaneously and that the sent data is valid, and the data to be sent is filled into the send data bit;

[0079] The determining whether valid data is fed back to the master end by combining the master data sent by the master end and whether slave data exists in the slave sending queue specifically includes:

[0080] When the slave receives the command bit in the master data sent by the master, which indicates that only sending and not receiving is allowed, and the sent data is valid, the slave parses the data from the send data bit of the master data, and the receive flag in the feedback data indicates that the data fed back this time is invalid data.

[0081] When the slave end receives the master data sent by the master end and the command bit is used to indicate that only reception is required and the data to be sent is invalid, it determines whether there is slave data in the slave send queue. If so, it takes the slave data from the slave send queue and fills it into the receive data bit of the feedback data, and the receive flag bit in the feedback data is used to indicate that the data fed back this time is valid data; if not, the receive flag bit in the feedback data is used to indicate that the data fed back this time is invalid data;

[0082] When the slave end receives the command bit in the master control data sent by the master control end, which is used to indicate simultaneous transmission and reception and the transmitted data is valid, the slave end parses the data from the transmitted data bit in the master control data and determines whether there is slave control data in the slave control transmit queue. If so, the slave control data is taken out from the slave control transmit queue and filled into the received data bit of the feedback data, and the received identification bit in the feedback data is used to indicate that the data fed back this time is valid data; if not, the received identification bit in the feedback data is used to indicate that the data fed back this time is invalid data.

[0083] In one embodiment of the present invention, a slave receiving queue is further provided at the slave end, and the second processing unit at the slave end is further configured to parse data from the data bits in the slave master data and write the parsed data into the slave receiving queue.

[0084] In one embodiment of the present invention, the lengths of the slave control sending queue and the slave control receiving queue are both N, and N satisfies the following relationship:

[0085]

[0086] Among them, L is the total length of the master data and feedback data, T is the cycle of the master end querying the SPI interface, and S is the communication rate between the master end and the slave end.

[0087] In one embodiment of the present invention, the total length of the main control data and the feedback data is an integer multiple of 8.

[0088] It should be noted that the SPI interface-based reliability data transmission device provided in the above embodiment is only illustrated by the division of the above functional modules. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above. In addition, the SPI interface-based reliability data transmission device provided in the above embodiment and the SPI interface-based reliability data transmission method embodiment are based on the same concept. The specific implementation process is detailed in the method embodiment and will not be repeated here.

[0089] The embodiment of the present application also provides a computer device, please refer to Figure 4The computer device includes a processor and a memory, wherein the memory stores at least one instruction, at least one program, code set or instruction set, and the at least one instruction, at least one program, code set or instruction set is loaded and executed by the processor to implement the reliable data transmission method based on the SPI interface provided by the above-mentioned method embodiments.

[0090] An embodiment of the present application also provides a computer-readable storage medium, on which is stored at least one instruction, at least one program, code set, or instruction set. The at least one instruction, at least one program, code set, or instruction set is loaded and executed by a processor to implement the reliable data transmission method based on the SPI interface provided by the above-mentioned method embodiments.

[0091] An embodiment of the present application also provides a computer program product, which includes a computer program. A processor of a computer device reads the computer program from a computer-readable storage medium, and the processor executes the computer program, so that the computer device executes the reliable data transmission method based on the SPI interface described in any of the above embodiments.

[0092] For the convenience of description, the above systems or devices are described as being divided into various modules or units according to their functions. Of course, when implementing the present application, the functions of each unit can be implemented in the same or multiple software and / or hardware.

[0093] Through the description of the above embodiments, it can be seen that those skilled in the art can clearly understand that the present application can be implemented by means of software plus a necessary general hardware platform. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a software product, which can be stored in a storage medium such as ROM / RAM, a magnetic disk, an optical disk, etc., and includes a number of instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in various embodiments of the present application or certain parts of the embodiments.

[0094] Finally, it should be noted that, in this document, relational terms such as first, second, third, and fourth are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus comprising the element.

[0095] The above is only a preferred embodiment of the present application. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present application. These improvements and modifications should also be regarded as the scope of protection of the present application.

Claims

1. A reliable data transmission method based on SPI interface, characterized in that: The SPI interface includes a master end and a slave end, wherein the slave end is provided with a slave transmission queue, and when there is slave data to be sent to the master end, the slave end writes the slave data into the slave transmission queue; the method further includes: The master end periodically sends master control data to the slave end in accordance with the data frame format; The slave end feeds back data to the master end for each master data sent by the master end, and determines whether valid data is fed back to the master end by combining the master data sent by the master end and whether slave data exists in the slave sending queue; wherein the slave end feeds back data to the master end in accordance with the received data frame format; The sending data frame format and the receiving data frame format are asymmetric; the data frame length required by the receiving data frame format is shorter by a set number of bits than the data frame length required by the sending data frame format, and the set number of bits is left vacant starting from the start bit of the receiving data frame format, and is used by the control end to implement information discrimination and data processing of the master control data by using the vacant set number of bits; The transmission data frame format includes at least the following data frames in sequence starting from the start bit: a command bit, a padding bit and a transmission data bit; the command bit and the padding bit occupy a total of the set number of bits; The received data frame format includes at least the following data frames in sequence after the set number of bits is left out from the start bit: a received identification bit and a received data bit; The master end periodically sends master control data to the slave end according to the data frame format, including: the master end periodically queries the SPI interface to determine the content of each data frame in the master control data sent to the slave end this time; wherein, When it is determined that data needs to be sent to the slave end but not received, the command bit in the master data sent to the slave end is used to indicate that only sending and not receiving is required and the sent data is valid, and the data to be sent is filled into the send data bit; When it is determined that data does not need to be sent to the slave end but needs to be received, the command bit in the master data sent to the slave end this time is used to indicate that only data is received and sending data is invalid; When it is determined that data needs to be sent to the slave end and data needs to be received, the command bit in the master data sent to the slave end is used to indicate that both sending and receiving are performed simultaneously and that the sent data is valid, and the data to be sent is filled into the send data bit; The determining whether valid data is fed back to the master end by combining the master data sent by the master end and whether slave data exists in the slave sending queue includes: When the slave receives the command bit in the master data sent by the master, which indicates that only sending and not receiving is allowed, and the sent data is valid, the slave parses the data from the send data bit of the master data, and the receive flag in the feedback data indicates that the data fed back this time is invalid data. When the slave end receives the master data sent by the master end and the command bit is used to indicate that only reception is required and the data to be sent is invalid, it determines whether there is slave data in the slave send queue. If so, it takes the slave data from the slave send queue and fills it into the receive data bit of the feedback data, and the receive flag bit in the feedback data is used to indicate that the data fed back this time is valid data; if not, the receive flag bit in the feedback data is used to indicate that the data fed back this time is invalid data; When the slave end receives the command bit in the master control data sent by the master control end, which is used to indicate simultaneous transmission and reception and the transmitted data is valid, the slave end parses the data from the transmitted data bit in the master control data and determines whether there is slave control data in the slave control transmit queue. If so, the slave control data is taken out from the slave control transmit queue and filled into the received data bit of the feedback data, and the received identification bit in the feedback data is used to indicate that the data fed back this time is valid data; if not, the received identification bit in the feedback data is used to indicate that the data fed back this time is invalid data.

2. The method according to claim 1, characterized in that A slave receiving queue is also provided at the slave end. After parsing data from the data bits in the master data, the method further includes: writing the parsed data into the slave receiving queue.

3. The method according to claim 2, characterized in that The lengths of the slave control sending queue and the slave control receiving queue are both N, and N satisfies the following relationship: Among them, L is the total length of the master data and feedback data, T is the cycle of the master end querying the SPI interface, and S is the communication rate between the master end and the slave end.

4. The method according to claim 3, characterized in that The total length of the master control data and feedback data is an integer multiple of 8.

5. A reliable data transmission device based on SPI interface, characterized in that: The SPI interface includes a master end and a slave end, wherein the slave end is provided with a slave transmission queue. When there is slave data to be sent to the master end, the slave end writes the slave data into the slave transmission queue. The device includes: The first processing unit located at the master end is used for the master end to periodically send master control data to the slave end in accordance with the data transmission frame format; a second processing unit located at the slave end, configured to provide data feedback from the slave end to the master end for each master data sent by the master end, and to determine whether valid data is fed back to the master end by combining the master data sent by the master end and whether slave data exists in the slave transmission queue; wherein the slave end feeds data back to the master end in accordance with a received data frame format; The sending data frame format and the receiving data frame format are asymmetric; the data frame length required by the receiving data frame format is shorter by a set number of bits than the data frame length required by the sending data frame format, and the set number of bits is left vacant starting from the start bit of the receiving data frame format, and is used by the control end to implement information discrimination and data processing of the master control data by using the vacant set number of bits; The transmission data frame format includes at least the following data frames in sequence starting from the start bit: a command bit, a padding bit and a transmission data bit; the command bit and the padding bit occupy a total of the set number of bits; The received data frame format includes at least the following data frames in sequence after the set number of bits is left out from the start bit: a received identification bit and a received data bit; The master end periodically sends master control data to the slave end according to the data frame format, including: the master end periodically queries the SPI interface to determine the content of each data frame in the master control data sent to the slave end this time; wherein, When it is determined that data needs to be sent to the slave end but not received, the command bit in the master data sent to the slave end is used to indicate that only sending and not receiving is required and the sent data is valid, and the data to be sent is filled into the send data bit; When it is determined that data does not need to be sent to the slave end but needs to be received, the command bit in the master data sent to the slave end this time is used to indicate that only data is received and sending data is invalid; When it is determined that data needs to be sent to the slave end and data needs to be received, the command bit in the master data sent to the slave end is used to indicate that both sending and receiving are performed simultaneously and that the sent data is valid, and the data to be sent is filled into the send data bit; The determining whether valid data is fed back to the master end by combining the master data sent by the master end and whether slave data exists in the slave sending queue includes: When the slave receives the command bit in the master data sent by the master, which indicates that only sending and not receiving is allowed, and the sent data is valid, the slave parses the data from the send data bit of the master data, and the receive flag in the feedback data indicates that the data fed back this time is invalid data. When the slave end receives the master data sent by the master end and the command bit is used to indicate that only reception is required and the data to be sent is invalid, it determines whether there is slave data in the slave send queue. If so, it takes the slave data from the slave send queue and fills it into the receive data bit of the feedback data, and the receive flag bit in the feedback data is used to indicate that the data fed back this time is valid data; if not, the receive flag bit in the feedback data is used to indicate that the data fed back this time is invalid data; When the slave end receives the command bit in the master control data sent by the master control end, which is used to indicate simultaneous transmission and reception and the transmitted data is valid, the slave end parses the data from the transmitted data bit in the master control data and determines whether there is slave control data in the slave control transmit queue. If so, the slave control data is taken out from the slave control transmit queue and filled into the received data bit of the feedback data, and the received identification bit in the feedback data is used to indicate that the data fed back this time is valid data; if not, the received identification bit in the feedback data is used to indicate that the data fed back this time is invalid data.

6. A computer device, characterized in that: The computer device includes a memory and a processor, the memory is used to store a computer program, and the processor is used to execute the computer program stored in the memory to implement the steps of any one of the methods described in claims 1-4.

7. A computer-readable storage medium, characterized in that The storage medium stores a computer program, which, when executed by a processor, implements the steps of the method according to any one of claims 1 to 4.

8. A computer program product, characterized in that The method comprises a computer program, which implements the steps of the method according to any one of claims 1 to 4 when the computer program is executed by a processor.

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