Data access method and storage subsystem implementing said method

Abstract

The invention discloses a data access method and a storage subsystem for implementing the method. The storage subsystem comprises two storage virtualization controllers (SVC1 and SVC2), a backplane, a physical storage device (PSD) and a clock generation circuit. Wherein the clock generating circuit is installed on the backboard and provides an exclusive clock signal to the physical storage device (PSD). The physical storage device (PSD) has a single port, the channel of which is split into two halves and each coupled to two storage virtualization controllers (SVC1, SVC2). Therefore, the invention does not need to assist the single-port physical storage device (PSD) to be connected to the two storage virtualization controllers (SVC) through any redundant intermediate component, and has the advantages of simple circuit and low cost; and the physical storage device (PSD) is not influenced by the failure of the intermediate component, so that the redundant architecture of the storage subsystem is enhanced.

Description

Technical Field

[0001] The present invention relates to a data access method and a storage subsystem implementing the method, and in particular to a data access method for helping a single-port physical storage device (PSD) communicate with multiple controllers and a storage subsystem implementing the method. Background Art

[0002] See also Figure 1A , which is a block diagram of a conventional storage system architecture 1A (hereinafter referred to as "storage system architecture 1A"). The storage system architecture 1A is composed of a host 15 and a redundant array of independent disks subsystem (RAID subsystem) 3A (also referred to as "RAID subsystem" 3A), wherein the RAID subsystem 3A includes a controller pair composed of two controllers 100, 200, and a plurality of solid state disk (SSD) units 301a, 301b.

[0003] In order to increase the reliability of the data storage system, it is often seen that a redundant architecture is used to configure two controllers (e.g., the first controller 100 and the second controller 200) into a controller pair (also called a "redundant pair"), so that when one controller (e.g., the first controller 100) fails or cannot operate, the other controller (e.g., the second controller 200) can take over the work of the failed controller (e.g., take over the data storage device originally managed by the failed controller), so that the host can continue to perform data access work on all data storage devices without interruption. Furthermore, more and more data storage systems now use solid state drives (SSDs) as their data storage devices. SSDs may provide a single port or dual ports for connecting to the controller. However, SSDs with dual ports are not only few in number but also much more expensive. Therefore, in actual applications, the industry currently uses single-port SSDs as the majority. It can be seen that, if both system reliability and cost-effectiveness are to be taken into account, configuring two controllers in the data storage system and using a single-port solid state disk (SSD) as its data storage device is a common combination.

[0004] by Figure 1AFor example, since the first solid state drive (SSD) unit 301a and the second solid state drive (SSD) unit 301b in the RAID subsystem 3A include the first solid state drive (SSD) 12 and the second solid state drive (SSD) 22, both of which are configured with only a single port, the two solid state drive (SSD) units 301a, 301b each need a multiplexer 16, 26, a solid state drive (SSD) controller 14, 24, and a clock multiplexer 18, 28 to help the solid state drives (SSD) 12, 22 connect to the two controllers 100, 200 respectively, and to help the solid state drive (SSD) units 301a, 301b switch and process data and signals from the controllers (SVC) 100, 200. The first SSD controller 14 and the second SSD controller 24 are used to receive control signals from a primary controller (e.g., the first controller 100 or the second controller 200) to control the multiplexers 16, 26 and the clock multiplexers 18, 28 to use the data and signals of the primary controller, and also to notify the primary controller about the connection and operation status of the SSD 12, 22; the first multiplexer 1 16 and the second multiplexer 2 26 are used to receive control signals from the SSD controllers 14, 24 to conduct the data and signals on the designated paths; and the first clock multiplexer 1 18 and the second clock multiplexer 2 28 are used to control the data and signals of the primary controller. 2) 28 is used to receive control signals from the solid state drive (SSD) controller 14, 24 and adopt the clock signal provided by the primary controller; more specifically, the clock signal of the primary controller is provided by its device-side input / output controller, for example, the first device-side input / output controller 1007 of the first controller 100 or the second device-side input / output controller 2007 of the second controller 200.

[0005] For example, assume that the primary controller is the first controller 100 and the secondary controller is the second controller 200. At the system initialization, the primary controller (the first controller 100) detects notification signals from the first solid state drive (SSD) controller 14 in the first solid state drive (SSD) unit 301a and the second solid state drive (SSD) controller 24 in the second solid state drive (SSD) unit 301b to notify the primary controller (the first controller 100) that the first solid state drive (SSD) 12 and the second solid state drive (SSD) 22 are connected. Next, the main controller (first controller 100) sends a signal to notify the first solid state drive (SSD) controller 14 and the second solid state drive (SSD) controller 24, and controls the first multiplexer (multiplexer 1) 16 and the second multiplexer (multiplexer 2) 26 through the first solid state drive (SSD) controller 14 and the second solid state drive (SSD) controller 24 respectively, so as to conduct the paths between the main controller (first controller 100) and the first solid state drive (SSD) 12, and the main controller (first controller 100) and the second solid state drive (SSD) 22. At the same time, the main controller (first controller 100) sends a signal to notify the first solid state drive (SSD) controller 14 and the second solid state drive (SSD) controller 24, and controls the first clock multiplexer (clock multiplexer 1) 18 and the second clock multiplexer (clock multiplexer 2) 28 through the first solid state drive (SSD) controller 14 and the second solid state drive (SSD) controller 24 respectively to receive a clock signal provided by the main controller (specifically, the first device-side input / output controller 1007 of the first controller 100), so that the first solid state drive (SSD) 12 and the second solid state drive (SSD) 22 can operate according to the aforementioned clock signal.

[0006] From the above, it can be known that when the first controller 100 as the main controller fails and cannot operate normally, and the second controller 200 as the backup has not completed the takeover operation, the first solid state drive (SSD) 12 and the second solid state drive (SSD) 22 will inevitably have no clock signal from the controller 100, 200 to follow, so that the solid state drive (SSD) 12, 22 needs to suspend the original operation process, thereby generating access latency and affecting system performance. This is the first problem faced by the existing storage system architecture 1A.

[0007] See also Figure 1B, which is a block diagram of another existing storage system architecture 1B (hereinafter referred to as "storage system architecture 1B"). The storage system architecture 1B is composed of a host 15 and an independent redundant disk array subsystem (RAID subsystem) 3B (also referred to as "RAID subsystem" 3B). Among them, the RAID subsystem 3B is composed of a redundant controller pair, a plurality of solid state drive (SSD) units 301, and a plurality of distributors 113, 115, 117, 213, 215, 217. The redundant controller pair includes a first controller 100 and a second controller 200; the plurality of solid state drive (SSD) units 301 include a first solid state drive (SSD) unit 301a, a second solid state drive (SSD) unit 301b, a third solid state drive (SSD) unit 301c, a fourth solid state drive (SSD) unit 301d, a fifth solid state drive (SSD) unit 301e, a sixth solid state drive (SSD) unit 301f, a seventh solid state drive (SSD) unit 301g, an eighth solid state drive (SSD) unit 301h, a ninth solid state drive (SSD) unit 301i, a tenth solid state drive (SSD) unit 301j, an eleventh solid state drive (SSD) unit 301k, and a tenth The second solid state drive (SSD) unit 301l, the thirteenth solid state drive (SSD) unit 301m, the fourteenth solid state drive (SSD) unit 301n, the fifteenth solid state drive (SSD) unit 301o, the sixteenth solid state drive (SSD) unit 301p, the seventeenth solid state drive (SSD) unit 301q, the eighteenth solid state drive (SSD) unit 301r, the nineteenth solid state drive (SSD) unit 301s, the twentieth solid state drive (SSD) unit 301t, the twenty-first solid state drive (SSD) unit 301u, the twenty-second solid state drive (SSD) unit 301v, the twenty-third solid state drive (SSD) unit 301w, and the twenty-fourth solid state drive (SSD) unit 301x. Figure 1B RAID subsystem 3B in Figure 1A The RAID subsystem 3A in the figure is similar to the RAID subsystem 3A in the figure. The difference between the two is that the RAID subsystem 3B includes more solid state disk (SSD) units 301 and adds six distributors 113, 115, 117, 213, 215, 217.

[0008] exist Figure 1BIn the architecture of the RAID subsystem 3B, since the two controllers 100, 200 need to connect more solid state disk (SSD) units 301 and provide clock signals to the multiple solid state disk (SSD) units 301, it is necessary to use distributors 113, 115, 117, 213, 215, 217 to assist in routing multiple clock signal lines to each solid state disk (SSD) unit 301. Figure 1B For example, the first device-side input / output controller 1007 of the first controller 100 routes three clock signal lines to the three associated distributors 113, 115, 117), and then the three associated distributors 113, 115, 117 each route eight clock signal lines to the corresponding solid state drive (SSD) unit 301, so that there are a total of 24 clock signal lines, which can cover Figure 1B More specifically, the distributor 113 routes eight clock signal lines (clock signal line #1 to clock signal line #8) to the first solid state drive (SSD) unit 301a to the eighth solid state drive (SSD) unit 301h; the distributor 115 routes eight clock signal lines (clock signal line #9 to clock signal line #16) to the ninth solid state drive (SSD) unit 301i to the sixteenth solid state drive (SSD) unit 301p; and the distributor 117 routes eight clock signal lines (clock signal line #17 to clock signal line #24) to the seventeenth solid state drive (SSD) unit 301q to the twenty-fourth solid state drive (SSD) unit 301x.

[0009] Similarly, in order to provide clock signals to all SSD units 301a-301x, the second device-side input / output controller 2007 of the second controller 200 routes three clock signal lines to the three associated distributors 213, 215, 217, and then the three associated distributors 213, 215, 217 each route eight clock signal lines to the corresponding SSD unit 301, so that there are a total of 24 clock signal lines, which can cover Figure 1B All solid state drive (SSD) units 301a-301x in.

[0010] From the above, we can see that Figure 1BIn the architecture of the existing RAID subsystem 3B, since the redundant controller pair needs to be connected to more solid-state drive (SSD) units 301 with the help of distributors 113, 115, 117, 213, 215, 217, and the distributors 113, 115, 117, 213, 215, 217 do not have a redundant backup design, when any distributor 113, 115, 117, 213, 215, 217 fails to operate normally, the multiple solid-state drive (SSD) units 301 that rely on the failed distributor to provide clock signals will not be able to receive signals from the controllers 100, 200, thus causing the multiple solid-state drive (SSD) units 301 to fail to operate normally, thereby reducing the performance of the system. For example, if the distributor 113 fails to operate normally due to a fault, the first solid state drive (SSD) unit 301a to the eighth solid state drive (SSD) unit 301h connected to the distributor 113 will fail and fail to operate normally, thereby causing the performance of the entire storage system architecture 1B to be low. It can be seen that this existing storage system architecture 1B may cause a loophole in the design of the redundant controller pair due to the fault of the distributor, which is the second problem faced by the existing storage system architecture 1B.

[0011] In addition, in order to realize the clock signal provided by the controller 1007, 2007 from the device end of the controller 100, 200 to multiple solid state disk (SSD) units 301, it is necessary to use an expensive precision distributor that can provide signals synchronously to achieve the routing of multiple clock signal lines to different solid state disk (SSD) units 301, which virtually increases the overall manufacturing cost. This is the third problem currently faced by the existing storage system architecture 1B. Furthermore, the distributor itself requires a certain space to be configured, so the routing between the distributor and the solid state disk (SSD) unit 301 must be designed and planned according to the routing rules under the crowded space occupied by the distributor to avoid signal attenuation and signal interference (for example, electromagnetic interference (EMI)). Therefore, under the factors that the distributor occupies space and is relatively expensive, the cost of the system and the difficulty of implementation are increased. This is the fourth problem currently faced by the existing storage system architecture 1B.

[0012] In summary, how to provide a data access method with low cost, high reliability and high performance to assist the communication between a single-port storage device and two controllers is an urgent problem to be solved in the storage industry. Summary of the invention

[0013] The purpose of the present invention is to disclose a data access method, which is applied to a RAID subsystem, wherein the RAID subsystem includes a first storage virtualization controller, a second storage virtualization controller, a first switch, a second switch, a first physical storage device, a backplane, and a first clock generating circuit, wherein the method includes: installing the first clock generating circuit on the backplane to provide a first dedicated clock signal for the first physical storage device; coupling the first half of a single port of the first physical storage device to the first storage virtualization controller through the first switch; coupling the second half of the single port of the first physical storage device to the second storage virtualization controller through the second switch; setting The first storage virtualization controller is set as the user end of the first physical storage device; the first physical storage device receives at least one first input / output request from the first storage virtualization controller, and processes the at least one first input / output request according to the first dedicated clock signal provided by the first clock generation circuit; the second storage virtualization controller is set as the user end of the first physical storage device; and through the second half of the single port, the first physical storage device receives at least one second input / output request from the second storage virtualization controller, and processes the at least one second input / output request according to the first dedicated clock signal provided by the first clock generation circuit.

[0014] According to another embodiment of the present invention, the step of setting the first storage virtualization controller as the user end of the first physical storage device also includes: the first storage virtualization controller activates at least one first channel coupled to the first physical storage device, the at least one first channel corresponding to the channel of the first half of the single port of the first physical storage device; the first storage virtualization controller sends a first reset signal to the first physical storage device, requesting the first physical storage device to set the first storage virtualization controller as its user end; the first storage virtualization controller confirms the at least one first channel; the first storage virtualization controller sorts the at least one first channel; and the first storage virtualization controller activates the at least one first channel.

[0015] According to another embodiment of the present invention, the step of setting the first storage virtualization controller as the user end of the first physical storage device also includes: the first storage virtualization controller and the second storage virtualization controller are connected to each other through a redundant controller communication link to confirm that the first storage virtualization controller is the main controller of the first physical storage device.

[0016] According to another embodiment of the present invention, the redundant controller communication link is selected from one of the following communication link combinations, including: Peripheral Component Interconnect Express (PCI Express, PCI-E), Ethernet (ethernet), remote direct memory access (RDMA), Fiber Channel-Arbitrated Loop (FC-AL), parallel small computer system interface (parallel SCSI) operating in target mode, and serial advanced technology attachment (SATA) operating in target mode.

[0017] According to another embodiment of the present invention, the step of setting the second storage virtualization controller as the user end of the first physical storage device also includes: the second storage virtualization controller activates at least one second channel coupled to the first physical storage device, the at least one second channel corresponding to the channel of the second half of the single port of the first physical storage device; the second storage virtualization controller sends a first reset signal to the first physical storage device, requesting the first physical storage device to set the second storage virtualization controller as its user end; the second storage virtualization controller confirms the at least one second channel; the second storage virtualization controller sorts the at least one second channel; and the second storage virtualization controller activates the at least one second channel.

[0018] According to another embodiment of the present invention, the first clock generation circuit provides the first dedicated clock signal to the first physical storage device in a one-to-one manner.

[0019] According to another embodiment of the present invention, the first storage virtualization controller and the second storage virtualization controller do not need additional circuit components to assist in directing their own clock signals to the first physical storage device.

[0020] According to another embodiment of the present invention, the second storage virtualization controller learns through a monitoring mechanism that the first storage virtualization controller does not operate normally.

[0021] According to another embodiment of the present invention, the monitoring mechanism is that the first storage virtualization controller sends a confirmation signal to the second storage virtualization controller every first time interval.

[0022] According to another embodiment of the present invention, the monitoring mechanism is that the second storage virtualization controller sends an inquiry signal to the first storage virtualization controller every second time interval and waits for a response signal from the first storage virtualization controller.

[0023] According to another embodiment of the present invention, the first clock generating circuit is a component directly mounted on the backplane.

[0024] According to another embodiment of the present invention, the first clock generating circuit is connected to a first socket on the backplane.

[0025] According to another embodiment of the present invention, the first clock generating circuit is connected to the first socket on the backplane via a first interposer.

[0026] According to another embodiment of the present invention, the first storage virtualization controller, the second storage virtualization controller, the first switch, and the second switch are separate and independent circuit systems.

[0027] According to another embodiment of the present invention, the first switch and the second switch are integrated into the first storage virtualization controller and the second storage virtualization controller respectively.

[0028] According to another embodiment of the present invention, the first switch and the second switch are integrated into a single switch, and the first storage virtualization controller and the second storage virtualization controller are respectively coupled to the first physical storage device through the single switch.

[0029] According to another embodiment of the present invention, during the process of switching the use end of the first physical storage device from the first storage virtualization controller to the second storage virtualization controller, the first physical storage device continues to execute the at least one first input / output request (I / O request) from the first storage virtualization controller according to the first dedicated clock signal provided by the first clock generating circuit.

[0030] According to another embodiment of the present invention, during the process of switching the user end of the first physical storage device from the first storage virtualization controller to the second storage virtualization controller, the first physical storage device suspends the execution of the at least one first input / output request (I / O request) from the first storage virtualization controller.

[0031] According to another embodiment of the present invention, the RAID subsystem further includes a second physical storage device and a second clock generating circuit, wherein the method further includes: installing the second clock generating circuit on the backplane to provide a second dedicated clock signal for the second physical storage device; coupling the first half of the single port of the second physical storage device to the second storage virtualization controller through the second switch; coupling the second half of the single port of the second physical storage device to the first storage virtualization controller through the first switch; setting the second storage virtualization controller as the user end of the second physical storage device; receiving at least one second input / output request from the second storage virtualization controller through the first half of the single port, and processing the at least one second input / output request according to the second dedicated clock signal provided by the second clock generating circuit; the first storage virtualization controller sending a setting signal to the second switch, resetting the user end of the second physical storage device to the first storage virtualization controller through the second switch; and processing at least one first input / output request from the first storage virtualization controller according to the second dedicated clock signal provided by the second clock generating circuit through the second half channel.

[0032] According to another embodiment of the present invention, the second clock generating circuit provides the second dedicated clock signal to the second physical storage device in a one-to-one manner.

[0033] Another object of the present invention is to disclose a RAID subsystem, which is coupled to a host and is used to receive and process at least one access request from the host. The RAID subsystem includes: a first storage virtualization controller including a first switch; a second storage virtualization controller including a second switch and communicating information with the first storage virtualization controller through a redundant controller communication link; a first physical storage device including a single port, and the channel of the single port is divided into a first half and a second half, wherein the channel of the first half is coupled to the first switch of the first storage virtualization controller, and the channel of the second half is coupled to the second switch of the second storage virtualization controller; and a first clock generating circuit coupled to the first physical storage device to provide a first dedicated clock signal to the first physical storage device; wherein the first storage virtualization controller and the second storage virtualization controller communicate via a redundant controller. The redundant controller communication connection confirms that the first storage virtualization controller is the user end of the first physical storage device, the first storage virtualization controller sets itself as the user end of the first physical storage device, and sends at least one first input / output request to the first physical storage device through the first switch, and the first physical storage device processes the at least one first input / output request according to the first dedicated clock signal provided by the first clock generating circuit; and wherein, when the user end of the first physical storage device is changed to the second storage virtualization controller, the second storage virtualization controller sets itself as the user end of the first physical storage device, and sends at least one second input / output request to the first physical storage device through the second switch, and the first physical storage device processes the at least one second input / output request according to the first dedicated clock signal provided by the first clock generating circuit.

[0034] According to another embodiment of the present invention, the first storage virtualization controller also includes: a first central processing circuit, which is used to process the at least one access request from the host; and a first device-side input / output device connection controller, which is used to receive information and instructions from the first central processing circuit and is coupled to the first physical storage device through the first switch to serve as an interface and buffer between the first physical storage device and the first central processing circuit.

[0035] According to another embodiment of the present invention, the first switch is integrated into the first device-side input / output device link controller.

[0036] According to another embodiment of the present invention, the first switch and the first device-side I / O device connection controller are integrated into the first central processing circuit.

[0037] According to another embodiment of the present invention, the second storage virtualization controller also includes: a second central processing circuit, which is used to process the at least one access request from the host; and a second device-side input / output device connection controller, which is used to receive information and instructions from the second central processing circuit and couple to the first physical storage device through the second switch to serve as an interface and buffer between the first physical storage device and the second central processing circuit.

[0038] According to another embodiment of the present invention, the second switch is integrated into the second device-side input / output device link controller.

[0039] According to another embodiment of the present invention, the second switch and the second device-side I / O device connection controller are integrated into the second central processing circuit.

[0040] According to another embodiment of the present invention, the redundant controller communication link is selected from one of the following communication link combinations, including: Peripheral Component Interconnect Express (PCI Express, PCI-E), Ethernet (ethernet), remote direct memory access (RDMA), Fiber Channel-Arbitrated Loop (FC-AL), parallel small computer system interface (parallel SCSI) operating in target mode, and serial advanced technology attachment (SATA) operating in target mode.

[0041] According to another embodiment of the present invention, the first clock generation circuit provides the first dedicated clock signal to the first physical storage device in a one-to-one manner.

[0042] According to another embodiment of the present invention, the first storage virtualization controller and the second storage virtualization controller do not need additional circuit components to assist in directing their own clock signals to the first physical storage device.

[0043] According to another embodiment of the present invention, the first storage virtualization controller, the second storage virtualization controller, the first switch, and the second switch are separate and independent circuit systems.

[0044] According to another embodiment of the present invention, the first switch and the second switch are integrated into the first storage virtualization controller and the second storage virtualization controller respectively.

[0045] According to another embodiment of the present invention, the first switch and the second switch are integrated into a single switch, and the first storage virtualization controller and the second storage virtualization controller are respectively coupled to the first physical storage device through the single switch.

[0046] According to another embodiment of the present invention, a backplane is further included, and the first clock generating circuit is a component directly mounted on the backplane and coupled to the first physical storage device through the backplane.

[0047] According to another embodiment of the present invention, a backplane is further included, and the first clock generating circuit is accommodated in a first socket on the backplane and coupled to the first physical storage device through the backplane.

[0048] According to another embodiment of the present invention, the first clock generating circuit is connected to the first socket on the backplane via a first interposer.

[0049] According to another embodiment of the present invention, a first interposer is also included, on which the first clock generating circuit and a slot are provided, wherein the slot is used to accommodate the first physical storage device and assist the first physical storage device to be coupled to the first storage virtualization controller and the second storage virtualization controller.

[0050] According to another embodiment of the present invention, during the process of switching the use end of the first physical storage device from the first storage virtualization controller to the second storage virtualization controller, the first physical storage device continues to execute the at least one first input / output request from the first storage virtualization controller based on the first dedicated clock signal provided by the first clock generating circuit.

[0051] According to another embodiment of the present invention, during the process of switching the user end of the first physical storage device from the first storage virtualization controller to the second storage virtualization controller, the physical storage device suspends execution of the at least one first input / output request from the first storage virtualization controller.

[0052] According to another embodiment of the present invention, the first storage virtualization controller sets itself as the user end of the first physical storage device by executing the following steps: activating at least one first channel coupled to the first physical storage device, sending a first reset signal to the first physical storage device to request setting the first storage virtualization controller as its user end, confirming the at least one first channel, sorting the at least one first channel, and activating the at least one first channel, wherein the at least one first channel is a channel corresponding to the first half of the single port of the first physical storage device.

[0053] According to another embodiment of the present invention, the second storage virtualization controller sets itself as the user end of the first physical storage device by executing the following steps: activating at least one second channel coupled to the first physical storage device, sending a second reset signal to the first physical storage device to request setting the second storage virtualization controller as its user end, confirming the at least one second channel, sorting the at least one second channel, and activating the at least one second channel, wherein the at least one second channel is a channel corresponding to the second half of the single port of the first physical storage device. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] Figure 1A It is a block diagram of a conventional storage system architecture 1A.

[0055] Figure 1B It is a block diagram of another conventional storage system architecture 1B.

[0056] Figure 2A and Figure 2B is a block diagram of a second embodiment of a storage system architecture 2D according to the present invention.

[0057] Figure 2C and Figure 2D FIG. 2 is a storage system architecture 2D according to the present invention, illustrating the changes in the setting values ​​of multiple channels in a single port of a physical storage device (PSD) before and after the main controller of the physical storage device (PSD) is switched.

[0058] Figure 3 is a block diagram of a storage system architecture 2F according to the present invention.

[0059] Figure 4is a flow chart of setting a main controller according to an embodiment of the present invention.

[0060] Figure 5 It is a flow chart of setting a user end of a physical storage device (PSD) according to an embodiment of the present invention.

[0061] Figure 6 It is a flow chart of the operation of the physical storage device (PSD) when the main controller is in the normal operation mode according to an embodiment of the present invention.

[0062] Fig. 7A The flowchart of a storage system switching a user of a physical storage device (PSD) to a new primary controller according to an embodiment of the present invention.

[0063] Figure 7B The present invention is another embodiment of a flow chart of a storage system switching a user of a physical storage device (PSD) to a new primary controller.

[0064] The reference numerals are described as follows:

[0065] 1A, 1B: Existing storage system architecture

[0066] 2D, 2E: Storage system architecture

[0067] 4D, 4E: Redundant Array of Independent Disks Subsystem (RAID Subsystem)

[0068] 7: Redundant controller communication link

[0069] 9: Physical Storage Device (PSD)

[0070] 9a: First physical storage device

[0071] 9b: Second physical storage device

[0072] 10: First storage virtualization controller

[0073] 12: The first solid-state drive

[0074] 14: First solid state drive (SSD) controller

[0075] 15: Host

[0076] 16: First multiplexer

[0077] 18: First clock multiplexer

[0078] 20: Second storage virtualization controller

[0079] 22: Second SSD

[0080] 24: Second solid state drive (SSD) controller

[0081] 26: Second multiplexer

[0082] 28: Second clock multiplexer

[0083] 85: Clock generation circuit

[0084] 85a: first clock generating circuit

[0085] 85b: Second clock generating circuit

[0086] 100: First controller

[0087] 101: First host-side input / output device connected to controller

[0088] 103: First central processing circuit

[0089] 105: First Memory

[0090] 107: The first device end input / output device is connected to the controller 109: First switch 113、115、

[0092] 117, 213, : Allocator 215, 217

[0094] 200: Second controller

[0095] 201: Second host input / output device connected to controller

[0096] 203: Second central processing circuit

[0097] 205: Second memory

[0098] 207: The second device end input / output device is connected to the controller

[0099] 209: Second switch

[0100] 301: Solid State Drive (SSD) Unit

[0101] 301a-301x: first solid state drive (SSD) unit to twenty-fourth solid state drive (SSD) unit 401: backplane

[0102] 901: The first half

[0103] 902: The Second Half

[0104] 1007: First device-side input / output controller

[0105] 2007: Second device input / output controller

[0106] 401-417: main controller setting process steps in the storage system architecture 2D and 2E of the present invention 501-515: storage system architecture 2D and 2E of the present invention, with the first storage virtualization controller 10 as the main controller coupled to the physical storage device (PSD) setting process steps 601-605: storage system architecture 2D and 2E of the present invention, with the first storage virtualization controller 10 as the main controller and the main controller in normal operation mode, the operation process steps of the physical storage device (PSD) 7001-7017: storage system architecture 2D and 2E of the present invention, with the first storage virtualization controller 10 as the main controller and the main controller is not in normal operation mode, the operation process steps of the physical storage device (PSD) 7101-7119: storage system architecture 2D and 2E of the present invention, with the first storage virtualization controller 10 as the main controller and the main controller is not in normal operation mode, another operation process step of the physical storage device (PSD) DETAILED DESCRIPTION

[0107] Certain words are used in the specification and subsequent claims to refer to specific components. It should be understood by those with ordinary knowledge in the field that hardware manufacturers may use different terms to refer to the same component. This specification and subsequent claims do not use differences in names as a way to distinguish components, but rather use differences in the functions of components as the criteria for distinction. The term "including" mentioned throughout the specification and subsequent claims is an open-ended term and should be interpreted as "including but not limited to". In addition, the term "coupled" here includes any direct and indirect electrical connection means. Therefore, if the text describes a first device coupled to a second device, it means that the first device can be directly electrically connected to the second device, or indirectly electrically connected to the second device through other devices or connection means.

[0108] See also Figure 2A and Figure 2B, which is a block diagram of two embodiments of the storage system architecture 2D according to the present invention. The storage system architecture 2D is composed of a host 15 and a redundant array of independent disks subsystem (RAID subsystem) 4D (also referred to as "RAID subsystem" 4D). The RAID subsystem 4D includes a storage virtualization controller pair (SVC pair) composed of two storage virtualization controllers (SVC) 10, 20, a plurality of physical storage devices (PSD) 9a, 9b, a backplane 401, a plurality of clock generation circuits 85a, 85b, and a plurality of switches 109, 209. The plurality of clock generation circuits 85a, 85b are installed on the backplane 401 and are respectively connected to the plurality of physical storage devices (PSD) 9a, 9b. The multiple switches 109, 209 include a first switch 1 109 and a second switch 209, and the two storage virtualization controllers (SVC) 10, 20 are respectively coupled to the multiple physical storage devices (PSD) 9a, 9b through their corresponding first switch 1 109 and second switch 2 209. In actual application, the first switch 1 109 and the second switch 2 209 are PCIe switches according to an embodiment of the present invention.

[0109] According to one embodiment of the present invention, the multiple clock generation circuits 85a, 85b are components directly mounted on the backplane 401. According to another embodiment of the present invention, the backplane 401 includes two sockets, and the two sockets are used to accommodate the multiple clock generation circuits 85a, 85b. In this way, the multiple clock generation circuits 85a, 85b can be easily replaced according to needs. According to another embodiment of the present invention, the backplane 401 includes a first socket (socket 1) and a second socket (socket 2), and the first socket (socket 1) and the second socket (socket 2) are respectively used to accommodate a first interposer card (Interposer 1) and a second interposer card (Interposer 2). The multiple clock generation circuits (clock generation circuits) are respectively installed on the first interposer card (Interposer 1) and the second interposer card (Interposer 2).

[0110] One of the switches 85a, 85b is used to provide a dedicated clock signal to the physical storage device (PSD) 9a, 9b coupled to the interposer 1 or interposer 2. The multiple physical storage devices (PSD) 9a, 9b are respectively coupled to the first interposer 1 and the second interposer 2, and are respectively coupled to the first switch 109 and the second switch 209 of the two storage virtualization controllers (SVC) 10, 20 through the first interposer 1 and the second interposer 2. In this way, one or both of the first interposer 1 and the second interposer 2 can be removed as needed to facilitate replacement of the clock generation circuits 85a, 85b on the interposer. According to another embodiment of the present invention, the plurality of clock generation circuits 85a, 85b are respectively mounted on a first interposer card (Interposer 1) and a second interposer card (Interposer 2) in a one-to-one manner. The first interposer card (Interposer 1) and the second interposer card (Interposer 2) each include a slot for receiving one of the corresponding plurality of physical storage devices (PSD) 9a, 9b, and assisting the connected physical storage device (PSD) 9a, 9b to be coupled to two storage virtualization controllers (SVC1 and SVC2) 10, 20. Thus, one or both of the first interposer card (Interposer 1) and the second interposer card (Interposer 2) can be removed as needed, so as to facilitate replacement of the clock generation circuits 85a, 85b on the interposer cards.

[0111] In order to increase the reliability of the data storage system, it is often seen that a redundant architecture is used to configure two storage virtualization controllers (SVCs) (for example, a first storage virtualization controller (SVC 1) 10 and a second storage virtualization controller (SVC 2) 20) into a storage virtualization controller pair (SVC pair). In this way, when one storage virtualization controller (for example, the first storage virtualization controller (SVC 1) 10) fails or cannot operate, the other storage virtualization controller (for example, the second storage virtualization controller (SVC 2) 20) can take over the work that the failed storage virtualization controller is responsible for (for example, taking over the physical storage device (PSD) originally managed by the failed storage virtualization controller), so that the host can continue to perform data access work on all physical storage devices (PSD) 9 continuously and uninterruptedly. Therefore, in the RAID subsystem 4D of the storage system architecture 2D, the first storage virtualization controller (SVC1) 10 and the second storage virtualization controller (SVC2) 20 form a storage virtualization controller pair (SVC pair) for mutual redundancy.

[0112] A redundant controller communicating (RCC) connection 7 is provided between the first storage virtualization controller (SVC 1) 10 and the second storage virtualization controller (SVC 2) 20. The first storage virtualization controller (SVC 1) 10 and the second storage virtualization controller (SVC 2) 20 establish an inter-controller communications channel (ICC) between each other through the redundant controller communication (RCC) connection 7 to transmit information or data to each other. Common implementations of implementing an inter-controller channel (ICC) include using peripheral component interconnect express (PCI Express, PCI-E), Ethernet (Ethernet), remote direct memory access (RDMA), Fiber Channel-Arbitrated Loop (FC-AL), parallel small computer system interface (parallel SCSI) operating in target mode, or serial advanced technology attachment (SATA) operating in target mode and other communication links to achieve implementation, but are not limited to these.

[0113] The first storage virtualization controller (SVC 1) 10 includes a first host-side I / O device interconnect controller 101, a first central processing circuit (CPC1) 103, a first memory (memory 1) 105, a first device-side I / O device interconnect controller 107, and a first switch (switch 1) 109. Figure 2A In the embodiment shown, the first switch (switch 1) 109 is integrated into the first device-side I / O device interconnect controller (device-side I / O device interconnect controller 1) 107; Figure 2B In the illustrated embodiment, the first device-side I / O device interconnect controller 1 107 and the first switch 1 109 are integrated into the first central process circuit 1 (CPC1) 103. In another embodiment of the present invention, the first device-side I / O device interconnect controller 1 107, the first switch 1 109, and the first central process circuit 1 (CPC1) 103 may also be independent components.

[0114] Among them, the first host-side I / O device interconnect controller 1 101 in the first storage virtualization controller (SVC 1) 10 is coupled to the host 15 and the first central processing circuit (CPC 1) 103 respectively, and is used to receive access requests from the host 15 and convert and / or map them to the first central processing circuit (CPC 1) 103.

[0115] The first central processing circuit (CPC 1 ) 103 in the first storage virtualization controller (SVC 1 ) 10 is used to process and / or monitor access requests from the host 15 .

[0116] Among them, the first memory (memory 1) 105 in the first storage virtualization controller (SVC 1) 10 is coupled to the first central processing circuit (CPC 1) 103, which is used as a buffer for buffering data transmitted between the host 15 and multiple physical storage devices (PSD) 9a, 9b through the first central processing circuit (CPC 1) 103.

[0117] Among them, the first device-side I / O device interconnect controller 1 107 in the first storage virtualization controller (SVC 1) 10 receives information and instructions from the first central processing circuit (CPC1) 103, and is coupled to multiple physical storage devices (PSD) 9a, 9b on the device side through the first switch (switch 1) 109, which is used as an interface and buffer between the multiple physical storage devices (PSD) 9a, 9b and the first central processing circuit (CPC1) 103. For example, the first device-side I / O device interconnect controller 1 107 receives control signals, I / O requests and related data from the first central processing circuit (CPC 1) 103, and converts and / or maps the I / O requests and related data from the first central processing circuit (CPC 1) 103 to the plurality of physical storage devices (PSD) 9a, 9b through the medium of the first switch (switch 1) 109. The first device-side I / O device interconnect controller 107 also receives data and signals from the plurality of physical storage devices (PSD) 9a, 9b through the medium of the first switch (switch 1) 109. In addition, the first device-side I / O device interconnect controller 107 also learns the connection and operation status of the plurality of physical storage devices (PSD) 9a, 9b through the first switch (switch 1) 109.

[0118] Similarly, the second storage virtualization controller (SVC 2) 20 includes a second host-side I / O device interconnect controller 201, a second central processing circuit (CPC 2) 203, a second memory 205, a second device-side I / O device interconnect controller 206, and a second storage virtualization controller (SVC 2).

[0119] 207, and a second switch (switch 2) 209. Figure 2A In the embodiment shown, the second switch 209 is integrated into the second device-side I / O device interconnect controller 207; Figure 2B In the embodiment shown, the second device-side I / O device interconnect controller 207 and the second switch 209 are integrated into the second central process circuit 2 (CPC 2) 203. In another embodiment of the present invention, the second device-side I / O device interconnect controller 207, the second switch 209, and the second central process circuit 2 (CPC 2) 203 may also be independent components.

[0120] Among them, the second host-side I / O controller 2 201 in the second storage virtualization controller (SVC 2) 20 is coupled to the host 15 and the second central processing circuit (CPC 2) 203 respectively, and is used to receive access requests from the host 15 and convert and / or map them to the second central processing circuit (CPC 2) 203.

[0121] The second central processing circuit (CPC 2 ) 203 in the second storage virtualization controller (SVC 2 ) 20 is used to process and / or monitor access requests from the host 15 .

[0122] Among them, the second memory (memory 2) 205 in the second storage virtualization controller (SVC 2) 20 is connected to the second central processing circuit (CPC 2) 203, which is used as a buffer to buffer the data transmitted between the host (host) 15 and multiple physical storage devices (PSD) 9a, 9b through the second central processing circuit (CPC 2) 203.

[0123] Among them, the second device-side I / O device interconnect controller 2 207 in the second storage virtualization controller (SVC 2) 20 receives information and instructions from the second central processing circuit (CPC2) 203, and is coupled to multiple physical storage devices (PSD) 9a, 9b on the device side through a second switch (switch 2) 209, which is used as an interface and buffer between the multiple physical storage devices (PSD) 9a, 9b and the second central processing circuit (CPC 2) 203. For example, the second device-side I / O device interconnect controller 207 receives control signals, I / O requests and related data from the second central processing circuit (CPC 2) 203, and converts and / or maps the I / O requests and related data from the second central processing circuit (CPC 2) 203 to the plurality of physical storage devices (PSD) 9a, 9b through the medium of the second switch (switch 2) 209. The second device-side I / O device interconnect controller 207 also receives data and signals from the plurality of physical storage devices (PSD) 9a, 9b through the medium of the second switch (switch 2) 209. In addition, the second device-side I / O device interconnect controller 207 also learns the connection and operation status of the plurality of physical storage devices (PSD) 9a, 9b through the second switch (switch 2) 209.

[0124] Among them, the first clock generation circuit (clock generation circuit 1) 85a is a dedicated clock generation circuit of the first physical storage device (PSD) 9a, which independently provides a first clock signal to the first physical storage device (PSD) 9a, so that the first physical storage device (PSD) 9a can operate normally according to the first clock signal. Similarly, the second clock generation circuit (clock generation circuit 2) 85b is a dedicated clock generation circuit of the second physical storage device (PSD) 9b, which independently provides a second clock signal to the second physical storage device (PSD) 9b, so that the second physical storage device (PSD) 9b can operate normally according to the second clock signal. In other words, the first clock generation circuit (clock generation circuit 1) 85a and the second clock generation circuit (clock generation circuit 2) 85b are independently operated components and are not controlled by the storage virtualization controller 10, 20 or the switch 109, 209. According to an embodiment of the present invention, the first clock generating circuit 85a and the second clock generating circuit 85b can be selected from oscillators, clock generators, or crystal circuits, or any other circuit modules or devices that can achieve the same function in practical applications.

[0125] See also Figure 2AAccording to an embodiment of the present invention, the first switch (switch 1) 109 is integrated into the first device-side I / O device interconnect controller 107, and the second switch (switch 1) 209 is integrated into the second device-side I / O device interconnect controller 1 207. Therefore, the first storage virtualization controller (SVC1) 10 and the second storage virtualization controller (SVC2) 20 are coupled to the first physical storage device (PSD) 9a and the second physical storage device (PSD) 9b of the plurality of physical storage devices (PSD) 9 through the first device-side I / O device interconnect controller 107 (including the first switch (switch 1) 109) and the second device-side I / O device interconnect controller 207 (including the second switch (switch 2) 209), respectively.

[0126] See also Figure 2B According to another embodiment of the present invention, the first switch (switch 1) 109 and the second switch (switch 2) 209 are respectively included in the first storage virtualization controller (SVC 1) 10 and the second storage virtualization controller (SVC 2) 20, and the first switch (switch 1) 109 and the second switch (switch 2) 209 are independent of the first device-side I / O device interconnect controller (device-side I / O device interconnect controller 1) 107 and the second device-side I / O device interconnect controller (device-side I / O device interconnect controller 1) 207.

[0127] According to another embodiment of the present invention, the first switch 1 109 and the second switch 2 209 are independent circuit systems. According to another embodiment of the present invention, the first switch 1 109 and the second switch 2 are further integrated into a single switch. According to one embodiment of the present invention, the positions of the first switch 1 109 and the second switch 2 209 are on the backplane 401. Furthermore, according to one embodiment of the present invention, the first switch 1 109 and the second switch 2 209 are PCIe switches in actual applications. The first storage virtualization controller (SVC 1) 10 and the second storage virtualization controller (SVC 2) 20 need to be coupled to the first physical storage device (PSD) 9a and the second physical storage device (PSD) 9b among multiple physical storage devices (PSD) 9 through the first switch (switch1) 109 and the second switch (switch 2) 209.

[0128] Please also read Figure 2A , Figure 2B and Figure 2C ;in, Figure 2C 1 is a functional block diagram of a storage system architecture 2D according to an embodiment of the present invention, which is used to illustrate how a single-port physical storage device (PSD) 9 is coupled to two storage virtualization controllers (SVC 1, SVC 2) 10, 20 through switches 109, 209. Figure 2C It is depicted with Figure 2A , Figure 2B The same storage system architecture 2D; however, in order to emphasize this coupling method and facilitate understanding, Figure 2COnly one physical storage device (PSD) 9 (for example, the first physical storage device (PSD) 9a) is shown to illustrate the method of coupling the physical storage device (PSD) 9 with two storage virtualization controllers (SVC 1, SVC 2) 10, 20 using a single port. In one embodiment of the present invention, it is assumed that the single port of the physical storage device (PSD) 9 has a plurality of even PCIe lanes, and the plurality of PCIe lanes can be further divided into two halves 901 and 902, each including half the number of lanes. The lanes of the first half 901 are coupled to the first storage virtualization controller (SVC 1) 10 through the first switch (switch 1) 109, and the lanes of the second half 902 are coupled to the second storage virtualization controller (SVC 2) 20 through the second switch (switch 2) 209. That is, the channels (lanes) that can be managed and used by the first storage virtualization controller (SVC 1) 10 and the second storage virtualization controller (SVC 2) 20 respectively correspond to exactly half of the multiple PCIe channels (lanes) of the single port (single port) of the physical storage device (PSD) 9.

[0129] Assume that the system initially uses the first storage virtualization controller (SVC 1) 10 as the primary controller of the physical storage device (PSD) 9 (for example, the first physical storage device (PSD) 9a), and uses the second storage virtualization controller (SVC 2) 20 as the secondary controller of the physical storage device (PSD) 9 (for example, the first physical storage device (PSD) 9a). Based on this assumption, when a single-port physical storage device (PSD) 9 (for example, the first physical storage device (PSD) 9a) is connected to the RAID subsystem 4D, the second storage virtualization controller (SVC 2) will disable the channels newly coupled to it through the second switch (switch 2) 209, and the multiple disabled channels correspond to the second half 902 of the single port of the physical storage device (PSD) 9 (for example, the first physical storage device (PSD) 9a); the first storage virtualization controller (SVC 1) 10 will perform a process to activate its newly coupled channels, and the multiple activated channels correspond to the first half 901 of the single port of the physical storage device (PSD) 9 (for example, the first physical storage device (PSD) 9a). The first storage virtualization controller (SVC 1) 10 will first sort the multiple channels newly coupled to it through the first switch (switch 1) 109, and the multiple channels correspond to the first half 901 of the single port (single port) of the physical storage device (PSD) 9 (for example, the first physical storage device (PSD) 9a). In one embodiment of the present invention, the sorting method is: the first storage virtualization controller (SVC 1) 10 sets the setting value of each channel (lane) in sequence through the first switch (switch 1) 109. According to Figure 2C In the illustrated embodiment, if a single port of a physical storage device (PSD) 9 (e.g., the first physical storage device (PSD) 9a) has four PCIe lanes, the first storage virtualization controller (SVC 1) 10 sets the two lanes connected to the physical storage device (PSD) 9 to lane “0”.

[0130] (lane 0) and channel "1" (lane 1), and the two channels of the first half 901 connected to the first storage virtualization controller (SVC 1) 10 in the single port (single port) of the physical storage device (PSD) 9 (for example: the first physical storage device (PSD) 9a) are correspondingly channel "0" (lane 0) and channel "1" (lane 1). Therefore, the four PCIe channels (lanes) (including the two channels of the first half 901 and the two channels of the second half 902) of the single port (single port) of the physical storage device (PSD) 9 (for example: the first physical storage device (PSD) 9a) are correspondingly channel "0" (lane 0), channel "1" (lane 1), channel "2" (lane 2) and channel "3" (lane 3) in sequence. After such setting, the first storage virtualization controller (SVC 1) 10 activates its own two channels (corresponding to the two channels (lane 0 and lane 1) of the first half 901 of the single port (single port) of the physical storage device (PSD) 9) through the first switch (switch 1) 109, and accesses the data stored in the physical storage device (PSD) 9 (for example: the first physical storage device (PSD) 9a) through its own two channels (corresponding to the two channels (lane 0 and lane 1) of the first half 901).

[0131] See also Figure 2D , is a functional block diagram of a storage system architecture 2D according to an embodiment of the present invention, used to illustrate the change of the channel setting value in the single port of the physical storage device (PSD) 9 when the user end of the physical storage device (PSD) 9 needs to be switched from the first storage virtualization controller (SVC 1) 10 to the second storage virtualization controller (SVC 2) 20. The reason for switching the user end of the physical storage device (PSD) 9 may be: Figure 2CThe first storage virtualization controller (SVC 1) in the storage virtualization controller (SVC 1) fails or fails; or when the first storage virtualization controller (SVC 1) 10 is still operating normally, the ownership of the physical storage device (PSD) 9 is simply transferred to the second storage virtualization controller (SVC 2) 20. When the switching process is performed, the second storage virtualization controller (SVC 2) 20 will take over the work of the first storage virtualization controller (SVC 1) 10, including: replacing the first storage virtualization controller (SVC 1) 10 to become the new primary controller of the physical storage device (PSD) 9 (for example, the first physical storage device (PSD) 9a). At this time, the second storage virtualization controller (SVC 2) 20 sorts its own channels through the second switch (switch 2) 209, and the multiple channels correspond to the multiple PCIe channels (lanes) of the second half 902 of the single port (single port) of the physical storage device (PSD) 9 (for example, the first physical storage device (PSD) 9a). According to an embodiment of the present invention, the second storage virtualization controller (SVC 2) 20 performs sorting through the second switch (switch 2) 209 by starting from the first channel of the plurality of channels (corresponding to the PCIe channels (lanes) in the second half 902 of the single port (single port) of the physical storage device (PSD) 9) and arranging them in sequence; that is, for the plurality of channels (corresponding to the PCIe channels (lanes) in the second half 902 of the single port (single port) connected to the second storage virtualization controller (SVC 2) 20), the setting values ​​of the channels are set in sequence. Figure 2DIn the illustrated embodiment, if the single port of the physical storage device (PSD) 9 (for example, the first physical storage device (PSD) 9a) has four PCIe channels (lanes), the second storage virtualization controller (SVC 2) 20 will set the two channels connected to the physical storage device (PSD) 9 (for example, the first physical storage device (PSD) 9a) as channel "0" (lane 0) and channel "1" (lane 1), so that the two channels of the second half 902 of the single port of the physical storage device (PSD) 9 (for example, the first physical storage device (PSD) 9a) connected to the second storage virtualization controller (SVC2) 20 will correspond to channel "0" (lane 0) and channel "1" (lane 1). Therefore, the four PCIe lanes (including the two lanes of the first half 901 and the two lanes of the second half 902) of the single port of the physical storage device (PSD) 9 (for example, the first physical storage device (PSD) 9a) correspond to lane "3" (lane 3), lane "2" (lane 2), lane "1" (lane 1) and lane "0" (lane 0) in sequence. After such setting, the second storage virtualization controller (SVC 2) 20 uses the two lanes connected to itself (corresponding to the two lanes (lane 0 and lane 1) of the second half 902 of the single port of the physical storage device (PSD) 9) through the second switch (switch 2) 209, and accesses the data stored in the physical storage device (PSD) 9 through its own two lanes (corresponding to the two lanes (lane 0 and lane 1) of the second half 902).

[0132] As for how to determine which of the two storage virtualization controllers (SVC) 10, 20 is the primary controller and which is the secondary controller at the beginning of the system, it will be described below. Figure 4 Detailed description in the description.

[0133] Please also see Figure 2A and Figure 2C. According to one embodiment of the present invention, it is assumed that the first storage virtualization controller (SVC 1) 10 serves as a primary controller, and the second storage virtualization controller (SVC 2) 20 serves as a secondary controller. When the physical storage devices (PSD) 9a, 9b are installed in the RAID subsystem 4A, the first clock generation circuit (clock generation circuit 1) 85a provides a dedicated first clock signal to the first physical storage device (PSD) 9a, and the second clock generation circuit (clock generation circuit 2) 85b provides a dedicated second clock signal to the second physical storage device (PSD) 9b. In this way, the first physical storage device (PSD) 9a and the second physical storage device (PSD) 9b can operate normally according to the aforementioned first clock signal and second clock signal, respectively. In addition, the primary controller (specifically, the first device-side input / output device connection controller 107 of the first storage virtualization controller (SVC 1) 10) knows which physical storage devices (PSD) 9 (i.e., the first physical storage device (PSD) 9a and the second physical storage device (PSD) 9b) are coupled to it through the first switch (switch 1) 109, and then sends a setting signal to the first switch (switch 1) 109, requesting to reset the multiple coupled physical storage devices (PSD) 9a, 9b. Then, the primary controller (i.e., the first storage virtualization controller (SVC 1) 10) confirms, sorts, and activates the lanes of the first half 901 coupled to it in the single port of the multiple coupled physical storage devices (PSD) 9 (e.g., the first physical storage device (PSD) 9a and the second physical storage device (PSD) 9b) through the first switch (switch 1) 109. Figure 2CFor example, assuming that the physical storage device (PSD) 9 (e.g., the first physical storage device (PSD) 9a and the second physical storage device (PSD) 9b) has four PCIe channels (lanes), the primary controller (i.e., the first storage virtualization controller (SVC 1) 10) will sort the PCIe channels (lanes) coupled to itself; that is, the primary controller (i.e., the first storage virtualization controller (SVC 1) 10) sets the channels coupled to itself (corresponding to the two channels of the first half 901) as channel "0" (lane 0) and channel "1" (lane 1), and the four PCIe channels (lanes) of the single port (single port) of the physical storage device (PSD) 9 (e.g., the first physical storage device (PSD) 9a and the second physical storage device (PSD) 9b) (including the two channels of the first half 901 and the two channels of the second half 902) are thus sequentially corresponding to channel "0" (lane 0), channel "1" (lane 1), channel "2" (lane 2) and channel "3". 2) and lane "3" (lane 3). Then, the primary controller (i.e., the first storage virtualization controller (SVC 1) 10) activates its own channels, and the multiple activated channels correspond to the two channels (Lane 0 and Lane 1) of the first half 901. At the same time, the secondary controller (specifically, the second device-side input / output device connection controller 207 of the second storage virtualization controller (SVC 2) 20) confirms and disables the multiple channels coupled to itself through the second switch (switch 2) 209, and the multiple disabled channels correspond to the channels (lanes) of the second half 902 of the single port (single port) of the physical storage device (PSD) 9 (e.g., the first physical storage device (PSD) 9a and the second physical storage device (PSD) 9b). In this way, the main controller (first storage virtualization controller (SVC 1) 10) can access the data of the first physical storage device (PSD) 9a and the second physical storage device (PSD) 9b respectively through the first switch (switch 1) 109 through its own activated channel (the channel (lane) of the first half 901 of the single port (single port) of the first physical storage device (PSD) 9a and the second physical storage device (PSD) 9b).

[0134] Please note that according to the present invention, since the physical storage devices (PSD) 9a, 9b are each equipped with a dedicated and independently operated clock generation circuit 85a, 85b, the physical storage devices (PSD) 9a, 9b do not need to rely on the storage virtualization controller 10, 20 or the switch 109, 209 to provide the clock signal required for operation. Even if the main controller (the first storage virtualization controller (SVC 1) 10) fails and cannot provide services, the physical storage devices (PSD) 9a, 9b can still maintain normal operation based on the dedicated clock generation circuit 85a, 85b, thereby maintaining system performance without causing delays.

[0135] See also Figure 3 , which is a block diagram of a storage system architecture 2E according to an embodiment of the present invention. The storage system architecture 2E is composed of a host 15 and a redundant array of independent disks subsystem (RAID subsystem) 4E (also referred to as "RAID subsystem" 4E). The RAID subsystem 4E includes a storage virtualization controller pair (SVC pair) composed of a first storage virtualization controller (SVC 1) 10 and a second storage virtualization controller (SVC 2) 20, a plurality of physical storage devices (PSD) 9, a plurality of clock generation circuits 85 and a backplane 401. The plurality of clock generation circuits 85 are installed on the backplane 401 and are respectively connected to the plurality of physical storage devices (PSD) 9 in a one-to-one manner.

[0136] According to one embodiment of the present invention, the multiple clock generation circuits 85a, 85b are components directly mounted on the backplane 401. According to another embodiment of the present invention, the backplane 401 further includes multiple sockets, and the multiple sockets provide a one-to-one manner to accommodate the multiple clock generation circuits 85. In this way, the multiple clock generation circuits 85 can be conveniently replaced according to needs. According to another embodiment of the present invention, the backplane 401 includes multiple sockets, and the multiple sockets respectively accommodate multiple interposers in a one-to-one manner. The multiple interposers are respectively installed with one of the multiple clock generation circuits 85, which are used to provide a dedicated clock signal to the physical storage device (PSD) 9 coupled to the interposer. The plurality of physical storage devices (PSD) 9 are respectively coupled to the plurality of interposers, and are respectively coupled to the first storage virtualization controller (SVC 1) 10 and the second storage virtualization controller (SVC 2) 20 through the interposers. In this way, one or more of the plurality of interposers can be removed as needed to facilitate replacement of the clock generation circuit 85 on the interposer. According to another embodiment of the present invention, the plurality of clock generation circuits 85 are respectively mounted on the plurality of interposers in a one-to-one manner. Each of the plurality of interposers includes a slot for accommodating one of the corresponding plurality of physical storage devices (PSD) 9, and assisting the connected physical storage device (PSD) 9 to be coupled to the first storage virtualization controller (SVC 1) 10 and the second storage virtualization controller (SVC 2) 20. In this way, one or more of the plurality of interposers can be removed as needed to facilitate replacement of the clock generation circuit 85 on the interposer.

[0137] The composition and connection of each component in the first storage virtualization controller (SVC 1) 10 and the second storage virtualization controller (SVC 2) 20 have been described above. Figure 2AThe two storage virtualization controllers (SVC) 10, 20 in the storage virtualization controller pair (SVC pair) are respectively coupled to the plurality of physical storage devices (PSD) 9 through the first switch (switch 1) 109 and the second switch (switch 2) 209 connected thereto. In practical applications, the first switch (switch 1) and the second switch (switch 2) can be PCIe switches or other switches that can achieve the same effect. The first switch (switch 1) 109 and the second switch (switch 2) 209 may be independent components respectively included in the first storage virtualization controller (SVC 1) 10 and the second storage virtualization controller (SVC 2) 20, or may be independent components located on the backplane 401; in other embodiments of the present invention, the first switch (switch 1) 109 and the second switch (switch 2) 209 are respectively integrated into the first central processing circuit (central process circuit 1, CPC 1) 103 of the first storage virtualization controller (SVC 1) 10 and the second central processing circuit (central process circuit 2, CPC 2) 203 of the second storage virtualization controller (SVC 2) 20; in other embodiments of the present invention, the first switch (switch 1) 109 and the second switch (switch 2) 209 are respectively integrated into the first device-side I / O device interconnect controller (device-side I / O device interconnect controller) of the first storage virtualization controller (SVC 1) 10. The second storage virtualization controller (SVC 2) 20 includes a second device-side I / O device interconnect controller 1 207 and a second storage virtualization controller (SVC 2) 20 .

[0138] The RAID subsystem 4E includes a first storage virtualization controller (SVC 1) 10 and a second storage virtualization controller (SVC 2) 20, whose architecture and functions are substantially the same as those of the aforementioned Figure 2A , Figure 2B The RAID subsystem 4D includes a first storage virtualization controller (SVC 1) 10 and a second storage virtualization controller (SVC 2) 20. Therefore, the following will not be repeated. Figure 3 Detailed description of the first storage virtualization controller (SVC 1) 10 and the second storage virtualization controller (SVC 2) 20 included in the RAID subsystem 4E.

[0139] According to one embodiment of the present invention, the plurality of physical storage devices (PSD) 9 may be physical storage devices that can permanently store data, such as a hard disk drive (HDD), a solid state drive (SSD), or an optical disc. According to another embodiment of the present invention, the plurality of physical storage devices (PSD) 9 may be volatile memory, such as a random access memory (RAM), a dynamic random access memory (DRAM), or a flash memory, or other physical storage devices that can achieve the same function.

[0140] According to an embodiment of the present invention, it is assumed that the first storage virtualization controller (SVC 1) 10 is the primary controller of all physical storage devices (PSD) 9, and the second storage virtualization controller (SVC 2) 20 is the secondary controller of all physical storage devices (PSD) 9. During operation, the primary controller (the first storage virtualization controller (SVC 1) 10) knows which physical storage devices (PSD) 9 are coupled to it through the first switch (switch 1) 109. When the plurality of physical storage devices (PSD) 9 are installed in the RAID subsystem 4E, each physical storage device (PSD) 9 is coupled to a dedicated clock generation circuit (clock generation circuit) 85 and receives a dedicated clock signal from its dedicated clock generation circuit 85. In this way, each physical storage device (PSD) 9 can operate normally according to its dedicated clock signal. In addition, the secondary controller (specifically, the second device-side input / output device link controller 207 of the second storage virtualization controller (SVC 2) 20) will confirm and disable its own channels coupled to the physical storage device (PSD) 9 through the second switch (switch 2) 209, and the multiple channels correspond to the channels (lanes) of the second half 902 of the single port (single port) of the physical storage device (PSD) 9. The primary controller (specifically, the first device-side input / output device link controller 107 of the first storage virtualization controller (SVC 1) 10) will send a reset signal to the physical storage device (PSD) 9 through the first switch (switch 1) 109, requesting the physical storage device (PSD) 9 to reset the multiple channels of its own single port (single port). Next, the primary controller (i.e., the first storage virtualization controller (SVC 1) 10) activates, confirms, and sorts the channels coupled to the physical storage device (PSD) 9 through the first switch (switch 1) 109, wherein the channels correspond to the channels (lanes) of the first half 901 coupled to the single port of the physical storage device (PSD) 9. For example, please also refer to Figure 2C, assuming that each single port of the physical storage device (PSD) 9 has four PCIe channels (lanes), the main controller (i.e., the first storage virtualization controller (SVC 1) 10) will first activate and sort its own channels, and the two channels (lanes) of the first half 901 of the single port of the physical storage device (PSD) 9 corresponding to the multiple channels are therefore set to channel "0" (lane 0) and channel "1" (lane 1). At this time, the four PCIe channels (lanes) of the single port of the physical storage device (PSD) 9 include the two channels of the first half 901 and the two channels of the second half 902, and thus correspond to channel "0" (lane 0), channel "1" (lane 1), channel "2" (lane 2) and channel "3" (lane 3) in sequence. In this way, the main controller (first storage virtualization controller (SVC 1)) can access the data of multiple physical storage devices (PSD) 9 through the first switch (switch 1) 109 and the lanes of the first half 901 corresponding to the single port of the physical storage device (PSD) 9. It can be seen that in the present invention, half of the lanes of the single port of the physical storage device (PSD) 9 are coupled to the first storage virtualization controller (SVC 1) 10 through the first switch (switch 1) 109, and the other half of the lanes are coupled to the second storage virtualization controller (SVC 2) 20 through the second switch (switch 2) 209. In other words, the channels managed and used by the first storage virtualization controller (SVC 1) 10 and the second storage virtualization controller (SVC 2) 20 respectively correspond to half of the four PCIe lanes of the single port of the physical storage device (PSD) 9.

[0141] Please note that the clock generation circuit 85 disclosed in the present invention is an independently operated circuit component. Therefore, even if the main controller fails to provide services, the physical storage device (PSD) 9 can still receive its dedicated clock signal from the dedicated clock generation circuit 85 to which it is connected. In this way, the physical storage device (PSD) 9 can continue to operate without being affected, thereby maintaining system performance and avoiding operational latency. In this way, the first problem in the prior art that the physical storage device (PSD) 9 needs to suspend the originally executed operation process due to the failure of the main controller and in the transition period before the handover of another controller is completed is solved.

[0142] In addition, since each physical storage device (PSD) 9 in the present invention is directly connected to a dedicated clock generation circuit 85 for directly providing a dedicated clock signal to the corresponding physical storage device (PSD) 9, when the storage system architecture 2E is connected to more physical storage devices (PSD) 9, no additional circuit components (e.g., Figure 1B The distributors 113, 115, 117 in the system assist the storage virtualization controllers (SVC) 10, 20 in routing to guide clock signals to multiple physical storage devices (PSD) 9. In this way, the second problem in the prior art that multiple physical storage devices (PSD) 9 connected thereto cannot operate normally due to distributor failure, thereby causing low system performance is solved.

[0143] Moreover, since the storage system architecture 2E does not require additional circuit components (e.g., distributors 113, 115, 117, 213, 215, 217), the component cost is saved, thereby avoiding the third cost increase problem in the prior art. In addition, since the storage system architecture 2E does not require additional circuit components (e.g., distributors 113, 115, 117, 213, 215, 217), its circuit is relatively simple and avoids the situation of complex routing, thereby solving the fourth complex routing problem in the prior art.

[0144] See also Figure 4, which is a flow chart for setting the primary controller according to an embodiment of the present invention. The following description takes the storage system architecture 2D as an example, but its technical content is also applicable to other storage system architectures 2E in the present invention. According to an embodiment of the present invention, the backplane 401 in the storage system architecture 2D includes a first slot and a second slot, which are used to install the storage virtualization controller (SVC) 10, 20 and assist the storage virtualization controller (SVC) 10, 20 to form an electrical connection with other components connected to the backplane. When establishing the RAID subsystem 4D, 4E, the storage virtualization controller (SVC) 10, 20 will first be inserted into the slot of the backplane, and after all components are in place and connected, the RAID subsystem 4D, 4E will be activated to set the primary controller. At this time, the RAID subsystems 4D and 4E will determine whether any storage virtualization controller (SVC) is installed in the slots (first slot and second slot) on the backplane (step 401). If the result of the determination of step 401 is "no", that is, no storage virtualization controller (SVC) is installed in the slots of the backplane, the RAID subsystems 4D and 4E may continue (or stop) at step 401; if the result of the determination of step 401 is "yes", that is, a storage virtualization controller (SVC) is installed in the slots of the backplane, the process proceeds to step 403 to continue the setting of the primary controller.

[0145] If the judgment result of step 401 is "yes", the RAID subsystems 4D and 4E will further judge whether the two slots (the first slot and the second slot) are both equipped with storage virtualization controllers (SVC) 10, 20 (step 403). If the judgment result of step 403 is "yes", that is, the first slot and the second slot are both equipped with storage virtualization controllers (SVC) 10, 20, then the process continues to step 405 for further judgment to help determine which storage virtualization controller (the first storage virtualization controller (SVC 1) 10 or the second storage virtualization controller (SVC 2) 20) should play the role of the primary controller. On the contrary, if the judgment result of step 403 is "No", which means that only one of the two slots has a storage virtualization controller (SVC) installed, then the process continues to step 413 to determine: which slot has the storage virtualization controller (SVC) installed, and the installed storage virtualization controller (the first storage virtualization controller (SVC1) 10 or the second storage virtualization controller (SVC 2) 20) is the primary controller.

[0146] If the result of step 403 is "yes", the process proceeds to step 405, where the two storage virtualization controllers (SVC) 10, 20 determine whether there are pending items recorded in the flash memory configured by themselves (step 405). If the result of step 405 is "no", that is, there are no pending items recorded in the flash memory configured by the two storage virtualization controllers (SVC) 10, 20, then the RAID subsystems 4D and 4E preset the storage virtualization controller installed in the first slot (i.e., the first storage virtualization controller (SVC 1) 10) as the primary controller, and the storage virtualization controller installed in the second slot (i.e., the second storage virtualization controller (SVC 2) 20) as the secondary controller (step 409). On the contrary, if the determination result of step 405 is “yes”, it means that there are pending items recorded in the flash memory configured by at least one storage virtualization controller (SVC) 10 , 20 , and thus the process proceeds to step 407 for further determination.

[0147] In step 407, it is further determined whether the flash memory configured in the first storage virtualization controller (SVC 1) 10 installed in the first slot has any pending items recorded. If the determination result of step 407 is "yes", the first storage virtualization controller (SVC 1) 10 installed in the first slot is used as the primary controller, and the second storage virtualization controller (SVC 2) 20 installed in the second slot is used as the secondary controller (step 409). If the determination result of step 407 is "no", it means that the flash memory that records the pending items is configured in the second storage virtualization controller (SVC 2) 20, so the second storage virtualization controller (SVC 2) 20 installed in the second slot is used as the primary controller, and the first storage virtualization controller (SVC 1) 10 installed in the first slot is used as the secondary controller (step 411).

[0148] Let's look back at another judgment result of step 403. If the judgment result of step 403 is "No", then go to step 413, and the RAID subsystems 4D and 4E further judge whether the first storage virtualization controller (SVC 1) 10 is installed in the first slot (step 413). If the judgment result of step 413 is "Yes", it means that only the first storage virtualization controller (SVC 1) 10 is installed in the first slot, and the first storage virtualization controller (SVC 1) 10 naturally plays the role of the primary controller (step 415). On the contrary, if the judgment result of step 413 is "No", it means that only the second storage virtualization controller (SVC 2) 20 is installed in the second slot, and no storage virtualization controller (SVC) is installed in the first slot. In this case, the second storage virtualization controller (SVC 2) 20 installed in the second slot is the primary controller (step 417).

[0149] See also Figure 5 , which is a flow chart of setting a user end (also called user) of a physical storage device (PSD) 9 according to an embodiment of the present invention. Figure 2AThe RAID subsystem 4D of the storage system architecture 2D in FIG. 1 is taken as an example, and it is assumed that the first storage virtualization controller (SVC 1) 10 is the primary controller of the first physical storage device (PSD) 9a, and the second storage virtualization controller (SVC 2) 20 is the secondary controller of the first physical storage device (PSD) 9a. Similarly, Figure 5 The illustrated technical content is also applicable to other storage system architectures 2E in the present invention. According to an embodiment of the present invention, in the RAID subsystems 4D and 4E, the first storage virtualization controller (SVC 1) 10 (i.e., the primary controller) detects through the first switch (switch 1) 109 whether a physical storage device (PSD) 9 without a usage end is coupled (step 501).

[0150] If the judgment result of step 501 is "No", that is, the first storage virtualization controller (SVC 1) 10 does not detect a physical storage device (PSD) 9 without a usage end through the first switch (switch 1) 109, then the first storage virtualization controller (SVC 1) 10 in the RAID subsystem 4D will continue to execute the operation of the aforementioned step 501 to ensure that each coupled physical storage device (PSD) 9 is equipped with a usage end (step 501).

[0151] If the result of the determination in step 501 is "yes", that is, there is a physical storage device (PSD) 9 (for example, Figure 2A The first physical storage device (PSD) 9a) is detected, then according to Figure 4From the description, it can be known that the system defaults that the first storage virtualization controller (SVC 1) 10 is the primary controller of the physical storage device (PSD) 9 (for example, the first physical storage device (PSD) 9a). In actual operation, the first storage virtualization controller (SVC 1) 10 and the second storage virtualization controller (SVC 2) 20 will confirm with each other through the redundant controller communication (RCC) link 7 which one is the primary controller of the newly coupled physical storage device (PSD) 9 (for example, the first physical storage device (PSD) 9a)? According to the above assumption, the result of the confirmation is: the first storage virtualization controller (SVC 1) 10 is the primary controller of the newly coupled physical storage device (PSD) 9 (for example, the first physical storage device (PSD) 9a), that is, it is the user end of the newly coupled physical storage device (PSD) 9 (for example, the first physical storage device (PSD) 9a) (step 503). Therefore, the second storage virtualization controller (SVC 2) 20 disables its newly coupled channels through the second switch (switch 2) 209, and the multiple disabled channels correspond to the channels of the second half 902 coupled to itself in the single port (single port) of the physical storage device (PSD) 9 (for example, the first physical storage device (PSD) 9a) (step 505); and the first storage virtualization controller (SVC 1) 10 activates the newly coupled channels through the first switch (switch 1) 109, and the multiple activated channels correspond to the channels of the first half 901 coupled to itself in the single port (single port) of the physical storage device (PSD) 9 (for example, the first physical storage device (PSD) 9a) (step 507). Afterwards, the first storage virtualization controller (SVC 1) 10 sends a reset signal to the newly coupled physical storage device (PSD) 9 (for example, the first physical storage device (PSD) 9a) through the first switch (switch 1) 109 to set itself as the user end of the physical storage device (PSD) 9 (step 509).

[0152] According to an embodiment of the present invention, the method in which the first storage virtualization controller (SVC 1) 10 detects through the first switch (switch 1) 109 in step 501 further includes: the first switch (switch 1) 109 detects whether a physical storage device (PSD) 9 without a use end is connected, and if it is detected that there is, the first storage virtualization controller (SVC 1) 10 (that is, the primary controller) is notified to let the first storage virtualization controller (SVC 1) 10 know that there is a newly coupled physical storage device (PSD) 9 (for example, Figure 2A The presence of a first physical storage device (PSD) 9a).

[0153] Next, when the first storage virtualization controller (SVC 1) 10 successfully sets itself as the user end of the newly coupled physical storage device (PSD) 9 (for example, the first physical storage device (PSD) 9a) through the first switch (switch 1) 109, the first storage virtualization controller (SVC 1) 10 confirms the number and status of the multiple activated channels (corresponding to the channels of the first half 901 of the single port of the physical storage device (PSD) 9) through the first switch (switch 1) 109 (step 511). For example, after the first storage virtualization controller (SVC 1) 10 confirms through the first switch (switch 1) 109, it is found that the multiple activated channels are two usable PCIe lanes corresponding to the physical storage device (PSD) 9. That is, the first storage virtualization controller (SVC 1) 10 learns through the first switch (switch 1) 109 that there is a newly coupled physical storage device (PSD) 9 (for example, the first physical storage device (PSD) 9a), whose single port (singleport) is coupled to the first switch (switch 1) 109 and can use two PCIe channels (lanes) therein.

[0154] After the confirmation work of step 511 is completed, the first storage virtualization controller (SVC 1) 10 will sort the multiple activated channels (corresponding to the channels of the first half 901 of the single port of the physical storage device (PSD) 9) through the first switch (switch 1) 109 (step 513). Figure 2CFor example, the first storage virtualization controller (SVC 1) 10 (primary controller) sets its own multiple activated channels (corresponding to the two channels of the first half 901) as channel "0" (lane 0) and channel "1" (lane 1), and the four PCIe channels (lanes) (including the two channels of the first half 901 and the two channels of the second half 902) of the single port (single port) of the physical storage device (PSD) 9 (for example: the first physical storage device (PSD) 9a) are thus corresponding to channel "0" (lane 0), channel "1" (lane 1), channel "2" (lane 2) and channel "3" (lane 3) in sequence.

[0155] After the sorting work of step 513 is completed, the first storage virtualization controller (SVC 1) 10 can use the multiple activated channels (corresponding to the two channels (i.e., channel “0” (lane 0) and channel “1” (lane 1)) of the first half 901 of the single port of the physical storage device (PSD) 9 through the first switch (switch 1) 109) (step 515). In this way, the process of setting the use end of the physical storage device (PSD) 9 is completed. Afterwards, when the first storage virtualization controller (SVC1) 10 issues a first input / output request to the physical storage device (PSD) 9 (e.g., the first physical storage device (PSD) 9a), the physical storage device (PSD) 9 (e.g., the first physical storage device (PSD) 9a) receives the first input / output request through the channel of the first half 901 of the single port, and processes the first input / output request according to the dedicated clock signal provided by its dedicated clock generation circuit 85 (e.g., the first clock generation circuit 85a).

[0156] According to an embodiment of the present invention, although it is assumed in the above description that Figure 2A , Figure 2B , Figure 2C , Figure 2D ,and Figure 3The primary controller (primary controller) of the physical storage device (PSD) 9 (for example, the first physical storage device (PSD) 9a) is the first storage virtualization controller (SVC 1) 10, and the secondary controller (secondary controller) is the second storage virtualization controller (SVC 2) 20; however, the primary controller (primary controller) and the secondary controller (secondary controller) of the second physical storage device (PSD) 9b do not necessarily need to be consistent with the first physical storage device (PSD) 9a. The second physical storage device (PSD) 9b can also set the second storage virtualization controller (SVC 2) 20 as its primary controller (primary controller) according to needs, and set the first storage virtualization controller (SVC 1) 10 as the secondary controller. Furthermore, the operation of the first storage virtualization controller (SVC 1) 10 and the second storage virtualization controller (SVC 2) 20 for the second physical storage device (PSD) 9b is essentially the same as the aforementioned Figure 5 The operation mode of the two storage virtualization controllers (SVC 1, SVC 2) 10, 20 on the first physical storage device (PSD) 9a is shown in FIG. Therefore, the relevant details are not repeated in the following.

[0157] See also Figure 6 , which is a flowchart of the operation of the physical storage device 9 when the main controller is in the normal operation mode according to an embodiment of the present invention. Figure 2A Take the RAID subsystem 4D of the storage system architecture 2D in FIG. 1 as an example, and assume that the first storage virtualization controller (SVC 1) 10 is the primary controller of the first physical storage device (PSD) 9a, and the second storage virtualization controller (SVC 2) 20 is the secondary controller of the first physical storage device (PSD) 9a. Similarly, Figure 6The illustrated technical content is also applicable to other storage system architectures 2E in the present invention. According to one embodiment of the present invention, a physical storage device (PSD) 9 (for example, a first physical storage device (PSD) 9a) is directly coupled to a dedicated first clock generation circuit (clock generation circuit 1) 85a, and is coupled to a storage virtualization controller pair (SVC pair) of a RAID subsystem 4D through a first switch (switch 1) 109; wherein the storage virtualization controller pair (SVC pair) includes a first storage virtualization controller (SVC 1) 10 (i.e., a primary controller) and a second storage virtualization controller (SVC 2) 20 (i.e., a secondary controller). When the physical storage device (PSD) 9 (e.g., the first physical storage device 9a) is coupled to the RAID subsystem 4D, the dedicated clock generation circuit 85 (e.g., the first clock generation circuit 85a) coupled thereto provides a dedicated clock signal (e.g., the first clock signal) to the physical storage device (PSD) 9 (e.g., the first physical storage device 9a) (step 601). The physical storage device (PSD) 9 (e.g., the first physical storage device 9a) receives the dedicated clock signal (e.g., the first clock signal) (step 603). After receiving one or more input / output requests (I / O request) from the primary controller (i.e., the first storage virtualization controller (SVC 1) 10), the physical storage device (PSD) 9 (e.g., the first physical storage device 9a) processes the one or more input / output requests (I / O request) according to the dedicated clock signal (e.g., the first clock signal) (step 605).

[0158] Please see below Fig. 7A and Figure 7B . Fig. 7A and Figure 7B The flowchart of switching the end of the physical storage device 9 to the new primary controller when data flow switching is required according to different embodiments of the present invention is shown. According to one embodiment of the present invention, the reason for the need to switch the data flow may be that the primary controller is not operating normally; in another embodiment of the present invention, when both controllers are operating normally, the data flow switching may also be required due to the conversion of the end of the physical storage device (PSD) 9. The following takes "the primary controller is not operating normally" as an example to explain Fig. 7A and Figure 7B Flowchart of the process.

[0159] The primary controller and the secondary controller establish a monitoring mechanism through the communication of the redundant controller communication (RCC) link 7, so that the secondary controller can grasp the operation status of the primary controller. According to an embodiment of the present invention, the monitoring mechanism can be: the primary controller sends a confirmation signal to the secondary controller every first time interval ΔT1, so that the secondary controller can know that the primary controller is still operating normally. That is, if the secondary controller does not receive any other confirmation signal from the primary controller after receiving the confirmation signal for more than the first time interval ΔT1, the secondary controller will determine that the primary controller is not operating normally, and thus start to prepare to take over the work that the primary controller is responsible for.

[0160] According to another embodiment of the present invention, the monitoring mechanism may be: the secondary controller sends an inquiry signal to the primary controller every second time interval ΔT2, and waits for a response signal from the primary controller. If the secondary controller receives a response signal from the primary controller, the secondary controller knows that the primary controller is still operating normally. When the system is operating, the secondary controller will continue to repeat the above operations to confirm whether the primary controller is operating normally. On the contrary, if the secondary controller does not receive a response signal from the primary controller, the secondary controller will determine that the primary controller is not operating normally, and thus begin to prepare to take over the work that the primary controller is responsible for.

[0161] Please refer to Fig. 7A The following instructions apply to Figure 2A , Figure 2B , Figure 3In the RAID subsystems 4D and 4E of the storage system architecture 2D and 2E shown, a first storage virtualization controller (SVC 1) 10 is preset as a primary controller of one or more physical storage devices (PSD) 9 (for example, a first physical storage device (PSD) 9a), and a second storage virtualization controller (SVC 2) 20 is a secondary controller of the one or more physical storage devices (PSD) 9 (for example, a first physical storage device (PSD) 9a). According to one embodiment of the present invention, when data flow switching is required (step 7001), for example, when the second storage virtualization controller (SVC 2) 20 determines that the first storage virtualization controller (SVC 1) 10 is not operating normally based on the above-mentioned monitoring mechanism, or when the user end of the physical storage device (PSD) 9 (for example, the first physical storage device (PSD) 9a) needs to be switched to the second storage virtualization controller (SVC 2) 20 while the first storage virtualization controller (SVC 1) 10 is still operating normally, the second storage virtualization controller (SVC2) 20 will set itself as the new primary controller (step 7003). At this time, although the original primary controller (i.e., the first storage virtualization controller (SVC 1) 10) interrupts service during the switching process, since the clock signal of the physical storage device (PSD) 9 (e.g., the first physical storage device (PSD) 9a) is provided by its dedicated clock generation circuit 85 (e.g., the first clock generation circuit 85a), the physical storage device (PSD) 9 can still receive its dedicated clock signal uninterruptedly and process the input / output request (I / O request) accordingly, including continuing to execute the input / output request (I / O request) that it originally received but has not yet completed (step 7005). After taking over the work of the first storage virtualization controller (SVC 1) 10, the second storage virtualization controller (SVC 2) 20 (i.e., the new primary controller) detects the existence of the physical storage device (PSD) 9 (e.g., the first physical storage device (PSD) 9a) through the second switch (switch 2) 209 (step 7007).

[0162] Next, the second storage virtualization controller (SVC 2) 20 (i.e., the new primary controller) activates the coupled channels through the second switch (switch 2) 209, wherein the multiple activated channels correspond to the channels of the second half 902 coupled to the second half 902 in the single port of the physical storage device (PSD) 9 (e.g., the first physical storage device (PSD) 9a)) (step 7009). Afterwards, the second storage virtualization controller (SVC 2) 20 (i.e., the new primary controller) sends a reset signal to the physical storage device (PSD) 9 (e.g., the first physical storage device (PSD) 9a) through the second switch (switch 2) 209 to set the second storage virtualization controller (SVC 2) 20 as its user end (step 7011). When the user end of the physical storage device (PSD) 9 (for example, the first physical storage device (PSD) 9a) is successfully set to the second storage virtualization controller (SVC 2) 20, the second storage virtualization controller (SVC 2) 20 confirms the multiple activated channels (corresponding to the channels of the second half 902 of the single port of the physical storage device (PSD) 9) through the second switch (switch 2) 209 (step 7013).

[0163] Afterwards, the second storage virtualization controller (SVC 2) 20 sorts the multiple activated channels (corresponding to the channels of the second half 902 of the single port of the physical storage device (PSD) 9) through the second switch (switch 2) 209; the sorting method is to arrange them in sequence starting from the first channel in the PCIe lane of the second half 902 of the single port coupled to it. (Step 7015). For example, assume that the single port of the physical storage device (PSD) 9 (for example, the first physical storage device (PSD) 9a) has four PCIe lanes. The second storage virtualization controller (SVC 2) 20, which becomes the new primary controller, sets the setting value of each channel in sequence for the multiple activated channels (corresponding to the second half 902 of the single port connected to itself) through the second switch (switch 2) 209. According to Figure 2DIn the illustrated embodiment, the new primary controller (i.e., the second storage virtualization controller (SVC 2) 20) sequentially sets the setting values ​​of each channel for the plurality of activated channels (corresponding to the channels of the second half 902 of the single port) through the switch (i.e., the second switch (switch 2) 209). In this way, the two channels of the second half 902 in the single port correspond to channel "lane 0" and channel "lane 1", and the four PCIe channels (lanes) in the single port (including the two channels of the first half 901 and the two channels of the second half 902) correspond to channel "lane 3", channel "lane 2", channel "lane 1" and channel "lane 0". This channel sequence number is exactly opposite to the channel sequence number of the original primary controller (i.e., the first storage virtualization controller (SVC 1) 10).

[0164] Finally, the second storage virtualization controller (SVC 2) 20 uses the multiple activation channels through the second switch (switch 2) 209. The multiple activation channels correspond to the channels (lanes) of the second half 902 coupled to itself in the single port (single port) of the physical storage device (PSD) 9 (for example, the first physical storage device (PSD) 9a); that is, the multiple activation channels correspond to the channel "0" (lane 0) and the channel "1" (lane 1) of the sorted second half 902 (step 7017). In this way, the signal connection between the new main controller (that is, the second storage virtualization controller (SVC 2) 20) and the physical storage device (PSD) 9 (for example, the first physical storage device (PSD) 9a) can be established; that is, the process of setting the user end of the physical storage device (PSD) 9 to the second storage virtualization controller (SVC 2) 20 is completed. When the second storage virtualization controller (SVC 2) 20 sends a second input / output request to the physical storage device (PSD) 9 (e.g., the first physical storage device (PSD) 9a), the physical storage device (PSD) 9 (e.g., the first physical storage device (PSD) 9a) receives the second input / output request through the channel of the second half 902 of the single port, and processes the second input / output request according to the dedicated clock signal provided by its dedicated clock generation circuit 85 (e.g., the first clock generation circuit 85a).

[0165] The following is an example, in which Figure 2AThe RAID subsystem 4D of the storage system architecture 2D in the embodiment of the present invention is assumed, and it is assumed that the first storage virtualization controller (SVC 1) 10 is the primary controller of the physical storage device (PSD) 9 (e.g., the first physical storage device (PSD) 9a), and the second storage virtualization controller (SVC 2) 20 is the secondary controller of the physical storage device (PSD) 9 (e.g., the first single-port physical storage device (PSD) 9a). At time point T1, the first storage virtualization controller (SVC 1) 10 transmits a first input / output request to the first physical storage device (PSD) 9a through its first device-side input / output device connection controller 107, requesting to read the read data (READ data) in the first physical storage device (PSD) 9a. At time point T2, after receiving the first input / output request, the first physical storage device (PSD) 9a prepares the read data (READ data) required by the first storage virtualization controller (SVC 1) 10. At a later time point T3, the first storage virtualization controller (SVC 1) 10 cannot function normally or for other reasons and must switch the data flow path to be provided by the second storage virtualization controller (SVC 2) 20 (step 7001). At time point T4, the second storage virtualization controller (SVC 2) 20 takes over the work of the first storage virtualization controller (SVC 1) 10 and becomes the new main controller (step 7003), and at time point T5, detects the existence of the first physical storage device (PSD) 9a through the second switch (switch 2) 209 (step 7007). Therefore, the second storage virtualization controller (SVC 2) 20 activates the coupled channels through the second switch (switch 2) 209, and the multiple activated channels correspond to the channels of the second half 902 coupled to itself in the single port (single port) of the physical storage device (PSD) 9 (for example, the first physical storage device (PSD) 9a) (step 7009). Afterwards, the second storage virtualization controller (SVC 2) 20 (i.e., the new primary controller) sends a reset signal to the physical storage device (PSD) 9 (e.g., the first physical storage device (PSD) 9a) through the second switch (switch 2) 209 to set the second storage virtualization controller (SVC 2) 20 as its user end (step 7011). At time point T6, the user end of the first physical storage device (PSD) 9a has been successfully set to the second storage virtualization controller (SVC 2) 20, and the second storage virtualization controller (SVC 2) 20 confirms the multiple activated channels (corresponding to the channels of the second half 902 of the single port of the first physical storage device (PSD) 9a) through the second switch (switch 2) 209 (step 7013).Next, at time point T7, the second storage virtualization controller (SVC 2) 20 sorts the plurality of active channels (corresponding to the channels of the second half 902 of the single port of the first physical storage device (PSD) 9a) through the second switch (switch 2) 209 (step 7015). Then, at time point T8, the second storage virtualization controller (SVC 2) 20 uses the sorted plurality of active channels (corresponding to the channels of the second half 902 of the single port of the first physical storage device (PSD) 9a coupled to itself) through the second switch (switch 2) 209 (step 7017). In this embodiment, although the service provided by the primary controller is interrupted during the process of switching the data stream, the first physical storage device (PSD) 9a still continues to perform the related operations of the input / output request (step 7005), and finally transmits the prepared read data (READdata) to the primary controller (i.e., the second storage virtualization controller (SVC 2) 20) to complete the input / output request operation.

[0166] Please refer to Figure 7B The following instructions apply to Figure 2A , Figure 2B and Figure 3In the RAID subsystem 4D, 4E of the storage system architecture 2D, 2E shown, a first storage virtualization controller (SVC 1) 10 is set as a primary controller of one or more physical storage devices (PSD) 9 (for example, a first physical storage device (PSD) 9a), and a second storage virtualization controller (SVC 2) 20 is a secondary controller of the one or more physical storage devices (PSD) 9 (for example, a first physical storage device (PSD) 9a). According to an embodiment of the present invention, when data flow switching is required (step 7101), for example, when the second storage virtualization controller (SVC 2) 20 determines that the first storage virtualization controller (SVC 1) 10 is not operating normally according to the above-mentioned monitoring mechanism, or when the user end of the physical storage device (PSD) 9 (for example, the first physical storage device (PSD) 9a) needs to be switched to the second storage virtualization controller (SVC 2) 20 when the first storage virtualization controller (SVC 1) 10 is still operating normally, the second storage virtualization controller (SVC2) 20 will set itself as the new primary controller (step 7103). At this time, according to another embodiment of the present invention, the RAID subsystems 4D and 4E can also choose to first allow the physical storage device (PSD) 9 (for example, the first physical storage device (PSD) 9a) to suspend the execution of the input / output request (I / O request) it has received but not yet completed (step 7105).

[0167] Then, after taking over the work of the first storage virtualization controller (SVC 1) 10, the second storage virtualization controller (SVC 2) 20 (i.e., the new primary controller) detects the existence of the physical storage device (PSD) 9 (e.g., the first single-port physical storage device (PSD) 9a) through the second switch (switch 2) 209 (step 7107). Then, the second storage virtualization controller (SVC 2) 20 (i.e., the new primary controller) activates the coupled channels through the second switch (switch 2) 209, and the multiple activated channels correspond to the channels of the second half 902 coupled to the second half 902 in the single port of the physical storage device (PSD) 9 (e.g., the first physical storage device (PSD) 9a) (step 7109). Afterwards, the second storage virtualization controller (SVC 2) 20 (i.e., the new primary controller) sends a reset signal to the physical storage device (PSD) 9 (e.g., the first physical storage device (PSD) 9a) through the second switch (switch 2) 209 to set the second storage virtualization controller (SVC 2) 20 as its user end (step 7111).

[0168] When the user end of the physical storage device (PSD) 9 (for example, the first physical storage device (PSD) 9a) is successfully set to the second storage virtualization controller (SVC 2) 20, the second storage virtualization controller (SVC 2) 20 confirms the multiple activated channels (corresponding to the channels of the second half 902 of the single port of the physical storage device (PSD) 9) through the second switch (switch 2) 209 (step 7113). Then, the second storage virtualization controller (SVC 2) 20 sorts the multiple activated channels (corresponding to the channels of the second half 902 of the single port of the physical storage device (PSD) 9) through the second switch (switch 2) 209; the sorting method is to start from the first channel in the PCIe lane of the second half 902 in the single port coupled thereto and arrange them in sequence. (step 7115). For example, assume that a single port of a physical storage device (PSD) 9 (e.g., the first physical storage device (PSD) 9a) has four PCIe lanes. The second storage virtualization controller (SVC 2) 20, which becomes the new primary controller, sequentially sets the setting value of each lane for the multiple activated lanes (corresponding to the second half 902 connected to the single port). Figure 2D In the illustrated embodiment, the new primary controller (i.e., the second storage virtualization controller (SVC 2) 20) sequentially sets the setting values ​​of each channel for the plurality of activated channels (corresponding to the channels of the second half 902 of the single port) through the second switch 209. In this way, the two channels of the second half 902 in the single port are correspondingly channel "lane 0" and channel "1".

[0169] (lane 1), the four PCIe lanes in the single port (including the two lanes in the first half 901 and the two lanes in the second half 902) are thus sequentially corresponding to lane "3" (lane 3), lane "2" (lane 2), lane "1" (lane 1) and lane "0" (lane 0). This lane sequence number is exactly opposite to the lane sequence number of the original primary controller (i.e., the first storage virtualization controller (SVC 1) 10).

[0170] Afterwards, the second storage virtualization controller (SVC 2) 20 uses the multiple activation channels through the second switch (switch 2) 209. The multiple activation channels correspond to the channels (lanes) of the second half 902 coupled to the physical storage device (PSD) 9 (for example, the first physical storage device (PSD) 9a) in the single port; that is, the multiple activation channels correspond to the channel "0" (lane 0) and the channel "1" (lane 1) of the second half 902 after sorting (step 7117). Afterwards, the physical storage device (PSD) 9 (for example, the first physical storage device (PSD) 9a) receives the second input / output request from the second storage virtualization controller (SVC 2) 20 through the channel of the second half 902 of its single port, and processes the second input / output request (I / O request) according to the dedicated clock signal issued by its dedicated clock generation circuit 85 (step 7119).

[0171] The following is an example, in which Figure 2A The RAID subsystem 4D of the storage system architecture 2D in the embodiment is assumed, and the first storage virtualization controller 10 is the primary controller of the physical storage device (PSD) 9 (e.g., the first physical storage device (PSD) 9a), and the second storage virtualization controller (SVC 2) 20 is the secondary controller of the physical storage device (PSD) 9 (e.g., the first single-port physical storage device (PSD) 9a). At time point T1, the first storage virtualization controller (SVC 1) 10 transmits a second input / output request to the first physical storage device (PSD) 9a through its first device-side input / output device connection controller 107, requesting to read the read data (READ data) in the first physical storage device (PSD) 9a. At time point T2, after receiving the second input / output request, the first physical storage device (PSD) 9a prepares the read data (READ data) required by the first storage virtualization controller (SVC 1) 10. At a later time point T3, the first storage virtualization controller (SVC 1) 10 cannot function normally or for other reasons and must switch the data flow path to the second storage virtualization controller (SVC 2) 20 to provide services (step 7101). At this time, the second storage virtualization controller (SVC 2) 20 takes over the work of the first storage virtualization controller (SVC 1) 10 at time point T4 and becomes the new primary controller.

[0172] (Step 7103). Afterwards, the first physical storage device (PSD) 9a stops executing the uncompleted input / output requests originally issued by the failed controller (i.e., the first storage virtualization controller (SVC 1) 10) (Step 7105). At time point T5, the second storage virtualization controller (SVC 2) 20 detects the existence of the first physical storage device (PSD) 9a through the second switch (switch 2) 209 (Step 7107). Therefore, the second storage virtualization controller (SVC 2) 20 activates the coupled channels through the second switch (switch 2) 209, and the multiple activated channels correspond to the channels of the second half 902 coupled to itself in the single port (single port) of the physical storage device (PSD) 9 (e.g., the first physical storage device (PSD) 9a) (Step 7109). Afterwards, the second storage virtualization controller (SVC 2) 20 (i.e., the new primary controller) sends a reset signal to the physical storage device (PSD) 9 (e.g., the first physical storage device (PSD) 9a) through the second switch (switch 2) 209 to set the second storage virtualization controller (SVC 2) 20 as its user end (step 7111). At time point T6, the user end of the first physical storage device (PSD) 9a has been successfully set to the second storage virtualization controller (SVC 2) 20, and the second storage virtualization controller (SVC 2) 20 confirms the multiple activated channels (corresponding to the channels of the second half 902 of the single port of the first physical storage device (PSD) 9a) through the second switch (switch 2) 209 (step 7113). Next, at time point T7, the second storage virtualization controller (SVC 2) 20 sorts the plurality of activated channels (channels corresponding to the second half 902 of the single port of the first physical storage device (PSD) 9a) through the second switch (switch 2) 209 (step 7115). Then, at time point T8, the second storage virtualization controller (SVC 2) 20 sorts the plurality of activated channels (channels corresponding to the second half 902 of the single port of the first physical storage device (PSD) 9a) through the second switch (switch 2) 209 (step 7115).

[0173] 209 uses the sorted multiple activated channels (corresponding to the channels of the second half 902 coupled to itself in the single port of the first physical storage device (PSD) 9a) (step 7117). Finally, at time point T9, the first physical storage device (PSD) 9a receives a dedicated clock signal from its dedicated clock generation circuit 85, and processes one or more second input / output requests (I / O request) from the new primary controller (i.e., the second storage virtualization controller (SVC 2) 20) according to the dedicated clock signal (step 7119). In this embodiment, when the first physical storage device (PSD) 9a needs to switch the data flow to the new primary controller (i.e., the second storage virtualization controller (SVC 2) 20), the execution of the input / output request originally from the first storage virtualization controller (SVC 1) 10 is suspended. Later, at time point T9, the second storage virtualization controller (SVC 2) 20 issues a new input / output request to the first physical storage device (PSD) 9a, requesting to re-read the required read data (READdata) from the first physical storage device (PSD) 9a (step 7119).

[0174] According to an embodiment of the present invention, although it is assumed in the above description that Figure 2A , Figure 2B , Figure 2C , Figure 2D ,and Figure 3 The primary controller (primary controller) of the first physical storage device (PSD) 9a is the first storage virtualization controller (SVC 1) 10, and the secondary controller (secondary controller) is the second storage virtualization controller (SVC 2) 20; however, the primary controller (primary controller) and the secondary controller (secondary controller) of the second physical storage device (PSD) 9b do not necessarily need to be consistent with the first physical storage device (PSD) 9a. The second physical storage device (PSD) 9b can also set the second storage virtualization controller (SVC 2) 20 as its primary controller (primary controller) according to needs, and set the first storage virtualization controller (SVC 1) 10 as the secondary controller. In addition, the operation of the first storage virtualization controller (SVC 1) 10 and the second storage virtualization controller (SVC 2) 20 for other physical storage devices (PSD) 9 (for example, the second physical storage device (PSD) 9b) is essentially the same as the aforementioned Fig. 7A and Figure 7BThe operation of the two storage virtualization controllers (SVC 1, SVC 2) 10, 20 on the physical storage device (PSD) 9 (eg, the first single port physical storage device (PSD) 9a) is not described in detail below.

[0175] In summary, according to the technology disclosed in the present invention, each physical storage device (PSD) 9 in the storage system architecture 2D, 2E is configured with an independently operated and dedicated clock generation circuit 85 to provide a dedicated clock signal in a one-to-one manner (that is, each physical storage device (PSD) 9 is configured with a dedicated clock generation circuit). Since the present invention uses an independently operated and dedicated clock generation circuit to provide a clock signal to its corresponding physical storage device (PSD) 9 in a one-to-one manner, it is not necessary to rely on the storage virtualization controller (SVC) 10, 20 to provide the clock signal, nor is it necessary to use additional circuit components (for example, distributors 113, 115, 117) to assist the storage virtualization controller (SVC) 10, 20 in wiring to guide the clock signal to multiple physical storage devices (PSD) 9 coupled thereto. In this way, not only the problem in the prior art that the physical storage device (PSD) 9 coupled thereto cannot operate normally due to the failure of the storage virtualization controller (SVC) to provide a clock signal is solved, but also the problem that the physical storage device (PSD) 9 coupled thereto cannot operate normally due to the failure of the distributor to provide a clock signal is solved. In addition, since no additional circuit components (e.g., distributors 113, 115, 117) are required, not only the cost and complex routing are saved, but also the problem of loopholes in the redundant design of the system due to the failure of the distributor is avoided.

[0176] Although the present invention is disclosed as above with the aforementioned preferred embodiments, it is not intended to limit the present invention. Anyone with similar skills can make some equivalent changes and modifications without departing from the spirit and scope of the present invention, which are still within the scope of the patent of the present invention. Therefore, the patent protection scope of the present invention shall be based on the definition of the claims attached to this specification.

[0177] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.

Claims

1. A data access method, applied to a RAID subsystem (4D, 4E), wherein the RAID subsystem (4D, 4E) comprises a first storage virtualization controller (10), a second storage virtualization controller (20), a first switch (109), a second switch (209), a first physical storage device (9, 9a), a backplane (401), and a first clock generation circuit (85, 85a), wherein: The method comprises: The first clock generating circuit (85, 85a) is installed on the backplane (401) to provide a first dedicated clock signal for the first physical storage device (9, 9a); coupling the first half (901) of the single port of the first physical storage device (9, 9a) to the first storage virtualization controller (10) via the first switch (109); coupling the second half (902) of the single port of the first physical storage device (9, 9a) to the second storage virtualization controller (20) via the second switch (209); Setting the first storage virtualization controller (10) as a user end of the first physical storage device (9, 9a); The first physical storage device (9, 9a) receives at least one first input / output request from the first storage virtualization controller (10), and processes the at least one first input / output request according to the first dedicated clock signal provided by the first clock generation circuit (85, 85a); Setting the second storage virtualization controller (20) as a user end of the first physical storage device (9, 9a); and Through the second half (902) of the single port, the first physical storage device (9, 9a) receives at least one second input / output request from the second storage virtualization controller (10), and processes the at least one second input / output request according to the first dedicated clock signal provided by the first clock generating circuit (85, 85a).

2. The data access method according to claim 1, characterized in that: The step of setting the first storage virtualization controller (10) as a user end of the first physical storage device (9, 9a) further includes: The first storage virtualization controller (10) activates at least one first channel coupled to the first physical storage device (9, 9a), the at least one first channel corresponding to a channel of the first half (901) of the single port of the first physical storage device (9, 9a); The first storage virtualization controller (10) sends a first reset signal to the first physical storage device (9, 9a), requesting the first physical storage device (9, 9a) to set the first storage virtualization controller (10) as its user end; The first storage virtualization controller (10) confirms the at least one first channel; The first storage virtualization controller (10) sorts the at least one first channel; and The first storage virtualization controller (10) activates the at least one first channel.

3. The data access method according to claim 2, characterized in that: The step of setting the first storage virtualization controller (10) as a user end of the first physical storage device (9, 9a) further includes: The first storage virtualization controller (10) and the second storage virtualization controller (20) mutually confirm that the first storage virtualization controller (10) is the primary controller of the first physical storage device (9, 9a) through a redundant controller communication link (7).

4. The data access method according to claim 3, characterized in that: The redundant controller communication link (7) is selected from one of the following communication link combinations, including: peripheral component interconnect rapid interface, Ethernet, remote memory direct access interface, fiber channel arbitration loop, parallel small computer system interface operating in target mode, and serial advanced technology access interface operating in target mode.

5. The data access method according to claim 1, characterized in that: The step of setting the second storage virtualization controller (20) as the user end of the first physical storage device (9, 9a) further includes: The second storage virtualization controller (20) activates at least one second channel coupled to the first physical storage device (9, 9a), the at least one second channel corresponding to a channel of the second half (902) of the single port of the first physical storage device (9, 9a); The second storage virtualization controller (20) sends a first reset signal to the first physical storage device (9, 9a), requesting the first physical storage device (9, 9a) to set the second storage virtualization controller (20) as its user end; The second storage virtualization controller (20) confirms the at least one second channel; The second storage virtualization controller (20) sorts the at least one second channel; and The second storage virtualization controller (20) activates the at least one second channel.

6. The data access method according to claim 1, characterized in that: The first clock generating circuit (85, 85a) provides the first dedicated clock signal to the first physical storage device (9, 9a) in a one-to-one manner.

7. The data access method according to claim 1, characterized in that: The first storage virtualization controller (10) and the second storage virtualization controller (20) do not require additional circuit components to assist in directing their own clock signals to the first physical storage device (9, 9a).

8. The data access method according to claim 1, characterized in that: It also includes the second storage virtualization controller (20) learning through a monitoring mechanism that the first storage virtualization controller (10) is not operating normally.

9. The data access method according to claim 8, characterized in that: The monitoring mechanism is that the first storage virtualization controller (10) sends a confirmation signal to the second storage virtualization controller (20) every time a first time interval passes.

10. The data access method according to claim 8, characterized in that: The monitoring mechanism is that the second storage virtualization controller (20) sends an inquiry signal to the first storage virtualization controller (10) every second time interval, and waits for a response signal from the first storage virtualization controller (10).

11. The data access method according to claim 1, characterized in that: The first clock generating circuit is a component directly mounted on the backplane (401).

12. The data access method according to claim 1, characterized in that: The first clock generating circuit is connected to the first socket on the backplane (401).

13. The data access method according to claim 12, characterized in that: The first clock generating circuit is connected to the first socket on the backplane (401) via a first plug-in card.

14. The data access method according to claim 1, characterized in that: The first storage virtualization controller (10), the second storage virtualization controller (20), the first switch (109) and the second switch (209) are separate and independent circuit systems.

15. The data access method according to claim 1, characterized in that: The first switch (109) and the second switch (209) are integrated into the first storage virtualization controller (10) and the second storage virtualization controller (20), respectively.

16. The data access method according to claim 1, characterized in that: The first switch (109) and the second switch (209) are integrated into a single switch, and the first storage virtualization controller (10) and the second storage virtualization controller (20) are respectively coupled to the first physical storage device (9, 9a) through the single switch.

17. The data access method according to claim 1, characterized in that: During the process of switching the user end of the first physical storage device (9, 9a) from the first storage virtualization controller (10) to the second storage virtualization controller (20), the first physical storage device (9, 9a) continues to execute the at least one first input / output request from the first storage virtualization controller (10) according to the first dedicated clock signal provided by the first clock generating circuit (85, 85a).

18. The data access method according to claim 1, characterized in that: During the process of the user end of the first physical storage device (9, 9a) switching from the first storage virtualization controller (10) to the second storage virtualization controller (20), the first physical storage device (9, 9a) suspends the execution of the at least one first input / output request from the first storage virtualization controller (10).

19. The data access method according to claim 1, characterized in that: The RAID subsystem (4D, 4E) further includes a second physical storage device (9, 9b) and a second clock generating circuit (85, 85b), wherein the method further includes: The second clock generating circuit (85, 85b) is installed on the backplane (401) to provide a second dedicated clock signal for the second physical storage device (9, 9b); coupling the first half (901) of the single port of the second physical storage device (9, 9b) to the second storage virtualization controller (20) via the second switch (209); coupling the second half (902) of the single port of the second physical storage device (9, 9b) to the first storage virtualization controller (10) via the first switch (109); Setting the second storage virtualization controller (20) as a user end of the second physical storage device (9, 9b); The second physical storage device (9, 9b) receives at least one second input / output request from the second storage virtualization controller (20) through the first half (901) of the single port, and processes the at least one second input / output request according to the second dedicated clock signal provided by the second clock generation circuit (85, 85b); The first storage virtualization controller (10) sends a setting signal to the second switch (209), and resets the user end of the second physical storage device (9, 9b) to the first storage virtualization controller (10) through the second switch (209); and Through the channel of the second half (902), the second physical storage device (9, 9b) processes at least one first input / output request from the first storage virtualization controller (10) according to the second dedicated clock signal provided by the second clock generating circuit (85, 85b).

20. The data access method according to claim 19, characterized in that: The second clock generating circuit (85, 85b) provides the second dedicated clock signal to the second physical storage device (9, 9b) in a one-to-one manner.

21. A RAID subsystem (4D, 4E), characterized in that: The RAID subsystem (4D, 4E) is coupled to a host (15) to receive and process at least one access request from the host (15), and the RAID subsystem (4D, 4E) includes: A first storage virtualization controller (10) includes a first switch (109); A second storage virtualization controller (20), including a second switch (209), and communicating information with the first storage virtualization controller (10) via a redundant controller communication link (7); A first physical storage device (9, 9a) comprises a single port, wherein a channel of the single port is divided into a first half (901) and a second half (902), wherein the channel of the first half (901) is coupled to the first switch (109) of the first storage virtualization controller (10), and the channel of the second half (902) is coupled to the second switch (209) of the second storage virtualization controller (20); as well as A first clock generating circuit (85, 85a), coupled to the first physical storage device (9, 9a), for providing a first dedicated clock signal to the first physical storage device (9, 9a); wherein the first storage virtualization controller (10) and the second storage virtualization controller (20) confirm through the redundant controller communication link (7) that the first storage virtualization controller (10) is the user end of the first physical storage device (9, 9a), the first storage virtualization controller (10) sets itself as the user end of the first physical storage device (9, 9a), and sends at least one first input / output request to the first physical storage device (9, 9a) through the first switch (109), and the first physical storage device (9, 9a) processes the at least one first input / output request according to the first dedicated clock signal provided by the first clock generating circuit (85, 85a); and When the user end of the first physical storage device (9, 9a) is changed to the second storage virtualization controller (20), the second storage virtualization controller (20) sets itself as the user end of the first physical storage device (9, 9a), and sends at least one second input / output request to the first physical storage device (9, 9a) through the second switch (209), and the first physical storage device (9, 9a) processes the at least one second input / output request according to the first dedicated clock signal provided by the first clock generating circuit (85, 85a).

22. The RAID subsystem (4D, 4E) according to claim 21, characterized in that: The first storage virtualization controller (10) further includes: A first central processing circuit (103) is used to process the at least one access request from the host (15); and The first device-side input / output device connection controller (107) is used to receive information and instructions from the first central processing circuit (103), and is coupled to the first physical storage device (9, 9a) through the first switch (109) to serve as an interface and buffer between the first physical storage device (9, 9a) and the first central processing circuit (103).

23. The RAID subsystem (4D, 4E) according to claim 22, characterized in that: The first switch (109) is integrated into the first device-side input / output device connection controller (107).

24. The RAID subsystem (4D, 4E) according to claim 22, characterized in that: The first switch (109) and the first device-side input / output device connection controller (107) are integrated into the first central processing circuit (103).

25. The RAID subsystem (4D, 4E) according to claim 21, characterized in that: The second storage virtualization controller (20) further comprises: A second central processing circuit (203) is used to process the at least one access request from the host (15); and The second device-side input / output device connection controller (207) is used to receive information and instructions from the second central processing circuit (203), and is coupled to the first physical storage device (9, 9a) through the second switch (209) to serve as an interface and buffer between the first physical storage device (9, 9a) and the second central processing circuit (203).

26. The RAID subsystem (4D, 4E) according to claim 25, characterized in that: The second switch (209) is integrated into the second device-side input / output device connection controller (207).

27. The RAID subsystem (4D, 4E) according to claim 25, characterized in that: The second switch (209) and the second device-side input / output device connection controller (207) are integrated into the second central processing circuit (203).

28. The RAID subsystem (4D, 4E) according to claim 21, characterized in that: The redundant controller communication link (7) is selected from one of the following communication link combinations, including: peripheral component interconnect rapid interface, Ethernet, remote memory direct access interface, fiber channel arbitration loop, parallel small computer system interface operating in target mode, and serial advanced technology access interface operating in target mode.

29. The RAID subsystem (4D, 4E) according to claim 21, characterized in that: The first clock generating circuit (85, 85a) provides the first dedicated clock signal to the first physical storage device (9, 9a) in a one-to-one manner.

30. The RAID subsystem (4D, 4E) according to claim 21, characterized in that: The first storage virtualization controller (10) and the second storage virtualization controller (20) do not require additional circuit components to assist in directing their own clock signals to the first physical storage device (9, 9a).

31. The RAID subsystem (4D, 4E) of claim 21, wherein: The first storage virtualization controller (10), the second storage virtualization controller (20), the first switch (109) and the second switch (209) are separate and independent circuit systems.

32. The RAID subsystem (4D, 4E) according to claim 21, characterized in that: The first switch (109) and the second switch (209) are integrated into the first storage virtualization controller (10) and the second storage virtualization controller (20), respectively.

33. The RAID subsystem (4D, 4E) according to claim 21, characterized in that: The first switch (109) and the second switch (209) are integrated into a single switch, and the first storage virtualization controller (10) and the second storage virtualization controller (20) are respectively coupled to the first physical storage device (9, 9a) through the single switch.

34. The RAID subsystem (4D, 4E) according to claim 21, characterized in that: It also includes a backplane (401), wherein the first clock generating circuit is a component directly mounted on the backplane (401) and is coupled to the first physical storage device (9, 9a) through the backplane (401).

35. The RAID subsystem (4D, 4E) of claim 21, wherein: A backplane (401) is also included. The first clock generating circuit is accommodated in a first socket on the backplane (401) and is coupled to the first physical storage device (9, 9a) through the backplane (401).

36. The RAID subsystem (4D, 4E) according to claim 35, characterized in that: The first clock generating circuit is connected to the first socket on the backplane (401) via a first plug-in card.

37. The RAID subsystem (4D, 4E) according to claim 21, characterized in that: Also included is a first transfer card having the first clock generating circuit and a slot thereon, wherein the slot is used to accommodate the first physical storage device (9, 9a) and to assist the first physical storage device (9, 9a) in coupling to the first storage virtualization controller (10) and the second storage virtualization controller (20).

38. The RAID subsystem (4D, 4E) of claim 21, wherein: In the process of switching the user end of the first physical storage device (9, 9a) from the first storage virtualization controller (10) to the second storage virtualization controller (20), the first physical storage device (9, 9a) continues to execute the at least one first input / output request from the first storage virtualization controller (10) according to the first dedicated clock signal provided by the first clock generating circuit (85, 85a).

39. The RAID subsystem (4D, 4E) of claim 21, wherein: In the process of switching the user end of the first physical storage device (9, 9a) from the first storage virtualization controller (10) to the second storage virtualization controller (20), the physical storage device (9) suspends the execution of the at least one first input / output request from the first storage virtualization controller (10).

40. The RAID subsystem (4D, 4E) according to claim 21, characterized in that: The first storage virtualization controller (10) sets itself as the user end of the first physical storage device (9, 9a) by executing the following steps: activating at least one first channel coupled to the first physical storage device (9, 9a), sending a first reset signal to the first physical storage device (9, 9a) to request that the first storage virtualization controller (10) be set as its user end, confirming the at least one first channel, sorting the at least one first channel, and activating the at least one first channel, wherein the at least one first channel is a channel corresponding to the first half (901) of the single port of the first physical storage device (9, 9a).

41. The RAID subsystem (4D, 4E) of claim 21, wherein: The second storage virtualization controller (20) sets itself as the user end of the first physical storage device (9, 9a) by executing the following steps: activating at least one second channel coupled to the first physical storage device (9, 9a), sending a second reset signal to the first physical storage device (9, 9a) to request that the second storage virtualization controller (20) be set as its user end, confirming the at least one second channel, sorting the at least one second channel, and activating the at least one second channel, wherein the at least one second channel is a channel corresponding to the second half (902) of the single port of the first physical storage device (9, 9a).

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