Communication system of chip module to be verified on FPGA (Field Programmable Gate Array)

Abstract

A communication system of a to-be-verified chip module on an FPGA (Field Programmable Gate Array) comprises a sampler, a clock signal generator, a level transmitter, a level receiver, a first restorer, a phase and voltage discriminator, a phase level transmitter, a phase level receiver, a loop filter, an oscillator and a second restorer, the level transmitter, the level receiver, the phase level transmitter and the phase level receiver can transmit or receive more data information in unit time, so that signals can be transmitted among the FPGAs only by using a small number of communication pins, and meanwhile, for a first signal, a first clock signal and the level information are transmitted among the FPGAs, so that the signal transmission efficiency is improved. Signal transmission adopts a mode of first sampling and sending and then receiving and restoring, high-precision transmission of a first signal is ensured, and for a second signal, a mode of first obtaining and transmitting level and phase information and then restoring the signal according to the level and phase information is adopted, and high-precision transmission of the second signal is ensured.

Description

Technical Field

[0001] The invention belongs to the field of FPGA verification technology, and in particular relates to a communication system of a chip module to be verified on an FPGA. Background Art

[0002] FPGA verification will be performed before the chip is taped out to ensure that the internal modules of the chip function normally. FPGA verification is to burn all or part of the chip modules into the FPGA and verify whether the logical functions of the chip are correct in the FPGA. The logic resources of a single FPGA are limited. If the scale of the chip to be verified is large, one FPGA cannot complete the verification of the entire chip. At this time, the chip to be verified needs to be placed in multiple FPGAs, and different FPGAs verify different chip modules. Data is transmitted between FPGAs through communication pins. For example, if the chip to be verified has a total of 4 modules, a single FPGA may hold up to 3 modules. At this time, 2 FPGAs are needed to hold 4 modules.

[0003] Currently, chip modules have many input and output signals, and a single FPGA has a limited number of communication pins. In many cases, the number of input and output signals of the chip module is greater than the number of FPGA communication pins, making it impossible to complete signal transmission between FPGAs. Summary of the invention

[0004] Based on this, in order to solve the above technical problems, a communication system for a chip module to be verified on an FPGA is provided.

[0005] The technical solution adopted by the present invention is as follows:

[0006] A communication system of a chip module to be verified on an FPGA, characterized by comprising:

[0007] A sampler, configured to sample and send level information of each first signal to a level transmitter under the drive of the first clock signal when the chip module to be verified on the FPGA outputs a plurality of first signals driven by the first clock signal of the module;

[0008] a clock signal generator, configured to output a second clock signal, wherein a frequency of the second clock signal is at least five times that of the first clock signal;

[0009] A level transmitter, used for sequentially transmitting the plurality of level information to a level receiver on the FPGA where the chip module to be verified is located at the receiving side under the driving of the second clock signal;

[0010] A level receiver, used for receiving, under the drive of the second clock signal, a plurality of level information sent from a level transmitter on the FPGA where the chip module to be verified is located on the sender in sequence, and sending the plurality of level information to the first restorer;

[0011] A first restorer, used for restoring the plurality of level information into the plurality of first signals under the drive of the first clock signal, and sending the first signals to the receiving chip module to be verified;

[0012] A phase detector and a voltage detector, configured to obtain and send level information and phase information of each second signal to a phase level transmitter under the drive of the second clock signal when the chip module to be verified on the FPGA outputs a plurality of second signals that are not driven by the first clock signal of the module;

[0013] A phase level transmitter, used for sequentially sending the plurality of level information and the plurality of phase information to a phase level receiver on the FPGA where the chip module to be verified is located at the receiving party under the drive of the second clock signal;

[0014] A phase level receiver, driven by the second clock signal, is used to sequentially receive a plurality of level information and a plurality of phase information sent from a phase level receiver on the FPGA where the chip module to be verified of the sender is located, and send the plurality of level information and a plurality of phase information to the loop filter;

[0015] A loop filter, used for filtering out clutter in the plurality of level information and the plurality of phase information, and sending the filtered information to an oscillator;

[0016] The oscillator is used to obtain multiple second signals under the drive of the second clock signal according to multiple level information and multiple phase information after filtering out noise, and send them to the receiving chip module to be verified.

[0017] The present invention provides a communication system for a chip module to be verified on an FPGA. Since the frequency of a second clock signal is at least 5 times the frequency of a first clock signal, under the drive of the second clock signal, a level transmitter, a level receiver, a phase level transmitter and a phase level receiver can send or receive more data information per unit time. Therefore, only a small number of communication pins are needed between FPGAs to transmit signals. At the same time, for the first signal, the first clock signal and level information are transmitted between FPGAs. The signal transmission adopts a method of first sampling and sending and then receiving and restoring, thereby ensuring high-precision transmission of the first signal. For the second signal, since it is not driven by the clock, a method of first acquiring and transmitting level and phase information and then restoring the signal according to the level and phase information is adopted, thereby ensuring high-precision transmission of the second signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The present invention is described in detail below with reference to the accompanying drawings and specific embodiments:

[0019] Figure 1 A schematic diagram of a communication system of a chip module to be verified on an FPGA provided by an embodiment of the present invention;

[0020] Figure 2 It is a principle diagram of sequentially receiving and sending information between a level transmitter and a level receiver according to an embodiment of the present invention;

[0021] Figure 3 It is a principle diagram of sequentially sending and receiving information between a phase level transmitter and a phase level receiver according to an embodiment of the present invention;

[0022] Figure 4 This is a schematic diagram of a first restorer recovering a signal according to an embodiment of the present invention. DETAILED DESCRIPTION

[0023] The following will illustrate the implementation methods of the present invention in conjunction with the drawings in the specification. It should be noted that the implementation methods involved in this specification are not exhaustive and do not represent the only implementation methods of the present invention. The following corresponding embodiments are only for the purpose of clearly illustrating the invention content of the patent of the present invention, and are not intended to limit its implementation methods. For ordinary technicians in this field, different forms of changes and modifications can be made on the basis of the description of this embodiment. All obvious changes or modifications that belong to the technical concept and invention content of the present invention are also within the scope of protection of the present invention.

[0024] like Figure 1 As shown, an embodiment of the present application provides a communication system of a chip module to be verified on an FPGA. The communication system is set on the FPGA, and includes a sampler 110, a clock signal generator 120, a level transmitter 130, a level receiver 140, a first restorer 150, a phase detector and a voltage detector 160, a phase level transmitter 170, a phase level receiver 180, a loop filter 190, an oscillator 197, a second restorer 198 and a delay control module 199.

[0025] The working principle of the communication system of the embodiment of the present application is explained below by taking the first FPGA21 and the second FPGA22 as examples, wherein the first FPGA21 has a chip module to be verified as a signal sender (hereinafter referred to as the sender module 3), and the second FPGA22 has a chip module to be verified as a signal receiver (hereinafter referred to as the receiver module 4), and both the first FPGA21 and the second FPGA22 have the above-mentioned communication system.

[0026] When the transmitter module 3 simultaneously sends 5 first signals and 3 second signals to the receiver module 4, the sampler 110, clock signal generator 120 and level transmitter 130 on the first FPGA 21, as well as the phase detector 160 and phase level transmitter 170 work, and the level receiver 140 and first restorer 150 on the second FPGA 22, as well as the phase level receiver 180, loop filter 190, oscillator 197, second restorer 198 and delay control module 199 work, wherein the first signal refers to a signal driven by the first clock signal of the transmitter module 3, and the change of its signal value is related to the edge of the first clock signal, and the signal value changes at the rising edge or falling edge of the clock. In this embodiment, the signal that changes at the rising edge of the clock is taken as an example, and the second signal refers to a signal that is not driven by the first clock signal of the transmitter module 3, and the change of its signal value is not related to the edge of the first clock signal, and the signal value may change at any time of the rising edge, falling edge, high level or low level of the clock. The specific process of signal transmission and reception is as follows:

[0027] 1. Driven by the first clock signal, the sampler 110 samples level information (0 or 1) of 5 first signals, and sends the 5 level information to the level transmitter 130. At the same time, the clock signal generator 120 outputs a second clock signal, and the frequency of the second clock signal is at least 5 times the frequency of the first clock signal. In this embodiment, the frequency of the second clock signal is 15 times the frequency of the first clock signal, such as the frequency of the first clock signal is 100 MHz, and the frequency of the second clock signal is 1.5 GHz.

[0028] 2. Driven by the second clock signal, the level transmitter 130 sends 5 level information to the level receiver 140 in sequence.

[0029] 3. Driven by the second clock signal, the level receiver 140 receives five level information in sequence and sends them to the first restorer 150 .

[0030] It can be seen that only one communication pin is needed between the first FPGA 21 and the second FPGA 22 to send and receive the first signal.

[0031] In this embodiment, the level transmitter 130 sends a level information to the level receiver 140 in each clock cycle after the first clock cycle of the second clock signal, and the level receiver 140 receives a level information in each clock cycle of the second clock signal, wherein the clock cycle for receiving the level information is the next clock cycle for sending the level information, and the specific process is as follows:

[0032] like Figure 2As shown, in the first FPGA 21, the sampler 110 completes the sampling of the five first signals in the first clock cycle of the second clock signal, the level transmitter 130 sends five level information in the 2nd to 6th clock cycles of the second clock signal respectively, and in the second FPGA 22, the level receiver 140 receives five level information in the 3rd to 7th clock cycles of the second clock signal respectively.

[0033] from Figure 2 It can be seen that after the level receiver 140 of the second FPGA 22 receives the signal, there are still 15-2-5=8 clock cycles, so more signals can be sent and received as a group, for example, 7 signals can be sent and received as a group, and there are still 15-2-7=6 clock cycles. The frequency of the second clock signal can also be changed. For example, the second clock signal is 1GHz, and the frequency of the second clock signal is 10 times the frequency of the first clock signal. At this time, after receiving 5 signals, there are still 10-2-5=3 clock cycles left.

[0034] 4. When receiving the five level information, the first restorer 150 outputs the first delay time Tm to the delay control module 199, and restores the five level information into five first signals under the drive of the first clock signal.

[0035] The first delay time Tm is related to two aspects: one is the delay TI of the entire link, which is a fixed value of the device; the other is the clock period T2 of the first clock signal, so the first delay time Tm=T1+T2.

[0036] like Figure 4 As shown, the first restorer 150 has a plurality of registers inside, the input value of the register is the received level information, and when the rising edge of the first clock signal arrives, the register outputs the first signal.

[0037] 5. Driven by the second clock signal, the phase detector and voltage detector 160 obtains level information and phase information of the three second signals, and sends the three level information and the three phase information to the phase level transmitter 170 .

[0038] Since the change of the signal value of the second signal is independent of the clock, such a signal cannot be simply transmitted by a clock sampling and recovery method, but needs to be transmitted by a phase level transmission method.

[0039] Among them, in each clock cycle of the second clock signal, the phase detector 160 determines the level of the three second signals and generates three level information. If the level of the three second signals changes in two adjacent clock cycles, it means that the three second signals have a level jump. At this time, the phase detector 160 records the phase difference between the level jump position and the rising edge or falling edge of the second clock signal to form three phase information. If the level does not jump, it means that the signal has not changed, and there is no need to transmit phase information. At this time, there is no phase information, and the level and phase information are transmitted only when the level jumps.

[0040] 6. Driven by the second clock signal, the phase level transmitter 170 sends three level information and three phase information to the phase level receiver 180 in sequence.

[0041] 7. Driven by the second clock signal, the phase level receiver 180 receives three level information and three phase information in sequence and sends them to the loop filter 190 .

[0042] It can be seen that only one communication pin is needed between the first FPGA 21 and the second FPGA 22 to send and receive the second signal.

[0043] In this embodiment, the phase level transmitter 170 sends a piece of information to the level receiver 180 in each clock cycle after the first clock cycle of the second clock signal in the order of sending a plurality of level information first and then sending a plurality of phase information. The level receiver 180 receives a piece of information in each clock cycle of the second clock signal, wherein the clock cycle for receiving the information is the next clock cycle for sending the information. The specific process is as follows:

[0044] like Figure 3 As shown, in the first FPGA 21, the phase detector 160 obtains 3 level information and 3 phase information in the 1st clock cycle of the second clock signal, the phase level transmitter 170 sends 3 level information and 3 phase information in the 2nd to 7th clock cycles of the second clock signal respectively, and in the second FPGA 22, the phase level receiver 180 receives 3 level information and 3 phase information in the 3rd to 8th clock cycles of the second clock signal respectively.

[0045] It should be pointed out that the three level information and three phase information at this time contain noises, and the noises have two sources, one is the noises generated by the phase detector 160, and the other is the noises introduced in the transmission process.

[0046] 8. The loop filter 190 filters out the noise in the three level information and the three phase information and sends them to the oscillator 197.

[0047] 9. Driven by the second clock signal, the oscillator 197 obtains three second signals (an oscillator is a physical device that can generate output signals based on input information) according to the three level information and three phase information after filtering out noise, and sends them to the second restorer 198. At the same time, the second delay time Tc is output to the delay control module 199.

[0048] The oscillator 197 determines the high and low levels of the three second signals according to the three level information, and determines the phases of the three second signals according to the three phase information. The oscillator 197 determines whether the signal to be transmitted has a level jump according to the size of the three level information. If the size of the three level information is the same in two adjacent clock cycles of the second clock signal, it means that the signal to be transmitted has not a level jump, and the three second signals remain unchanged. If the size of the three level information is different in two adjacent clock cycles of the second clock signal, it means that the signal to be transmitted has a level jump. At this time, according to the three phase information, the oscillator 197 generates the corresponding changed three second signals.

[0049] The second delay time Tc is related to two aspects: one is the delay T3 of the entire link, which is a fixed value of the device, and the other is the clock period T4 of the second clock signal. Therefore, the second delay time Tc=T3+T4*(2+number of second signals*2). In this embodiment, the number of second signals is 3, and Tc=T3+T4*8.

[0050] 10. Under the delay control of the delay control module 199 , the second restorer 198 sends the three second signals to the receiving module 4 , so that the three second signals and the five first signals sent by the first restorer 150 arrive at the receiving module 4 at the same time.

[0051] The delay time Tde l ay for the delay control module 199 to perform delay control on the second restorer 198 is the difference between the first delay time and the second delay time: Tm-Tc.

[0052] In the above process, driven by the second clock signal, the level transmitter 130, the level receiver 140, the phase level transmitter 170 and the phase level receiver 180 can send or receive more data information per unit time. Therefore, only two communication pins are needed between the first FPGA 21 and the second FPGA 22 to transmit the first signal and the second signal.

[0053] It is understandable that, in a scenario where the first signal or the second signal is sent separately, the delay control module 199 and the second restorer 198 can be omitted, and the oscillator 197 directly sends the three second signals to the receiving module 4 .

[0054] As can be seen from the above, in a communication system of a chip module to be verified on an FPGA provided by an embodiment of the present application, under the drive of a second clock signal, a level transmitter, a level receiver, a phase level transmitter and a phase level receiver can send or receive more data information per unit time. Therefore, only a small number of communication pins are needed between FPGAs to transmit signals. At the same time, for the first signal, the first clock signal and level information are transmitted between FPGAs, and the signal transmission adopts a method of first sampling and sending and then receiving and restoring, so that the phase and numerical relationship between the first signal and the first clock signal in the two FPGAs are consistent, thereby ensuring high-precision transmission of the first signal. For the second signal, since it is not driven by a clock, the method of first acquiring and transmitting the level and phase information and then restoring the signal based on the level and phase information is adopted, thereby ensuring high-precision transmission of the second signal.

[0055] In addition, in the scenario where the first signal and the second signal are transmitted simultaneously, the delay control module enables the first signal and the second signal to arrive at the receiving module at the same time, thereby ensuring the relative temporal relationship between the two.

[0056] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. A communication system for a chip module to be verified on an FPGA, characterized in that: include: A sampler, configured to sample and send level information of each first signal to a level transmitter under the drive of the first clock signal when the chip module to be verified on the FPGA outputs a plurality of first signals driven by the first clock signal of the module; a clock signal generator, configured to output a second clock signal, wherein the frequency of the second clock signal is at least five times the frequency of the first clock signal; A level transmitter, used for sequentially transmitting the plurality of level information to a level receiver on the FPGA where the chip module to be verified is located at the receiving side under the driving of the second clock signal; A level receiver, used for receiving, under the drive of the second clock signal, a plurality of level information sent from a level transmitter on the FPGA where the chip module to be verified is located on the sender in sequence, and sending the plurality of level information to the first restorer; A first restorer, used for restoring the plurality of level information into the plurality of first signals under the drive of the first clock signal, and sending the first signals to the receiving chip module to be verified; A phase detector and a voltage detector, configured to obtain and send level information and phase information of each second signal to a phase level transmitter under the drive of the second clock signal when the chip module to be verified on the FPGA outputs a plurality of second signals that are not driven by the first clock signal of the module; A phase level transmitter, used for sequentially sending the plurality of level information and the plurality of phase information to a phase level receiver on the FPGA where the chip module to be verified is located at the receiving party under the drive of the second clock signal; A phase level receiver, driven by the second clock signal, is used to sequentially receive a plurality of level information and a plurality of phase information sent from a phase level receiver on the FPGA where the chip module to be verified of the sender is located, and send the plurality of level information and a plurality of phase information to the loop filter; A loop filter, used for filtering out clutter in the plurality of level information and the plurality of phase information, and sending the filtered information to an oscillator; The oscillator is used to obtain multiple second signals under the drive of the second clock signal according to multiple level information and multiple phase information after filtering out noise, and send them to the receiving chip module to be verified.

2. The signal receiving and sending method of the chip module to be verified between FPGAs according to claim 1 is characterized in that: The frequency of the second clock signal is 15 times the frequency of the first clock signal.

3. The signal receiving and sending method of the chip module to be verified between FPGAs according to claim 1 is characterized in that: The step of sequentially sending the plurality of level information to a level receiver on the FPGA where the chip module to be verified is located at the receiving side under the driving of the second clock signal further comprises: In each clock cycle after the first clock cycle of the second clock signal, a level information is sent to a level receiver on the FPGA where the chip module to be verified is located on the receiving side.

4. The signal receiving and sending method of the chip module to be verified between FPGAs according to claim 3 is characterized in that: The method of sequentially receiving, under the driving of the second clock signal, a plurality of level information sent from a level transmitter on the FPGA where the chip module to be verified is located on the sender side further comprises: A level information is received in each clock cycle of the second clock signal, wherein the clock cycle for receiving the level information is the next clock cycle for sending the level information.

5. The signal receiving and sending method of the chip module to be verified between FPGAs according to claim 4 is characterized in that: The step of sequentially sending the plurality of level information and the plurality of phase information to a phase level receiver on the FPGA where the chip module to be verified is located at the receiving side under the driving of the second clock signal further comprises: In the order of sending multiple level information first and then sending multiple phase information, one information is sent to the level receiver on the FPGA where the receiving chip module to be verified is located in each clock cycle after the first clock cycle of the second clock signal.

6. The signal receiving and sending method of the chip module to be verified between FPGAs according to claim 5 is characterized in that: The sequentially receiving a plurality of level information and a plurality of phase information sent from a phase level receiver on an FPGA where the chip module to be verified of the transmitter is located further comprises: A message is received in each clock cycle of the second clock signal, wherein the clock cycle for receiving the message is the next clock cycle for sending the message.

7. The method for sending and receiving signals between chip modules to be verified between FPGAs according to claim 6, characterized in that: It also includes a delay control module and a second restorer. When the multiple first signals and the multiple second signals are simultaneously output by the chip module to be verified on the sending side, the first restorer outputs a first delay time to the delay control module upon receiving multiple level information. The oscillator sends the multiple second signals to the second restorer and outputs the second delay time to the delay control module. Under the delay control of the delay control module, the second restorer sends the multiple second signals to the chip module to be verified on the receiving side, so that the multiple second signals and the multiple first signals sent by the first restorer arrive at the chip module to be verified on the receiving side at the same time. Among them, the first delay time Tm = link delay TI + clock period T2 of the first clock signal, the second delay time Tc = link delay T3 + clock period T4 of the second clock signal * (2 + number of second signals * 2), and the delay time of the delay control module to delay the second restorer = Tm-Tc.

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