Scanning driver and display device including same

Abstract

The invention relates to a scan driver and a display device including the same. The scan driver includes a plurality of stages sequentially connected to each other. Each of the plurality of stages includes first and second output transistors and first to fourth control transistors. The second control transistor is connected between the second node and the first voltage terminal and to the input terminal, and operates in response to a start signal or a previous carry signal provided through the input terminal. Each of the first and second output transistors and the first, third, and fourth control transistors is a first type transistor, and the second control transistor is a second type transistor different from the first type transistor.

Description

Technical Field

[0001] Embodiments of the present disclosure described herein relate to a scan driver and a display device including the same, and more particularly, to a scan driver having a simplified circuit structure and a display device including the same. Background Art

[0002] A light-emitting display device among display devices displays images via a light-emitting diode that generates light through recombination of electrons and holes. Compared with the power and response speed of other display devices, the light-emitting display device consumes less power and supports a faster response speed.

[0003] The light-emitting display device includes a display panel in which pixels are arranged in an effective area. Each of the pixels generally includes a light-emitting diode and a pixel circuit unit for controlling the amount of current flowing to the light-emitting diode. The pixel circuit unit is connected to a data line receiving a data signal and a scan line receiving a scan signal. In response to the data signal, the pixel circuit unit controls the amount of current flowing from a first drive voltage line through the light-emitting diode to a second drive voltage line. In this case, light of a brightness corresponding to the amount of current flowing through the light-emitting diode is generated. Summary of the invention

[0004] Embodiments of the present disclosure provide a scan driver capable of simplifying a circuit structure and reducing power consumption, and a display device including the scan driver.

[0005] In an embodiment of the present disclosure, a scan driver includes a plurality of stages connected sequentially to each other. Each of the plurality of stages includes: a first output transistor connected between an output terminal and a first voltage terminal and operated in response to the potential of a first node; a second output transistor connected between an output terminal and a second voltage terminal and operated in response to the potential of a second node; a first control transistor connected between an input terminal receiving a start signal or receiving a previous carry signal from a previous stage and a third node and operated in response to a clock signal provided through a clock terminal; a second control transistor connected between a second node and a first voltage terminal and operated in response to a start signal or a previous carry signal provided through an input terminal or operated in response to the potential of a third node; a third control transistor connected between a third node and a first node and operated in response to a first voltage provided through a first voltage terminal; and a fourth control transistor connected between a second node and a second voltage terminal and operated in response to the potential of a third node. Each of the first and second output transistors and the first, third and fourth control transistors is a first type transistor, and the second control transistor is a second type transistor different from the first type transistor.

[0006] In an embodiment of the present disclosure, a scan driver includes a plurality of stages connected sequentially to each other. Each of the plurality of stages includes: a first output transistor, the first output transistor including a first electrode connected to an output terminal, a second electrode connected to a first voltage terminal, and a third electrode connected to a first node; a first capacitor, the first capacitor connected between the output terminal and the first node; a second output transistor, the second output transistor including a first electrode connected to the output terminal, a second electrode connected to a second voltage terminal, and a third electrode connected to a second node; a first control transistor, the first control transistor including a first electrode connected to an input terminal, a second electrode connected to a third node, and a third electrode connected to a clock terminal; a second control transistor, the second control transistor including a first electrode connected to a second node, a second electrode connected to a first voltage terminal, a third electrode connected to an input terminal or a third node, and a bottom gate electrode facing the third electrode; a third control transistor, the third control transistor including a first electrode connected to a third node, a second electrode connected to a first node, and a third electrode connected to a first voltage terminal; and a fourth control transistor, the fourth control transistor including a first electrode connected to a second node, a second electrode connected to a second voltage terminal, and a third electrode connected to a third node.

[0007] In an embodiment of the present disclosure, a display device includes: a display panel including a plurality of pixels; a data driver outputting a data signal to the display panel; and a scan driver outputting a scan signal to the display panel. The scan driver includes a plurality of stages connected to each other in sequence, and each of the plurality of stages includes: a first output transistor including a first electrode connected to an output terminal, a second electrode connected to a first voltage terminal, and a third electrode connected to a first node; a second output transistor including a first electrode connected to an output terminal, a second electrode connected to a second voltage terminal, and a third electrode connected to a second node; a first control transistor including a first electrode connected to an input terminal, a second electrode connected to a third node, and a third electrode connected to a clock terminal; a second control transistor including a first electrode connected to a second node, a second electrode connected to a first voltage terminal, and a third electrode connected to an input terminal or a third node; a third control transistor including a first electrode connected to a third node, a second electrode connected to a first node, and a third electrode connected to a first voltage terminal; and a fourth control transistor including a first electrode connected to a second node, a second electrode connected to a second voltage terminal, and a third electrode connected to a third node. Each of the first output transistor and the second output transistor and the first, third, and fourth control transistors is a P-type transistor, and the second control transistor is an N-type transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The above and other embodiments, advantages, and features of the present disclosure will become apparent by describing an embodiment of the present disclosure in detail with reference to the attached drawings.

[0009] Figure 1 is a block diagram of an embodiment of a display device according to the present disclosure.

[0010] Figure 2 is a circuit diagram of an embodiment of a pixel according to the present disclosure.

[0011] Figure 3 is a timing diagram of an embodiment of a pixel according to the present disclosure.

[0012] Figure 4A is a block diagram of an embodiment of a scan driver according to the present disclosure.

[0013] Figure 4B yes Figure 4A 0 is a block diagram of a first scan driving circuit illustrated in FIG.

[0014] Figure 5 yes Figure 4BThe circuit diagram of the first stage is shown in FIG.

[0015] Fig. 6A Is used to describe Figure 5 0047 is a waveform diagram of the operation of the first stage illustrated in FIG.

[0016] Figure 6B is a waveform diagram for describing an embodiment of the operation of the first stage according to the present disclosure.

[0017] Figure 7 yes Figure 4B The circuit diagram of the first stage is shown in FIG.

[0018] Figure 8 Is used to describe Figure 7 0047 is a waveform diagram of the operation of the first stage illustrated in FIG.

[0019] Fig. 9 is a circuit diagram of an embodiment of a first scan driving circuit according to the present disclosure.

[0020] Fig. 10A and Fig. 10B yes Fig. 9 The circuit diagram of the first stage is shown in FIG.

[0021] Fig.11A and Fig. 11B yes Fig. 9 The circuit diagram of the first stage is shown in FIG.

[0022] Fig.12 yes Figure 4A 0 is a block diagram of a first scan driving circuit illustrated in FIG.

[0023] Fig.13A yes Fig.12 The circuit diagram of the first stage is shown in FIG.

[0024] Fig. 13B yes Fig.12 The circuit diagram of the first stage is shown in FIG.

[0025] Fig.14A Is used to describe Fig.13A 0047 is a waveform diagram of the operation of the first stage illustrated in FIG.

[0026] Fig. 14B Is used to describe Fig.13A 0 is a waveform diagram of the operation of the second control transistor shown in .

[0027] Fig.15 yes Fig.12 The circuit diagram of the first stage is shown in FIG.

[0028] Fig.16 is a cross-sectional view of an embodiment of a display panel according to the present disclosure.

[0029] Fig.17 yes Figure 4A 0 is a block diagram of a first scan driving circuit illustrated in FIG.

[0030] Fig.18 yes Fig.17 The circuit diagram of the first stage is shown in FIG.

[0031] Fig.19 yes Fig.17 The circuit diagram of the first stage is shown in FIG. DETAILED DESCRIPTION

[0032] In the specification, the statement that a first component (or region, layer, part or portion) is "on", "connected to" or "coupled to" a second component means that the first component is directly on / directly connected to / directly coupled to the second component, or that a third component is interposed between the first and second components.

[0033] The same reference numerals refer to the same components. In addition, in the drawings, the thickness, proportion and size of the components are exaggerated for the effectiveness of the technical content description. The term "and / or" includes one or more combinations, and the associated elements are defined in each of the one or more combinations.

[0034] Although the terms "first", "second", etc. may be used to describe various components, these components should not be interpreted as being limited by these terms. These terms are only used to distinguish one component from another component. For example, a first component may be referred to as a "second component" and similarly, a second component may be referred to as a "first component" without departing from the scope and spirit of the present invention. The articles "a", "an", and "the" are singular because they have a single referent, but the use of the singular form in the specification should not exclude the presence of more than one referent.

[0035] In addition, the terms "lower", "below", "upper", "above", etc. are used to describe the relationship between components illustrated in the drawings. These terms are relative and are described with respect to the directions indicated in the drawings.

[0036] It will be further understood that the terms “includes,” “comprising,” “having,” etc. specify the presence of stated features, numbers, steps, operations, elements, parts, or a combination thereof, but do not preclude the presence or addition of one or more other features, numbers, steps, operations, elements, parts, or a combination thereof.

[0037] Unless otherwise defined, all terms (including technical terms and scientific terms) used in this specification have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. In addition, terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with the meaning in the context of the relevant technology, and should not be interpreted in an ideal or overly formal meaning unless explicitly defined herein.

[0038] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0039] Figure 1 is a block diagram of an embodiment of a display device according to the present disclosure.

[0040] refer to Figure 1 The display device DD includes a display panel DP and a panel driver PDD for driving the display panel DP. In an embodiment of the present disclosure, the panel driver PDD includes a driving controller 100, a data driver 200, a scan driver 300, an emission driver 350, and a voltage generator 400.

[0041] The driving controller 100 receives an input image signal RGB and a control signal CTRL from a main processor. In an embodiment of the present disclosure, the main processor may be a graphics processing unit (GPU). The driving controller 100 generates image data DATA by converting the data format of the input image signal RGB according to an interface specification with the data driver 200. The control signal CTRL may include at least one of a vertical synchronization signal, an input data enable signal, a main clock signal, etc. The driving controller 100 generates a first driving control signal SCS, a second driving control signal DCS, and a third driving control signal ECS based on the control signal CTRL.

[0042] The data driver 200 receives the second driving control signal DCS and the image data DATA from the driving controller 100. The data driver 200 converts the image data DATA into a data signal and outputs the data signal to a plurality of data lines DL1 to DLm to be described later. The data signal refers to an analog voltage corresponding to the grayscale value of the image data DATA. Herein, m is an integer of 1 or more.

[0043] The scan driver 300 receives a first driving control signal SCS from the driving controller 100. The scan driver 300 may output a scan signal to the scan line in response to the first driving control signal SCS.

[0044] The voltage generator 400 generates voltages required for the operation of the display panel DP. In an embodiment, the voltage generator 400 generates a first driving voltage ELVDD, a second driving voltage ELVSS, a first initialization voltage VINT, and a second initialization voltage AINT.

[0045] The display panel DP further includes initialization scan lines SIL1 to SILn, compensation scan lines SCL1 to SCLn, write scan lines SWL1 to SWLn+1, emission control lines EML1 to EMLn, and data lines DL1 to DLm. Herein, n is an integer of 1 or more. The initialization scan lines SIL1 to SILn, the compensation scan lines SCL1 to SCLn, the write scan lines SWL1 to SWLn+1, the emission control lines EML1 to EMLn, the data lines DL1 to DLm, and the pixels PX may overlap the active area AA. The initialization scan lines SIL1 to SILn, the compensation scan lines SCL1 to SCLn, the write scan lines SWL1 to SWLn+1, and the emission control lines EML1 to EMLn extend in the second direction DR2. The initialization scan lines SIL1 to SILn, the compensation scan lines SCL1 to SCLn, the write scan lines SWL1 to SWLn+1, and the emission control lines EML1 to EMLn are spaced apart from each other in the first direction DR1. The data lines DL1 to DLm extend in the first direction DR1 and are spaced apart from each other in the second direction DR2.

[0046] A plurality of pixels PX are electrically connected to initialization scan lines SIL1 to SILn, compensation scan lines SCL1 to SCLn, write scan lines SWL1 to SWLn+1, emission control lines EML1 to EMLn, and data lines DL1 to DLm. Each of the plurality of pixels PX may be electrically connected to four scan lines. In an embodiment, for example, the pixels PX belonging to the first row may be connected to the first initialization scan line SIL1, the first compensation scan line SCL1, the first write scan line SWL1, and the second write scan line SWL2. In addition, the pixels PX belonging to the second row may be connected to the second initialization scan line SIL2, the second compensation scan line SCL2, the second write scan line SWL2, and the third write scan line SWL3. However, the number of scan lines connected to each pixel PX is not limited thereto, and various changes or modifications may be made. In an alternative embodiment, each of the plurality of pixels PX may be electrically connected to five scan lines, and in this case, the display panel DP may further include a black scan line.

[0047] The scan driver 300 may be disposed in the non-active area NAA of the display panel DP. The scan driver 300 receives a first drive control signal SCS from the drive controller 100. In response to the first drive control signal SCS, the scan driver 300 may output an initialization scan signal to the initialization scan lines SIL1 to SILn, may output a compensation scan signal to the compensation scan lines SCL1 to SCLn, and may output a write scan signal to the write scan lines SWL1 to SWLn+1. The circuit configuration and operation of the scan driver 300 will be described in detail later.

[0048] The emission driver 350 receives the third driving control signal ECS from the driving controller 100. The emission driver 350 may output the emission control signal to the emission control lines EML1 to EMLn in response to the third driving control signal ECS. In another embodiment, the scan driver 300 may be connected to the emission control lines EML1 to EMLn. In this case, the scan driver 300 may output the emission control signal to the emission control lines EML1 to EMLn.

[0049] Each of the plurality of pixels PX includes a light emitting element ED (refer to Figure 2 ) and a pixel circuit unit PXC (reference Figure 2 ). The pixel circuit unit PXC may include a capacitor and a plurality of transistors. The scan driver 300 and the emission driver 350 may include transistors formed by the same process as the pixel circuit unit PXC.

[0050] Each of the plurality of pixels PX receives a first driving voltage ELVDD, a second driving voltage ELVSS, a first initialization voltage VINT, and a second initialization voltage AINT from the voltage generator 400 .

[0051] Figure 2 is a circuit diagram of an embodiment of a pixel according to the present disclosure, and Figure 3 is a timing diagram of an embodiment of a pixel according to the present disclosure.

[0052] Figure 2 The picture shows Figure 1 An equivalent circuit diagram of one pixel PXij among the plurality of pixels PX illustrated in FIG. 1 is shown as one of the embodiments. The plurality of pixels PX have the same structure, and therefore, additional description associated with the remaining pixels PX except the pixel PXij will be omitted to avoid redundancy.

[0053] refer to Figure 2, the pixel PXij is connected to the i-th data line (hereinafter also referred to as "data line") DLi among the data lines DL1 to DLm and the j-th emission control line (hereinafter also referred to as "emission control line") EMLj among the emission control lines EML1 to EMLn. In this article, i is an integer of 1 or greater and m or less, and j is an integer of 1 or greater and n or less. The pixel PXij is connected to the j-th initialization scan line (hereinafter also referred to as "initialization scan line") SILj among the initialization scan lines SIL1 to SILn, the j-th write scan line (hereinafter also referred to as "write scan line") SWLj among the write scan lines SWL1 to SWLn+1, and the j-th black scan line (hereinafter also referred to as "black scan line") SBLj. In addition, the pixel PXij is connected to the j-th compensation scan line (hereinafter also referred to as "compensation scan line") SCLj among the compensation scan lines SCL1 to SCLn. In an alternative embodiment, the pixel PXij may be connected to the j+1th writing scan line instead of the jth black scan line SBLj.

[0054] The pixel PXij includes a light emitting element ED and a pixel circuit unit PXC. The light emitting element ED may be a light emitting diode. The light emitting diode may include at least one of an organic light emitting material, an inorganic light emitting material, a quantum dot, a quantum rod, etc. as an emission layer.

[0055] The pixel circuit unit PXC includes first to seventh transistors T1, T2, T3, T4, T5, T6 and T7 and a single capacitor Cst. Each of the first to seventh transistors T1 to T7 may be a transistor including a low temperature polycrystalline silicon (LTPS) semiconductor layer. Some of the first to seventh transistors T1 to T7 may be P-type transistors, and the remaining transistors of the first to seventh transistors T1 to T7 may be N-type transistors. In an embodiment, among the first to seventh transistors T1 to T7, for example, the first transistor T1, the second transistor T2 and the fifth to seventh transistors T5 to T7 may be P-type transistors, and the third transistor T3 and the fourth transistor T4 may be N-type transistors using an oxide semiconductor as a semiconductor layer. However, the configuration of the pixel circuit unit PXC according to the present disclosure is not limited to Figure 2 The embodiment illustrated in FIG. Figure 2 The pixel circuit unit PXC illustrated in FIG. 1 is only one of the embodiments, and the configuration of the pixel circuit unit PXC may be modified and implemented. In the embodiment, for example, all of the first to seventh transistors T1 to T7 may be P-type transistors or N-type transistors.

[0056] The initialization scan line SILj, the compensation scan line SCLj, the write scan line SWLj, the black scan line SBLj and the emission control line EMLj can respectively transmit the jth initialization scan signal (hereinafter also referred to as the "initialization scan signal") SIj, the jth compensation scan signal (hereinafter also referred to as the "compensation scan signal") SCj, the jth write scan signal (hereinafter also referred to as the "write scan signal") SWj, the jth black scan signal (hereinafter also referred to as the "black scan signal") SBj and the jth emission control signal (hereinafter also referred to as the "emission control signal") EMj to the pixel PXij. The data line DLi transmits the data signal Di to the pixel PXij. The data signal Di may have the same value as that belonging to the input to the display device DD (reference Figure 1 ) The first to fourth driving voltage lines VL1, VL2, VL3, and VL4 may transmit the first driving voltage ELVDD, the second driving voltage ELVSS, the first initialization voltage VINT, and the second initialization voltage AINT to the pixel PXij, respectively.

[0057] The first transistor T1 includes a first electrode connected to the first driving voltage line VL1 through the fifth transistor T5, a second electrode electrically connected to the anode of the light emitting element ED through the sixth transistor T6, and a gate electrode connected to the first end of the capacitor Cst. The first transistor T1 may receive a data signal Di transmitted through the data line DLi depending on a switching operation of the second transistor T2, and may then supply a driving current Id to the light emitting element ED.

[0058] The second transistor T2 includes a first electrode connected to the data line DLi, a second electrode connected to the first electrode of the first transistor T1, and a gate electrode connected to the write scan line SWLj. The second transistor T2 may be turned on depending on a write scan signal SWj transmitted through the write scan line SWLj, and may then transmit a data signal Di from the data line DLi to the first electrode of the first transistor T1.

[0059] The third transistor T3 includes a first electrode connected to the second electrode of the first transistor T1, a second electrode connected to the gate electrode of the first transistor T1, and a gate electrode connected to the compensation scan line SCLj. The third transistor T3 may be turned on depending on the compensation scan signal SCj transmitted through the compensation scan line SCLj, and therefore, the gate electrode and the second electrode of the first transistor T1 may be connected to each other, that is, the first transistor T1 may be diode-connected.

[0060] The fourth transistor T4 includes a first electrode connected to the gate electrode of the first transistor T1, a second electrode connected to the third driving voltage line VL3 through which the first initialization voltage VINT is transmitted, and a gate electrode connected to the initialization scan line SILj. The fourth transistor T4 can be turned on depending on the initialization scan signal SIj transmitted through the initialization scan line SILj, and therefore, the first initialization voltage VINT can be transmitted to the gate electrode of the first transistor T1. In this way, the voltage of the gate electrode of the first transistor T1 can be initialized. This operation can also be referred to as an "initialization operation".

[0061] The fifth transistor T5 includes a first electrode connected to the first driving voltage line VL1, a second electrode connected to the first electrode of the first transistor T1, and a gate electrode connected to the emission control line EMLj.

[0062] The sixth transistor T6 includes a first electrode connected to the second electrode of the first transistor T1, a second electrode connected to the anode of the light emitting element ED, and a gate electrode connected to the emission control line EMLj.

[0063] The fifth transistor T5 and the sixth transistor T6 are simultaneously turned on in response to the emission control signal EMj transmitted through the emission control line EMLj. The first driving voltage ELVDD applied through the turned-on fifth transistor T5 may be transmitted to the light emitting element ED after being compensated by the diode-connected first transistor T1.

[0064] The seventh transistor T7 includes a first electrode connected to the second electrode of the sixth transistor T6, a second electrode connected to the fourth driving voltage line VL4 through which the second initialization voltage AINT is transmitted, and a gate electrode connected to the black scan line SBLj.

[0065] A first end of the capacitor Cst is connected to the gate electrode of the first transistor T1 as described above, and a second end of the capacitor Cst is connected to the first driving voltage line VL1. A cathode of the light emitting element ED may be connected to a second driving voltage line VL2 transmitting a second driving voltage ELVSS.

[0066] refer to Figure 2 and Figure 3 , display panel DP (reference Figure 1 ) can display an image during the driving frame DF.

[0067] A plurality of scan signals SIj, SCj, SWj, and SBj may be activated during a driving frame DF. In detail, the initialization scan signal SIj includes a first effective period AP1 having a relatively high level within the driving frame DF, and the compensation scan signal SCj includes a second effective period AP2 having a relatively high level within the driving frame DF. The write scan signal SWj includes a third effective period AP3 having a relatively low level within the driving frame DF, and the black scan signal SBj includes a fourth effective period AP4 having a relatively low level within the driving frame DF.

[0068] The emission control signal EMj may include a deactivated non-emission period NEP within the driving frame DF. In an embodiment of the present disclosure, the non-emission period NEP may be a high level period. The non-emission period NEP may overlap with the first to fourth effective periods AP1, AP2, AP3, and AP4.

[0069] When the initialization scan signal SIj of a relatively high level is supplied to the initialization scan line SILj during the first effective period AP1, the fourth transistor T4 is turned on in response to the initialization scan signal SIj of a relatively high level. The first initialization voltage VINT is transmitted to the gate electrode of the first transistor T1 through the turned-on fourth transistor T4, and the gate electrode of the first transistor T1 is initialized by the first initialization voltage VINT.

[0070] Next, when the compensation scan signal SCj of a relatively high level is supplied through the compensation scan line SCLj during the second effective period AP2, the third transistor T3 is turned on. During the second effective period AP2, the first transistor T1 is diode-connected through the turned-on third transistor T3 and is forward biased. The second effective period AP2 of the compensation scan signal SCj does not overlap with the first effective period AP1 of the initialization scan signal SIj. In addition, the first effective period AP1 of the initialization scan signal SIj may be before the second effective period AP2 of the compensation scan signal SCj.

[0071] In an embodiment of the present disclosure, the second effective period AP2 of the compensation scan signal SCj is defined as a period during which the compensation scan signal SCj has a relatively high level, and the first effective period AP1 of the initialization scan signal SIj is defined as a period during which the initialization scan signal SIj has a relatively high level. When each of the third transistor T3 and the fourth transistor T4 is a P-type transistor, the second effective period AP2 of the compensation scan signal SCj is defined as a period during which the compensation scan signal SCj has a relatively low level, and the first effective period AP1 of the initialization scan signal SIj is defined as a period during which the initialization scan signal SIj has a relatively low level.

[0072] The second effective period AP2 may overlap with a third effective period AP3 in which the write scan signal SWj has a relatively low level. During the third effective period AP3, the second transistor T2 is turned on by the write scan signal SWj of a relatively low level. Then, a compensation voltage "Di-Vth" obtained by subtracting the threshold voltage Vth of the first transistor T1 from the voltage of the data signal Di supplied by the data line DLi is applied to the gate electrode of the first transistor T1. That is, the potential of the gate electrode of the first transistor T1 may correspond to the compensation voltage "Di-Vth".

[0073] The first driving voltage ELVDD and the compensation voltage “Di−Vth” may be applied to opposite ends of the capacitor Cst, respectively, and charges corresponding to a voltage difference of the opposite ends of the capacitor Cst may be stored in the capacitor Cst.

[0074] Thereafter, during the fourth effective period AP4, the seventh transistor T7 is turned on by the relatively low level black scan signal SBj supplied through the black scan line SBLj. A portion of the driving current Id may flow out through the seventh transistor T7 as a bypass current Ibp.

[0075] Assuming that the pixel PXij displays a black image, when the light-emitting element ED emits light through the minimum driving current of the first transistor T1 as the driving current Id, the pixel PXij cannot display a black image normally. Therefore, the seventh transistor T7 of the pixel PXij in the embodiment of the present disclosure can flow a part of the minimum driving current of the first transistor T1 as a bypass current Ibp to a current path different from the current path to the light-emitting element ED. In this article, the minimum driving current of the first transistor T1 means the current flowing to the first transistor T1 under the condition that the gate-source voltage Vgs of the first transistor T1 is less than the threshold voltage Vth (that is, when the first transistor T1 is turned off). When the minimum driving current (for example, a current of 10 picoamperes (pA) or less) flowing to the first transistor T1 is transmitted to the light-emitting element ED under the condition that the first transistor T1 is turned off, an image of a black grayscale is displayed. In the case where the pixel PX displays a black image, the bypass current Ibp has a relatively large influence on the minimum driving current; on the contrary, in the case where the pixel PX displays an image such as a normal image or a white image, the bypass current Ibp has little influence on the driving current Id. Therefore, when the pixel PXij displays a black image, a current corresponding to the result of subtracting the bypass current Ibp flowing through the seventh transistor T7 from the driving current Id (i.e., the emission current Ied) can be provided to the light emitting element ED, and thus, a black image can be clearly displayed. Therefore, the pixel PXij can realize an accurate black grayscale image through the seventh transistor T7, and thus, the contrast can be improved.

[0076] Next, the emission control signal EMj supplied from the emission control line EMLj changes from a relatively high level to a relatively low level. The fifth transistor T5 and the sixth transistor T6 are turned on by the emission control signal EMj of a relatively low level. In this case, the drive current Id is generated depending on the difference between the gate voltage of the gate electrode of the first transistor T1 and the first drive voltage ELVDD, and is supplied to the light emitting element ED through the sixth transistor T6. That is, the emission current Ied flows through the light emitting element ED.

[0077] Figure 4A is a block diagram of an embodiment of a scan driver according to the present disclosure, and Figure 4B yes Figure 4A 0 is a block diagram of a first scan driving circuit illustrated in FIG.

[0078] refer to Figure 4A , the scan driver 300 includes a first scan drive circuit 310 and a second scan drive circuit 320. The first drive control signal SCS includes a first scan control signal SCS1 received by the first scan drive circuit 310 from the drive controller 100 and a second scan control signal SCS2 received by the second scan drive circuit 320 from the drive controller 100. The first scan drive circuit 310 may output a scan signal to the scan line in response to the first scan control signal SCS1, and the second scan drive circuit 320 may output a scan signal to the scan line in response to the second scan control signal SCS2. In an embodiment, Figure 4A 2 , a configuration in which the scan driver 300 includes two scan driving circuits 310 and 320 is illustrated, but the number of scan driving circuits included in the scan driver 300 is not limited thereto.

[0079] In response to the first scan control signal SCS1, the first scan driving circuit 310 may output the initialization scan signal to the initialization scan lines SIL1 to SILn, and may output the compensation scan signal to the compensation scan lines SCL1 to SCLn. The second scan driving circuit 320 may output the write scan signal to the write scan lines SWL1 to SWLn+1 in response to the second scan control signal SCS2. Figure 4B The first scan driving circuit 310 is illustrated in FIG. 1 as one of the embodiments.

[0080] refer to Figure 4B , the first scan driving circuit 310 may include a plurality of stages ST1 to STn+1 sequentially connected to each other. The stages ST1 to STn+1 may have substantially the same circuit configuration as each other. For ease of description, Figure 4B1, four stages ST1, ST2, STn and STn+1 are illustrated as one of the embodiments. Some of the stages ST1 to STn+1 are connected to the initialization scan lines SIL1 to SILn, respectively. Some of the stages ST2 to STn+1 are connected to the compensation scan lines SCL1 to SCLn, respectively.

[0081] The second scanning driving circuit 320 (refer to Figure 4A ) may be similar to the configuration of the first scan driving circuit 310. That is, the second scan driving circuit 320 may include a plurality of stages ST1 to STn+1 sequentially connected to each other, and the plurality of stages ST1 to STn+1 may be connected to the write scan lines SWL1 to SWLn+1, respectively (refer to Figure 4A ).

[0082] Each of the stages ST1 to STn+1 may include an input terminal IN, a clock terminal CKT, a first voltage terminal VT1 , a second voltage terminal VT2 , and an output terminal OUT.

[0083] The output terminal OUT may output a scan signal. The scan signal may be an initialization scan signal or a compensation scan signal. The input terminal IN may receive a scan signal (hereinafter also referred to as a "previous carry signal") output from the output terminal OUT of the previous stage, or may receive a start signal FLM. The start signal FLM may be input to the input terminal IN of the first stage ST1. The input terminal IN of the second stage ST2 may receive the first scan signal output from the output terminal OUT of the first stage ST1 as a previous carry signal.

[0084] Each of the stages ST1 to STn+1 may receive a clock signal CLK through a clock terminal CKT. The clock signal CLK may refer to a clock signal in a driving frame DF (reference Figure 3 ) during each given period (e.g., horizontal scanning period 1H (reference Fig. 6A ))Swinging signal.

[0085] The first voltage terminal VT1 may be a terminal supplied with a low voltage VGL (or a first voltage), and the second voltage terminal VT2 may be a terminal supplied with a high voltage VGH (or a second voltage). Each of the low voltage VGL and the high voltage VGH may have a direct current (DC) voltage level. The high voltage VGH may be used as a relatively high level (i.e., a gate-on voltage) of a scan signal, and the low voltage VGL may be used as a relatively low level (i.e., a gate-off voltage) of a scan signal. The voltage level of the low voltage VGL may be lower than the voltage level of the high voltage VGH.

[0086] The first voltage terminals VT1 of the stages ST1 to STn+1 may be connected to one another, and the second voltage terminals VT2 of the stages ST1 to STn+1 may be connected to one another.

[0087] Next, we will refer to Figure 5 A circuit configuration of the first stage ST1 among the stages ST1 to STn+1 is described. Because the stages ST1 to STn+1 have the same circuit configuration as one another, additional description associated with the circuit configurations of the remaining stages ST2 to STn+1 will be omitted to avoid redundancy.

[0088] Figure 5 yes Figure 4B The circuit diagram of the first stage is shown in FIG. Fig. 6A Is used to describe Figure 5 0047 is a waveform diagram of the operation of the first stage illustrated in FIG. Figure 6B is a waveform diagram for describing an embodiment of the operation of the first stage according to the present disclosure.

[0089] refer to Figure 5 , the first stage ST1 may include a first output transistor OT1 and a second output transistor OT2. The first output transistor OT1 and the second output transistor OT2 are connected to the output terminal OUT. The first output transistor OT1 is connected between the output terminal OUT and the first voltage terminal VT1, and operates in response to the potential of the first node Q1. The first output transistor OT1 includes a first electrode connected to the output terminal OUT, a second electrode connected to the first voltage terminal VT1, and a third electrode connected to the first node Q1. The second output transistor OT2 is connected between the second voltage terminal VT2 and the output terminal OUT, and operates in response to the potential of the second node QB. The second output transistor OT2 includes a first electrode connected to the second voltage terminal VT2, a second electrode connected to the output terminal OUT, and a third electrode connected to the second node QB. In an embodiment of the present disclosure, each of the first output transistor OT1 and the second output transistor OT2 may include an LTPS semiconductor layer and may be implemented with a first type (or P-type) transistor.

[0090] The first stage ST1 further includes a first control transistor to a fourth control transistor CT1, CT2, CT3 and CT4. The first control transistor CT1 is connected between an input terminal IN receiving a start signal FLM or a previous carry signal from a previous stage and a third node Q2, and operates in response to a clock signal CLK provided by a clock terminal CKT. The first control transistor CT1 includes a first electrode connected to the third node Q2, a second electrode connected to the input terminal IN, and a third electrode connected to the clock terminal CKT. The second control transistor CT2 is connected between the second node QB and the first voltage terminal VT1 and connected to the input terminal IN, and operates in response to a start signal FLM or a previous carry signal provided by the input terminal IN. The second control transistor CT2 includes a first electrode connected to the second node QB, a second electrode connected to the first voltage terminal VT1, and a third electrode connected to the input terminal IN. In an embodiment of the present disclosure, the first control transistor CT1 may include an LTPS semiconductor layer, and may be implemented with a first type (or P-type) transistor. The second control transistor CT2 may include an oxide semiconductor layer, and may be implemented with a second type (or N-type) transistor.

[0091] The third control transistor CT3 is connected between the third node Q2 and the first node Q1, and operates in response to the low voltage VGL provided by the first voltage terminal VT1. The third control transistor CT3 includes a first electrode connected to the third node Q2, a second electrode connected to the first node Q1, and a third electrode connected to the first voltage terminal VT1. The fourth control transistor CT4 is connected between the second node QB and the second voltage terminal VT2, and operates in response to the potential of the third node Q2. The fourth control transistor CT4 includes a first electrode connected to the second voltage terminal VT2, a second electrode connected to the second node QB, and a third electrode connected to the third node Q2. In an embodiment of the present disclosure, each of the third output transistor CT3 and the fourth output transistor CT4 may include an LTPS semiconductor layer and may be implemented with a first type (or P-type) transistor.

[0092] The second control transistor CT2 may be of the same type as Figure 2 The third transistor T3 and the fourth transistor T4 shown in the figure are transistors of the same type, and each of the first output transistor OT1 and the second output transistor OT2 and the first control transistor CT1, the third control transistor CT3 and the fourth control transistor CT4 can be a transistor whose type is different from the third transistor T3 and the fourth transistor T4.

[0093] The first stage ST1 further includes a first capacitor C1 connected between the output terminal OUT and the first node Q1 and a second capacitor C2 connected between the second node QB and the second voltage terminal VT2. A potential difference between the first electrode and the third electrode of the first output transistor OT1 may be maintained at a threshold voltage or more by the first capacitor C1.

[0094] refer to Figure 4B , Figure 5 and Fig. 6A , in a period (i.e., a high period) in which the start signal FLM is at a relatively high level, the second control transistor CT2 is turned on. In the high period of the start signal FLM, the second control transistor CT2 can be maintained in a turned-on state. The high period of the start signal FLM can be maintained during a time period 3H corresponding to three times the horizontal scanning period 1H.

[0095] Afterwards, in the period in which the clock signal CLK is at a relatively low level, the first control transistor CT1 is turned on. As the first control transistor CT1 is turned on, the potential of the third node Q2 increases to a relatively high level along the voltage level of the start signal FLM. When the potential of the third node Q2 increases to a relatively high level, the potential of the first node Q1 is also increased to a relatively high level through the third control transistor CT3 in the on state. Even if the clock signal CLK is converted to a relatively high level during the high period of the start signal FLM, the potentials of the first node Q1 and the third node Q2 can also be maintained at a relatively high level. When the potentials of the first node Q1 and the third node Q2 have a relatively high level, the first output transistor OT1 is turned off.

[0096] When the potential of the third node Q2 increases to a relatively high level, the fourth control transistor CT4 may be turned off. As the fourth control transistor CT4 is turned off, the potential of the second node QB may be lowered to the low voltage VGL through the on-state second control transistor CT2.

[0097] When the potential of the second node QB has a relatively low level due to the low voltage VGL, the second output transistor OT2 is turned on. The high voltage VGH can be output to the output terminal OUT through the second output transistor OT2 thus turned on. Therefore, the first initialization scan signal SI1 can be activated to a relatively high level during the low period of the second node QB. The high period of the first initialization scan signal SI1 can also be referred to as a "first effective period AP1". In an embodiment of the present disclosure, the first effective period AP1 of the first initialization scan signal SI1 can have a duration of 3H corresponding to three times the period 1H of the clock signal CLK.

[0098] When the start signal FLM is changed to a relatively low level, from the period in which the clock signal CLK is at a relatively low level (or from the time point when the clock signal CLK is changed from a relatively high level to a relatively low level), the first node Q1 and the third node Q2 can be maintained at a relatively low level. When the potential of the third node Q2 is reduced to a relatively low level, the fourth control transistor CT4 can be turned on. As the fourth control transistor CT4 is turned on, the potential of the second node QB can be increased to a high voltage VGH. The second output transistor OT2 is turned off in response to the potential of the high state of the second node QB, and the first output transistor OT1 is turned on in response to the potential of the low state of the first node Q1. The low voltage VGL can be output to the output terminal OUT through the first output transistor OT1 that is turned on. Therefore, the first initialization scan signal SI1 can be deactivated to a relatively low level during the high period of the second node QB. The low period of the first initialization scan signal SI1 can also be referred to as an "invalid period".

[0099] When the low voltage VGL is output to the output terminal OUT, the potential of the first node Q1 may become lower than the low voltage VGL by coupling of the first capacitor C1. Therefore, when the potential of the first node Q1 is lower than the low voltage VGL, the output characteristics of the first output transistor OT1 may be enhanced, and thus, the first initialization scan signal SI1 may have a stable low state.

[0100] refer to Figure 5 and Figure 6B In the period in which the start signal FLMa is at a relatively low level (i.e., a relatively low period), the second control transistor CT2 is turned off. In the low period of the start signal FLMa, the second control transistor CT2 can be maintained in the off state. The low period of the start signal FLMa can be maintained during one horizontal scanning period 1H.

[0101] Afterwards, in the period in which the clock signal CLK is at a relatively low level, the first control transistor CT1 is turned on. As the first control transistor CT1 is turned on, the potential of the third node Q2 is reduced to a relatively low level along the voltage level of the start signal FLMa. When the potential of the third node Q2 is reduced to a relatively low level, the potential of the first node Q1 is also reduced to a relatively low level by the third control transistor CT3 in the on state. When the potentials of the first node Q1 and the third node Q2 have a relatively low level, the first output transistor OT1 is turned on. The low voltage VGL can be output to the output terminal OUT through the first output transistor OT1 that is turned on. Therefore, the first write scan signal SW1 can be activated to a relatively low level during the low period of the first node Q1. The low period of the first write scan signal SW1 can also be referred to as the "third effective period AP3". In an embodiment of the present disclosure, the third effective period AP3 of the first write scan signal SW1 can have a duration corresponding to a period of the clock signal CLK.

[0102] When the potential of the third node Q2 decreases to a relatively low level, the fourth control transistor CT4 may be turned on. As the fourth control transistor CT4 is turned on, the potential of the second node QB may increase to a high voltage VGH through the on-state fourth control transistor CT4.

[0103] When the potential of the second node QB has a relatively high level due to the high voltage VGH, the second output transistor OT2 is turned off.

[0104] When the start signal FLMa is changed to a relatively high level, starting from the period in which the clock signal CLK is at a relatively low level (or starting from the time point when the clock signal CLK changes from a relatively high level to a relatively low level), the first node Q1 and the third node Q2 can be maintained at a relatively high level. When the potential of the third node Q2 increases to a relatively high level, the fourth control transistor CT4 can be turned off. As the fourth control transistor CT4 is turned off, the potential of the second node QB can be reduced to a low voltage VGL. The second output transistor OT2 is turned on in response to the potential of the low state of the second node QB, and the first output transistor OT1 is turned off in response to the potential of the high state of the first node Q1. The high voltage VGH can be output to the output terminal OUT through the second output transistor OT2 that is turned on. Therefore, the first write scan signal SW1 can be deactivated to a relatively high level during the low period of the second node QB. The high period of the first write scan signal SW1 can also be referred to as an "invalid period".

[0105] Each of the stages ST1 to STn+1 includes P-type control transistors CT1, CT3, and CT4 and an N-type control transistor CT2. Therefore, the circuit configuration of each of the stages ST1 to STn+1 can be simplified, and therefore, the width of the non-active area NAA of the display device DD can be prevented from increasing. In addition, the number of signals (e.g., clock signals CLK) input to each of the stages ST1 to STn+1 can be reduced, and therefore, the power consumption of the display device DD can be reduced.

[0106] Figure 7 yes Figure 4B The circuit diagram of the first stage is shown in FIG. Figure 8 Is used to describe Figure 7 0047 is a waveform diagram of the operation of the first stage illustrated in FIG. Figure 7 Among the components shown in the figure, Figure 5 The same components as those illustrated in FIG. 8 are marked by the same reference numerals / reference numerals, and thus, additional description will be omitted to avoid redundancy.

[0107] refer to Figure 7 , the first stage ST1a includes first and second output transistors OT1 and OT2, a first control transistor CT1, a second control transistor CT2a, a third control transistor CT3, a fourth control transistor CT4, and first and second capacitors C1 and C2.

[0108] The second control transistor CT2a is connected between the second node QB and the first voltage terminal VT1, and operates in response to the potential of the third node Q2. The second control transistor CT2a includes a first electrode connected to the second node QB, a second electrode connected to the first voltage terminal VT1, and a third electrode connected to the third node Q2. The fourth control transistor CT4 includes a first electrode connected to the second voltage terminal VT2, a second electrode connected to the second node QB, and a third electrode connected to the third node Q2. The third electrode of the second control transistor CT2a and the third electrode of the fourth control transistor CT4 can be commonly connected to the third node Q2. In an embodiment of the present disclosure, the fourth control transistor CT4 may include an LTPS semiconductor layer and may be implemented with a first type (or P-type) transistor. The second control transistor CT2a may include an oxide semiconductor layer and may be implemented with a second type (or N-type) transistor. Therefore, the second control transistor CT2a and the fourth control transistor CT4 may be alternately turned on in response to the potential of the third node Q2.

[0109] refer to Figure 7 and Figure 8, in the period (i.e., high period) in which the start signal FLM is at a relatively high level, when the clock signal CLK is changed to a relatively low level, the first control transistor CT1 is turned on. As the first control transistor CT1 is turned on, the potential of the third node Q2 increases to a relatively high level along the voltage level of the start signal FLM. When the potential of the third node Q2 increases to a relatively high level, the potential of the first node Q1 is also increased to a relatively high level by the third control transistor CT3 in the on state. Even if the clock signal CLK is changed to a relatively high level during the high period of the start signal FLM, the potentials of the first node Q1 and the third node Q2 can also be maintained at a relatively high level. When the potentials of the first node Q1 and the third node Q2 have a relatively high level, the first output transistor OT1 is turned off.

[0110] When the potential of the third node Q2 increases to a relatively high level, the fourth control transistor CT4 is turned off and the second control transistor CT2a is turned on. As the fourth control transistor CT4 is turned off, the potential of the second node QB can be reduced to a low voltage VGL through the turned-on second control transistor CT2a.

[0111] When the potential of the second node QB has a relatively low level due to the low voltage VGL, the second output transistor OT2 is turned on. The high voltage VGH can be output to the output terminal OUT through the second output transistor OT2 thus turned on. Therefore, the first initialization scan signal SI1 can be activated to a relatively high level during the low period of the second node QB. The high period of the first initialization scan signal SI1 can also be referred to as a "first effective period AP1".

[0112] When the start signal FLM is changed to a relatively low level, starting from a period in which the clock signal CLK is at a relatively low level (or starting from a time point when the clock signal CLK is changed from a relatively high level to a relatively low level), the first node Q1 and the third node Q2 can be maintained at a relatively low level. When the potential of the third node Q2 is reduced to a relatively low level, the fourth control transistor CT4 is turned on, and the second control transistor CT2a is turned off. As the fourth control transistor CT4 is turned on, the potential of the second node QB can be increased to a high voltage VGH. The second output transistor OT2 is turned off in response to the potential of the high state of the second node QB, and the first output transistor OT1 is turned on in response to the potential of the low state of the first node Q1. The low voltage VGL can be output to the output terminal OUT through the first output transistor OT1 that is turned on. Therefore, the first initialization scan signal SI1 can be deactivated to a relatively low level during the high period of the second node QB. The low period of the first initialization scan signal SI1 can also be referred to as an "invalid period".

[0113] Fig. 9 is a circuit diagram of an embodiment of a first scan driving circuit according to the present disclosure. Fig. 9 Among the components shown in the figure, Figure 4B The same components as those illustrated in FIG. 8 are marked by the same reference numerals / reference numerals, and thus, additional description will be omitted to avoid redundancy.

[0114] refer to Fig. 9 , the first scan driving circuit 310a may include a plurality of stages ST1c to STn+1c sequentially connected to each other. The stages ST1c to STn+1c may have substantially the same circuit configuration as each other. For ease of description, Fig. 9 1 and 2 are shown in FIG. 4 as one of the embodiments. Some of the stages ST1c to STnc among the plurality of stages ST1c to STn+1c are connected to the initialization scan lines SIL1 to SILn, respectively. Some of the stages ST2c to STn+1c among the plurality of stages ST1c to STn+1c are connected to the compensation scan lines SCL1 to SCLn, respectively.

[0115] Each of the stages ST1 c to STn+1 c may include an input terminal IN, a clock terminal CKT, first and second voltage terminals VT1 and VT2 , an output terminal OUT, and a carry terminal CR.

[0116] The output terminal OUT may output a scan signal. The scan signal may be an initialization scan signal or a compensation scan signal. The input terminal IN may receive a scan signal output from a carry terminal CR of a previous stage (hereinafter also referred to as a "previous carry signal"), or may receive a start signal FLM. The start signal FLM may be input to the input terminal IN of the first stage ST1c. The input terminal IN of the second stage ST2c may receive the first scan signal output from the carry terminal CR of the first stage ST1c as a previous carry signal.

[0117] The carry terminal CR may output a carry signal. The phase and amplitude of the carry signal may be substantially the same as the phase and amplitude of the scan signal output through the output terminal OUT. The carry terminal CR may be connected to the input terminal IN of the next stage. Therefore, the carry signal output through the carry terminal CR may be supplied to the input terminal IN of the next stage as the previous carry signal.

[0118] Fig. 10A and Fig. 10B yes Fig. 9 The circuit diagram of the first stage is shown in FIG. Fig. 10A and 10B Among the components shown in FIG. Figure 5, and thus, additional description will be omitted to avoid redundancy.

[0119] refer to Fig. 10A The first stage ST1c includes first and second output transistors OT1 and OT2, first to fourth control transistors CT1 to CT4, and first and second capacitors C1 and C2. The first stage ST1c further includes first and second carry transistors IT1 and IT2.

[0120] The first carry transistor IT1 and the second carry transistor IT2 are connected to the carry terminal CR. The first carry transistor IT1 is connected between the carry terminal CR and the first voltage terminal VT1, and operates depending on the potential of the first node Q1. The first carry transistor IT1 includes a first electrode connected to the carry terminal CR, a second electrode connected to the first voltage terminal VT1, and a third electrode connected to the first node Q1. The second carry transistor IT2 is connected between the carry terminal CR and the second voltage terminal VT2, and operates depending on the potential of the first node Q1. The second carry transistor IT2 includes a first electrode connected to the second voltage terminal VT2, a second electrode connected to the carry terminal CR, and a third electrode connected to the first node Q1.

[0121] In an embodiment of the present disclosure, each of the first control transistor CT1, the third control transistor CT3, the fourth control transistor CT4, the first output transistor OT1, the second output transistor OT2, and the first carry transistor IT1 may include an LTPS semiconductor layer and may be implemented with a first type (or P-type) transistor. Each of the second control transistor CT2 and the second carry transistor IT2 may include an oxide semiconductor layer and may be implemented with a second type (or N-type) transistor.

[0122] When the potential of the first node Q1 is at a relatively high level, the first carry transistor IT1 may be turned off, and the second carry transistor IT2 may be turned on. Therefore, the high voltage VGH may be output to the carry terminal CR through the second carry transistor IT2 thus turned on. When the potential of the first node Q1 changes to a relatively low level, the first carry transistor IT1 is turned on, and the second carry transistor IT2 is turned off. Therefore, the low voltage VGL may be output to the carry terminal CR through the first carry transistor IT1 thus turned on.

[0123] The first carry transistor IT1 and the first output transistor OT1 can be turned on at the same time and can be turned off at the same time. In addition, the second carry transistor IT2 and the second output transistor OT2 can be turned on at the same time and can be turned off at the same time. Therefore, the phase and amplitude of the carry signal output through the carry terminal CR can be the same as the phase and amplitude of the scan signal.

[0124] refer to Fig. 10B , the first stage ST1c_1 includes first and second output transistors OT1 and OT2, first to fourth control transistors CT1 to CT4, and first and second capacitors C1 and C2.

[0125] The first stage ST1 c_1 further includes a first carry transistor IT1 a and a second carry transistor IT2 a .

[0126] The first carry transistor IT1a and the second carry transistor IT2a are connected to the carry terminal CR. The first carry transistor IT1a is connected between the carry terminal CR and the first voltage terminal VT1, and operates depending on the potential of the second node QB. The first carry transistor IT1a includes a first electrode connected to the carry terminal CR, a second electrode connected to the first voltage terminal VT1, and a third electrode connected to the second node QB. The second carry transistor IT2a is connected between the carry terminal CR and the second voltage terminal VT2, and operates depending on the potential of the second node QB. The second carry transistor IT2a includes a first electrode connected to the second voltage terminal VT2, a second electrode connected to the carry terminal CR, and a third electrode connected to the second node QB.

[0127] In the embodiment of the present disclosure, each of the first control transistor CT1, the third control transistor CT3 and the fourth control transistor CT4, the first output transistor OT1 and the second output transistor OT2, and the second carry transistor IT2a may include an LTPS semiconductor layer and may be implemented with a first type (or P-type) transistor. Each of the second control transistor CT2 and the first carry transistor IT1a may include an oxide semiconductor layer and may be implemented with a second type (or N-type) transistor.

[0128] When the potential of the second node QB is at a relatively low level, the first carry transistor IT1a may be turned off, and the second carry transistor IT2a may be turned on. Therefore, the high voltage VGH may be output to the carry terminal CR through the second carry transistor IT2a thus turned on. When the potential of the second node QB changes to a relatively high level, the first carry transistor IT1a is turned on, and the second carry transistor IT2a is turned off. Therefore, the low voltage VGL may be output to the carry terminal CR through the first carry transistor IT1a thus turned on.

[0129] The first carry transistor IT1a and the first output transistor OT1 can be turned on at the same time and can be turned off at the same time. In addition, the second carry transistor IT2a and the second output transistor OT2 can be turned on at the same time and can be turned off at the same time. Therefore, the phase and amplitude of the carry signal output through the carry terminal CR can be the same as the phase and amplitude of the scan signal.

[0130] Fig.11A and Fig. 11B yes Fig. 9 The circuit diagram of the first stage is shown in FIG. Fig.11A and Fig. 11B Among the components shown in FIG. Figure 7 , and thus, additional description will be omitted to avoid redundancy.

[0131] refer to Fig.11A The first stage ST1d includes first and second output transistors OT1 and OT2, first to fourth control transistors CT1, CT2a, CT3 and CT4, and first and second capacitors C1 and C2. The first stage ST1d further includes first and second carry transistors IT1 and IT2.

[0132] The first carry transistor IT1 and the second carry transistor IT2 are connected to the carry terminal CR. The first carry transistor IT1 is connected between the carry terminal CR and the first voltage terminal VT1, and operates depending on the potential of the first node Q1. The first carry transistor IT1 includes a first electrode connected to the carry terminal CR, a second electrode connected to the first voltage terminal VT1, and a third electrode connected to the first node Q1. The second carry transistor IT2 is connected between the carry terminal CR and the second voltage terminal VT2, and operates depending on the potential of the first node Q1. The second carry transistor IT2 includes a first electrode connected to the second voltage terminal VT2, a second electrode connected to the carry terminal CR, and a third electrode connected to the first node Q1.

[0133] In the embodiment of the present disclosure, each of the first control transistor CT1, the third control transistor CT3, the fourth control transistor CT4, the first output transistor OT1, the second output transistor OT2, and the first carry transistor IT1 may include an LTPS semiconductor layer and may be implemented with a first type (or P-type) transistor. Each of the second control transistor CT2a and the second carry transistor IT2 may include an oxide semiconductor layer and may be implemented with a second type (or N-type) transistor.

[0134] When the potential of the first node Q1 is at a relatively high level, the first carry transistor IT1 may be turned off, and the second carry transistor IT2 may be turned on. Therefore, the high voltage VGH may be output to the carry terminal CR through the second carry transistor IT2 thus turned on. When the potential of the first node Q1 changes to a relatively low level, the first carry transistor IT1 is turned on, and the second carry transistor IT2 is turned off. Therefore, the low voltage VGL may be output to the carry terminal CR through the first carry transistor IT1 thus turned on.

[0135] The first carry transistor IT1 and the first output transistor OT1 can be turned on at the same time and can be turned off at the same time. In addition, the second carry transistor IT2 and the second output transistor OT2 can be turned on at the same time and can be turned off at the same time. Therefore, the phase and amplitude of the carry signal output through the carry terminal CR can be the same as the phase and amplitude of the scan signal.

[0136] refer to Fig. 11B The first stage ST1d_1 includes first and second output transistors OT1 and OT2, first to fourth control transistors CT1, CT2a, CT3 and CT4, and first and second capacitors C1 and C2. The first stage ST1d_1 further includes first and second carry transistors IT1a and IT2a.

[0137] The first carry transistor IT1a and the second carry transistor IT2a are connected to the carry terminal CR. The first carry transistor IT1a is connected between the carry terminal CR and the first voltage terminal VT1, and operates depending on the potential of the second node QB. The first carry transistor IT1a includes a first electrode connected to the carry terminal CR, a second electrode connected to the first voltage terminal VT1, and a third electrode connected to the second node QB. The second carry transistor IT2a is connected between the carry terminal CR and the second voltage terminal VT2, and operates depending on the potential of the second node QB. The second carry transistor IT2a includes a first electrode connected to the second voltage terminal VT2, a second electrode connected to the carry terminal CR, and a third electrode connected to the second node QB.

[0138] In an embodiment of the present disclosure, each of the first control transistor CT1, the third control transistor CT3, and the fourth control transistor CT4, the first output transistor OT1 and the second output transistor OT2, and the second carry transistor IT2a may include an LTPS semiconductor layer and may be implemented with a first type (or P-type) transistor. Each of the second control transistor CT2a and the first carry transistor IT1a may include an oxide semiconductor layer and may be implemented with a second type (or N-type) transistor.

[0139] When the potential of the second node QB is at a relatively low level, the first carry transistor IT1a may be turned off, and the second carry transistor IT2a may be turned on. Therefore, the high voltage VGH may be output to the carry terminal CR through the second carry transistor IT2a thus turned on. When the potential of the second node QB changes to a relatively high level, the first carry transistor IT1a is turned on, and the second carry transistor IT2a is turned off. Therefore, the low voltage VGL may be output to the carry terminal CR through the first carry transistor IT1a thus turned on.

[0140] The first carry transistor IT1a and the first output transistor OT1 can be turned on at the same time and can be turned off at the same time. In addition, the second carry transistor IT2a and the second output transistor OT2 can be turned on at the same time and can be turned off at the same time. Therefore, the phase and amplitude of the carry signal output through the carry terminal CR can be the same as the phase and amplitude of the scan signal.

[0141] Fig.12 yes Figure 4A 0 is a block diagram of a first scan driving circuit illustrated in FIG. Fig.12 Among the components shown in the figure, Figure 4B The same components as those illustrated in FIG. 8 are marked by the same reference numerals / reference numerals, and thus, additional description will be omitted to avoid redundancy.

[0142] refer to Fig.12 , the first scan driving circuit 310b may include a plurality of stages ST1e to STn+1e connected sequentially to each other. The stages ST1e to STn+1e may have substantially the same circuit configuration as each other. For ease of description, Fig.12 Four stages ST1e, ST2e, STne, and STn+1e are illustrated in FIG. 1 as one of the embodiments.

[0143] Each of the stages ST1e to STn+1e may include an input terminal IN, a clock terminal CKT, a first voltage terminal VT1, a second voltage terminal VT2, and an output terminal OUT.

[0144] The output terminal OUT may output a scan signal. The scan signal may be an initialization scan signal or a compensation scan signal. The input terminal IN may receive a scan signal (hereinafter also referred to as a "previous carry signal") output from the output terminal OUT of the previous stage, or may receive a start signal FLMb. The start signal FLMb may be input to the input terminal IN of the first stage ST1e. The input terminal IN of the second stage ST2e may receive the first scan signal output from the output terminal OUT of the first stage ST1e as a previous carry signal.

[0145] Each of the stages ST1e to STn+1e can receive the first clock signal CLK or the second clock signal CLKB through the clock terminal CKT. The first clock signal CLK may refer to the first clock signal CLK in the driving frame DF (reference Figure 3 ) during each given period (e.g., with the horizontal scanning period 1H (reference Fig. 6A ) three times of the time period corresponding to 3H (i.e., 3H). The time period of the second clock signal CLKB may be the same as the time period of the first clock signal CLK, and the phase of the second clock signal CLKB may be different from the phase of the first clock signal CLK. The second clock signal CLKB may refer to a signal that swings in each time period corresponding to 3H.

[0146] The first clock signal CLK may include a clock active period C1_AP (reference Fig.14A ), and the second clock signal CLKB may include a clock effective period C2_AP (reference Fig.14A ). The clock active period C1_AP of the first clock signal CLK may have the same duration as that of the clock active period C2_AP of the second clock signal CLKB.

[0147] In an embodiment of the present disclosure, the first clock signal CLK may be applied to the clock terminal CKT of each of the odd stages ST1e and STne among the stages ST1e to STn+1e, and the second clock signal CLKB may be applied to the clock terminal CKT of each of the even stages ST2e and STn+1e among the stages ST1e to STn+1e.

[0148] Next, we will refer to Fig.13A and Fig. 13B A circuit configuration of the first stage ST1e among the stages ST1e to STn+1e is described. Because the stages ST1e to STn+1e have the same circuit configuration as each other, additional description associated with the circuit configurations of the remaining stages ST2e to STn+1e will be omitted to avoid redundancy.

[0149] Fig.13A and Fig. 13B yes Fig.12 The circuit diagram of the first stage is shown in FIG. Fig.14A Is used to describe Fig.13A 0047 is a waveform diagram of the operation of the first stage illustrated in FIG. Fig. 14B Is used to describe Fig.13A 0 is a waveform diagram of the operation of the second control transistor shown in . Fig.13A , Fig. 13B and Fig.14A Among the components shown in the figure, Figure 5 and Fig. 6AThe same components as those illustrated in FIG. 8 are marked with the same reference numerals, and thus, additional description will be omitted to avoid redundancy.

[0150] refer to Fig.13A The first stage ST1e includes first and second output transistors OT1 and OT2, a first control transistor CT1, a second control transistor CT2c, a third control transistor CT3, a fourth control transistor CT4, and first and second capacitors C1 and C2.

[0151] The second control transistor CT2c is connected between the second node QB and the first voltage terminal VT1, and operates in response to the potential of the third node Q2. The second control transistor CT2c includes a first electrode connected to the second node QB, a second electrode connected to the first voltage terminal VT1, and a third electrode connected to the third node Q2. The second control transistor CT2c further includes a bottom gate electrode BGE connected to the first node Q1.

[0152] The fourth control transistor CT4 includes a first electrode connected to the second voltage terminal VT2, a second electrode connected to the second node QB, and a third electrode connected to the third node Q2. The third electrode of the second control transistor CT2c and the third electrode of the fourth control transistor CT4 can be commonly connected to the third node Q2. In an embodiment of the present disclosure, the fourth control transistor CT4 may include an LTPS semiconductor layer and may be implemented with a first type (or P-type) transistor. The second control transistor CT2c may include an oxide semiconductor layer and may be implemented with a second type (or N-type) transistor. Therefore, the second control transistor CT2c and the fourth control transistor CT4 may be alternately turned on in response to the potential of the third node Q2.

[0153] refer to Figure 4B , Fig.13A and Fig.14A In the period (i.e., high period) in which the start signal FLMb is at a relatively high level, the second control transistor CT2c is turned on. In the high period of the start signal FLMb, the second control transistor CT2c can be maintained in the on state. The high period of the start signal FLMb can be maintained during the three horizontal scanning periods 3H.

[0154] Afterwards, in the period in which the first clock signal CLK is at a relatively low level, the first control transistor CT1 is turned on. As the first control transistor CT1 is turned on, the potential of the third node Q2 increases to a relatively high level along the voltage level of the start signal FLMb. When the potential of the third node Q2 increases to a relatively high level, the potential of the first node Q1 is also increased to a relatively high level through the third control transistor CT3 in the on state. Even if the first clock signal CLK is converted to a relatively high level during the high period of the start signal FLMb, the potentials of the first node Q1 and the third node Q2 can also be maintained at a relatively high level. When the potentials of the first node Q1 and the third node Q2 have a relatively high level, the first output transistor OT1 is turned off.

[0155] When the potential of the third node Q2 increases to a relatively high level, the fourth control transistor CT4 may be turned off. As the fourth control transistor CT4 is turned off, the potential of the second node QB may be lowered to the low voltage VGL through the on-state second control transistor CT2c.

[0156] When the potential of the second node QB has a relatively low level due to the low voltage VGL, the second output transistor OT2 is turned on. The high voltage VGH can be output to the output terminal OUT through the second output transistor OT2 that is turned on. Therefore, the first initialization scan signal SI1 can be activated to a relatively high level during the low period of the second node QB. The high period of the first initialization scan signal SI1 can also be referred to as a "first effective period AP1". In an embodiment of the present disclosure, the first effective period AP1 of the first initialization scan signal SI1 can have a duration corresponding to one period of the first clock signal CLK (i.e., corresponding to 3H).

[0157] When the start signal FLMb is changed to a relatively low level, starting from a period in which the first clock signal CLK is at a relatively low level (or starting from a time point when the first clock signal CLK is changed from a relatively high level to a relatively low level), the first node Q1 and the third node Q2 may be maintained at a relatively low level. When the potential of the third node Q2 is reduced to a relatively low level, the fourth control transistor CT4 may be turned on, and the second control transistor CT2c may be turned off. As the fourth control transistor CT4 is turned on, the potential of the second node QB may be increased to a high voltage VGH. The second output transistor OT2 is turned off in response to the potential of the high state of the second node QB, and the first output transistor OT1 is turned on in response to the potential of the low state of the first node Q1. The low voltage VGL may be output to the output terminal OUT through the first output transistor OT1 thus turned on.

[0158] When the low voltage VGL is output to the output terminal OUT, the potential of the first node Q1 may be lowered to a voltage lower than the low voltage VGL (hereinafter also referred to as a "lower low voltage DVGL") by coupling of the first capacitor C1. Therefore, when the potential of the first node Q1 is lower than the lower low voltage DVGL, the output characteristics of the first output transistor OT1 may be enhanced, and thus, the first initialization scan signal SI1 may have a stable low state.

[0159] exist Fig. 14B , a current-voltage curve Gh1 represents a current-voltage characteristic of the second control transistor excluding the bottom gate electrode BGE, a current-voltage curve Gh2 represents a current-voltage characteristic of the second control transistor CT2c in a cut-off state, and a current-voltage curve Gh3 represents a current-voltage characteristic of the second control transistor CT2c in a turn-on state.

[0160] The bottom gate electrode BGE of the second control transistor CT2c may be connected to the first node Q1 and may receive the lower low voltage DVGL. Therefore, the third electrode of the second control transistor CT2c may have the low voltage VGL, and the bottom gate electrode BGE may have the lower low voltage DVGL lower than the low voltage VGL. In the cut-off state of the second control transistor CT2c, the voltage Vgs between the gate electrode and the source electrode of the second control transistor CT2c may be "|(VGL+Vth)-VGL|", and the voltage Vbs between the bottom gate electrode and the source electrode of the second control transistor CT2c may be "|DVGL-VGL|". That is, Vbs may be greater than Vgs.

[0161] like Fig. 14B As shown in FIG. 1 , when the second control transistor CT2c is in the off state, due to the bottom gate electrode BGE, the current-voltage curve Gh1 of the second control transistor CT2c may be shifted in the positive direction and may be changed to the current-voltage curve Gh2. Therefore, when the second control transistor CT2c is in the off state, the off margin may be increased, and thus, a stable off state may be maintained.

[0162] In addition, in the on state of the second control transistor CT2c, the voltage Vgs between the gate electrode and the source electrode of the second control transistor CT2c may be "|VGH-VGL|", and the voltage Vbs between the bottom gate electrode and the source electrode of the second control transistor CT2c may also be "|VGH-VGL|".

[0163] like Fig. 14BAs illustrated in FIG. 1 , when the second control transistor CT2c is in the on-state, due to the bottom gate electrode BGE, the current-voltage curve Gh1 of the second control transistor CT2c may be shifted to the negative direction and may be changed to the current-voltage curve Gh3. Therefore, when the second control transistor CT2c is in the on-state, the on-margin may be increased, and thus, the response characteristics of the second control transistor CT2c may be enhanced.

[0164] refer to Fig. 13B , the first stage ST1e_1 includes first and second output transistors OT1 and OT2, first to fourth control transistors CT1, CT2c, CT3 and CT4, a fifth control transistor CT5, and first and second capacitors C1 and C2.

[0165] The first stage ST1e_1 may further include a reset terminal ESR. The first stage ST1e_1 may receive a reset signal for resetting the third node Q2 through the reset terminal ESR.

[0166] The fifth control transistor CT5 is connected between the second voltage terminal VT2 and the third node Q2, and operates in response to a reset signal received through the reset terminal ESR. The fifth control transistor CT5 includes a first electrode connected to the second voltage terminal VT2, a second electrode connected to the third node Q2, and a third electrode connected to the reset terminal ESR. The reset signal can be in the display device DD (reference Figure 1 ) is applied to the reset terminal ESR in the boosting phase when the device is powered on and ready for operation, and is not applied to the reset terminal ESR in the display phase when an image is actually displayed. Therefore, the fifth control transistor CT5 can be turned on only in the boosting phase, and can reset the stages ST1e to STn+1e (reference Fig.12 ) in each stage; in the display stage, the fifth control transistor CT5 can be kept in the cut-off state.

[0167] The reset terminals ESR of the stages ST1e to STn+1e may be connected to each other. Therefore, the third nodes Q2 of the stages ST1e to STn+1e may be reset at the same time.

[0168] Fig.15 yes Fig.12 The circuit diagram of the first stage is shown in FIG.

[0169] refer to Fig.14A and Fig.15 The first stage ST1e_2 includes first and second output transistors OT1 and OT2, a first control transistor CT1, a second control transistor CT2d, a third control transistor CT3, a fourth control transistor CT4, and first and second capacitors C1 and C2.

[0170] The second control transistor CT2d includes a first electrode connected to the second node QB, a second electrode connected to the first voltage terminal VT1, and a third electrode connected to the input terminal IN. The second control transistor CT2d further includes a bottom gate electrode BGEa connected to the first node Q1.

[0171] When the start signal FLMb is changed to a relatively low level, the second control transistor CT2d is turned off. In addition, when the start signal FLMb is changed to a relatively low level, starting from a period in which the first clock signal CLK is at a relatively low level (or starting from a time point when the first clock signal CLK is changed from a relatively high level to a relatively low level), the potentials of the first node Q1 and the third node Q2 can be maintained at a relatively low level. The first output transistor OT1 is turned on in response to the potential of the low state of the first node Q1. The low voltage VGL can be output to the output terminal OUT through the first output transistor OT1 thus turned on.

[0172] When the low voltage VGL is output to the output terminal OUT, the potential of the first node Q1 may be lowered to a lower low voltage DVGL lower than the low voltage VGL by coupling of the first capacitor C1. Therefore, when the potential of the first node Q1 is lowered to the lower low voltage DVGL, the output characteristics of the first output transistor OT1 may be enhanced, and thus, the first initialization scan signal SI1 may have a stable low state.

[0173] Fig.16 is a cross-sectional view of a display panel according to the present disclosure.

[0174] refer to Fig.16 , the display panel DP may include a base layer BL, a circuit layer DP_CL and an element layer DP_ED.

[0175] The base layer BL may include a synthetic resin layer. The synthetic resin layer may include a thermosetting resin material. Specifically, the synthetic resin layer may be a polyimide resin layer, and its material is not particularly limited. The synthetic resin layer may include at least one of acrylic resin, methacrylic resin, polyisoprene, vinyl resin, epoxy resin, polyurethane resin, cellulose resin, siloxane resin, polyamide resin, and perylene resin. In addition, the base layer BL may include at least one of a glass substrate, a metal substrate, an organic / inorganic composite substrate, and the like.

[0176] At least one inorganic layer is formed on the upper surface of the base layer BL. The inorganic layer may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide, and hafnium oxide. The inorganic layer may be composed of a plurality of layers.

[0177] The circuit layer DP_CL is disposed on the base layer BL. Fig.16 , the shielding layer BML may be disposed on the base layer BL. The shielding layer BML may overlap with the first transistor T1. The shielding layer BML may include metal and may be supplied with a constant voltage. When the constant voltage is applied to the shielding layer BML, the value of the threshold voltage Vth of the first transistor T1 disposed on the shielding layer BML may remain unchanged.

[0178] In addition, the shielding layer BML may block light incident on the first transistor T1 from below the shielding layer BML. In an embodiment, for example, the shielding layer BML may include a reflective metal. In an embodiment of the present disclosure, the shielding layer BML may be omitted. The buffer layer BFL may be disposed on the base layer BL, and the buffer layer BFL may be an inorganic layer. The buffer layer BFL may cover the shielding layer BML.

[0179] The semiconductor pattern is disposed on the buffer layer BFL. Below, the semiconductor pattern directly disposed on the buffer layer BFL is defined as a first semiconductor pattern. The first semiconductor pattern may include a silicon semiconductor. The first semiconductor pattern may include polycrystalline silicon. However, the present disclosure is not limited thereto. In an embodiment, for example, the first semiconductor pattern may include amorphous silicon.

[0180] Fig.16 Only a portion of the first semiconductor pattern is shown, and the first semiconductor pattern may be further provided in the pixel PXij (refer to Figure 2 ). The electrical characteristics of the first semiconductor pattern vary depending on whether it is doped. The first semiconductor pattern may include a doped region and an undoped region. The doped region may be doped with an N-type dopant or a P-type dopant. The P-type transistor includes a doped region doped with a P-type dopant, and the N-type transistor includes a doped region doped with an N-type dopant.

[0181] The doped region has a higher conductivity than that of the undoped region and operates substantially as an electrode or a signal line. The undoped region substantially corresponds to an active portion (or channel) of the transistor. In other words, a portion of the first semiconductor pattern may be an active portion of the transistor, another portion thereof may be a source or drain of the transistor, and the remaining portion thereof may be a connection signal line (or a connection electrode).

[0182] like Fig.16 As shown in FIG. 1 , a first electrode S1 , a channel portion A1 , and a second electrode D1 of the first transistor T1 are formed of a first semiconductor pattern. The first electrode S1 and the second electrode D1 of the first transistor T1 extend from the channel portion A1 in opposite directions.

[0183] Fig.161 and 2 illustrate a portion of a connection signal line CSL formed by a semiconductor pattern. Although not separately illustrated, the connection signal line CSL may be electrically connected to the sixth transistor T6 (refer to FIG. 1 ) in a plan view. Figure 2 )'s second electrode.

[0184] The first insulating layer 10 is disposed on the buffer layer BFL. Figure 1 ) overlap together and cover the first semiconductor pattern. The first insulating layer 10 may be an inorganic layer and / or an organic layer, and may have a single-layer structure or a multi-layer structure. The first insulating layer 10 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide, and hafnium oxide. In an embodiment, the first insulating layer 10 may be a single silicon oxide layer. In addition to the first insulating layer 10, the insulating layer of the circuit layer DP_CL to be described later may be an inorganic layer and / or an organic layer, and may have a single-layer structure or a multi-layer structure. The inorganic layer may include at least one of the above materials.

[0185] The third electrode G1 of the first transistor T1 is disposed on the first insulating layer 10. The third electrode G1 of the first transistor T1 overlaps the channel portion A1 of the first transistor T1. The third electrode G1 of the first transistor T1 may be used as a mask in a process of doping the first semiconductor pattern.

[0186] The second insulating layer 20 covering the third electrode G1 is disposed on the first insulating layer 10. The second insulating layer 20 overlaps with the plurality of pixels PX. The second insulating layer 20 may be an inorganic layer and / or an organic layer and may have a single-layer or multi-layer structure. In an embodiment, the second insulating layer 20 may be a silicon oxide layer of a single-layer structure.

[0187] The upper electrode UE may be disposed on the second insulating layer 20. The upper electrode UE may overlap the third electrode G1. A portion of the third electrode G1 and the upper electrode UE overlapping a portion of the third electrode G1 may define a capacitor Cst (refer to Figure 2 ). In the embodiment of the present disclosure, the upper electrode UE may be omitted.

[0188] In an embodiment of the present disclosure, the second insulating layer 20 may be replaced with an insulating pattern. The upper electrode UE is disposed on the insulating pattern. The upper electrode UE may be used as a mask for forming the insulating pattern from the second insulating layer 20.

[0189] The third insulating layer 30 covering the upper electrode UE is disposed on the second insulating layer 20. In an embodiment, the third insulating layer 30 may be a silicon oxide layer of a single-layer structure. The semiconductor pattern is disposed on the third insulating layer 30. Below, the semiconductor pattern directly disposed on the third insulating layer 30 is defined as a second semiconductor pattern. The second semiconductor pattern may include a metal oxide. The oxide semiconductor may include a crystalline or amorphous oxide semiconductor. In an embodiment, for example, the oxide semiconductor may include a combination of oxides of at least one of metals such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), and titanium (Ti). The oxide semiconductor may include at least one of indium tin oxide (ITO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), indium zinc oxide (IZO), zinc indium oxide (ZIO), indium oxide (InO), titanium oxide (TiO), indium zinc tin oxide (IZTO), zinc tin oxide (ZTO), etc.

[0190] Fig.16 Only a portion of the second semiconductor pattern is shown, and the second semiconductor pattern may be further disposed in any other region of the pixel PXij. The second semiconductor pattern may include a plurality of regions distinguished depending on whether the metal oxide is reduced. The region in which the metal oxide is reduced (hereinafter also referred to as the "reduction region") has a higher conductivity than the region in which the metal oxide is not reduced (hereinafter also referred to as the "non-reduction region"). The reduction region substantially has the function of an electrode or a signal line. The non-reduction region substantially corresponds to the channel portion A3 of the third transistor T3. In other words, a portion of the second semiconductor pattern may be the channel portion A3 of the third transistor T3, and the remainder thereof may be the first electrode S3 or the second electrode D3 of the third transistor T3.

[0191] The circuit layer DP_CL may further include a portion of a semiconductor pattern disposed in the non-active area NAA. For ease of description, a second control transistor CT2c of the semiconductor pattern of the scan driver is illustrated, which is disposed in the non-active area NAA. The first electrode C_S2, the channel portion C_A2, and the second electrode C_D2 of the second control transistor CT2c are formed by a second semiconductor pattern. In an embodiment of the present disclosure, the second semiconductor pattern may include a metal oxide. The first electrode C_S2 and the second electrode C_D2 include a metal reduced from a metal oxide semiconductor. The first electrode C_S2 and the second electrode C_D2 may include a metal layer having a given thickness from an upper surface of the second semiconductor pattern, and include a reduced metal.

[0192] The fourth insulating layer 40 is disposed to cover the first electrode S3, the channel portion A3, and the second electrode D3 of the third transistor T3 and the first electrode C_S2, the channel portion C_A2, and the second electrode C_D2 of the second control transistor CT2c. The third electrode G3 of the third transistor T3 and the third electrode C_G2 of the second control transistor CT2c are disposed on the fourth insulating layer 40. The third electrode G3 of the third transistor T3 overlaps the channel portion A3 of the third transistor T3, and the third electrode C_G2 of the second control transistor CT2c overlaps the channel portion C_A2 of the second control transistor CT2c.

[0193] In an embodiment of the present disclosure, the bottom gate electrode BGE of the second control transistor CT2c and the shielding layer BML may be disposed in the same layer (i.e., the base layer BL). However, the present disclosure is not limited thereto. In an alternative embodiment, the bottom gate electrode BGE of the second control transistor CT2c and the upper electrode UE may be disposed in the same layer (i.e., the second insulating layer 20). The bottom gate electrode BGE may be connected to the second electrode of the third control transistor CT3 or the third electrode of the first output transistor OT1, and the first output transistor OT1 is connected to the first node Q1, as shown in FIG. Fig.13A and Fig. 13B As shown in the figure.

[0194] The fifth insulating layer 50 covering the third electrode G3 of the third transistor T3 and the third electrode C_G2 of the second control transistor CT2c is disposed on the fourth insulating layer 40. In this embodiment, the fifth insulating layer 50 may include at least one of a silicon oxide layer and a silicon nitride layer. The fifth insulating layer 50 may include a plurality of silicon oxide layers and a plurality of silicon nitride layers alternately stacked.

[0195] At least one insulating layer is further disposed on the fifth insulating layer 50. Like this embodiment, the sixth insulating layer 60 and the seventh insulating layer 70 may be disposed on the fifth insulating layer 50. The sixth insulating layer 60 and the seventh insulating layer 70 may be organic layers, and may have a single-layer structure or a multi-layer structure. Each of the sixth insulating layer 60 and the seventh insulating layer 70 may be a polyimide-based resin layer of a single-layer structure. However, the present disclosure is not limited thereto. In an embodiment, for example, the sixth insulating layer 60 and the seventh insulating layer 70 may include at least one of acrylic resin, methacrylic resin, polyisoprene, vinyl resin, epoxy resin, polyurethane resin, cellulose resin, siloxane resin, polyamide resin, and perylene resin.

[0196] The first connection electrode CNE1 may be disposed on the fifth insulating layer 50. The first connection electrode CNE1 is connected to the connection signal line CSL through a first contact hole CH1 penetrating the first to fifth insulating layers 10, 20, 30, 40, and 50. The second connection electrode CNE2 may be connected to the first connection electrode CNE1 through a second contact hole CH2 penetrating the sixth insulating layer 60. In an embodiment of the present disclosure, at least one of the fifth to seventh insulating layers 50 to 70 may be omitted, and one of the first and second connection electrodes CNE1 and CNE2 may be omitted.

[0197] The third connection electrode CNE3 may be further disposed on the fifth insulating layer 50. The third connection electrode CNE3 is connected to the second electrode C_D2 of the second control transistor CT2c through a third contact hole CH3 penetrating the fourth insulating layer 40 and the fifth insulating layer 50.

[0198] The fourth connection electrode CNE4 may be further disposed on the seventh insulating layer 70. The fourth connection electrode CNE4 may be connected to the second connection electrode CNE2 through a fourth contact hole CH4 penetrating the seventh insulating layer 70. The fourth connection electrode CNE4 is covered by the eighth insulating layer 80.

[0199] The element layer DP_ED is disposed on the circuit layer DP_CL. The element layer DP_ED may include a light emitting element ED (refer to Figure 2 ).like Fig.16 As illustrated in FIG. 8 , the anode electrode P_AE of the light emitting element ED may be connected to the fourth connection electrode CNE4 through a fifth contact hole CH5 penetrating the eighth insulating layer 80 .

[0200] Fig.16 4 illustrates a structure in which the circuit layer DP_CL includes the fourth connection electrode CNE4, but the present disclosure is not limited thereto. In an alternative embodiment, the fourth connection electrode CNE4 may be omitted in the circuit layer DP_CL. In this case, the anode electrode P_AE may be directly connected to the second connection electrode CNE2.

[0201] The element layer DP_ED further includes a pixel defining layer PDL disposed on the circuit layer DP_CL. A pixel opening OP1 corresponding to the light emitting element ED may be defined in the pixel defining layer PDL. The pixel opening OP1 exposes at least a portion of the anode electrode P_AE of the light emitting element ED. The pixel opening OP1 of the pixel defining layer PDL may define an emission area PXA. In an embodiment, for example, a plurality of pixels PX (refer to Figure 3 ) can be set on the display panel DP (reference Figure 3). The region in which the plurality of pixels PX are arranged may be defined as a pixel region, and one pixel region may include an emission region PXA and a non-emission region NPXA adjacent to the emission region PXA. The non-emission region NPXA may surround the emission region PXA.

[0202] The emission layer P_EL is arranged to correspond to the pixel opening OP1 defined in the pixel defining layer PDL. In an embodiment, a patterned emission layer P_EL is illustrated in an embodiment, but the present disclosure is not limited thereto. The common emission layer may be arranged in common in a plurality of pixels PX. In this case, the common emission layer may generate white light or blue light. The cathode electrode C_CE may face the anode electrode P_AE. The cathode electrode C_CE may be arranged in common in a plurality of pixels PX.

[0203] Fig.17 yes Figure 4A , and Fig.18 yes Fig.17 The circuit diagram of the first stage is shown in FIG. Fig.17 and Fig.18 Among the components shown in the figure, Fig.12 The same components as those illustrated in FIG. 13 are denoted by the same reference numerals, and thus, additional description will be omitted to avoid redundancy.

[0204] refer to Fig.17 , the first scan driving circuit 310c may include a plurality of stages ST1f to STn+1f connected sequentially to each other. The stages ST1f to STn+1f may have substantially the same circuit configuration as each other. For ease of description, Fig.17 Four stages ST1f, ST2f, STnf, and STn+1f are illustrated in FIG. 1 as one of the embodiments.

[0205] Each of the stages ST1 f to STn+1 f may include an input terminal IN, a clock terminal CKT, first and second voltage terminals VT1 and VT2 , a dummy voltage terminal VT3 , and an output terminal OUT.

[0206] The first voltage terminal VT1 may be a terminal to which a low voltage VGL (or a first voltage) is applied, and the second voltage terminal VT2 may be a terminal to which a high voltage VGH (or a second voltage) is applied. The low voltage VGL and the high voltage VGH may have a DC voltage level. The high voltage VGH may be used as a relatively high level (i.e., a gate-on voltage) of a scan signal, and the low voltage VGL may be used as a relatively low level (i.e., a gate-off voltage) of a scan signal. The voltage level of the low voltage VGL may be lower than the voltage level of the high voltage VGH.

[0207] The dummy voltage terminal VT3 may refer to a terminal to which a dummy low voltage D_VGL (or a third voltage) having a voltage level lower than that of the low voltage VGL is applied. The dummy low voltage D_VGL may have a DC voltage level.

[0208] The first voltage terminals VT1 of the stages ST1f to STn+1f may be connected to each other, and the second voltage terminals VT2 of the stages ST1f to STn+1f may be connected to each other. The dummy voltage terminals VT3 of the stages ST1f to STn+1f may be connected to each other.

[0209] Next, we will refer to Fig.18 A circuit configuration of a first stage ST1f among the stages ST1f to STn+1f is described. Because the stages ST1f to STn+1f have the same circuit configuration as one another, additional description associated with the circuit configurations of the remaining stages ST2f to STn+1f will be omitted to avoid redundancy.

[0210] refer to Fig.18 The first stage ST1f includes first and second output transistors OT1 and OT2, a first control transistor CT1, a second control transistor CT2e, a third control transistor CT3, a fourth control transistor CT4, and first and second capacitors C1 and C2.

[0211] The second control transistor CT2e is connected between the second node QB and the first voltage terminal VT1, and operates in response to the potential of the third node Q2. The second control transistor CT2e includes a first electrode connected to the second node QB, a second electrode connected to the first voltage terminal VT1, and a third electrode connected to the third node Q2. The second control transistor CT2e further includes a bottom gate electrode BGE connected to the dummy voltage terminal VT3. The third electrode of the second control transistor CT2e and the third electrode of the fourth control transistor CT4 can be commonly connected to the third node Q2.

[0212] In an embodiment of the present disclosure, the fourth control transistor CT4 may include an LTPS semiconductor layer and may be implemented with a first type (or P type) transistor. The second control transistor CT2e may include an oxide semiconductor layer and may be implemented with a second type (or N type) transistor. Therefore, the second control transistor CT2e and the fourth control transistor CT4 may be alternately turned on in response to the potential of the third node Q2.

[0213] The bottom gate electrode BGE of the second control transistor CT2e may receive a dummy low voltage D_VGL through a dummy voltage terminal VT3. When the second control transistor CT2e is in the off state, the third electrode of the second control transistor CT2e may have a low voltage VGL, but the bottom gate electrode BGE may have a dummy low voltage D_VGL lower than the low voltage VGL. Therefore, when the second control transistor CT2c is in the off state, the voltage Vgs between the gate electrode and the source electrode of the second control transistor CT2c may be "|(VGL+Vth)-VGL|", and the voltage Vbs between the bottom gate electrode and the source electrode of the second control transistor CT2c may be "|D_VGL-VGL|". That is, Vbs may be greater than Vgs.

[0214] In this way, Fig. 14B As shown in FIG. 1 , when the second control transistor CT2e is in the off state, due to the bottom gate electrode BGE, the current-voltage curve Gh1 of the second control transistor CT2c may be shifted in the positive direction and may be changed to the current-voltage curve Gh2. Therefore, when the second control transistor CT2e is in the off state, the off margin may be increased, and thus, a stable off state may be maintained.

[0215] Fig.19 yes Fig.17 The circuit diagram of the first stage is shown in FIG.

[0216] refer to Fig.19 The first stage ST1f_1 includes first and second output transistors OT1 and OT2, a first control transistor CT1, a second control transistor CT2f, a third control transistor CT3, a fourth control transistor CT4, and first and second capacitors C1 and C2.

[0217] The second control transistor CT2f includes a first electrode connected to the second node QB, a second electrode connected to the first voltage terminal VT1, and a third electrode connected to the input terminal IN. The second control transistor CT2f further includes a bottom gate electrode BGEa connected to the dummy voltage terminal VT3.

[0218] The bottom gate electrode BGEa of the second control transistor CT2f may receive the dummy low voltage D_VGL through the dummy voltage terminal VT3. When the second control transistor CT2f is in the off state, the third electrode of the second control transistor CT2f may have the low voltage VGL, but the bottom gate electrode BGEa may have the dummy low voltage D_VGL lower than the low voltage VGL. Therefore, when the second control transistor CT2f is in the off state, the off margin may increase due to the bottom gate electrode BGEa, and therefore, a stable off state may be maintained.

[0219] According to the present disclosure, each level of the scan driver includes a P-type control transistor and an N-type control transistor. Therefore, the circuit configuration of each level can be simplified, and therefore, the width of the non-effective area of ​​the display device can be prevented from increasing. In addition, as the number of signals input to each level is reduced, the power consumption of the display device can be reduced.

[0220] While the present disclosure has been described with reference to the embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications can be made thereto without departing from the spirit and scope of the present disclosure as set forth in the claims.

Claims

1. A scanning driver, comprising: A plurality of stages connected sequentially to each other, each of the plurality of stages comprising: a first output transistor connected between the output terminal and the first voltage terminal and operating in response to a potential of the first node; a second output transistor connected between the output terminal and a second voltage terminal and operating in response to a potential of a second node; a first control transistor connected between an input terminal receiving a start signal or a previous carry signal from a previous stage and a third node and operating in response to a clock signal supplied through a clock terminal; a second control transistor connected between the second node and the first voltage terminal and operating in response to the start signal or the previous carry signal provided through the input terminal or operating in response to a potential of the third node; a third control transistor connected between the third node and the first node and operating in response to a first voltage provided through the first voltage terminal; and a fourth control transistor connected between the second node and the second voltage terminal and operating in response to the potential of the third node, wherein each of the first output transistor and the second output transistor and the first control transistor, the third control transistor and the fourth control transistor is a first type transistor, and The second control transistor is a second type transistor different from the first type transistor.

2. The scan driver according to claim 1, further comprising: a first capacitor connected between the output terminal and the first node; as well as A second capacitor is connected between the second node and the second voltage terminal.

3. The scan driver according to claim 1, wherein: The first type transistor is a P-type transistor, and the second type transistor is an N-type transistor.

4. The scan driver according to claim 3, wherein: The second control transistor includes an oxide semiconductor layer, and Wherein, each of the first output transistor, the second output transistor, and the first control transistor, the third control transistor, and the fourth control transistor includes a low temperature polysilicon semiconductor layer.

5. The scan driver according to any one of claims 1 to 4, wherein: A voltage level of the first voltage applied to the first voltage terminal is lower than a voltage level of a second voltage applied to the second voltage terminal.

6. The scan driver according to claim 1, wherein: The second control transistor comprises: a first electrode connected to the second node; a second electrode connected to the first voltage terminal; and A third electrode connected to the input terminal.

7. The scan driver according to claim 6, wherein: The second control transistor further comprises: A bottom gate electrode connected to the first node.

8. The scan driver according to claim 6, wherein: The second control transistor further comprises: A bottom gate electrode receives a dummy voltage lower than the first voltage supplied to the first voltage terminal.

9. The scan driver according to claim 1, wherein: The second control transistor comprises: a first electrode connected to the second node; a second electrode connected to the first voltage terminal; and A third electrode is connected to the third node.

10. The scan driver according to claim 9, wherein: The second control transistor further comprises: A bottom gate electrode connected to the first node.

11. The scan driver according to claim 9, wherein: The second control transistor further comprises: A bottom gate electrode receives a dummy voltage lower than the first voltage supplied to the first voltage terminal.

12. The scan driver according to claim 1, wherein: Each of the plurality of stages further comprises: a first carry transistor connected between a carry terminal and the first voltage terminal and operating in response to the potential of the first node; and a second carry transistor connected between the carry terminal and the second voltage terminal and operating in response to the potential of the first node, wherein the first carry transistor is the first type transistor, and The second carry transistor is the second type transistor.

13. The scan driver according to claim 12, wherein: The first type transistor is a P-type transistor, and the second type transistor is an N-type transistor.

14. The scan driver according to claim 13, wherein: Each of the second control transistor and the second carry transistor includes an oxide semiconductor layer, and Wherein, each of the first carry transistor, the first output transistor, the second output transistor, and the first control transistor, the third control transistor, and the fourth control transistor includes a low temperature polysilicon semiconductor layer.

15. The scan driver according to claim 1, wherein: Each of the plurality of stages further comprises: a first carry transistor connected between a carry terminal and the first voltage terminal and operating in response to the potential of the second node; and a second carry transistor connected between the carry terminal and the second voltage terminal and operating in response to the potential of the second node, wherein the first carry transistor is the second type transistor, and The second carry transistor is the first type transistor.

16. The scan driver according to claim 15, wherein: The first type transistor is a P-type transistor, and the second type transistor is an N-type transistor.

17. The scan driver according to claim 16, wherein: Each of the second control transistor and the first carry transistor includes an oxide semiconductor layer, and Wherein, each of the second carry transistor, the first output transistor, the second output transistor, and the first control transistor, the third control transistor, and the fourth control transistor includes a low temperature polysilicon semiconductor layer.

18. A scanning driver, comprising: A plurality of stages connected sequentially to each other, each of the plurality of stages comprising: A first output transistor including: a first electrode connected to the output terminal; a second electrode connected to the first voltage terminal; and a third electrode connected to the first node; a first capacitor connected between the output terminal and the first node; a second output transistor including: a first electrode connected to the output terminal; a second electrode connected to the second voltage terminal; and a third electrode connected to the second node; A first control transistor including: a first electrode connected to the input terminal; a second electrode connected to the third node; and a third electrode connected to the clock terminal; a second control transistor comprising: a first electrode connected to the second node; a second electrode connected to the first voltage terminal; a third electrode connected to the input terminal or the third node; and a bottom gate electrode facing the third electrode; a third control transistor including: a first electrode connected to the third node; a second electrode connected to the first node; and a third electrode connected to the first voltage terminal; and The fourth control transistor includes: a first electrode connected to the second node; a second electrode connected to the second voltage terminal; and a third electrode connected to the third node.

19. The scan driver according to claim 18, wherein: The bottom gate electrode is connected to the first node.

20. The scan driver according to claim 18, wherein: The bottom gate electrode is connected to a dummy voltage terminal that receives a dummy voltage lower than a voltage supplied through the first voltage terminal.

21. The scan driver according to claim 18, wherein: Each of the plurality of stages further comprises: A second capacitor is connected between the second node and the second voltage terminal.

22. The scan driver according to any one of claims 18 to 21, wherein: Each of the first output transistor and the second output transistor and the first control transistor, the third control transistor and the fourth control transistor is a P-type transistor, and Wherein, the second control transistor is an N-type transistor.

23. The scan driver according to claim 22, wherein: The second control transistor includes an oxide semiconductor layer, and Wherein, each of the first output transistor, the second output transistor, and the first control transistor, the third control transistor, and the fourth control transistor includes a low temperature polysilicon semiconductor layer.

24. A display device comprising: A display panel including a plurality of pixels; a data driver, the data driver outputting a data signal to the display panel; as well as A scan driver, the scan driver outputting a scan signal to the display panel, the scan driver comprising: A plurality of stages connected sequentially to each other, each of the plurality of stages comprising: A first output transistor including: a first electrode connected to the output terminal; a second electrode connected to the first voltage terminal; and a third electrode connected to the first node; a second output transistor including: a first electrode connected to the output terminal; a second electrode connected to the second voltage terminal; and a third electrode connected to the second node; A first control transistor including: a first electrode connected to the input terminal; a second electrode connected to the third node; and a third electrode connected to the clock terminal; a second control transistor comprising: a first electrode connected to the second node; a second electrode connected to the first voltage terminal; and a third electrode connected to the input terminal or the third node; a third control transistor including: a first electrode connected to the third node; a second electrode connected to the first node; and a third electrode connected to the first voltage terminal; and a fourth control transistor comprising: a first electrode connected to the second node; a second electrode connected to the second voltage terminal; and a third electrode connected to the third node, wherein each of the first output transistor, the second output transistor, and the first control transistor, the third control transistor, and the fourth control transistor is a P-type transistor, and Wherein, the second control transistor is an N-type transistor.

25. The display device according to claim 24, wherein: The third electrode of the second control transistor is connected to the input terminal.

26. The display device according to claim 25, wherein: The second control transistor further comprises: A bottom gate electrode connected to the first node.

27. The display device according to claim 25, wherein: The second control transistor further comprises: A bottom gate electrode receives a dummy voltage lower than a voltage supplied through the first voltage terminal.

28. The display device according to claim 24, wherein: The third electrode of the second control transistor is connected to the third node.

29. The display device according to claim 28, wherein: The second control transistor further comprises: A bottom gate electrode connected to the first node.

30. The display device according to claim 28, wherein: The second control transistor further comprises: A bottom gate electrode receives a dummy voltage lower than a voltage supplied through the first voltage terminal.

31. The display device according to any one of claims 24 to 30, wherein: Each of the plurality of stages further comprises: A first carry transistor includes: a first electrode connected to a carry terminal; a second electrode connected to the first voltage terminal; and a third electrode connected to the first node; and a second carry transistor including: a first electrode connected to the carry terminal; a second electrode connected to the second voltage terminal; and a third electrode connected to the first node, Wherein, the first carry transistor is the P-type transistor, and Wherein, the second carry transistor is the N-type transistor.

32. The display device according to claim 31, wherein: Each of the second control transistor and the second carry transistor includes an oxide semiconductor layer, and Wherein, each of the first carry transistor, the first output transistor, the second output transistor, and the first control transistor, the third control transistor, and the fourth control transistor includes a low temperature polysilicon semiconductor layer.

33. The display device according to any one of claims 24 to 30, wherein: Each of the plurality of stages further comprises: A first carry transistor includes: a first electrode connected to a carry terminal; a second electrode connected to the first voltage terminal; and a third electrode connected to the second node; and a second carry transistor including: a first electrode connected to the carry terminal; a second electrode connected to the second voltage terminal; and a third electrode connected to the second node, Wherein, the first carry transistor is the N-type transistor, and Wherein, the second carry transistor is the P-type transistor.

34. The display device according to claim 33, wherein: Each of the second control transistor and the first carry transistor includes an oxide semiconductor layer, and Wherein, each of the second carry transistor, the first output transistor, the second output transistor, and the first control transistor, the third control transistor, and the fourth control transistor includes a low temperature polysilicon semiconductor layer.

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