Upconversion successive approximation analog-to-digital converter and switching method thereof

Abstract

The invention relates to an up-conversion successive approximation type analog-to-digital converter which comprises a comparator, a DAC capacitor array and a control logic circuit, the output end of the comparator is connected to the control logic circuit, and the DAC capacitor array comprises a forward capacitor array connected with the positive input end of the comparator and a reverse capacitor array connected with the negative input end of the comparator; the invention further provides a switching method of the up-conversion successive approximation type analog-to-digital converter. Compared with a 10-bit traditional structure, the capacitance area is reduced by 75%, power consumption generated in the switching process is reduced by 99.41%, and DAC output common-mode voltage is continuously increased to approach VREF.

Description

Technical Field

[0001] The invention relates to the field of analog-digital mixed signal integrated circuits, and in particular to an upward conversion successive approximation analog-to-digital converter and a switching method thereof. Background Art

[0002] The successive approximation analog-to-digital converter has a simple structure, low power consumption and small area, and is widely used in wearable devices, CMOS image sensors and other fields with high power consumption and speed requirements. The DAC capacitor array occupies a large area and consumes a lot of energy in the successive approximation analog-to-digital converter, so it is necessary to reduce the switching energy consumption of the capacitor array, reduce the area of ​​the DAC capacitor array, reduce the chip manufacturing cost, and improve economic benefits.

[0003] The existing method is to reduce the area of ​​the capacitor array by reducing the physical size of the capacitor unit, but this will introduce greater matching errors and thermal noise, which will affect the linearity and accuracy of the ADC. To reduce the energy consumption during the charging and discharging process of the capacitor, optimized switch control and charge redistribution technology can be introduced. However, these solutions often require more complex circuit design and still have limitations in high-speed applications.

[0004] For high-speed comparators, NMOS input pairs are usually more suitable because NMOS has high mobility and low input bias current, thus having better noise performance and higher speed. However, when the DAC output voltage continues to decrease, the NMOS input pair may face some problems: insufficient input voltage to turn on the NMOS and reduced common-mode input range. Summary of the invention

[0005] In view of the shortcomings of the prior art, the present invention provides an upward conversion successive approximation analog-to-digital converter and a switching method thereof. Compared with the 10-bit traditional structure, the capacitor area is reduced by 75%, the power consumption generated during the switching process is reduced by 99.41%, and the DAC output common mode voltage continues to increase and approaches V REF .

[0006] To achieve the above objectives, the present invention is implemented through the following technical solutions: a bottom plate sampling successive approximation analog-to-digital converter, including a comparator, a DAC capacitor array and a control logic circuit, wherein the output end of the comparator is connected to the control logic circuit, The DAC capacitor array includes two parts: one is a forward capacitor array connected to the positive input terminal of the comparator, and the forward capacitor array is composed of a binary weight capacitor array; The second is a reverse capacitor array connected to the negative input terminal of the comparator, and the reverse capacitor array is composed of a binary weight capacitor array; The upper plate of the positive capacitor array is connected through the switch S P With V INThe lower plate of the positive capacitor array is connected to V CM , Vaq, gnd are connected; the upper plate of the reverse capacitor array is connected through the switch S N With V CM The lower plate of the reverse capacitor array is connected to V CM , Vaq, and gnd are connected.

[0007] Furthermore, the forward capacitor array includes a total of 2 N-2 The unit capacitance is two bits less than the N bits of accuracy of the successive approximation analog-to-digital converter.

[0008] Furthermore, the reverse capacitor array includes 2 N-2 The unit capacitance is two bits less than the N bits of accuracy of the successive approximation analog-to-digital converter.

[0009] The present invention provides an up-conversion successive approximation analog-to-digital converter and a switching method thereof, which are specifically implemented as follows: Sampling phase: Input signal V IN The sampling switch is turned on and connected to the upper plate of the forward capacitor array, and the lower plates of all capacitors in the forward capacitor array are connected to gnd; V CM The upper plate of the reverse capacitor array is connected to the upper plate of the reverse capacitor array through the conduction of the sampling switch, and the lower plates of all capacitors in the reverse capacitor array are connected to gnd; Comparison phase: First, S P , S N Disconnect, the connections of all capacitor bottom plates in the forward capacitor array and the reverse capacitor array remain unchanged, start the first comparison, and get the MSB; if V IN Greater than V REF / 2, then the lower plates of all capacitors in the reverse capacitor array are connected to Vaq, and the negative input voltage of the comparator is V DACN Increased V REF / 4, the connection of the lower plates of all capacitors in the forward capacitor array remains unchanged; conversely, the lower plates of all capacitors in the forward capacitor array are connected to Vaq, and the voltage at the positive input of the comparator V DACP Increased V REF / 4, the connections of the lower plates of all capacitors in the reverse capacitor array remain unchanged; Then start the second comparison; if V IN Greater than (3 / 4) V REF , then the lower plate connection of the largest capacitor in the reverse capacitor array is switched from Vaq to V CM , the lower plate connections of the remaining capacitors in the reverse capacitor array remain unchanged, V DACN Increased V REF / 8, the connection of the lower plates of all capacitors in the forward capacitor array remains unchanged; if V IN Greater than V REF / 2 and less than or equal to (3 / 4) V REF , then all capacitor connections in the reverse capacitor array remain unchanged, the lower plate connection of the largest capacitor in the forward capacitor array is switched from gnd to Vaq, and the lower plate connections of the remaining capacitors in the forward capacitor array remain unchanged, V DACP Increased V REF / 8, the lower plate connections of the remaining capacitors in the reverse capacitor array remain unchanged; if V IN Greater than V REF / 4 and less than or equal to V REF / 2, the lower plate connections of all capacitors in the forward capacitor array remain unchanged, and the lower plate connection of the largest capacitor in the reverse capacitor array is switched from gnd to V aq , the lower plate connections of the remaining capacitors in the reverse capacitor array remain unchanged, V DACN Increased V REF / 8; if V INP Less than or equal to V REF / 4, then the lower plate connections of all capacitors in the reverse capacitor array remain unchanged, and the lower plate connection of the largest capacitor in the forward capacitor array is switched from Vaq to V CM , the lower plates of all capacitors in the forward capacitor array remain connected unchanged, V DACP Increased V REF / 8; Then the third comparison is performed; if V INP Greater than (7 / 8) V REF , then the lower plate of the second largest capacitor in the reverse capacitor array switches from Vaq to V CM , V DACN Increased V REF / 16, the lower plate connections of all capacitors in the forward capacitor array remain unchanged; if V IN Greater than (3 / 4) V REF And less than or equal to (7 / 8)V REF , then the lower plate voltage of the second largest capacitor in the forward capacitor array switches from gnd to Vaq, and the lower plate connections of other capacitors in the forward capacitor array remain unchanged, V DACP Increased V REF / 16, the lower plate connections of all capacitors in the reverse capacitor array remain unchanged; if V IN Greater than (5 / 8) V REF And less than or equal to (3 / 4) V REF , then the lower plate of the second largest capacitor in the reverse capacitor array switches from Vaq to V CM , the other capacitor connections in the reverse capacitor array remain unchanged, V DACN Increased V REF / 16, the voltage on the lower plate of the forward capacitor array remains unchanged; if V IN Greater than (1 / 2) V REF And less than or equal to (5 / 8)V REF , then the lower plate voltage of the second largest capacitor in the forward capacitor array switches from gnd to Vaq, and the other capacitor connections in the forward capacitor array remain unchanged, V DACP Increased V REF / 16, the lower plate connection of the reverse capacitor array remains unchanged; if V IN Greater than (3 / 8) V REF And less than or equal to (1 / 2) V REF , then the lower plate of the second largest capacitor in the reverse capacitor array switches from gnd to Vaq, and the other capacitors in the reverse capacitor array remain connected unchanged, V DACN Increased V REF / 16, the lower plate connection of the forward capacitor array remains unchanged; if V IN Greater than (1 / 4) V REF And less than or equal to (3 / 8)V REF , the lower plate voltage of the second largest capacitor in the forward capacitor array switches from Vaq to V CM , the other capacitor connections in the forward capacitor array remain unchanged, V DACP Increased V REF / 16, the lower plate connection of the reverse capacitor array remains unchanged; if V INP Greater than (1 / 8) V REF And less than or equal to (1 / 4) V REF , then the lower plate of the second largest capacitor in the reverse capacitor array switches from gnd to Vaq, and the other capacitors in the reverse capacitor array remain connected unchanged, V DACN Increased V REF / 16, the lower plate connection of the forward capacitor array remains unchanged; if V IN Less than or equal to (1 / 8) V REF , the lower plate voltage of the second largest capacitor in the forward capacitor array switches from Vaq to V CM , the other capacitor bottom plates of the forward capacitor array remain connected unchanged, V DACP Increased V REF / 16, the lower plate connection of the reverse capacitor array remains unchanged; Next, the fourth comparison is performed, and the switching process is similar to the third one, until the LSB is obtained and the analog-to-digital conversion is completed. Beneficial Effects

[0010] Compared with the prior art, it has the following beneficial effects: The present invention introduces V CM (equal to V REF / 2), Vaq (equal to VREF / 4) and gnd three reference voltages, the DAC capacitor area is reduced by 75% compared with the traditional structure; the present invention reduces the switching energy consumed by 99.41% compared with the traditional structure through unilateral sampling and upward conversion (the voltage is increased on the low voltage side, the high voltage side remains unchanged, and the output common mode voltage continues to increase), and the reset energy consumption is 0; the DAC output common mode voltage of the present invention continues to increase and approaches V REF， Suitable for high-speed applications and has good economic benefits. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 It is a structural schematic diagram of a 10-bit successive approximation analog-to-digital converter; Figure 2 The schematic diagram of the DAC capacitor array switch switching operation of the sampling phase and the first and second comparisons of a four-bit successive approximation analog-to-digital converter is shown; Figure 3 The working principle diagram of the DAC capacitor array switch switching of the third and fourth comparisons of a four-bit successive approximation analog-to-digital converter (D3=1); Figure 4 The working principle diagram of the DAC capacitor array switch switching of the third and fourth comparisons of a four-bit successive approximation analog-to-digital converter (D3=0); Figure 5 It is a MATLAB simulation result diagram of the switch power consumption changing with the output code during the conversion process of the 10-bit successive approximation analog-to-digital converter in a specific embodiment of the present invention; Figure 6 Schematic diagram of the change of DAC output voltage. DETAILED DESCRIPTION

[0012] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the accompanying drawings in the embodiments of the present invention. However, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention. Example

[0013] like Figure 1 As shown in the figure, an N-bit successive approximation analog-to-digital converter is taken as an example, which includes a comparator, a control logic circuit and a DAC capacitor array. The DAC capacitor array includes a positive capacitor array connected to the positive input of the comparator and a reverse capacitor array connected to the negative input of the comparator. The capacitor array is composed of a binary weighted capacitor array, and the maximum capacitance increases exponentially with the increase of the accuracy of the analog-to-digital converter, which is 2 N-3 C, such as Figure 1As shown, when N=10, the maximum capacitance is 128C. For simplicity, a 4-bit successive approximation analog-to-digital converter is used as an example. The switching method of the converter is: Sampling stage like Figure 2 As shown in (a), the sampling switch is turned on and the input signal V IN 、V CM The upper plates of the forward capacitor array and the reverse capacitor array are sampled respectively, and at the same time, all the lower plates of the capacitors in the forward capacitor array and the reverse capacitor array are connected to gnd.

[0014] Comparison Phase After sampling, the upper plate switch S P , S N When it is turned on, the connection of the lower plates of all capacitors in the forward capacitor array and the reverse capacitor array remains unchanged, and the switching energy consumed in this process is 0, such as Figure 2 (b) as shown.

[0015] Start the first comparison, if V IN Greater than V REF / 2, the output digital code D3 is 1; if V IN Less than or equal to V REF / 2, the output digital code D3 is 0; like Figure 2 As shown in (c), if D3 is 1, all lower plates in the reverse capacitor array switch from gnd to V aq , the forward capacitor array remains unchanged, and the switching energy consumed in this process is 0; if D3 is 0, the lower plates of all capacitors in the forward capacitor array are switched from gnd to V aq , the reverse capacitor array remains unchanged, and the switching energy consumed in this process is 0; Next, a second comparison is performed to obtain the output digital code D2. IN Greater than (3 / 4) V REF , then the output digital code D2 = 1; if V IN Greater than (1 / 2) V REF Less than or equal to (3 / 4) V REF , then the output digital code D2 = 0; if V IN Greater than (1 / 4) V REF Less than or equal to (1 / 2) V REF , then the output digital code D2 = 1; if V IN Greater than 0 and less than or equal to (1 / 4) V REF , then the output digital code D2 = 0; like Figure 3 As shown in (a), when D3D2 = 11, the lower plate connection of the largest capacitor in the reverse capacitor array is switched from Vaq to VCM , the lower plates of the other capacitors in the reverse capacitor array remain connected unchanged, and the lower plates of all capacitors in the forward capacitor array remain connected unchanged. The switching energy consumed in this process is 1 / 16 V REF 2 ; When D3D2 = 10, the lower plate connection of the largest capacitor in the forward capacitor array is switched from gnd to Vaq, the lower plate connections of the remaining capacitors in the forward capacitor array remain unchanged, and the lower plate connections of all capacitors in the reverse capacitor array remain unchanged. The switching energy consumed in this process is 1 / 16 V REF 2 ; like Figure 4 As shown in (a), when D3D2 = 01, the lower plate connection of the largest capacitor in the reverse capacitor array is switched from gnd to Vaq, and the lower plate connections of the remaining capacitors in the reverse capacitor array remain unchanged. The switching energy consumed in this process is 1 / 16 V REF 2 ; When D3D2 = 00, the lower plate connection of the largest capacitor in the forward capacitor array is switched from Vaq to V CM , the lower plate connections of the remaining capacitors in the forward capacitor array remain unchanged, and the lower plate connections of all capacitors in the reverse capacitor array remain unchanged. The switching energy consumed in this process is 1 / 16 V REF 2 ; Next, the third comparison is performed to obtain D1. IN Greater than (7 / 8) V REF , then the output digital code D1 = 1; if V IN Greater than (3 / 4) V REF Less than or equal to (7 / 8) V REF , then the output digital code D1 = 0; if V IN Greater than (5 / 8) V REF Less than or equal to (3 / 4) V REF , then the output digital code D1 = 1; if V IN Greater than (1 / 2) V REF Less than or equal to (5 / 8) V REF , then the output digital code D1 = 0; if V IN Greater than (3 / 8) V REF Less than or equal to (1 / 2) V REF , then the output digital code D1 = 1; if V IN Greater than (1 / 4) V REF Less than or equal to (3 / 8) V REF , then the output digital code D1 = 0; if V IN Greater than (1 / 8) V REF Less than or equal to (1 / 4) VREF , then the output digital code D1 = 1; if V IN Less than or equal to (1 / 8) V REF ,, then the output digital code D1 = 0; like Figure 3 As shown in (b), when D3D2D1 = 111, the lower plate of the second largest capacitor C in the reverse capacitor array changes from V aq Switch to V CM , the connection of the lower plates of the other capacitors remains unchanged, and the switching energy consumed in this process is (3 / 64)CV REF 2 ; When D3D2D1 = 110, the lower plate of the second largest capacitor C in the forward capacitor array switches from 0 to V aq , the connection of the lower plates of the other capacitors remains unchanged, and the switching energy consumed in this process is (1 / 64)CV REF 2 ; When D3D2D1 = 101, the lower plate of the second largest capacitor C in the reverse capacitor array is connected from V aq Switch to V CM , the connection of the lower plates of the other capacitors remains unchanged, and the switching energy consumed in this process is (1 / 64)CV REF 2 ; When D3D2D1 = 100, the lower plate of the second largest capacitor C in the forward capacitor array switches from gnd to V aq , the connection of the lower plates of the other capacitors remains unchanged, and the switching energy consumed in this process is (3 / 64)CV REF 2 ; like Figure 4 As shown in (b), when D3D2D1 = 011, the lower plate of the second largest capacitor C in the reverse capacitor array switches from gnd to V aq , the connection of the lower plates of the other capacitors remains unchanged, and the switching energy consumed in this process is (3 / 64)CV REF 2 ; When D3D2D1=010, the lower plate of the second largest capacitor C in the forward capacitor array changes from V aq Switch to V CM , the connection of the lower plates of the other capacitors remains unchanged, and the switching energy consumed in this process is (1 / 64)CV REF 2 ; When D3D2D1 = 001, the lower plate of the second largest capacitor C in the reverse capacitor array switches from gnd to V aq , the connection of the lower plates of the other capacitors remains unchanged, and the switching energy consumed in this process is (1 / 64)CV REF 2 ; When D3D2D1 = 000, the lower plate of the second largest capacitor C in the forward capacitor array is connected from Vaq Switch to V CM , the lower plates of the other capacitors remain unchanged, and the switching energy consumed in this process is (3 / 64)CV REF 2 ; Next, the fourth comparison is performed to obtain D0. IN Greater than (15 / 16) V REF , then the output digital code D0 = 1; if V IN Greater than (7 / 8) V REF Less than or equal to (15 / 16) V REF , then the output digital code D0 = 0; if V IN Greater than (13 / 16) V REF Less than or equal to (7 / 8) V REF , the output digital code D0 = 1; if VIN is greater than (3 / 4) V REF If V is less than or equal to (13 / 16) VREF, the output digital code D0 = 0; IN Greater than (11 / 16) V REF Less than or equal to (3 / 4) V REF , then the output digital code D0 = 1; if V IN Greater than (5 / 8) V REF Less than or equal to (11 / 16) V REF , then the output digital code D0 = 0; if V IN Greater than (9 / 16) V REF Less than or equal to (5 / 8) V REF , then the output digital code D0 = 1; if V IN Greater than (1 / 2) V REF Less than or equal to (9 / 16) V REF , then the output digital code D0 = 0; if V IN Greater than (7 / 16) V REF Less than or equal to (1 / 2) V REF , then the output digital code D0 = 1; if V IN Greater than (3 / 8) V REF Less than or equal to (7 / 16) V REF , then the output digital code D0 = 0; if V IN Greater than (5 / 16) V REF Less than or equal to (3 / 8) V REF , then the output digital code D0 = 1; if V IN Greater than (1 / 4) V REF Less than or equal to (5 / 16) V REF , then the output digital code D0 = 0; if V INGreater than (3 / 16) V REF Less than or equal to (1 / 4) V REF , then the output digital code D0 = 1; if V IN Greater than (1 / 8) V REF Less than or equal to (3 / 16) V REF , then the output digital code D0 = 0; if V IN Greater than (1 / 16) V REF Less than or equal to (1 / 8) V REF , then the output digital code D0 = 1; if V IN Less than or equal to (1 / 16) V REF , then the output digital code D0 = 0; like Figure 5 As shown, taking a 10-bit successive approximation analog-to-digital converter as an example, the MATLAB simulation result diagram of the switching energy consumption changing with the digital output code during the conversion process.

[0016] like Figure 6 As shown in the figure, the change of DAC output voltage. Obviously, the output common-mode voltage continues to increase and finally exceeds V CM , approaching V REF .

[0017] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device.

[0018] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. An up-conversion successive approximation analog-to-digital converter and a switching method thereof, comprising a comparator, a DAC capacitor array and a control logic circuit, characterized in that: The comparator output is connected to a control logic circuit, The DAC capacitor array includes two parts: one is a forward capacitor array connected to the positive input terminal of the comparator, and the forward capacitor array is composed of a binary weight capacitor array; The second is a reverse capacitor array connected to the negative input terminal of the comparator, and the reverse capacitor array is composed of a binary weight capacitor array; The upper plate of the positive capacitor array is connected through the switch S P With V IN The lower plate of the positive capacitor array is connected to V CM , Vaq, gnd are connected; the upper plate of the reverse capacitor array is connected through the switch S N With V CM The lower plate of the reverse capacitor array is connected to V CM , Vaq, and gnd are connected.

2. A lower plate sampling successive approximation analog-to-digital converter according to claim 1, characterized in that: The forward capacitor array includes a total of 2 N-2 The unit capacitance is two bits less than the N bits of accuracy of the successive approximation analog-to-digital converter.

3. A bottom plate sampling successive approximation analog-to-digital converter according to claim 1, characterized in that: The reverse capacitor array includes a total of 2 N-2 The unit capacitance is two bits less than the N bits of accuracy of the successive approximation analog-to-digital converter.

4. An up-conversion successive approximation analog-to-digital converter and a switching method thereof, characterized in that: The specific implementation is: Sampling phase: Input signal V IN The sampling switch is turned on and connected to the upper plate of the forward capacitor array, and the lower plates of all capacitors in the forward capacitor array are connected to gnd; V CM The upper plate of the reverse capacitor array is connected to the upper plate of the reverse capacitor array through the conduction of the sampling switch, and the lower plates of all capacitors in the reverse capacitor array are connected to gnd; Comparison phase: First, S P , S N Disconnect, the connections of all capacitor bottom plates in the forward capacitor array and the reverse capacitor array remain unchanged, start the first comparison, and get the MSB; if V IN Greater than V REF / 2, then the lower plates of all capacitors in the reverse capacitor array are connected to Vaq, and the negative input voltage of the comparator is V DACN Increased V REF / 4, the connection of the lower plates of all capacitors in the forward capacitor array remains unchanged; conversely, the lower plates of all capacitors in the forward capacitor array are connected to Vaq, and the voltage at the positive input of the comparator V DACP Increased V REF / 4, the connections of the lower plates of all capacitors in the reverse capacitor array remain unchanged; Then start the second comparison; if V IN Greater than (3 / 4) V REF , then the lower plate connection of the largest capacitor in the reverse capacitor array is switched from Vaq to V CM , the lower plate connections of the remaining capacitors in the reverse capacitor array remain unchanged, V DACN Increased V REF / 8, the connection of all capacitor bottom plates in the forward capacitor array remains unchanged; if V IN Greater than V REF / 2 and less than or equal to (3 / 4) V REF , then all capacitor connections in the reverse capacitor array remain unchanged, the lower plate connection of the largest capacitor in the forward capacitor array is switched from gnd to Vaq, and the lower plate connections of the remaining capacitors in the forward capacitor array remain unchanged, V DACP Increased V REF / 8; if V IN Greater than V REF / 4 and less than or equal to V REF / 2, the connection of the bottom plate of all capacitors in the forward capacitor array remains unchanged, and the connection of the bottom plate of the largest capacitor in the reverse capacitor array is switched from gnd to V aq , the lower plate connections of the remaining capacitors in the reverse capacitor array remain unchanged, V DACN Increased V REF / 8; if V INP Less than or equal to V REF / 4, then the lower plate connections of all capacitors in the reverse capacitor array remain unchanged, and the lower plate connection of the largest capacitor in the forward capacitor array is switched from Vaq to V CM , the lower plates of all capacitors in the forward capacitor array remain connected unchanged, V DACP Increased V REF / 8; Then the third comparison is performed; if V INP Greater than (7 / 8) V REF , then the lower plate of the second largest capacitor in the reverse capacitor array switches from Vaq to V CM , the other capacitor bottom plates of the reverse capacitor array remain connected unchanged, V DACN Increased V REF / 16, the lower plate connections of all capacitors in the forward capacitor array remain unchanged; if V IN Greater than (3 / 4) V REF And less than or equal to (7 / 8)V REF , then the lower plate voltage of the second largest capacitor in the forward capacitor array switches from gnd to Vaq, V DACP Increased V REF / 16, the lower plate connections of other capacitors in the forward capacitor array remain unchanged, and the lower plate connections of all capacitors in the reverse capacitor array remain unchanged; if V IN Greater than (5 / 8) V REF And less than or equal to (3 / 4) V REF , then the lower plate of the second largest capacitor in the reverse capacitor array switches from Vaq to V CM , the other capacitor connections in the reverse capacitor array remain unchanged, V DACN Increased V REF / 16, the voltage on the lower plate of the forward capacitor array remains unchanged; if V IN Greater than (1 / 2) V REF And less than or equal to (5 / 8)V REF , then the lower plate voltage of the second largest capacitor in the forward capacitor array switches from gnd to Vaq, and the other capacitor connections in the forward capacitor array remain unchanged, V DACP Increased V REF / 16, the lower plate connection of the reverse capacitor array remains unchanged; if V IN Greater than (3 / 8) V REF And less than or equal to (1 / 2) V REF , then the lower plate of the second largest capacitor in the reverse capacitor array switches from gnd to Vaq, and the other capacitors in the reverse capacitor array remain connected unchanged, V DACN Increased V REF / 16, the lower plate connection of the forward capacitor array remains unchanged; if V IN Greater than (1 / 4) V REF And less than or equal to (3 / 8)V REF , the lower plate voltage of the second largest capacitor in the forward capacitor array switches from Vaq to V CM , the other capacitor connections in the forward capacitor array remain unchanged, V DACP Increased V REF / 16, the lower plate connection of the reverse capacitor array remains unchanged; if V INP Greater than (1 / 8) V REF And less than or equal to (1 / 4) V REF , then the lower plate of the second largest capacitor in the reverse capacitor array switches from gnd to Vaq, and the other capacitors in the reverse capacitor array remain connected unchanged, V DACN Increased V REF / 16, the lower plate connection of the forward capacitor array remains unchanged; if V IN Less than or equal to (1 / 8) V REF , the lower plate voltage of the second largest capacitor in the forward capacitor array switches from Vaq to V CM , the other capacitor bottom plates of the forward capacitor array remain connected unchanged, V DACP Increased V REF / 16, the lower plate connection of the reverse capacitor array remains unchanged; Next, the fourth comparison is performed, and the switching process is similar to the third one, until the LSB is obtained and the analog-to-digital conversion is completed.

Images