A low temperature drift delay circuit for asynchronous timing

Abstract

The application discloses a low-temperature drift delay circuit for asynchronous timing, and relates to the technical field of analog integrated circuits, and aims at solving the problem of the conversion precision of a SAR ADC asynchronous timing circuit being reduced due to the influence of temperature on an existing delay circuit. At least, the low-temperature drift delay circuit comprises a temperature detection coding circuit, an inverter chain circuit and an adjusting tube circuit. The adjusting tube circuit is connected with the inverter chain circuit and the temperature detection coding circuit respectively, and the adjusting tube circuit comprises a plurality of parallelly connected NMOS tubes. The temperature detection coding circuit at least comprises a temperature sensor, a flash analog-digital converter and a digital coding logic circuit. The flash analog-digital converter is used for converting a temperature voltage signal into a thermometer code. The digital coding logic circuit is used for converting the thermometer code into a first control code, and the first control code is used for controlling the conduction and the cut-off of the NMOS tubes in the adjusting tube circuit. The low-temperature drift delay circuit provided by the application can adjust the delay time according to the temperature, and improve the conversion precision of the asynchronous timing circuit.

Description

Technical Field

[0001] This invention relates to the field of analog integrated circuit technology, and more particularly to a low-temperature drift delay circuit for asynchronous timing. Background Technology

[0002] The control logic of a SAR ADC successive approximation analog-to-digital converter (ADC) latches the digital code generated by the comparator output in each comparison cycle using a latch, and outputs the final digital code after one sampling cycle. The control logic is mainly divided into synchronous control logic and asynchronous control logic. Asynchronous control logic uses a low-frequency signal generated internally by the circuit to generate a clock control signal that matches the operating frequency of the ADC's capacitor array module and comparator module based on combinational logic. This reduces the wasted time in each comparison cycle and lowers the overall system power consumption. The delay module in the asynchronous control logic circuit provides sufficient setup time for the capacitor DAC. Its delay time directly determines the conversion frequency. Traditional delay modules use multiple inverters cascaded to achieve the delay effect, but this type of delay unit is greatly affected by temperature. As the temperature rises, the lattice vibration amplitude of the MOS device increases, leading to a decrease in electron mobility and a reduction in signal setup speed. MOSFET on-resistance is typically thermally dependent, with a positive temperature coefficient. At high temperatures, the on-resistance increases, also increasing the signal setup time. Therefore, the delay time of the delay module is longer at high temperatures than at room temperature.

[0003] The ambient temperature and internal heat generated by the chip can cause the ADC to operate in a high-temperature environment. Since the delay module controls the conversion frequency of the SAR ADC, the increased delay at high temperatures will increase the SAR ADC conversion time. This may result in the inability to complete all conversion cycles within the designed comparison time, leading to a decrease in conversion accuracy. Current circuit simulation designs typically ensure that all conversion cycles can be completed under high-temperature conditions. At room temperature and low temperature, the delay time of the delay module is shorter, resulting in a faster conversion rate and allowing all comparison cycles to be completed in a shorter time. However, at room temperature and low temperature, the settling time of the small signal in the capacitor DAC is insufficient, affecting conversion accuracy. Summary of the Invention

[0004] The purpose of this invention is to provide a low-temperature drift delay circuit for asynchronous timing, which solves the problem that the conversion accuracy of SAR ADC asynchronous timing circuits is reduced due to the influence of temperature on existing delay circuits.

[0005] To achieve the above objectives, the present invention provides the following technical solution:

[0006] A low-temperature drift delay circuit for asynchronous timing includes at least: a temperature detection encoding circuit, an inverter chain circuit, and a regulating transistor circuit;

[0007] The regulating transistor circuit is connected to the inverter chain circuit and the temperature detection encoding circuit respectively, and the regulating transistor circuit includes multiple NMOS transistors connected in parallel;

[0008] The temperature detection encoding circuit includes at least a temperature sensor, a flash memory analog-to-digital converter, and a digital encoding logic circuit; the temperature sensor is connected to the input terminal of the flash memory analog-to-digital converter, the output terminal of the flash memory analog-to-digital converter is connected to the input terminal of the digital encoding logic circuit, and the output terminal of the digital encoding logic circuit is connected to the regulating tube circuit.

[0009] The flash memory analog-to-digital converter is used to convert the temperature voltage signal detected by the temperature sensor into a thermometer code.

[0010] The digital encoding logic circuit is used to convert the thermometer code into a first control code; the first control code is used to control the conduction and cutoff of the NMOS transistors in the regulating transistor circuit; the smaller the number of NMOS transistors on, the shorter the delay time of the low temperature drift delay circuit.

[0011] Compared with the prior art, the present invention provides a low-temperature drift delay circuit for asynchronous timing, comprising at least: a temperature detection encoding circuit, an inverter chain circuit, and a regulating transistor circuit; the regulating transistor circuit is connected to both the inverter chain circuit and the temperature detection encoding circuit, and includes multiple NMOS transistors connected in parallel; the temperature detection encoding circuit includes at least a temperature sensor, a flash memory analog-to-digital converter (A / D converter), and a digital encoding logic circuit; the temperature sensor is connected to the input terminal of the flash memory A / D converter, the output terminal of the flash memory A / D converter is connected to the input terminal of the digital encoding logic circuit, and the output terminal of the digital encoding logic circuit is connected to the regulating transistor circuit; the flash memory A / D converter is used to convert the temperature voltage signal detected by the temperature sensor into a thermometer code; the digital encoding logic circuit is used to convert the thermometer code into a first control code; this application monitors temperature changes using a temperature sensor, uses a flash memory A / D converter and a digital encoding logic circuit to convert the temperature signal into a control code, and adjusts the delay time by controlling the number of NMOS transistors in the regulating transistor circuit using the control code, thus realizing a delay circuit whose delay time can be adjusted according to temperature, avoiding the influence of temperature on the delay circuit in the asynchronous logic circuit of the SAR ADC, thereby improving SAR performance. Conversion accuracy of ADC asynchronous sequential circuit.

[0012] Optionally, the temperature detection encoding circuit further includes a unity-gain buffer, the input of which is connected to the output of the temperature sensor, and the output of which is connected to the input of the flash memory analog-to-digital converter.

[0013] Optionally, the flash memory analog-to-digital converter includes multiple dynamic comparators and a reference voltage generation circuit disposed between the power supply and the multiple dynamic comparators. The first input terminal of each dynamic comparator is connected to the reference voltage generation circuit, and the second input terminal of the dynamic comparator is connected to the output terminal of the unity-gain buffer. The dynamic comparator includes a comparator and a latch. The output terminal of the comparator is connected to the input terminal of the latch, and the output terminal of the latch is connected to the input terminal of the digital encoding logic circuit. The clock signal input terminal of the comparator is connected to a first clock signal, and the clock signal input terminal of the latch is connected to a second clock signal. The rising edge of the second clock signal arrives later than the rising edge of the first clock signal.

[0014] Optionally, the inverter chain circuit includes multiple inverters connected in parallel, the inverter chain circuit includes a first inverter and a second inverter, and the regulating transistor circuit includes a first regulating transistor and a second regulating transistor; both the first regulating transistor and the second regulating transistor include multiple NMOS transistors connected in parallel; the number of NMOS transistors in the first regulating transistor is the same as the number of NMOS transistors in the second regulating transistor; the first inverter is composed of a first PMOS transistor and a first NMOS transistor; the second inverter is composed of a second PMOS transistor and a second NMOS transistor; the drain of the first regulating transistor is connected to the drain of the first PMOS transistor, and the source of the first regulating transistor is connected to the drain of the first NMOS transistor; the gate of the first regulating transistor is connected to the temperature detection encoding circuit, the drain of the second regulating transistor is connected to the drain of the second PMOS transistor, and the source of the second regulating transistor is connected to the drain of the second NMOS transistor; the gate of the second regulating transistor is connected to the temperature detection encoding circuit.

[0015] Optionally, the low-temperature drift delay circuit further includes a first RC circuit and a second RC circuit, and the inverter chain circuit further includes a third inverter and a fourth inverter; the third inverter is composed of a third PMOS transistor and a third NMOS transistor, the fourth inverter is composed of a fourth PMOS transistor and a fourth NMOS transistor, the first RC circuit is connected to the third PMOS transistor and the third NMOS transistor respectively, and the second RC circuit is connected to the fourth PMOS transistor and the fourth NMOS transistor respectively.

[0016] Optionally, the cryogenic drift delay circuit further includes a digital trimming circuit, and the adjustment transistor circuit further includes a third adjustment transistor and a fourth adjustment transistor; the third adjustment transistor and the fourth adjustment transistor each include multiple NMOS transistors connected in parallel, and the inverter chain circuit further includes a fifth inverter and a sixth inverter, the fifth inverter being composed of a fifth PMOS transistor and a fifth NMOS transistor, and the sixth inverter being composed of a sixth PMOS transistor and a sixth NMOS transistor. The digital trimming circuit is used to configure a second control code according to the output waveform of the cryogenic drift delay circuit to control the number of NMOS transistors turned on in the third adjustment transistor and the fourth adjustment transistor.

[0017] Optionally, the reference voltage generation circuit includes a reset switch, a first resistor, a second resistor, a third resistor, and a fourth resistor connected in series. The reset switch is connected to a power supply, and the fourth resistor is grounded. Multiple dynamic comparators include a first dynamic comparator, a second dynamic comparator, and a third dynamic comparator. The first input terminal of the first dynamic comparator is connected to the wire between the first and second resistors. The first input terminal of the second dynamic comparator is connected to the wire between the second and third resistors. The first input terminal of the third dynamic comparator is connected to the wire between the third and fourth resistors. The switching frequency of the reset switch is the same as the frequency of the first clock signal, and the reset switch is turned on before the rising edge of the first clock signal arrives.

[0018] Optionally, the first RC circuit includes a fifth resistor, a sixth resistor, and a first capacitor; the second RC circuit includes a seventh resistor, an eighth resistor, and a second capacitor; one end of the fifth resistor is connected to the drain of the third PMOS transistor; the other end of the fifth resistor is connected to one end of the sixth resistor, the gate of the fourth PMOS transistor, and one end of the first capacitor; the other end of the sixth resistor is connected to the drain of the third NMOS transistor; the gate of the third NMOS transistor is connected to the gate of the third PMOS transistor; the wire between the gate of the third NMOS transistor and the gate of the third PMOS transistor is connected to the output of the second inverter; the third NMOS transistor's... The source of the third PMOS transistor is grounded, the source of the third PMOS transistor is connected to the power supply, and the other end of the first capacitor is grounded; one end of the seventh resistor is connected to the drain of the fourth PMOS transistor, the other end of the seventh resistor is connected to one end of the eighth resistor and one end of the second capacitor, the other end of the eighth resistor is connected to the drain of the fourth NMOS transistor, the gate of the fourth NMOS transistor is connected to the gate of the fourth PMOS transistor, the wire between the gate of the fourth NMOS transistor and the gate of the fourth PMOS transistor is connected to the output of the third inverter, the source of the fourth NMOS transistor is grounded, the source of the fourth PMOS transistor is connected to the power supply, and the other end of the second capacitor is grounded.

[0019] Optionally, the temperature sensor is used to generate a temperature voltage signal that varies with temperature based on the characteristic that the voltage between the base and emitter of the transistor is negatively correlated with temperature.

[0020] Optionally, both inputs of each dynamic comparator can be connected to a capacitor to ground. Attached Figure Description

[0021] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings:

[0022] Figure 1 This is a schematic diagram of the structure of the asynchronous control logic circuit of SARADC in the prior art;

[0023] Figure 2 The output waveform of the inverter chain delay circuit in the prior art varies with temperature.

[0024] Figure 3 A schematic diagram of a low-temperature drift delay circuit for asynchronous timing provided by the present invention;

[0025] Figure 4 A schematic diagram of the temperature detection encoding circuit provided by the present invention;

[0026] Figure 5 The timing diagram of the Flash ADC circuit provided by this invention;

[0027] Figure 6 A comparison chart of the delay time versus temperature provided by the present invention.

[0028] Figure label:

[0029] 1-Temperature detection encoding circuit, 2-First RC circuit, 3-Second RC circuit, 4-Digital adjustment circuit, 5-Temperature sensor, 6-Unity gain buffer, 7-Flash memory analog-to-digital converter, 71-Reference voltage generation circuit, 72-First dynamic comparator, 73-Second dynamic comparator, 74-Third dynamic comparator, 8-Digital encoding logic circuit, MN1-First regulating transistor, MN2-Second regulating transistor, MN3-Third regulating transistor, MN4-Fourth regulating transistor, M1-First NMOS transistor, M7-First PMOS transistor, M2-Second NMOS transistor, M8-Second PMOS transistor, M3-Third NMOS transistor, M9-Third PMOS transistor, M4-Fourth NMOS transistor, M10-Fourth PMOS transistor, M5-Fifth NMOS transistor, M11-Fifth PMOS transistor, M6-Sixth NMOS transistor, M12-Sixth PMOS transistor, RST-Reset switch. Detailed Implementation

[0030] To facilitate a clear description of the technical solutions in the embodiments of the present invention, the terms "first" and "second" are used to distinguish identical or similar items with essentially the same function and effect. For example, the first threshold and the second threshold are merely used to distinguish different thresholds and do not limit their order. Those skilled in the art will understand that the terms "first" and "second" do not limit the quantity or execution order, and that the terms "first" and "second" are not necessarily different.

[0031] It should be noted that in this invention, the terms "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in this invention should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0032] In this invention, "at least one" refers to one or more, and "more than one" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can represent: a, b, c, a combination of a and b, a combination of a and c, a combination of b and c, or a, b, and c, where a, b, and c can be single or multiple.

[0033] Before introducing the embodiments of the present invention, the relevant terms involved in the embodiments of the present invention are first defined as follows:

[0034] A Flash ADC, or Flash Memory Analog-to-Digital Converter, is a high-speed analog-to-digital converter that uses comparators and encoders to convert an input analog signal into a binary number in one step. It contains a series of comparators, each associated with a reference voltage. When the input analog signal is compared with the reference voltage, each comparator produces a digital output representing the relationship between the input signal and the reference voltage. These digital outputs are then encoded by the encoder, ultimately outputting a binary number representing the magnitude of the input analog signal.

[0035] Figure 1In existing SAR ADC asynchronous control logic circuits, the comparator output signals VP and VN are always one high and one low level. After reset, they are high. Performing a NAND operation on them can serve as the clock signal for asynchronous timing. Valid is low during reset and becomes high after the comparator outputs its result. NCLKs is the system sampling clock signal; its low level resets the control logic circuit. Valid sequentially triggers each D flip-flop to generate output signals Clk1-Clkn, which are used to control the digital logic circuit. Clkc is the clock signal controlling the comparator's comparison and reset; after all comparison cycles are completed, Clkc outputs a low level.

[0036] The delay module in the above structure allows sufficient setup time for the capacitor DAC. Its delay time directly determines the conversion frequency, therefore, the impact of various PVT conditions on the delay must be strictly considered. Traditional delay modules achieve the delay effect by cascading multiple inverters, but this type of delay unit is significantly affected by temperature. As temperature increases, the lattice vibration amplitude of the MOS device increases, leading to a decrease in electron mobility and reducing the signal setup speed. MOSFET on-resistance is typically heat-dependent, with a positive temperature coefficient; at high temperatures, the on-resistance increases, also increasing the signal setup time. Therefore, the delay time of the delay module will be longer at high temperatures than at room temperature. Figure 2 It can be seen that the delay time of the delay module of the common inverter chain structure varies greatly with temperature, with the maximum deviation reaching 23%.

[0037] The ambient temperature outside the chip and the heat generated during chip operation may cause the ADC to operate in a high-temperature environment. Since the delay module controls the conversion frequency of the SAR ADC, the increased delay at high temperatures will increase the conversion time of the SAR ADC. This may result in the inability to complete the conversion of all cycles within the designed comparison time, leading to a decrease in conversion accuracy.

[0038] To address the aforementioned issues, this invention proposes a low-temperature drift delay circuit for asynchronous timing, applied in the asynchronous timing control logic circuit of a SARADC. It uses a temperature sensor to monitor temperature changes in real time, converting the temperature signal into digital code to control the number of MOSFETs on, thereby achieving the low-temperature drift delay circuit. Furthermore, the delay time can be manually adjusted via register configuration. A detailed explanation follows.

[0039] See Figure 3 and Figure 4This invention discloses a low-temperature drift delay circuit for asynchronous timing, comprising a temperature detection encoding circuit 1, an inverter chain circuit, an adjustment transistor circuit, a first RC circuit 2, a second RC circuit 3, and a digital adjustment circuit 4. The adjustment transistor circuit is connected to both the inverter chain circuit and the temperature detection encoding circuit 1, and includes multiple parallel NMOS transistors. The adjustment transistor circuit may include a first adjustment transistor MN1, a second adjustment transistor MN2, a third adjustment transistor MN3, and a fourth adjustment transistor MN4. Each of the first, second, third, and fourth adjustment transistors includes multiple parallel NMOS transistors of the same size. The number of NMOS transistors in the first, second, third, and fourth adjustment transistors is the same. When the number of NMOS transistors conducting increases, the parasitic capacitance at point C1 of the inverter increases, slowing down the signal setup time and increasing the delay time of the inverter chain circuit, thereby increasing the delay of the low-temperature drift delay circuit. When the first control code Vd<7:0> is 00000001, the regulating transistor circuit is in the minimum delay state, and consequently, the low-temperature drift delay circuit is in the minimum delay state. When the first control code Vd<7:0> is 11111111, the regulating transistor circuit is in the maximum delay state, and consequently, the low-temperature drift delay circuit is in the maximum delay state. It's important to understand that in the diagram, connected wires are indicated by black dots; the absence of black dots indicates that the two wires are not connected.

[0040] The temperature detection encoding circuit 1 includes a temperature sensor 5, a flash memory analog-to-digital converter 7, and a digital encoding logic circuit 8; the temperature sensor 5 is connected to the input terminal of the flash memory analog-to-digital converter 7, the output terminal of the flash memory analog-to-digital converter 7 is connected to the input terminal of the digital encoding logic circuit 8, and the output terminal of the digital encoding logic circuit 8 is connected to the regulating tube circuit.

[0041] Flash memory analog-to-digital converter 7 is used to convert the temperature voltage signal detected by temperature sensor 5 into thermometer code;

[0042] The digital encoding logic circuit 8 is used to convert the thermometer code into the first control code; the first control code is used to control the conduction and cutoff of the NMOS transistors in the first and second regulating transistors of the regulating transistor circuit; the smaller the number of NMOS transistors on, the shorter the delay time of the low temperature drift delay circuit.

[0043] In the above structure, the thermometer codes obtained by the flash memory analog-to-digital converter 7 are "000", "001", "011" and "111".

[0044] This application monitors temperature changes using a temperature sensor and converts the temperature signal into a control code using a flash memory analog-to-digital converter and digital encoding logic circuit. The delay time is adjusted by controlling the number of NMOS transistors in the regulating transistor circuit using the control code. This achieves a delay circuit where the delay time can be adjusted according to temperature, avoiding the influence of temperature on the delay circuit in the asynchronous logic circuit of the SAR ADC, thereby improving the conversion accuracy of the asynchronous timing circuit of the SAR ADC.

[0045] As an alternative, the temperature detection encoding circuit 1 described above may also include a unity-gain buffer 6. The input terminal of the unity-gain buffer 6 is connected to the output terminal of the temperature sensor 5, and the output terminal of the unity-gain buffer 6 is connected to the input terminal of the flash memory analog-to-digital converter 7. Connecting the output terminal of the temperature sensor 5 to the unity-gain buffer can improve the load-carrying capacity.

[0046] See Figure 3 The inverter chain circuit in the above structure includes multiple inverters connected in parallel. The inverter chain circuit may include a first inverter, a second inverter, a third inverter, a fourth inverter, a fifth inverter, and a sixth inverter. The number of inverters in the inverter chain can be set according to requirements. The first inverter consists of a first PMOS transistor M7 and a first NMOS transistor M1; the second inverter consists of a second PMOS transistor M8 and a second NMOS transistor M2; the third inverter consists of a third PMOS transistor M9 and a third NMOS transistor M3; the fourth inverter consists of a fourth PMOS transistor M10 and a fourth NMOS transistor M4; and the fifth inverter... The inverter consists of a fifth PMOS transistor M11 and a fifth NMOS transistor M5, and the sixth inverter consists of a sixth PMOS transistor M12 and a sixth NMOS transistor M6. The drain of the first regulating transistor MN1 is connected to the drain of the first PMOS transistor M7, and the source of the first regulating transistor MN1 is connected to the drain of the first NMOS transistor M1. The gate of the first regulating transistor MN1 is connected to the temperature detection encoding circuit 1. The drain of the second regulating transistor MN2 is connected to the drain of the second PMOS transistor M8, and the source of the second regulating transistor MN2 is connected to the drain of the second NMOS transistor M2. The gate of the second regulating transistor MN2 is connected to the temperature detection encoding circuit 1. The first RC circuit 2 is connected to the third PMOS transistor M9 and the third NMOS transistor M3, respectively, and the second RC circuit 3 is connected to the fourth PMOS transistor M10 and the fourth NMOS transistor M4, respectively. The sources of the first PMOS transistor M7, the second PMOS transistor M8, the third PMOS transistor M9, the fourth PMOS transistor M10, the fifth PMOS transistor M11, and the sixth PMOS transistor M12 are connected to the power supply, while the sources of the first NMOS transistor M1, the second NMOS transistor M2, the third NMOS transistor M3, the fourth NMOS transistor M4, the fifth NMOS transistor M5, and the sixth NMOS transistor M6 are grounded.

[0047] In the above structure, the first RC circuit 2 includes a fifth resistor R5, a sixth resistor R6, and a first capacitor Ca; the second RC circuit 3 includes a seventh resistor R7, an eighth resistor R8, and a second capacitor Cb; one end of the fifth resistor R5 is connected to the drain of the third PMOS transistor M9; the other end of the fifth resistor R5 is connected to one end of the sixth resistor R6, one end of the first capacitor Ca, and the wire between the gate of the fourth PMOS transistor M10 and the gate of the fourth NMOS transistor M4; the other end of the sixth resistor R6 is connected to the drain of the third NMOS transistor M3; the gate of the third NMOS transistor M3 is connected to the gate of the third PMOS transistor M9; the output terminal of the second inverter is connected to the gate of the third NMOS transistor M3 and the gate of the third PMOS transistor M9. The wires connecting the gates of transistor M9 are connected, and the other end of the first capacitor Ca is grounded; one end of the seventh resistor R7 is connected to the drain of the fourth PMOS transistor M10, and the other end of the seventh resistor R7 is connected to one end of the eighth resistor R8 and one end of the second capacitor Cb, respectively; the other end of the seventh resistor R7 is connected to the wire between the gates of the fifth PMOS transistor M11 and the fifth NMOS transistor M5, and the other end of the eighth resistor R8 is connected to the drain of the fourth NMOS transistor M4. The gate of the fourth NMOS transistor M4 is connected to the gate of the fourth PMOS transistor M10, and the wire between the gates of the fourth NMOS transistor M4 and the gate of the fourth PMOS transistor M10 is connected to the output of the third inverter, and the other end of the second capacitor Cb is grounded. The gates of the third regulating transistor MN3 and the fourth regulating transistor MN4 are connected to the output of the digital trimming circuit 4. The drain of the fifth PMOS transistor M11 is connected to the drain of the third regulating transistor MN3. The source of the third regulating transistor MN3 is connected to the drain of the fifth NMOS transistor M5. The gate of the fifth PMOS transistor M11 is connected to the gate of the fifth NMOS transistor M5. The wire between the gates of the fifth PMOS transistor M11 and the fifth NMOS transistor M5 is connected to the output of the fourth inverter. The drain of the sixth PMOS transistor M12 is connected to the drain of the fourth regulating transistor MN4. The source of the fourth regulating transistor MN4 is connected to the source of the sixth NMOS transistor M6. The gate of the sixth PMOS transistor M12 is connected to the gate of the sixth NMOS transistor M6. The wire between the gates of the sixth PMOS transistor M12 and the sixth NMOS transistor M6 is connected to the output of the fifth inverter.

[0048] In the above structure, the total resistance of the first RC circuit 2 is greater than the on-resistance of the third PMOS transistor M9 and the third NMOS transistor M3, and the total resistance of the second RC circuit 3 is greater than the on-resistance of the fourth PMOS transistor M10 and the fourth NMOS transistor M4. Adding RC circuits to the delay circuit composed of the inverter chain circuit improves the stability of the delay to some extent. RC devices change little with temperature; when RC is large, the signal setup time at the inverter output is mainly determined by RC, reducing the impact of temperature on the delay circuit.

[0049] The digital adjustment circuit 4 in the above structure is used to configure the second control code according to the output waveform of the low-temperature drift delay circuit. The second control code is used to control the number of NMOS transistors turned on in the third and fourth adjustment transistors. The digital adjustment circuit uses a register to configure the control code input to the encoding circuit, and also uses NMOS transistors to adjust the delay time. When changes in the PVT conditions of the SAR ADC affect the delay circuit, it can provide a small-scale delay adjustment.

[0050] The flash memory analog-to-digital converter 7 in the above structure includes multiple dynamic comparators and a reference voltage generation circuit disposed between the power supply and the multiple dynamic comparators. The first input terminal of each dynamic comparator is connected to the reference voltage generation circuit, and the second input terminal of the dynamic comparator is connected to the output terminal of the unity-gain buffer. The dynamic comparator includes a comparator and a latch. The output terminal of the comparator is connected to the input terminal of the latch, and the output terminal of the latch is connected to the input terminal of the digital encoding logic circuit. The clock signal input terminal of the comparator is connected to the first clock signal CLK1, and the clock signal input terminal of the latch is connected to the second clock signal CLK2.

[0051] The reference voltage generation circuit in the above structure includes a reset switch RST, a first resistor R1, a second resistor R2, a third resistor R3, and a fourth resistor R4 connected in series. The reset switch RST is connected to the power supply, and the fourth resistor R4 is grounded. Multiple dynamic comparators include a first dynamic comparator 72, a second dynamic comparator 73, and a third dynamic comparator 74. The first input terminal of the first dynamic comparator is connected to the wire between the first resistor R1 and the second resistor R2. The first input terminal of the second dynamic comparator is connected to the wire between the second resistor R2 and the third resistor R3. The first input terminal of the third dynamic comparator is connected to the wire between the third resistor R3 and the fourth resistor R4.

[0052] like Figure 5 As shown, since temperature changes are generally slow, a low-speed clock CLK1 is used to limit the sampling rate of the Flash ADC in order to save power. The latch can only open after the voltage signal comparison is complete, so CLK1 needs a delay before it can be used to control the latch switch. That is, after delaying CLK1 to obtain CLK2, CLK2 controls the latch switch. The switching frequency of the reset switch RST is the same as the frequency of the first clock signal CLK1. The reset switch signal is turned on before the rising edge of the first clock signal CLK1 arrives, generating a stable Vref reference voltage. The rising edge of the second clock signal CLK2 arrives later than the rising edge of the first clock signal CLK1.

[0053] The temperature sensor in the above structure is based on the voltage V between the base and emitter of the transistor.BE Its characteristic of being negatively correlated with temperature generates a temperature voltage signal that changes approximately linearly with temperature.

[0054] In the above structure, both input terminals of the comparator in each dynamic comparator are connected to ground, which can effectively reduce comparator kickback noise.

[0055] In the specific implementation process, the circuit first automatically detects the chip temperature and inputs the temperature voltage signal to the flash memory analog-to-digital converter (FADC). The FADC converts the temperature voltage signal into a 3-bit digital signal, which is then encoded by the digital encoding logic circuit to output an 8-bit control code, controlling the conduction and cutoff of the NMOS transistors in MN1 and MN2. The FlashADC uses a resistor string R1-R4 to generate a stable reference voltage. A dynamic comparator compares the temperature voltage signal with the reference voltage, avoiding DC power consumption. Normally, the comparator's output voltage is coupled to the input through parasitic capacitance, causing voltage fluctuations at the comparator input and generating significant kickback noise, affecting the comparator's judgment of the input voltage magnitude. By connecting capacitors to ground at both inputs of the comparator, the kickback noise can be effectively reduced. The comparison result output by the comparator is latched and held until the next detection cycle. The comparison result D2-D0 is finally input to the digital encoding logic circuit to generate an 8-bit first control code. At high temperatures, the delay of the MOSFETs in the inverter chain increases. Therefore, to keep the regulating transistors in a low-delay state, the first control code "00000001" is needed. At low temperatures, the MOSFET delay is small, and the asynchronous timing comparison period decreases. To ensure the SAR ADC fully utilizes the designed comparison phase time, the number of regulating transistors turned on is increased to improve the delay time; that is, the first control code is "11111111". The possible operating temperature range of the chip is divided into four temperature zones. The number of NMOS transistors turned on and the size of the turned-on NMOS transistors are determined based on the simulated delay time of the delay module in each zone. For example, the possible operating temperature ranges of the chip can be: -40~0℃, 0~50℃, 50~100℃, and 100~130℃. The first control code for the temperature range of -40 to 0℃ is: 11111111; the first control code for the temperature range of 0 to 50℃ is: 00111111; the first control code for the temperature range of 50 to 100℃ is: 00001111; and the first control code for the temperature range of 100 to 130℃ is: 00000001.

[0056] like Figure 6As shown, the delay time of a traditional inverter chain delay circuit is positively correlated with temperature, with a deviation of 23.6% and a variance of 0.5. The delay circuit of this invention, after being adjusted by a temperature detection encoding circuit, exhibits a reduced delay time variation with temperature, with a maximum deviation of 8.9% and a variance of only 0.23. This invention's delay circuit demonstrates good low-temperature drift performance, enabling it to generate a relatively stable conversion frequency under various temperature conditions when used in SAR ADC asynchronous timing, fully utilizing the designed comparison time. Furthermore, when other factors affect the delay time, the digital adjustment circuit can perform foreground adjustment and calibration, keeping the delay time within a reasonable range.

[0057] As can be seen from the above structure and specific implementation, the advantages of the low-temperature drift delay circuit for asynchronous timing of the present invention include: 1. It has good low-temperature drift characteristics, with the delay time changing little with temperature, and the maximum deviation is only 8.9%, making it very suitable for controlling the conversion speed in SAR ADC asynchronous timing. 2. The delay circuit is simple and efficient, using fewer MOS transistors, requiring only fewer hardware resources to achieve a stable delay time, reducing adjustment costs. 3. Considering power consumption, the delay circuit reduces the temperature detection frequency and uses a reset switch to control the current consumption of the FlashADC resistor string. When no temperature detection is performed, the switch is open, reducing the power consumption of the temperature detection circuit. 4. The addition of an RC circuit to the inverter chain delay circuit reduces the degree to which the inverter chain delay circuit is affected by temperature, further improving the stability of the delay circuit of the present invention.

[0058] Although the invention has been described herein in conjunction with various embodiments, those skilled in the art will understand and implement other variations of the disclosed embodiments by reviewing the accompanying drawings, the disclosure, and the appended claims in carrying out the claimed invention. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality. A single processor or other unit can implement several functions listed in the claims. While different dependent claims may recite certain measures, this does not mean that these measures cannot be combined to produce good results.

[0059] Although the invention has been described in conjunction with specific features and embodiments, it is obvious that various modifications and combinations can be made therein without departing from the spirit and scope of the invention. Accordingly, this specification and drawings are merely exemplary descriptions of the invention as defined by the appended claims, and are considered to cover any and all modifications, variations, combinations, or equivalents within the scope of the invention. Clearly, those skilled in the art can make various alterations and modifications to the invention without departing from its spirit and scope. Thus, if such modifications and modifications of the invention fall within the scope of the claims and their equivalents, the invention is also intended to include such modifications and modifications.

Claims

1. A low temperature drift delay circuit for asynchronous timing, characterized by At least comprising: temperature detection encoding circuit, inverter chain circuit and regulating tube circuit; The regulating tube circuit is connected with the inverter chain circuit and the temperature detection encoding circuit respectively, and the regulating tube circuit comprises a plurality of parallelly connected NMOS tubes; The inverter chain circuit comprises a plurality of parallelly connected inverters, the inverter chain circuit comprises a first inverter and a second inverter, the regulating tube circuit comprises a first regulating tube and a second regulating tube, the first regulating tube and the second regulating tube each comprise a plurality of parallelly connected NMOS tubes, the number of NMOS tubes in the first regulating tube is the same as that in the second regulating tube, the first inverter is composed of a first PMOS tube and a first NMOS tube, the second inverter is composed of a second PMOS tube and a second NMOS tube, the drain of the first regulating tube is connected with the drain of the first PMOS tube, the source of the first regulating tube is connected with the drain of the first NMOS tube, the gate of the first regulating tube is connected with the temperature detection encoding circuit, the drain of the second regulating tube is connected with the drain of the second PMOS tube, the source of the second regulating tube is connected with the drain of the second NMOS tube, and the gate of the second regulating tube is connected with the temperature detection encoding circuit; The temperature detection encoding circuit at least comprises a temperature sensor, a flash analog-digital converter and a digital encoding logic circuit, the temperature sensor is connected with the input end of the flash analog-digital converter, the output end of the flash analog-digital converter is connected with the input end of the digital encoding logic circuit, and the output end of the digital encoding logic circuit is connected with the regulating tube circuit; The flash analog-digital converter is used for converting the temperature voltage signal detected by the temperature sensor into a thermometer code; The digital encoding logic circuit is used for converting the thermometer code into a first control code, the first control code is used for controlling the conduction and cutoff of the NMOS tubes in the regulating tube circuit, and the smaller the number of the conduction of the NMOS tubes is, the smaller the delay time of the low temperature drift delay circuit is.

2. The low temperature drift delay circuit for asynchronous timing of claim 1, wherein, The temperature detection encoding circuit further comprises a unit gain buffer, the input end of the unit gain buffer is connected with the output end of the temperature sensor, and the output end of the unit gain buffer is connected with the input end of the flash analog-digital converter.

3. The low temperature drift delay circuit for asynchronous timing of claim 2, wherein, The flash analog-digital converter comprises a plurality of dynamic comparators and a reference voltage generating circuit arranged between a power supply and the plurality of dynamic comparators, the first input end of each dynamic comparator is connected with the reference voltage generating circuit, the second input end of the dynamic comparator is connected with the output end of the unit gain buffer, the dynamic comparator comprises a comparator and a latch, the output end of the comparator is connected with the input end of the latch, the output end of the latch is connected with the input end of the digital encoding logic circuit, the clock signal input end of the comparator is connected with a first clock signal, the clock signal input end of the latch is connected with a second clock signal, and the rising edge arrival time of the second clock signal is later than that of the first clock signal.

4. The low temperature drift delay circuit for asynchronous timing of claim 1, wherein, The low-temperature drift delay circuit further comprises a first RC circuit and a second RC circuit, and the inverter chain circuit further comprises a third inverter and a fourth inverter; the third inverter is composed of a third PMOS tube and a third NMOS tube, and the fourth inverter is composed of a fourth PMOS tube and a fourth NMOS tube; the first RC circuit is connected with the third PMOS tube and the third NMOS tube respectively, and the second RC circuit is connected with the fourth PMOS tube and the fourth NMOS tube respectively.

5. The low temperature drift delay circuit for asynchronous timing of claim 1, wherein, The low-temperature drift delay circuit further comprises a digital trimming circuit, and the adjusting tube circuit further comprises a third adjusting tube and a fourth adjusting tube; the third adjusting tube and the fourth adjusting tube each comprise a plurality of NMOS tubes connected in parallel, and the inverter chain circuit further comprises a fifth inverter and a sixth inverter; the fifth inverter is composed of a fifth PMOS tube and a fifth NMOS tube, and the sixth inverter is composed of a sixth PMOS tube and a sixth NMOS tube; the digital trimming circuit is configured to configure a second control code according to an output waveform of the low-temperature drift delay circuit, so as to control the number of NMOS tubes turned on in the third adjusting tube and the fourth adjusting tube.

6. The low temperature drift delay circuit for asynchronous timing of claim 3, wherein, The reference voltage generating circuit comprises a reset switch, a first resistor, a second resistor, a third resistor and a fourth resistor connected in series, the reset switch is connected with a power supply, and the fourth resistor is grounded; the plurality of dynamic comparators comprises a first dynamic comparator, a second dynamic comparator and a third dynamic comparator; a first input end of the first dynamic comparator is connected with a wire between the first resistor and the second resistor, a first input end of the second dynamic comparator is connected with a wire between the second resistor and the third resistor, and a first input end of the third dynamic comparator is connected with a wire between the third resistor and the fourth resistor; a switching frequency of the reset switch is the same as a frequency of the first clock signal, and the reset switch is turned on before a rising edge of the first clock signal comes.

7. The low temperature drift delay circuit for asynchronous timing of claim 4, wherein, The first RC circuit comprises a fifth resistor, a sixth resistor and a first capacitor, and the second RC circuit comprises a seventh resistor, an eighth resistor and a second capacitor; one end of the fifth resistor is connected with the drain of the third PMOS tube, the other end of the fifth resistor is connected with one end of the sixth resistor, the gate of the fourth PMOS tube and one end of the first capacitor respectively, the other end of the sixth resistor is connected with the drain of the third NMOS tube, the gate of the third NMOS tube is connected with the gate of the third PMOS tube, the wire between the gate of the third NMOS tube and the gate of the third PMOS tube is connected with the output of the second inverter, the source of the third NMOS tube is grounded, the source of the third PMOS tube is connected with a power supply, and the other end of the first capacitor is grounded; one end of the seventh resistor is connected with the drain of the fourth PMOS tube, the other end of the seventh resistor is connected with one end of the eighth resistor and one end of the second capacitor respectively, the other end of the eighth resistor is connected with the drain of the fourth NMOS tube, the gate of the fourth NMOS tube is connected with the gate of the fourth PMOS tube, the wire between the gate of the fourth NMOS tube and the gate of the fourth PMOS tube is connected with the output of the third inverter, the source of the fourth NMOS tube is grounded, the source of the fourth PMOS tube is connected with a power supply, and the other end of the second capacitor is grounded.

8. The low temperature drift delay circuit for asynchronous timing of claim 3, wherein, The temperature sensor is used to generate a temperature-voltage signal varying with temperature according to the characteristic that the voltage between the base and the emitter of the triode is negatively related to temperature.

9. The low temperature drift delay circuit for asynchronous timing of claim 3, wherein, The two input terminals of each dynamic comparator are connected to a ground capacitor.

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