Static random access memory array, memory and electronic equipment

Abstract

The invention provides a static random access memory array and a preparation method thereof, a memory and electronic equipment. Relates to the technical field of memories. The purpose is to improve the storage density. The SRAM memory array comprises a semiconductor substrate, a front-channel device layer formed in the semiconductor substrate and a rear-channel device layer stacked on the front-channel device layer, the SRAM storage array further comprises a plurality of storage units, each storage unit comprises at least one P-type field effect transistor and at least one N-type field effect transistor which are electrically connected, for example, the storage units can be 6T storage units or 8T storage units; at least one P-type field effect transistor is formed in the front channel device layer; at least one N-type field effect transistor is formed in the back-end device layer. According to the invention, the P-type field effect transistor and the N-type field effect transistor are stacked in a three-dimensional manner, so that the storage density is improved.

Description

Technical Field

[0001] The present application relates to the field of memory technology, and in particular to a static random access memory array, and a memory and an electronic device including the static random access memory. Background Art

[0002] Static random-access memory (SRAM) is a type of random access memory. Static means that as long as the memory remains powered, the stored data can be kept constant. This type of memory is widely used in computer equipment because of its high speed.

[0003] In the SRAM process, for example, a memory cell includes six transistors, all of which are made in silicon using the front-end process. Since the requirements for the conduction performance of the six transistors are inconsistent, for example, the conduction performance requirement of the pull-down transistor is the highest, the conduction performance of the access transistor is the second, and the conduction performance requirement of the pull-up transistor is the weakest, the size of the transistor is one of the key factors affecting the conduction performance. If you want to increase the storage density by compressing the size of these transistors, the conduction performance of the transistor and the storage performance of the memory will be affected.

[0004] Therefore, the size of transistors is strictly limited, so that it cannot be further reduced with the miniaturization of process nodes, and the storage density of SRAM is limited. Summary of the invention

[0005] The present application provides a static random access memory array, a method for preparing the static random access memory array, a memory and an electronic device, with the purpose of providing a static random access memory array capable of improving storage density.

[0006] In order to achieve the above objectives, this application adopts the following technical solutions:

[0007] On the one hand, the present application provides an SRAM memory array, which includes a semiconductor substrate, a front-end device layer and a back-end device layer, the front-end device layer is arranged in the semiconductor substrate, and the back-end device layer is arranged above the front-end device layer; the SRAM memory array also includes a plurality of memory cells, each memory cell includes at least one P-type field effect transistor and at least one N-type field effect transistor electrically connected, for example, it can be a 3T memory cell, a 6T memory cell or an 8T memory cell; at least one P-type field effect transistor is formed in the front-end device layer; at least one N-type field effect transistor is formed in the back-end device layer.

[0008] The memory cells of the SRAM memory array provided in the present application include P-type field effect transistors and N-type field effect transistors. The P-type field effect transistors are manufactured in the front-end device layer using the front-end process, while the N-type field effect transistors are manufactured in the back-end device layer using the back-end process. Instead of the prior art, all P-type field effect transistors and N-type field effect transistors are manufactured using the front-end process. In the present application, multiple field effect transistors in a memory cell are formed in a three-dimensional stacking manner, which can improve the storage density and storage capacity.

[0009] The N-type field effect transistor in the storage unit can be used as a pull-down tube with higher conduction performance requirements through the back-end process, and the P-type field effect transistor can be used as a pull-up tube with lower conduction performance requirements through the front-end process. Compared with the existing front-end process, when the same process node is used, not only can the high conduction performance of the pull-down tube be guaranteed, but the present application can also integrate more storage units per unit area to improve storage density.

[0010] In one achievable manner, an orthographic projection of the N-type field effect transistor on the semiconductor substrate at least partially overlaps with an orthographic projection of the P-type field effect transistor on the semiconductor substrate.

[0011] By adopting this process structure, the vertical projection area of ​​a memory cell can be reduced to 2 / N of the existing structure (all transistors of a memory cell are made by the front-end process), which can significantly improve the storage density.

[0012] In one achievable manner, the at least one N-type field effect transistor includes a first N-type field effect transistor and a second N-type field effect transistor, and the first N-type field effect transistor and the second N-type field effect transistor are located in the same back-end device layer.

[0013] The P-type field effect transistors are arranged in the same back-end device layer, and the N-type field effect transistors are arranged in the front-end device layer, so that the preparation process of each device layer can be simplified.

[0014] In one achievable manner, a first N-type field effect transistor and a second N-type field effect transistor are located in a first back-end device layer; a first interconnect routing layer is formed between the front-end device layer and the first back-end device layer; a second interconnect routing layer is formed on a side of the first back-end device layer away from the first interconnect routing layer; at least one P-type field effect transistor includes a first P-type field effect transistor and a second P-type field effect transistor; the first P-type field effect transistor is electrically connected to the second P-type field effect transistor through the first interconnect routing layer; and the first N-type field effect transistor is electrically connected to the second N-type field effect transistor through the second interconnect routing layer.

[0015] A first interconnect routing layer is used to electrically connect a first P-type field effect transistor and a second P-type field effect transistor located in a front-end device layer, and a second interconnect routing layer is used to electrically connect a first N-type field effect transistor and a second N-type field effect transistor located in the same back-end device layer.

[0016] In one achievable manner, the orthographic projection of the first N-type field effect transistor on the semiconductor substrate at least partially overlaps with the orthographic projection of the first P-type field effect transistor on the semiconductor substrate; the orthographic projection of the second N-type field effect transistor on the semiconductor substrate at least partially overlaps with the orthographic projection of the second P-type field effect transistor on the semiconductor substrate.

[0017] That is, the first N-type field effect transistor can be located above the vertical projection of the first P-type field effect transistor; the second N-type field effect transistor can be located above the vertical projection of the second P-type field effect transistor. Thus, the projection area of ​​these transistors on the semiconductor substrate can be compressed to improve the storage density.

[0018] In one achievable manner, the gate of the first P-type field effect transistor is electrically connected to the first electrode of the second P-type field effect transistor through the first interconnect routing layer; the gate of the second P-type field effect transistor is electrically connected to the first electrode of the first P-type field effect transistor through the first interconnect routing layer; the second electrode of the first P-type field effect transistor is electrically connected to the second electrode of the second P-type field effect transistor through the first interconnect routing layer; the gate of the first N-type field effect transistor is electrically connected to the first electrode of the second N-type field effect transistor through the second interconnect routing layer; the gate of the second N-type field effect transistor is electrically connected to the first electrode of the first N-type field effect transistor through the second interconnect routing layer; the second electrode of the first N-type field effect transistor is electrically connected to the second electrode of the second N-type field effect transistor through the second interconnect routing layer; the first electrode is one of the source or the drain, and the second electrode is the other of the source or the drain.

[0019] The above exemplary electrical connection relationships that can be realized by four field effect transistors in a 6T memory cell or an 8T memory cell are given.

[0020] In one achievable manner, the first electrode of the first P-type field effect transistor is electrically connected to the first electrode of the first N-type field effect transistor; the first electrode of the second P-type field effect transistor is electrically connected to the first electrode of the second N-type field effect transistor.

[0021] In some process structures, the first electrode of the first P-type field effect transistor can be interconnected with the first electrode of the first N-type field effect transistor, and the first electrode of the second P-type field effect transistor can be interconnected with the first electrode of the second N-type field effect transistor through a conductive through hole penetrating the dielectric layer.

[0022] In one achievable manner, at least one N-type field effect transistor also includes: a third N-type field effect transistor and a fourth N-type field effect transistor; the third N-type field effect transistor and the fourth N-type field effect transistor are located in a second back-end device layer of the same back-end device layer; and the second interconnect routing layer is located between the first back-end device layer and the second back-end device layer.

[0023] This can form a 6T memory cell or an 8T memory cell. In this example, two of the six field effect transistors, the P-type field effect transistors, are located in the front-end device layer, and the other four N-type field effect transistors are distributed in two back-end device layers, with two N-type field effect transistors arranged in each back-end device layer.

[0024] For example, the channel materials of the third N-type field effect transistor and the fourth N-type field effect transistor may both be made of oxide semiconductor materials.

[0025] In one achievable manner, the orthographic projection of the third N-type field effect transistor on the semiconductor substrate at least partially overlaps with the orthographic projection of the first P-type field effect transistor on the semiconductor substrate; the orthographic projection of the fourth N-type field effect transistor on the semiconductor substrate at least partially overlaps with the orthographic projection of the second P-type field effect transistor on the semiconductor substrate.

[0026] In this way, the projected area of ​​each storage unit on the semiconductor substrate can be further compressed, thereby improving storage density and storage capacity.

[0027] In one achievable manner, the first electrode of the third N-type field effect transistor is electrically connected to the first electrode of the first N-type field effect transistor; the first electrode of the fourth N-type field effect transistor is electrically connected to the first electrode of the second N-type field effect transistor.

[0028] Field effect transistors located in different device layers can be electrically connected through interconnection wiring layers and conductive vias located in the device layers.

[0029] In one achievable manner, the static random access memory array further includes: a first electrode line, a second electrode line, and a third electrode line; the first electrode of the third N-type field effect transistor is electrically connected to the first electrode of the first N-type field effect transistor; the first electrode of the fourth N-type field effect transistor is electrically connected to the first electrode of the second N-type field effect transistor; the gate of the third N-type field effect transistor and the gate of the fourth N-type field effect transistor are both electrically connected to the first electrode line; the second electrode of the third N-type field effect transistor is electrically connected to the second electrode line; the second electrode of the fourth N-type field effect transistor is electrically connected to the third electrode line; the first electrode line is located in a second back-end device layer; the second electrode line and the third electrode line are located in a third interconnect routing layer, and the second back-end device layer is located between the second interconnect routing layer and the third interconnect routing layer.

[0030] For example, the first electrode line may be a word line, and the second electrode line and the third electrode line may be a bit line.

[0031] In one achievable manner, at least one N-type field effect transistor also includes: a fifth N-type field effect transistor and a sixth N-type field effect transistor; the first electrode of the fifth N-type field effect transistor is electrically connected to the first electrode of the sixth N-type field effect transistor; the fifth N-type field effect transistor and the sixth N-type field effect transistor are located in the same back-end device layer.

[0032] Such a memory cell may be an 8T memory cell.

[0033] In one achievable manner, the static random access memory array further includes: a fourth electrode line and a fifth electrode line; the second electrode of the sixth N-type field effect transistor is electrically connected to the fourth electrode line; and the gate of the sixth N-type field effect transistor is electrically connected to the fifth electrode line.

[0034] For example, the fourth electrode line is the electrode line RBL, and the fifth electrode line may be RWL.

[0035] In one achievable manner, the fifth N-type field effect transistor and the sixth N-type field effect transistor are located in a third back-end device layer, and the third back-end device layer is closer to the first back-end device layer than the second back-end device layer; a fourth interconnect routing layer is formed between the third back-end device layer and the second back-end device layer; the first electrode of the fifth N-type field effect transistor is electrically connected to the first electrode of the sixth N-type field effect transistor through the fourth interconnect routing layer; the fifth electrode line is located in the fourth interconnect routing layer; and the fourth electrode line is located in the third interconnect routing layer.

[0036] In the above examples, the third back-end device where the fifth N-type field effect transistor and the sixth N-type field effect transistor are located is located between the second back-end device layer and the first back-end device layer. In other examples, the third back-end device layer may also be located above the second back-end device layer.

[0037] In one implementation, a channel material of the at least one N-type field effect transistor includes an oxide semiconductor material.

[0038] When manufacturing N-type field effect transistors based on oxide semiconductor materials, it can be compatible with the back-end process and will not complicate the preparation process.

[0039] In one achievable manner, any storage unit includes a first inverter and a second inverter, the input end of the first inverter is electrically connected to the output end of the second inverter, and the output end of the first inverter is electrically connected to the input end of the second inverter; the first inverter includes a first P-type field effect transistor and a first N-type field effect transistor; the second inverter includes a second P-type field effect transistor and a second N-type field effect transistor.

[0040] The example given in the present application may be a storage unit including six field effect transistors or eight field effect transistors, wherein the P-type field effect transistors in the first inverter and the second inverter in the storage unit are both manufactured using the front-end process, and the N-type field effect transistors are both manufactured using the back-end process.

[0041] On the other hand, the present application also provides a method for preparing a static random access memory array, the preparation method comprising:

[0042] A front-end device layer is formed in a semiconductor substrate by a front-end process, wherein at least one P-type field effect transistor is formed in the front-end device layer;

[0043] A back-end device layer is formed on the front-end device layer by a back-end process, wherein at least one N-type field effect transistor is formed in the back-end device layer, so as to obtain a storage unit including at least one P-type field effect transistor and at least one N-type field effect transistor.

[0044] In the preparation method provided in the present application, the P-type field effect transistor of the storage unit is manufactured using a front-end process, and the N-type field effect transistor of the storage unit is manufactured using a back-end process, so that the field effect transistors of the storage unit are three-dimensionally stacked, thereby improving the storage density.

[0045] In one achievable manner, when a front-end device layer is formed in a semiconductor substrate by a front-end process, the method includes:

[0046] When a front-end device layer is formed in a semiconductor substrate using a front-end process, it includes:

[0047] Forming a first P-type field effect transistor and a second P-type field effect transistor in a semiconductor substrate by using a front-end process;

[0048] When a back-end device layer is formed on a front-end device layer using a back-end process, it includes:

[0049] A first N-type field effect transistor and a second N-type field effect transistor are formed on a front-end device layer by a back-end process, and the first N-type field effect transistor and the second N-type field effect transistor are located in the same back-end device layer, so as to obtain a first inverter including a first P-type field effect transistor and a first N-type field effect transistor, and to obtain a second inverter including a second N-type field effect transistor electrically connected to a second P-type field effect transistor.

[0050] In this way, two cross-coupled inverters in a 6T memory cell or an 8T memory cell can be manufactured.

[0051] In one achievable manner, the first N-type field effect transistor and the second N-type field effect transistor are located in a first back-end device layer; after forming the front-end device layer and before forming the first back-end device layer, the preparation method further includes: forming a first interconnect routing layer, and the first P-type field effect transistor is electrically connected to the second P-type field effect transistor through the first interconnect routing layer; after forming the first back-end device layer, the preparation method further includes: forming a second interconnect routing layer, and the first N-type field effect transistor is electrically connected to the second N-type field effect transistor through the second interconnect routing layer.

[0052] A first interconnect routing layer is used to electrically connect a first P-type field effect transistor and a second P-type field effect transistor located in a front-end device layer, and a second interconnect routing layer is used to electrically connect a first N-type field effect transistor and a second N-type field effect transistor located in a first back-end device layer.

[0053] In one achievable manner, after forming a first N-type field effect transistor and a second N-type field effect transistor located in the same back-end device layer, it also includes: forming a third N-type field effect transistor and a fourth N-type field effect transistor located in the same back-end device layer, the third N-type field effect transistor is electrically connected to the output end of the first inverter, and the fourth N-type field effect transistor is electrically connected to the output end of the second inverter.

[0054] In this way, a 6T memory cell can be manufactured, in which six field effect transistors can be arranged in a front-end device layer and two back-end device layers.

[0055] In one achievable method, a third N-type field effect transistor and a fourth N-type field effect transistor are formed in the same back-end device layer, including: forming a first electrode line, the gate of the third N-type field effect transistor and the gate of the fourth N-type field effect transistor are electrically connected to the first electrode line, and the first electrode line, the third N-type field effect transistor and the fourth N-type field effect transistor are located in the same back-end device layer.

[0056] The first electrode line may be a word line WL.

[0057] In one achievable manner, after forming a third N-type field effect transistor and a fourth N-type field effect transistor located in the same back-end device layer, the preparation method further includes: forming a third interconnect routing layer, in which a second electrode line and a third electrode line are formed, so that the second electrode of the third N-type field effect transistor is electrically connected to the second electrode line, and the second electrode of the fourth N-type field effect transistor is electrically connected to the third electrode line.

[0058] The second electrode line and the third electrode line may be a bit line BL and a bit line BLB, respectively.

[0059] In one achievable manner, after forming the first N-type field effect transistor and the second N-type field effect transistor located in the same back-end device layer, it also includes: forming a fifth N-type field effect transistor and a sixth N-type field effect transistor located in the same back-end device layer, the gate of the fifth N-type field effect transistor being electrically connected to the input end of the first inverter; and the first electrode of the fifth N-type field effect transistor being electrically connected to the first electrode of the sixth N-type field effect transistor.

[0060] On the other hand, the present application also provides a memory, including a controller and a static random access memory array in any of the above-mentioned implementations, the controller is electrically connected to the static random access memory array, and the controller is used to control the reading and writing of the static random access memory array.

[0061] In the memory provided in the present application, since the static random access memory array of the above example is included, the P-type field effect transistor of each memory cell in the static random access memory array is integrated in the front-end device layer, and the N-type field effect transistor is integrated in the back-end device layer, so that multiple field effect transistors of the memory cell are three-dimensionally stacked, thereby improving the storage density of the memory.

[0062] On the other hand, the present application also provides an electronic device, including a processor and the above-mentioned memory, wherein the processor is electrically connected to the memory, and the memory is used to store data generated by the processor.

[0063] The electronic device provided in the embodiment of the present application includes the memory in any of the above-mentioned implementation methods. Therefore, the electronic device provided in the embodiment of the present application and the memory of the above-mentioned technical solution can solve the same technical problems and achieve the same expected effects. BRIEF DESCRIPTION OF THE DRAWINGS

[0064] Figure 1 A circuit diagram of an electronic device;

[0065] Figure 2 A circuit diagram of a memory;

[0066] Figure 3A A packaging structure diagram of a storage array and a controller;

[0067] Figure 3B A packaging structure diagram of a storage array and a controller;

[0068] Figure 3C A packaging structure diagram of a storage array and a controller;

[0069] Figure 4 A simple circuit diagram of a memory;

[0070] Figure 5 A circuit diagram of a 6T memory cell provided in an embodiment of the present application;

[0071] Figure 6 A circuit diagram of an 8T memory cell provided in an embodiment of the present application;

[0072] Figure 7 A simplified process structure diagram of a storage array provided in an embodiment of the present application;

[0073] Fig. 8A A layout of a front-end device layer of a memory array provided in an embodiment of the present application;

[0074] Figure 8B and Figure 8C A layout of a back-end device layer of a memory array provided in an embodiment of the present application;

[0075] Fig. 9A A layout of a front-end device layer of a memory array provided in an embodiment of the present application;

[0076] Fig. 9B , Fig. 9C and Fig.9D A layout of a back-end device layer of a memory array provided in an embodiment of the present application;

[0077] Fig.10 A flowchart of a method for preparing a storage array provided in an embodiment of the present application. DETAILED DESCRIPTION

[0078] Before introducing the embodiments provided in this application, the relevant technical terms are first introduced.

[0079] Pull-up means clamping the signal at a high level.

[0080] Pull-down means clamping the signal at a low level.

[0081] Oxide semiconductor: a type of oxide with semiconductor properties.

[0082] The following embodiments of the present application are described below in conjunction with the drawings in the embodiments of the present application.

[0083] The technical solution of the present application can be applied to various electronic devices using memory, such as: Figure 1 This is a circuit block diagram of an electronic device 100 provided in an embodiment of the present application. The electronic device 100 can be a terminal device, such as a mobile phone, a tablet computer, a smart bracelet, or a personal computer (PC), a server, a workstation, etc.

[0084] like Figure 1 , the electronic device 100 may include a bus 205, and a system on chip (SOC) 210 connected to the bus 205. The SOC 210 may be used to process data, such as processing application data, processing image data, and caching temporary data. In one embodiment, the SOC 210 may include an application processor (AP) 211 for processing applications, a graphics processing unit (GPU) 212 for processing image data, and a first random access memory (RAM) 213 for caching high-speed data. The first RAM 213 may be a static random access memory (SRAM) or an embedded flash (EFlash), etc. The above-mentioned AP 211, GPU 212 and first RAM 213 may be integrated into a die, or may be separately set in multiple dies.

[0085] For example Figure 1 As shown, the electronic device 100 may further include a second RAM 220 connected to the SOC 210 via the bus 205. The second RAM 220 may be a dynamic random access memory (DRAM). The second RAM 220 may be used to store volatile data, such as temporary data generated by the SOC 210. The storage capacity of the second RAM 220 is generally greater than that of the first RAM 213, but the reading speed is generally slower than that of the first RAM 213.

[0086] In addition, the electronic device 100 may also include a communication chip 230 and a power management chip 240 connected to the SOC 210 via the bus 205. The communication chip 230 can be used for processing the protocol stack, or amplifying and filtering analog radio frequency signals, or realizing the above functions at the same time. The power management chip 240 can be used to power other chips. In one embodiment, the SOC 210 and the second RAM 220 can be packaged in a packaging structure, such as using 2.5D (dimension) or 3D packaging, etc., to obtain a faster data transmission rate between chips.

[0087] like Figure 2 As shown, the memory 300 includes a storage array 31 and a controller 32 for accessing the storage array 31 , wherein the controller 32 is used to control the read and write operations of the storage array 31 .

[0088] in, Figure 2 The storage array 31 and the controller 32 shown have a variety of achievable packaging structures. For example, several achievable packaging structures are given below.

[0089] Figure 3A It is one of the packaging structures of the storage array 31 and the controller 32 given in the embodiment of the present application, that is, the storage array 31 and the controller 32 are two independent chips, and the storage array 31 and the controller 32 are respectively integrated on the substrate 33. For example, the storage array 31 and the controller 32 can be electrically connected through metal traces arranged on the substrate 33. In this structure, since the storage array 31 and the controller 32 are two independent chips, the storage array 31 can be called a stand-alone memory.

[0090] Figure 3B This is another packaging structure of the storage array 31 and the controller 32 provided in the embodiment of the present application. Figure 3A Similarly, the storage array 31 and the controller 32 are two independent chips, so the storage array 31 can also be called an independent memory. Figure 3A The difference is that in Figure 3B In the embodiment, the memory array 31 and the controller 32 are stacked. For example, the memory array 31 and the controller 32 may be connected to each other through a through silicon via (TSV) or a redistribution layer (RDL).

[0091] Figure 3CThis is another packaging structure of the storage array 31 and the controller 32 provided in the embodiment of the present application. In this exemplary structure, the storage array 31 and the controller 32 are integrated into the same chip 3, and the chip 3 is integrated on the substrate 33. Therefore, the storage array 31 can be called an embedded memory.

[0092] In one embodiment, the storage array 31 in the memory may include Figure 4 The memory cells 400 shown are arranged in a plurality of arrays, wherein each memory cell 400 can be used to store 1 bit (bit) or multiple bits of data. The memory array 31 can also include electrode lines such as word lines (WL) and bit lines (BL). Each memory cell 400 is electrically connected to the corresponding word line WL and bit line BL. Different memory cells 400 can be electrically connected through word lines WL and bit lines BL. One or more of the above-mentioned word lines WL and bit lines BL are used to select the memory cell 400 to be read or written in the memory array by receiving the control level output by the control circuit, thereby realizing the read and write operation of the data.

[0093] The controller 32 in the memory may include Figure 4 One or more circuit structures of the decoder 320, driver 330, timing controller 340, buffer 350 or input / output driver 360 are shown.

[0094] exist Figure 4 In the memory 300 structure shown, the decoder 320 is used to decode according to the received address to determine the storage unit 400 that needs to be accessed. The driver 330 is used to control the level of the signal line according to the decoding result generated by the decoder 320, so as to achieve access to the specified storage unit 400. The buffer 350 is used to cache the read data, for example, it can be cached using a first-in first-out (FIFO). The timing controller 340 is used to control the timing of the buffer 350, and control the driver 330 to drive the signal lines in the storage array 310. The input and output driver 360 is used to drive the transmission signal, such as driving the received data signal and driving the data signal to be sent, so that the data signal can be transmitted over a long distance.

[0095] The storage array 310 , decoder 320 , driver 330 , timing controller 340 , buffer 350 and input / output driver 360 may be integrated into one chip or may be integrated into multiple chips.

[0096] In some examples, the memory 300 may be electrically connected to the processor, and the memory is used to store data generated by the processor.

[0097] The memory involved in the embodiment of the present application may include Figure 5 or Figure 6 The memory cell of the static random access memory array is shown. Figure 5 A memory cell 400 of the static random access memory array shown in FIG. 1 includes six field effect transistors (Oxide semiconductor based Field-Effect Transistor, OS-FET), which can be called a 6T memory cell. Figure 6 A memory cell 400 of the static random access memory array shown in FIG. 4 includes 8 field effect transistors and can be called an 8T memory cell.

[0098] In some other examples, a memory cell may be a 3T memory cell, a 4T memory cell, a 5T memory cell, a 7T memory cell, a 9T memory cell, or a 10T memory cell, or a memory cell including more field effect transistors.

[0099] In an embodiment of the present application, a memory cell of a static random access memory array includes at least three field effect transistors, and the at least three field effect transistors may include a P-type field effect transistor and an N-type field effect transistor.

[0100] For example, Figure 5 The exemplary 6T memory cell 400 includes field effect transistors MP1, MN1, MP2, MN2, MA1 and MA2. Field effect transistors MP1 and MP2 are P-type field effect transistors, and the rest are N-type field effect transistors.

[0101] For example, Figure 6 The exemplary 8T memory cell 400 includes field effect transistors MP1, FET MN1, FET MP2, FET MN2, FET MA1 and FET MA2, and field effect transistors MR1 ​​and FET MR2. Field effect transistors MP1 and MP2 are P-type field effect transistors, and the rest are N-type field effect transistors.

[0102] In some examples given in this application, Figure 5 and Figure 6 , P-type field effect transistors are fabricated in semiconductor substrates using front-end of the line (FEOL) processes. For example, Figure 5 and Figure 6The field effect transistors MP1 and MP2 are manufactured using the front end of line (FEOL) process, and the remaining N-type field effect transistors are manufactured in the back end of line (BEOL) device layer using the back end of line (BEOL) process.

[0103] In the example of this application, the P-type field effect transistor is manufactured in the semiconductor substrate using the front-end process FEOL, and the N-type field effect transistor is manufactured in the back-end device layer using the back-end process. It can be understood that: Figure 7 In the chip manufacturing process, a front-end device layer can be first manufactured in a semiconductor substrate using a front-end process. The electronic devices in the front-end device layer may include: Figure 5 and Figure 6 In the example of a P-type field effect transistor, the source and drain of the P-type field effect transistor can be formed by doping in a semiconductor substrate; after the front-end device layer is prepared, the back-end device layer can be prepared by a back-end process, such as Figure 5 and Figure 6 The exemplary N-type field effect transistor may be formed in a back-end device layer using a back-end process.

[0104] like Figure 7 ,like Figure 5 and Figure 6 The example N-type field effect transistor can be integrated in the back-end device layer, and the interconnection routing layer is used to form metal routing to electrically connect the electronic devices in the back-end device layer. The back-end device layer and the interconnection routing layer are separated by a dielectric layer, and the back-end device layer and the interconnection routing layer can be electrically connected through conductive through holes (for example, silicon through vias) that pass through the dielectric layer.

[0105] The channel material of the N-type field effect transistor in the back-end device layer of the present application example includes an oxide semiconductor material, which may include at least one of ZnO, CdO, TiO2, Al2O3, and SnO. Alternatively, the channel material of the N-type field effect transistor may include polysilicon.

[0106] The field-effect transistor (OS-FET) process based on oxide semiconductor as the channel material is compatible with the back-end process, that is, the active device N-type field-effect transistor can be placed in the back-end device layer without complicating the process.

[0107] like Figure 5 and Figure 6, multiple field effect transistors in a storage unit are formed by three-dimensional stacking to form a three-dimensional stacked memory (3-Dimensions Memory, 3D Memory). Compared with all field effect transistors in a storage unit manufactured by front-end process, this application can significantly improve the storage density.

[0108] In the example of this application, the P-type field effect transistor that can be used as a pull-up tube is manufactured using a front-end process, and the N-type field effect transistor that can be used as a pull-down tube is manufactured using a back-end process. Compared with the existing method in which both the P-type field effect transistor and the N-type field effect transistor are manufactured using the front-end process, when the same process node is used, this application can not only ensure the high conduction performance of the pull-down tube, but also improve the storage density.

[0109] This application takes a 6T memory cell and an 8T memory cell as examples to introduce a process structure that can be implemented for the memory cell.

[0110] like Figure 5 and Figure 6 A 6T memory cell 400 or an 8T memory cell 400 includes a first inverter 501 and a second inverter 502, wherein the input end of the first inverter 501 is electrically connected to the output end of the second inverter 502, and the output end of the first inverter 501 is electrically connected to the input end of the second inverter 502, and the first inverter 501 and the second inverter 502 form a cross-coupled circuit structure.

[0111] The first inverter 501 includes a field effect transistor MP1 and a field effect transistor MN1 which are electrically connected, and the second inverter 502 includes a field effect transistor MP2 and a field effect transistor MN2 which are electrically connected.

[0112] The field effect transistor MP1 and the field effect transistor MP2 are respectively arranged in the semiconductor substrate by the front-end process and are located in the front-end device layer of the semiconductor substrate; the field effect transistor MN1 and the field effect transistor MN2 are respectively manufactured in the back-end device layer above the semiconductor substrate by the back-end process.

[0113] In order to further improve the storage density, such as Figure 5 and Figure 6 , the field effect transistor MP1 and the field effect transistor MP2 are located in the front-end device layer, and the field effect transistor MN1 and the field effect transistor MN2 can be arranged in the same back-end device layer, for example, Figure 5 and Figure 6 The OSL1 device layer is shown.

[0114] In some examples, in the field effect transistor MN1 and the field effect transistor MN2 of the N-type field effect transistor, the channel can be made of oxide semiconductor material. Placing the field effect transistor MN1 and the field effect transistor MN2 in the same back-end device layer can not only improve the storage density, but also simplify the process due to the same channel material.

[0115] In some achievable process structures, in the first inverter 501, the field effect transistor MN1 is formed on the side of the field effect transistor MP1 away from the semiconductor substrate using a back-end process. In some examples, the orthographic projections of the field effect transistor MN1 and the field effect transistor MP1 on the semiconductor substrate partially overlap. In the second inverter 502, the field effect transistor MN2 is formed on the side of the field effect transistor MP2 away from the semiconductor substrate using a back-end process. In some examples, the orthographic projections of the field effect transistor MN2 and the field effect transistor MP2 on the semiconductor substrate partially overlap. In this way, the orthographic projection area of ​​each storage unit on the semiconductor substrate can be further compressed, further improving the storage density.

[0116] See also Figure 5 and Figure 6 The gate of the field effect transistor MP1 is electrically connected to the first electrode of the field effect transistor MP2, the gate of the field effect transistor MP2 is electrically connected to the first electrode of the field effect transistor MP1, and the second electrode of the field effect transistor MP1 is electrically connected to the second electrode of the field effect transistor MP2. For example, the second electrode of the field effect transistor MP1 and the second electrode of the field effect transistor MP2 can both be electrically connected to VDD.

[0117] The gate of field effect transistor MN1 is electrically connected to the first electrode of field effect transistor MN2, the gate of field effect transistor MN2 is electrically connected to the first electrode of field effect transistor MN1, and the second electrode of field effect transistor MN1 is electrically connected to the second electrode of field effect transistor MN2. For example, the second electrode of field effect transistor MN1 and the second electrode of field effect transistor MN2 can both be electrically connected to VSS.

[0118] The first electrode of the field effect transistor MP1 is electrically connected to the first electrode of the field effect transistor MN1, and the electrical connection node forms the output terminal of the first inverter 501; the gate of the field effect transistor MP1 is electrically connected to the gate of the field effect transistor MN1, and the electrical connection node forms the input terminal of the first inverter 501.

[0119] The first electrode of the field effect transistor MP2 is electrically connected to the first electrode of the field effect transistor MN2, and the electrical connection node forms the output terminal of the second inverter 502; the gate of the field effect transistor MP2 is electrically connected to the gate of the field effect transistor MN2, and the electrical connection node forms the input terminal of the second inverter 502.

[0120] In the example of the present application, the first electrode is one of the source electrode and the drain electrode, and the second electrode is the other of the source electrode and the drain electrode.

[0121] In conjunction with the process structure diagram, the process structures that can be implemented by each field effect transistor in the first inverter 501 and the second inverter 502 and the process connection structures between different electrodes are described in detail below.

[0122] Fig. 8A , Figure 8B and Figure 8C This is the layout structure of each device layer given in the embodiments of the present application.

[0123] Storage arrays include Figure 7 The exemplary stacked layers include a front-end device layer, an interconnect routing layer 1, a back-end device layer 1, an interconnect routing layer 2, a back-end device layer 2 and an interconnect routing layer 3.

[0124] like Fig. 8A The field effect transistor MP1 and the field effect transistor MP2 are arranged along a first direction (eg, X direction) parallel to a surface of a semiconductor substrate (not shown in the figure).

[0125] In the first inverter 501, as Fig. 8A The first electrode 11A and the second electrode 12A of the field effect transistor MP1 are arranged along a second direction (such as the Y direction) parallel to the surface of the semiconductor substrate, and a channel of the field effect transistor MP1 is formed between the first electrode 11A and the second electrode 12A. The gate 13A of the field effect transistor MP1 is arranged above the channel and can be isolated from the channel by a gate dielectric layer.

[0126] In the second inverter 502, as Fig. 8A The first electrode 11B and the second electrode 12B of the field effect transistor MP2 are arranged along the second direction, and a channel of the field effect transistor MP2 is formed between the first electrode 11B and the second electrode 12B. The gate 13B of the field effect transistor MP2 is arranged above the channel and can be isolated from the channel by a gate dielectric layer.

[0127] The source, drain and channel of the field effect transistor MP1 are in the front-end device layer, and the source, drain and channel of the field effect transistor MP2 are also in the front-end device layer. In some examples, the source and drain of the field effect transistor MP1 and the field effect transistor MP2 can be made by ion implantation.

[0128] Since the field effect transistor MP1 and the field effect transistor MP2 need to be electrically connected, in some process structures, an interconnection wiring layer 1 may be provided above the front-end device layer of the semiconductor substrate. Fig. 8A The gate 13A of the field effect transistor MP1 is electrically connected to the first electrode 11B of the field effect transistor MP2 through the metal wiring 1, the gate 13B of the field effect transistor MP2 is electrically connected to the first electrode 11A of the field effect transistor MP1 through the metal wiring 2, and the second electrode 12A of the field effect transistor MP1 is electrically connected to the second electrode 12B of the field effect transistor MP2 through the metal wiring 3. The metal wiring 1, the metal wiring 2 and the metal wiring 3 are part of the wiring in the interconnect wiring layer 1.

[0129] There is a dielectric layer between the front-end device layer and the interconnect wiring layer 1. The metal wiring can be electrically connected to the corresponding structure through a conductive via (e.g., silicon through via) that penetrates the dielectric layer. For example, the gate 13A of the field effect transistor MP1 can be connected to the metal wiring 1 through the conductive via 11.

[0130] In the front-end device layer, a plurality of field effect transistors MP1 and field effect transistors MP2 are integrated. These field effect transistors MP1 and field effect transistors MP2 are arranged in an array. In order to electrically connect the second electrode of the field effect transistor MP1 and the second electrode of the field effect transistor MP2 in the same direction, as shown in FIG. Fig. 8A The metal wiring 3 can be extended along the X direction to electrically connect the second electrodes of the plurality of field effect transistors MP1 and the second electrodes of the plurality of field effect transistors MP2 in the X direction. For example, the metal wiring 3 can be electrically connected to VDD.

[0131] The field effect transistor MN1 of the first inverter 501 and the field effect transistor MN2 of the second inverter 502 are both arranged in the back-end device layer 1. Figure 8B , the field effect transistor MN1 and the field effect transistor MN2 are arranged along the X direction.

[0132] like Figure 8B In the first inverter 501, the first electrode 11C and the second electrode 12C of the field effect transistor MN1 are arranged along the Y direction. In the example of the present application, the field effect transistor MN1 is a ring gate structure. In other examples, a ring channel structure may also be used.

[0133] like Figure 8B In the second inverter 502, the first electrode 11D and the second electrode 12D of the field effect transistor MN2 are also arranged in the Y direction. The field effect transistor MN2 is similar to the field effect transistor MN1 in the example, both of which have a ring gate structure. Other structures may also be used.

[0134] The orthographic projection of the field effect transistor MN1 on the semiconductor substrate at least partially overlaps with the orthographic projection of the field effect transistor MP1 on the semiconductor substrate; that is, the field effect transistor MN1 is located above the vertical projection of the field effect transistor MP1. The orthographic projection of the field effect transistor MN2 on the semiconductor substrate at least partially overlaps with the orthographic projection of the field effect transistor MP2 on the semiconductor substrate, and the field effect transistor MN2 is located above the vertical projection of the field effect transistor MP2. In this way, the orthographic projection area of ​​the first inverter and the second inverter in the storage unit on the semiconductor substrate can be reduced by half compared with the prior art, thereby improving the storage density and storage capacity.

[0135] like Figure 7 and Figure 8B An interconnection wiring layer 2 is provided above the back-end device layer 1 , and the field effect transistor MN1 can be electrically connected to the field effect transistor MN2 through the interconnection wiring layer 2 .

[0136] For example, the gate 13C of the field effect transistor MN1 is electrically connected to the first electrode 11D of the field effect transistor MN2 through the metal wiring 4, the gate 13D of the field effect transistor MN2 is electrically connected to the first electrode 11C of the field effect transistor MN1 through the metal wiring 5, and the second electrode 12C of the field effect transistor MN1 is electrically connected to the second electrode 12D of the field effect transistor MN2 through the metal wiring 6. The metal wiring 4, the metal wiring 5 and the metal wiring 6 are part of the wiring in the second interconnect wiring layer.

[0137] There is a dielectric layer between the back-end device layer 1 and the interconnection wiring layer 2, and the metal wiring in the interconnection wiring layer 2 can be electrically connected to the corresponding structure in the back-end device layer 1 through the conductive through-holes penetrating the dielectric layer.

[0138] The field effect transistor MP1 located in the front-end device layer needs to be electrically connected to the field effect transistor MN1 located in the back-end device layer. The field effect transistor MP2 located in the front-end device layer needs to be electrically connected to the field effect transistor MN2 located in the back-end device layer.

[0139] The first electrode 11A of the field effect transistor MP1 is electrically connected to the first electrode 11C of the field effect transistor MN1. In some examples, the first electrode 11A and the first electrode 11C may be interconnected via a conductive through hole penetrating through the dielectric layer.

[0140] The first electrode 11B of the field effect transistor MP2 is electrically connected to the first electrode 11D of the field effect transistor MN2. In some structures, the first electrode 11B and the first electrode 11D may be interconnected via a conductive through hole 13 penetrating through the dielectric layer.

[0141] In some other process structures, the first electrode 11A is interconnected with the first electrode 11C, and the first electrode 11B is interconnected with the first electrode 11D. Other wiring methods may also be used.

[0142] like Figure 5 In the example 6T memory cell, and Figure 6 The exemplary 8T memory cell further includes a field effect transistor MA1 and a field effect transistor MA2. The field effect transistor MA1 and the field effect transistor MA2 may be N-type field effect transistors, which may be manufactured using a back-end process. For example, the channel material of the field effect transistor MA1 and the field effect transistor MA2 includes an oxide semiconductor material.

[0143] In some examples, the field effect transistor MA1 and the field effect transistor MA2 may be formed in the same back-end device layer using a back-end process, for example. Figure 5 and Figure 6 The example is located in the OSL2 device layer.

[0144] The field effect transistor MA2 is electrically connected to the output terminal of the first inverter 501 , and the field effect transistor MA1 is electrically connected to the output terminal of the second inverter 502 .

[0145] The field effect transistor MA1 and the field effect transistor MA2 are disposed in the back-end device layer 2 .

[0146] like Figure 8C , the field effect transistor MA1 and the field effect transistor MA2 are arranged along the X direction.

[0147] like Figure 8C The first electrode 11E and the second electrode 12E of the field effect transistor MA1 are arranged along the Y direction. In the example of the present application, the field effect transistor MA1 is a ring gate structure. In other examples, a ring channel structure may also be used.

[0148] like Figure 8C The first electrode 11F and the second electrode 12F of the field effect transistor MA2 are also arranged in the Y direction. The field effect transistor MA2 is similar to the field effect transistor MA1 in the example, both of which have a ring gate structure. Other structures may also be used.

[0149] like Figure 8C , the gate 13E of the field effect transistor MA1 and the gate 13F of the field effect transistor MA2 are electrically connected.

[0150] For example, the first electrode of the field effect transistor MA2 is electrically connected to the gate of the field effect transistor MN1, or the first electrode of the field effect transistor MA2 is electrically connected to the first electrode of the field effect transistor MN2.

[0151] The first electrode of the field effect transistor MA1 is electrically connected to the gate of the field effect transistor MN2 , or the first electrode of the field effect transistor MA1 is electrically connected to the first electrode of the field effect transistor MN1 .

[0152] Referring to the example 6T memory cell, the six field effect transistors in a memory cell are distributed in three device layers, wherein two P-type field effect transistors are arranged in the front-end device layer, and the other four N-type field effect transistors are arranged in two back-end device layers, so that a memory cell can be made by three-dimensionally stacked device layers, and the interconnection wiring layer arranged between two adjacent device layers is used to realize the interconnection of different field effect transistors.

[0153] like Figure 5 The exemplary 6T memory cell also includes electrode lines for controlling the reading and writing of the memory cell, for example, including a word line WL, a first bit line BL, and a second bit line BLB. Among them, the second electrode of the field effect transistor MA1 is electrically connected to the first bit line BL, the second electrode of the field effect transistor MA2 is electrically connected to the second bit line BLB, and the gate of the field effect transistor MA1 and the gate of the field effect transistor MA2 are both electrically connected to the word line WL.

[0154] In the achievable process structure, an interconnection routing layer 3 is provided above the back-end device layer 2 where the field effect transistors MA1 and MA2 are located, the first bit line BL and the second bit line BLB are located in the interconnection routing layer 3 , and the word line WL is located in the back-end device layer 2 .

[0155] In some examples given in the present application, the first bit line BL and the second bit line BLB may be parallel to each other, and the word line WL may be perpendicular to both the first bit line BL and the second bit line BLB.

[0156] like FIG. 8A to FIG. 8C , the example is the process structure diagram of 6T storage unit, 9A to 9D This is the layout of the 8T storage unit of the present application example.

[0157] 9A to 9D Example storage array: includes Figure 7 The example stacked layers include front-end device layer, interconnect routing layer 1, back-end device layer 1, interconnect routing layer 2, back-end device layer 2, interconnect routing layer 3, back-end device layer 3, and interconnect routing layer 4.

[0158] This example is the same as the above, and each memory cell includes: a field effect transistor MP1, a field effect transistor MN1, a field effect transistor MP2, a field effect transistor MN2, and a field effect transistor MA1 and a field effect transistor MA2.

[0159] Field effect transistor MP1 and field effect transistor MP2 are located in the front-end device layer, field effect transistor MN1 and field effect transistor MN2 are located in the back-end device layer 1, field effect transistor MP1 and field effect transistor MP2 are electrically connected through interconnect wiring layer 1, and field effect transistor MN1 and field effect transistor MN2 are electrically connected through interconnect wiring layer 2.

[0160] The 8T memory cell of the present application example further includes field effect transistors MA1 and MA2, as well as field effect transistors MR1 ​​and MR2. In some examples, for example Figure 6 , the field effect transistor MA1 and the field effect transistor MA2 are set in the OSL2 device layer, and the field effect transistor MR1 and the field effect transistor MR2 can be set in the OSL3 device layer.

[0161] In some other examples, the field effect transistor MR1 and the field effect transistor MR2 may be located in the OSL2 device layer, and the field effect transistor MA1 and the field effect transistor MA2 may be located in the OSL3 device layer. For example, the field effect transistor MR1 and the field effect transistor MR2 may be located in the back-end device layer 2, and the field effect transistor MA1 and the field effect transistor MA2 may be located in the back-end device layer 3.

[0162] In the 8T memory cell process structure of the present application example, the process structure that can be implemented for field effect transistors MP1, FET MN1, FET MP2 and FET MN2, as well as the process connection structure between electrodes can refer to the above-mentioned 6T memory cell.

[0163] Fig. 9C The layout of the process structure of the field effect transistor MR1 and the field effect transistor MR2 is exemplarily shown. The first electrode 11G and the second electrode 12G of the field effect transistor MR2 are arranged along the X direction, and the first electrode 11H and the second electrode 12H of the field effect transistor MR1 are arranged along the Y direction. The first electrode 11G of the field effect transistor MR2 and the first electrode 11H of the field effect transistor MR1 share the same electrode layer, so that the first electrode 11G and the first electrode 11H are electrically connected.

[0164] Fig. 9C What is shown is a process structure in which field effect transistor MR1 and field effect transistor MR2 are electrically connected. In some other examples, an interconnection wiring layer is arranged above the back-end device layer where field effect transistor MR1 and field effect transistor MR2 are located, and the first electrode 11G and the first electrode 11H can be electrically connected to each other through the metal wiring of the interconnection wiring layer.

[0165] The memory array further includes an electrode line RBL and an electrode line RWL. The second electrode of the field effect transistor MR2 is electrically connected to the electrode line RBL, and the gate of the field effect transistor MR2 is electrically connected to the electrode line RWL. The second electrode 12H of the field effect transistor MR1 can be electrically connected to VSS.

[0166] An electrode line RWL electrically connected to the gate of the field effect transistor MR2 may be located in the interconnect wiring layer 3 .

[0167] The electrode line RBL electrically connected to the second electrode of the field effect transistor MR2 can be arranged in the interconnection wiring layer 4 located above the field effect transistor MA1 and the field effect transistor MA2, that is, the first bit line BL, the second bit line BLB and the electrode line RBL can be arranged in the same interconnection wiring layer. In some examples, the first bit line BL, the second bit line BLB and the electrode line RBL can also be arranged parallel to each other. The electrode line RWL can be arranged perpendicular to the electrode line RBL.

[0168] The present application also provides a method for preparing a static random access memory array, such as Fig.10 , Fig.10 The flowchart of the method for preparing a static random access memory array is exemplarily shown, and the method for preparing the static random access memory array comprises:

[0169] Step S1: forming a front-end device layer in a semiconductor substrate by adopting a front-end process, wherein at least one P-type field effect transistor is formed in the front-end device layer.

[0170] In some feasible processes, a doping process may be used to manufacture a P-type field effect transistor.

[0171] Step S2: forming a back-end device layer on the front-end device layer by a back-end process, wherein at least one N-type field effect transistor is formed in the back-end device layer, so as to obtain a memory cell including at least one P-type field effect transistor and at least one N-type field effect transistor.

[0172] The present application is to manufacture an N-type field effect transistor using a back-end process. In some examples, an oxide semiconductor material compatible with the back-end process may be used to manufacture the N-type field effect transistor. The oxide semiconductor material may include at least one of ZnO, CdO, TiO2, Al2O3, and SnO.

[0173] In some process steps, a memory cell may include more field effect transistors, such as a 6T memory cell or an 8T memory cell.

[0174] In each memory cell of the SRAM memory array manufactured by the preparation method given in the present application, the P-type field effect transistor is manufactured in the front-end device layer, and the N-type field effect transistor is manufactured in the back-end interconnection layer, that is, the multiple field effect transistors of the memory cell are integrated on the semiconductor substrate in a three-dimensional stacking manner, which can improve the storage density.

[0175] For example, when a 6T memory cell is manufactured, a front-end process can be first used to manufacture a plurality of P-type field effect transistors arranged in an array in a semiconductor substrate (for example, pull-down transistors in a memory cell); a back-end process can then be used to manufacture an interconnection wiring layer for electrically connecting the P-type field effect transistors; a back-end process can then be used to manufacture a plurality of N-type field effect transistors arranged in an array (for example, pull-up transistors in a memory cell); an interconnection wiring layer for electrically connecting the N-type field effect transistors can be manufactured; a back-end process can then be used to manufacture a plurality of N-type field effect transistors (for example, gate transistors in a memory cell); and an interconnection wiring layer for electrically connecting the N-type field effect transistors to the gate transistors can be manufactured.

[0176] The present application takes the preparation of a 6T memory cell as an example. When executing step S1, a first P-type field effect transistor and a second P-type field effect transistor in the 6T memory cell are prepared, and the first P-type field effect transistor and the second P-type field effect transistor can be arranged in a direction parallel to the surface of the semiconductor substrate; when executing step S2, a first N-type field effect transistor and a second N-type field effect transistor in the 6T memory cell are prepared, and the first P-type field effect transistor and the first N-type field effect transistor can form a first inverter, and the second N-type field effect transistor of the second P-type field effect transistor can form a second inverter.

[0177] Before manufacturing the first N-type field effect transistor and the second N-type field effect transistor, an interconnection wiring layer may be manufactured to electrically connect a plurality of P-type field effect transistors located in the front-end device layer, for example, to electrically connect the first P-type field effect transistor and the second P-type field effect transistor.

[0178] After the first P-type field effect transistor and the second P-type field effect transistor are manufactured, an interconnection wiring layer may be manufactured to electrically connect a plurality of N-type field effect transistors located in the front-end device layer, for example, to electrically connect the first N-type field effect transistor and the second N-type field effect transistor.

[0179] After the first inverter and the second inverter are manufactured, the third N-type field effect transistor and the fourth N-type field effect transistor in the 6T memory cell can also be manufactured, so that the third N-type field effect transistor and the fourth N-type field effect transistor are located in the same back-end device layer. And the word line WL, the first bit line BL and the second bit line BLB are manufactured.

[0180] In some examples, an 8T memory cell may be fabricated using the above process for fabricating a 6T memory cell, wherein two N-type field effect transistors are formed in each back-end device layer.

[0181] In the description of this specification, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0182] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A static random access memory array, characterized in that: include: Semiconductor substrate; A front-end device layer and a back-end device layer, wherein the front-end device layer is arranged in the semiconductor substrate, and the back-end device layer is arranged above the front-end device layer; The static random access memory array further comprises a plurality of memory cells, each of which comprises: at least one P-type field effect transistor and at least one N-type field effect transistor; The at least one P-type field effect transistor is formed in the front-end device layer; The at least one N-type field effect transistor is formed in the back-end device layer.

2. The static random access memory array according to claim 1, characterized in that: The orthographic projection of the N-type field effect transistor on the semiconductor substrate at least partially overlaps with the orthographic projection of the P-type field effect transistor on the semiconductor substrate.

3. The static random access memory array according to claim 1 or 2, characterized in that: The at least one N-type field effect transistor includes a first N-type field effect transistor and a second N-type field effect transistor, and the first N-type field effect transistor and the second N-type field effect transistor are located in the same back-end device layer.

4. The static random access memory array according to claim 3, characterized in that: The first N-type field effect transistor and the second N-type field effect transistor are located in a first back-end device layer; A first interconnection wiring layer is formed between the front-end device layer and the first back-end device layer; A second interconnection routing layer is formed on a side of the first back-end device layer away from the first interconnection routing layer; The at least one P-type field effect transistor includes a first P-type field effect transistor and a second P-type field effect transistor; The first P-type field effect transistor is electrically connected to the second P-type field effect transistor through the first interconnect wiring layer; The first N-type field effect transistor is electrically connected to the second N-type field effect transistor through the second interconnect wiring layer.

5. The static random access memory array according to claim 4, characterized in that: The orthographic projection of the first N-type field effect transistor on the semiconductor substrate at least partially overlaps with the orthographic projection of the first P-type field effect transistor on the semiconductor substrate; An orthographic projection of the second N-type field effect transistor on the semiconductor substrate at least partially overlaps with an orthographic projection of the second P-type field effect transistor on the semiconductor substrate.

6. The static random access memory array according to claim 4 or 5, characterized in that: The gate of the first P-type field effect transistor is electrically connected to the first electrode of the second P-type field effect transistor through the first interconnect wiring layer; The gate of the second P-type field effect transistor is electrically connected to the first electrode of the first P-type field effect transistor through the first interconnect wiring layer; The second electrode of the first P-type field effect transistor is electrically connected to the second electrode of the second P-type field effect transistor through the first interconnect wiring layer; The gate of the first N-type field effect transistor is electrically connected to the first electrode of the second N-type field effect transistor through the second interconnect wiring layer; The gate of the second N-type field effect transistor is electrically connected to the first electrode of the first N-type field effect transistor through the second interconnect wiring layer; The second electrode of the first N-type field effect transistor is electrically connected to the second electrode of the second N-type field effect transistor through the second interconnect wiring layer; The first electrode is one of a source and a drain, and the second electrode is the other of the source and the drain.

7. The static random access memory array according to any one of claims 4 to 6, characterized in that: The first electrode of the first P-type field effect transistor is electrically connected to the first electrode of the first N-type field effect transistor; The first electrode of the second P-type field effect transistor is electrically connected to the first electrode of the second N-type field effect transistor.

8. The static random access memory array according to any one of claims 4 to 7, characterized in that: The at least one N-type field effect transistor further comprises: a third N-type field effect transistor and a fourth N-type field effect transistor; The third N-type field effect transistor and the fourth N-type field effect transistor are located in a second back-end device layer of the same back-end device layer; The second interconnect routing layer is located between the first back-end device layer and the second back-end device layer; The orthographic projection of the third N-type field effect transistor on the semiconductor substrate at least partially overlaps with the orthographic projection of the first P-type field effect transistor on the semiconductor substrate; An orthographic projection of the fourth N-type field effect transistor on the semiconductor substrate at least partially overlaps with an orthographic projection of the second P-type field effect transistor on the semiconductor substrate.

9. The static random access memory array according to claim 8, characterized in that: The static random access memory array further includes: a first electrode line, a second electrode line and a third electrode line; The first electrode of the third N-type field effect transistor is electrically connected to the first electrode of the first N-type field effect transistor; The first electrode of the fourth N-type field effect transistor is electrically connected to the first electrode of the second N-type field effect transistor; The gate of the third N-type field effect transistor and the gate of the fourth N-type field effect transistor are both electrically connected to the first electrode line; The second electrode of the third N-type field effect transistor is electrically connected to the second electrode line; The second electrode of the fourth N-type field effect transistor is electrically connected to the third electrode line; The first electrode line is located in the second back-end device layer; The second electrode line and the third electrode line are located in a third interconnection wiring layer; The second back-end device layer is located between the second interconnect routing layer and the third interconnect routing layer.

10. The static random access memory array according to claim 8 or 9, characterized in that: The at least one N-type field effect transistor further comprises: a fifth N-type field effect transistor and a sixth N-type field effect transistor; The first electrode of the fifth N-type field effect transistor is electrically connected to the first electrode of the sixth N-type field effect transistor; The fifth N-type field effect transistor and the sixth N-type field effect transistor are located in the same back-end device layer.

11. The static random access memory array according to claim 10, characterized in that: The static random access memory array further includes: a fourth electrode line and a fifth electrode line; The second electrode of the sixth N-type field effect transistor is electrically connected to the fourth electrode line; A gate of the sixth N-type field effect transistor is electrically connected to the fifth electrode line.

12. The static random access memory array according to claim 11, characterized in that: The fifth N-type field effect transistor and the sixth N-type field effect transistor are located in a third back-end device layer, and the third back-end device layer is closer to the first back-end device layer than the second back-end device layer; A fourth interconnection routing layer is formed between the third back-end device layer and the second back-end device layer; The first electrode of the fifth N-type field effect transistor is electrically connected to the first electrode of the sixth N-type field effect transistor through the fourth interconnect wiring layer; The fifth electrode line is located in the fourth interconnection wiring layer; The fourth electrode line is located in the third interconnection wiring layer.

13. The static random access memory array according to any one of claims 1 to 12, characterized in that: A channel material of the at least one N-type field effect transistor includes an oxide semiconductor material.

14. A method for preparing a static random access memory array, characterized in that: The preparation method comprises: Forming a front-end device layer in a semiconductor substrate by a front-end process, wherein at least one P-type field effect transistor is formed in the front-end device layer; A back-end device layer is formed on the front-end device layer by a back-end process, wherein at least one N-type field effect transistor is formed in the back-end device layer, so as to obtain a storage unit including the at least one P-type field effect transistor and the at least one N-type field effect transistor.

15. The method for preparing a static random access memory array according to claim 14, characterized in that: When the back-end process is used to form the back-end device layer on the front-end device layer, the method includes: The N-type field effect transistor is manufactured in the back-end device layer so that an orthographic projection of the N-type field effect transistor on the semiconductor substrate at least partially overlaps with an orthographic projection of the P-type field effect transistor on the semiconductor substrate.

16. The method for preparing a static random access memory array according to claim 14 or 15, characterized in that: The method of forming a front-end device layer in a semiconductor substrate by using a front-end process comprises: Forming a first P-type field effect transistor and a second P-type field effect transistor in the semiconductor substrate by a front-end process; When the back-end process is used to form a back-end interconnect layer on the front-end device layer, the method includes: A first N-type field effect transistor and a second N-type field effect transistor are formed on the front-end device layer by a back-end process, and the first N-type field effect transistor and the second N-type field effect transistor are located in the same back-end device layer, so as to obtain a storage unit including the first P-type field effect transistor and the first N-type field effect transistor, and the second P-type field effect transistor and the second N-type field effect transistor.

17. The method for preparing a static random access memory array according to claim 16, characterized in that: The first N-type field effect transistor and the second N-type field effect transistor are located in a first back-end device layer; After forming the front-end device layer and before forming the first back-end device layer, the preparation method further includes: forming a first interconnection wiring layer, wherein the first P-type field effect transistor is electrically connected to the second P-type field effect transistor through the first interconnection wiring layer; After forming the first back-end device layer, the preparation method further includes: A second interconnection wiring layer is formed, and the first N-type field effect transistor is electrically connected to the second N-type field effect transistor through the second interconnection wiring layer.

18. The method for preparing a static random access memory array according to claim 16 or 17, characterized in that: After forming the first N-type field effect transistor and the second N-type field effect transistor located in the same back-end device layer, the method further includes: A third N-type field effect transistor and a fourth N-type field effect transistor are formed in the same back-end device layer.

19. A memory, characterized in that: include: A static random access memory array as claimed in any one of claims 1 to 13, or a memory array prepared by the method for preparing a static random access memory array as claimed in any one of claims 14 to 18; A controller is electrically connected to the static random access memory array, and is used to control the reading and writing of the static random access memory array.

20. An electronic device, characterized in that: include: processor; The memory according to claim 19, wherein the processor is electrically connected to the memory, and the memory is used to store data generated by the processor.

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