Ultra-low power consumption nano floating gate 3D NAND structure and preparation method thereof

Abstract

The application relates to an ultra-low-power nanometer floating gate 3D NAND structure, which comprises a substrate, a stack structure arranged on the substrate, the stack structure comprising a plurality of first insulating medium layers and nanometer floating gate storage structures which are alternately stacked, a plurality of through holes penetrating through the stack structure, a tunneling medium layer and a center channel layer being sequentially arranged on the sidewall of each through hole, and a center insulating medium layer being filled in the center channel layer; the nanometer floating gate storage structure is vertically arranged with the tunneling medium layer of the sidewall of the through hole, a second insulating medium layer and a blocking medium layer are sequentially arranged in the direction from the tunneling medium layer to the outside of the through hole, a gate word line metal is embedded on the outside of the blocking medium layer, and a nanometer floating gate layer is arranged below the second insulating medium layer and part of the blocking medium layer. The structure can effectively inhibit charge coupling interference and reduce working voltage and power consumption while further reducing the word line spacing to realize high-density size miniaturization.

Description

Technical Field

[0001] This invention relates to the field of storage devices, and more particularly to an ultra-low power nano-floating gate 3D NAND structure and its fabrication method. Background Technology

[0002] With the rapid development of mobile terminals, artificial intelligence, and big data applications, memory chips need to continuously increase storage capacity within a limited area while meeting low-power operation requirements. As a mainstream storage technology, 3D NAND flash memory's operating voltage and power consumption have become key factors restricting system performance and battery life.

[0003] Current 3D NAND technology primarily increases storage density per unit area by increasing the number of word line stacking layers. However, continuously increasing the number of layers means longer vias and more complex stacking structures, leading to a corresponding increase in the voltage required for programming and erasing operations, resulting in additional energy consumption and posing challenges to power management and thermal design. Simultaneously, to further increase bit density, it is necessary to continuously reduce the word line pitch, i.e., reduce the vertical spacing between adjacent word lines. Reducing the word line pitch faces multiple physical effects and process limitations.

[0004] Specifically, excessively small word line spacing significantly enhances capacitive coupling interference between adjacent word lines, broadening the threshold voltage distribution of memory cells and affecting the ability to distinguish multiple memory states. Furthermore, during programming or erasing operations, the electric field tends to concentrate at word line edges or dielectric layer corners, intensifying the local electric field strength, causing tunnel oxide layer degradation and charge trapping effects, leading to increased threshold voltage fluctuations and decreased data retention characteristics. To suppress these adverse effects and maintain programming reliability, higher operating voltages are often required to enhance the gate's control over the channel, which directly contradicts the goal of low-power design.

[0005] From a manufacturing perspective, the reduction in word pitch places more stringent demands on key steps such as thin film deposition, high aspect ratio etching, and gap filling. Traditional chemical vapor deposition or physical deposition methods struggle to ensure uniform film thickness and step coverage within ultra-small pitch vertical trenches, easily leading to uneven deposition layer thickness, voids, or filling defects. During etching, loading effects and microvia deformation can cause word line morphology distortion, potentially resulting in short circuits or isolation failures between adjacent word lines. These process non-uniformity issues become increasingly prominent with further miniaturization of word pitch, severely impacting the yield and long-term reliability of memory arrays.

[0006] Therefore, how to effectively suppress charge coupling interference, reduce operating voltage and power consumption, and ensure process compatibility and storage reliability with existing 3D NAND manufacturing processes while further reducing word line spacing to achieve high-density size miniaturization has become a technical problem that urgently needs to be solved in this field. Summary of the Invention

[0007] The present invention aims to provide an ultra-low power nano-floating gate 3D NAND structure and its fabrication method to overcome the shortcomings of the prior art. The technical problem to be solved by the present invention is achieved through the following technical solution.

[0008] According to a first aspect of this application, an ultra-low power nano-floating gate 3D NAND structure is provided. Includes a substrate, A stacked structure is disposed on the substrate, the stacked structure comprising a plurality of interleaved first insulating dielectric layers and a nano-floating gate storage structure; A plurality of through holes penetrating the stacked structure are provided, and a tunneling dielectric layer and a central channel layer are sequentially disposed on the sidewall of each through hole, wherein a central insulating dielectric layer is filled in the central channel layer; The nano-floating gate storage structure is perpendicular to the tunneling dielectric layer on the sidewall of the channel. A second insulating dielectric layer and a barrier dielectric layer are sequentially arranged along the tunneling dielectric layer toward the outside of the through hole. A gate wire metal is embedded on the outside of the barrier dielectric layer. A nano-floating gate layer is arranged below the second insulating dielectric layer and part of the barrier dielectric layer.

[0009] Preferably, the nano-floating grid layer is selected from graphene, ALD metal layer, or a composite layer of graphene and ALD metal, and has a thickness of 1-5 nanometers.

[0010] Preferably, the tunneling dielectric layer is selected from one or more composite structures of silicon dioxide, silicon nitride, silicon oxynitride, and high-k dielectric materials.

[0011] Preferably, the grid line metal is made of tungsten, titanium, titanium nitride, polycrystalline silicon, or an alloy of the above materials.

[0012] According to a second aspect of this application, a method for fabricating the above-mentioned ultra-low power nano-floating gate 3D NAND structure is provided, comprising the following steps: Step 1: Vertically deposit several periodic stacked structures on the substrate, wherein the periodic stacked structures, from bottom to top, include a first insulating dielectric layer, a nano-floating gate layer, and a second insulating dielectric layer. Step 2: Etch through holes, the through holes penetrating the plurality of periodic stacked structures; Step 3: After depositing the tunneling dielectric layer and the central channel layer sequentially on the sidewall of the through hole, the through hole is filled with an insulating dielectric to form a central insulating dielectric layer; Step 4: Use selective etching to etch back the second insulating dielectric layer and the nano-floating gate layer to form the first cavity; Step 5: Continue selectively etching the second insulating dielectric layer in the first cavity, and terminate the etching at a distance of 2nm to 30nm from the tunneling dielectric layer to form the second cavity; Step 6: Deposit a barrier dielectric layer on the inner wall of the first cavity and the second cavity, the thickness of the barrier dielectric layer being 5nm to 20nm; Step 7: Fill the space enclosed by the barrier dielectric layer with metal grid material to form grid line metal.

[0013] Preferably, the material of the first insulating dielectric layer is different from the material of the second insulating dielectric layer.

[0014] Preferably, in step 2, the via pattern is defined by photolithography, and then a high aspect ratio via is formed by reactive ion etching based on Cl2 / HBr gas.

[0015] Preferably, in step 3, a tunneling medium layer is deposited using atomic layer deposition or chemical vapor deposition, wherein the equivalent oxide layer thickness EOT of the tunneling medium layer is < 8 nm.

[0016] Preferably, in step 4, dry plasma etching and / or wet chemical etching are used to selectively etch the second insulating dielectric layer and the nano-floating gate layer, so that the etching stops at a distance of 5nm to 50nm from the tunneling dielectric layer.

[0017] Preferably, in step 7, the metal gate material is filled using atomic layer deposition or physical vapor deposition techniques, and the gate line metal is formed after CMP planarization.

[0018] According to the embodiments of this application, the beneficial effects of using the above-described 3D NAND stacked structure and its fabrication method are as follows: This application redesigns the word line stacking method in the vertical direction and introduces a nanoscale floating gate storage layer structure. Utilizing the charge accumulation and electric field enhancement effects of the nanoscale floating gate, a highly localized strong electric field control region is constructed within the storage cell. This effectively amplifies the ability of the local electric field to control the channel charge, thereby significantly improving the gate control efficiency of the floating gate charge. This design enables efficient and reliable charge injection and erasure with only a lower programming voltage, significantly reducing the device's operating voltage and dynamic power consumption. This application optimizes and reconstructs the word line stacking cycle by introducing a symmetrical nano-floating gate structure. This further reduces the spacing between adjacent word lines and increases stacking density while effectively suppressing charge coupling interference between adjacent memory cells under ultra-small word line spacing. The symmetrical structure design enhances the electrical isolation characteristics between word lines, reduces threshold voltage fluctuations and crosstalk risks between multiple storage states, thus maintaining good programming / read windows and data retention reliability even under miniaturized dimensions. This application develops a highly consistent 3D integration process suitable for ultra-small word line pitch. Combining high-precision thin film deposition technologies such as atomic layer deposition and plasma-enhanced chemical vapor deposition with precise etching control, it can form a floating gate memory layer with uniform thickness and steep interface. By introducing a sacrificial layer optimization design, coupled with multi-step etching and selective filling schemes, it effectively solves the process challenges of insufficient uniformity and morphology distortion in thin film deposition under ultra-small pitch, ensuring the morphology consistency and interface quality of the memory cells in the vertical direction, and providing process assurance for the stable operation of the device under ultra-low voltage conditions. The overall process solution of this application is highly compatible with existing 3D NAND manufacturing processes, achieving higher memory layer counts and storage density within the same wafer area. It successfully overcomes the technical bottlenecks of existing 3D NAND in word pitch miniaturization, operating voltage reduction, and power consumption control. The resulting high-density, low-power 3D NAND memory can fully meet the energy- and storage capacity-sensitive needs of artificial intelligence, mobile terminals, and big data applications, powerfully promoting the industrialization of next-generation low-power, high-density storage technologies. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of the ultra-low power nano-floating gate 3D NAND structure in Embodiment 1 of the present invention; Figure 2 This is a schematic diagram of the structure after the deposition of the layered structure in step 1 of embodiment 2 of the present invention; Figure 3 This is a schematic diagram of the structure after etching the through-hole in step 2; Figure 4 This is a schematic diagram of the structure after the tunneling medium layer is deposited in step 3; Figure 5 This is a schematic diagram of the structure after the central channel layer is deposited in step 4; Figure 6 This is a schematic diagram of the structure after the insulating medium is filled into the through hole in step 5; Figure 7 This is a schematic diagram of the structure after the second insulating dielectric layer and the nano-floating gate layer are etched back in step 6; Figure 8 This is a schematic diagram of the structure after selectively etching back the second insulating dielectric layer in step 7; Figure 9 This is a schematic diagram of the structure after the barrier medium layer is deposited in step 8; Figure 10 This is a schematic diagram of the structure after the grid lines are filled with metal in step 9.

[0020] Figure 11 a is a schematic diagram showing the effect of applying a 4V programming voltage to a 20nm floating gate device on the device's memory window; Figure 11 b is a schematic diagram illustrating the effect of applying a 4V programming voltage to a 1nm floating gate device on the device's memory window. Detailed Implementation

[0021] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. The present invention will now be described in detail with reference to the accompanying drawings and embodiments.

[0022] It should be noted that the above detailed descriptions are exemplary and intended to provide further explanation of this application. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains.

[0023] Example 1

[0024] like Figure 1 As shown, the ultra-low power nano-floating gate 3D NAND structure in this embodiment includes a substrate 100, on which a stacked structure is disposed, and on the stacked structure, there are a plurality of first insulating dielectric layers 110 and a nano-floating gate storage structure stacked in an alternating manner. A plurality of through holes 101 penetrate the stacked structure, and a tunneling dielectric layer 210 and a central channel layer 220 are sequentially disposed on the sidewall of each through hole 101, and a central insulating dielectric layer 230 is filled in the central channel layer 220. The nano-floating gate storage structure is perpendicular to the tunneling dielectric layer 210 of the through hole sidewall. A second insulating dielectric layer 130 and a barrier dielectric layer 140 are sequentially arranged along the tunneling dielectric layer 210 toward the outside of the through hole 101. A gate wire metal 150 is embedded on the outside of the barrier dielectric layer 140. A nano-floating gate layer 120 is arranged below the second insulating dielectric layer 130 and part of the barrier dielectric layer 140.

[0025] In this embodiment, the substrate 100 may be a single-crystal silicon substrate 100, a silicon-on-insulator (SOI) substrate 100, a silicon-germanium (SiGe) substrate 100, or a compound semiconductor substrate 100 (such as GaAs or InP), used to provide mechanical support and serve as an electrical reference for the bottom layer of the device; its surface flatness, lattice integrity, and thermal stability must meet the requirements of subsequent high-precision thin film deposition and etching processes; in this application, the substrate 100 undertakes the functions of substrate support, heat sink heat dissipation, and bottom electrode lead-out, and forms a physical and electrical isolation interface with the first insulating dielectric layer 110 to prevent leakage current from spreading to the substrate 100 body.

[0026] In this embodiment, the first insulating dielectric layer 110 can be any one of silicon nitride (SiN), silicon oxide (SiO2), silicon oxynitride (SiON), phosphorus-doped glass (PSG), boron-doped glass (BSG), or a low dielectric constant medium (such as SiCOH, porous SiO2) or a composite stack thereof; its thickness is in the range of 10-50 nm; the first insulating dielectric layer 110 is located on the substrate 100, and together with the subsequent stacked structure, it forms the vertical interlayer isolation base. Its material selection needs to take into account the etching selectivity ratio with the substrate 100 and the sacrificial layer above, so as to achieve selective removal in subsequent steps; in this application, the first insulating dielectric layer 110 serves as the initial isolation layer, and its composition needs to have distinguishable etching characteristics from the second insulating dielectric layer 130. The first insulating dielectric layer 110 and the nano-floating gate memory structure are stacked alternately, together forming the physical carrier of the three-dimensional word line and memory cell; its function is to provide electrical isolation, mechanical support, and stress buffering between adjacent nano-floating gate memory structures.

[0027] The second insulating dielectric layer 130 can be SiO2, SiN, SiON, high-k dielectrics (such as HfO2, Al2O3) or a combination thereof, with a thickness in the range of 10-50 nm. The second insulating dielectric layer 130 and the first insulating dielectric layer 110 are independent of each other in terms of material to ensure a high selectivity between different layers in the anisotropic etching process.

[0028] The barrier dielectric layer 140 can be one or more of alumina, hafnium oxide, zirconium oxide, yttrium oxide, tantalum oxide, lanthanum oxide, titanium oxide and their silicates, nitrides or stacked structures (such as Al2O3 / HfO2), with a thickness of 5-20 nanometers.

[0029] The nano-floating gate layer 120 can be graphene, an ALD metal layer (such as TiN, TaN, W), or a composite layer of graphene and ALD metal, with a thickness of 1-5 nm. The nano-floating gate layer 120 is directly located above the first insulating dielectric layer 110 and below the gate line metal 150, and is in physical contact with the tunneling dielectric layer 210. Its nanoscale thickness and high aspect ratio structure can generate a significant electric field enhancement effect at the tip / edge when a gate voltage is applied, so that the local electric field intensity can reach several times that of the macroscopic electric field. In this application, the nano-floating gate layer 120 is the core physical carrier for realizing ultra-low voltage operation. Its material selection needs to take into account work function matching (to control the threshold voltage), etching process compatibility (to avoid damaging the underlying first insulating dielectric layer 110), and thermal stability (to withstand subsequent high-temperature processes). For example, graphene has atomic-level thickness and excellent carrier mobility, while the ALD metal layer has good step coverage and conductivity. The combination of the two can take into account both electrical performance and structural robustness.

[0030] The gate word line metal 150 can be tungsten (W), titanium (Ti), titanium nitride (TiN), polysilicon (poly-Si), or an alloy thereof. The gate word line metal 150 is located above the nano-floating gate layer 120 and is separated by a barrier dielectric layer 140, serving as the input port for the word line potential. It is isolated from the tunneling dielectric layer 210 by a second insulating dielectric layer 130 to prevent the word line voltage from being directly applied to the tunneling dielectric layer 210, causing breakdown or irreversible degradation. In this application, the resistivity and linewidth of the gate word line metal 150 must meet the 3D NAND word line RC delay requirements to ensure high-speed read and write response.

[0031] The central channel layer 220 can be any one or a combination of polycrystalline silicon, monocrystalline silicon, IGZO, SiGe, MoS2, WSe2, WS2, and MoSe2; it can be formed by chemical vapor deposition (CVD), epitaxial growth, physical vapor deposition (PVD), or spin coating; the central channel layer 220 covers the inner side of the tunneling dielectric layer 210, forming a vertical carrier transport trunk; its conductivity type, doping concentration, and lattice quality determine the on-state current and subthreshold swing of the device; in this application, the central channel layer 220, the tunneling dielectric layer 210, and the central insulating dielectric layer 230 form a coaxial channel structure, which is surrounded by the tunneling dielectric layer 210, thereby achieving full circumferential electric field modulation under the action of the gate voltage, improving gate control efficiency and suppressing short-channel effects.

[0032] The central insulating dielectric layer 230 can be any one of SiO2, SiON, SiONH, SiCN, HfO2, Al2O3, ZrO2, HfZrO, TiO2, SiCOH, high-k dielectric, spin-coated glass, or spin-coated carbon. It is filled into the cavity inside the central channel layer 220 by chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), or spin coating, and its surface is planarized by chemical mechanical polishing (CMP). The central insulating dielectric layer 230 is used to isolate the central channel layer 220 from other conductive structures in the via 101, preventing leakage and parasitic capacitance formation. Its conformal and compact filling properties directly affect the reliability and yield of the device. In this application, the central insulating dielectric layer 230, together with the tunneling dielectric layer 210 and the central channel layer 220, constitutes a three-layer coaxial structure of insulation-dielectric-channel, providing electrostatic shielding for the channel and enhancing anti-interference capability.

[0033] The tunneling dielectric layer 210 is made of materials such as silicon dioxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), high-k dielectrics, and their multilayer composite structures. Among them, the high-k dielectrics are such as hafnium oxide (HfO2), zirconium oxide (ZrO2), or lanthanum oxide (La2O3), and the multilayer composite structures are such as the composite structure of silicon dioxide (SiO2), silicon nitride (SiN), and its oxide. The equivalent oxide layer thickness EOT < 8nm ensures the charge tunneling efficiency.

[0034] This embodiment constructs a three-dimensional stacked memory cell with a nano-floating gate and a tunneling dielectric layer 210 vertically coupled. Utilizing the synergistic mechanism of the tip field enhancement effect of the nano-floating gate layer 120 and the charge storage of the floating gate, efficient charge control at ultra-low voltage is achieved in the three-dimensional architecture. By employing a nano-floating gate memory layer structure, this embodiment leverages its charge accumulation and electric field enhancement effects to significantly improve the gate's control efficiency over the charge in the floating gate. Therefore, during programming operations, only a lower voltage is needed to achieve effective electron injection and erasure, thereby directly reducing the core's operating voltage and power consumption.

[0035] By reconstructing the word line stacking cells, a nanofloating gate layer 120 and a barrier dielectric are embedded between the gate word line metal 150 and the tunneling dielectric layer 210, achieving efficient conversion from word line voltage to a localized strong electric field. This structure utilizes its charge focusing effect and electric field enhancement effect to significantly improve the gate's control efficiency over the charges in the floating gate, reducing operating voltage and power consumption. Simultaneously, the field focusing effect of the nanofloating gate layer 120 and the sufficient isolation from the first insulating dielectric layer 110 effectively suppress electrical crosstalk between adjacent memory cells in the vertical stacking direction, ensuring accurate data access.

[0036] This application innovatively introduces field enhancement physics from vacuum field emission into 3D NAND memory cell design, achieving an interdisciplinary fusion of nanoelectronics and vacuum microelectronics. By reducing the thickness of the 120mm nanofloating gate layer to the atomic / nanometer level and utilizing its edge tip effect, the gate charge is locally highly concentrated, forming a localized field with a strength several times greater than the macroscopic electric field. This gate geometry optimization design significantly enhances the programming electric field strength while reducing the gate size, thereby significantly improving the programming efficiency of the memory cell and effectively reducing operating power consumption.

[0037] This localized enhanced electric field significantly improves the controllability of the channel region: during programming and erasing operations, it enables more efficient charge injection and extraction, noticeably altering the channel surface potential distribution and carrier concentration, thereby causing a wider range of shifts in the device threshold voltage. This characteristic effectively widens the storage window and improves the device's performance and reliability.

[0038] like Figure 11 a and Figure 11 As shown in b, when the floating gate size is reduced from the conventional 20 nanometers to a 1-nanometer scale metal nanofloating gate structure, a significant electric field concentration enhancement phenomenon can be generated under the same programming voltage. This effect has a similar physical mechanism to the formation of a strong electric field concentration at a needle tip. This study innovatively integrates the field enhancement mechanism from vacuum field emission theory into NAND memory cell design, realizing an interdisciplinary combination of nanoelectronic devices and vacuum physics effects. After optimizing the floating gate geometry, the tip concentration effect is effectively utilized while the size is reduced, causing the charge to accumulate highly locally in the floating gate, thereby improving the programming efficiency of the memory cell and reducing power consumption.

[0039] Example 2

[0040] like Figures 2 to 10 As shown, the fabrication method of the ultra-low power nano-floating gate 3D NAND structure in this embodiment includes the following steps: Step 1, Stacked Structure Deposition: Several periodic stacked structures are deposited alternately on the substrate 100 using chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), or atomic layer deposition (ALD) processes as needed; specifically: The periodic stacked structure includes, from bottom to top, a first insulating dielectric layer 110, a nano-floating gate layer 120, and a second insulating dielectric layer 130. The materials of the first insulating dielectric layer 110 and the second insulating dielectric layer 130 can be silicon dioxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), low-k dielectrics (such as carbon-doped oxide SiCOH, porous silicon dioxide) or high-k dielectrics (such as hafnium oxide HfO2, aluminum oxide Al2O3) and their composite stacks (such as SiO2 / SiN stacks), with a thickness ranging from 10 to 50 nanometers. The first insulating dielectric layer 110 and the second insulating dielectric layer 130 need to be made of different materials (e.g., the first insulating dielectric layer 110 is silicon nitride, and the second insulating dielectric layer 130 is a doped oxide) to facilitate subsequent selective etching.

[0041] Nanoscale floating grating layer 120: transferred graphene / alone ALD metal layer / or graphene and ALD metal composite layer, with a thickness of 1-5 nanometers.

[0042] After the periodic stacked structure is deposited, it is annealed at 800-1000℃ to improve the film quality.

[0043] Step 2, Etching Through-Hole 101: The pattern of through-hole 101 is defined using photolithography, followed by reactive ion etching (RIE) based on Cl2 / HBr gas to form the high aspect ratio through-hole 101 structure. Specifically: A high-performance inductively coupled plasma reactive ion etching (ICP-IR) system was employed, utilizing Cl2 for efficient vertical chemical etching, and HBr to form a protective passivation layer on the sidewalls to suppress lateral etching; finally, Ar was used... + Physical bombardment is used to enhance the reaction and selectively remove the passivation layer at the bottom of the via. This method can successfully fabricate high aspect ratio via 101 structures with steep sidewalls and controllable profiles, which can be used in 3D stacked structures to improve etching accuracy.

[0044] Step 3, Deposition of tunneling dielectric layer 210: Silicon dioxide, silicon nitride, silicon oxynitride, high-k dielectrics (such as hafnium oxide, zirconium oxide, lanthanum oxide) and their multilayer composite structures (such as SiO2 / SiN / Oxide) are prepared on the inner wall of the through hole 101 by atomic layer deposition or chemical vapor deposition as tunneling layer (equivalent oxide layer thickness EOT < 8nm) to ensure charge tunneling efficiency.

[0045] Taking atomic layer deposition (ALD) technology as an example, the specific steps are as follows: First, the stacked structure with the formed through-hole 101 is placed in the ALD reaction chamber, and the inner wall of the through-hole 101 is cleaned in situ by remote hydrogen plasma to remove the surface natural oxides and organic residues. Then, the chamber is heated to the deposition temperature window of 150-300℃, and high-purity nitrogen or argon is introduced as a carrier gas to stabilize the pressure in the chamber to 0.1-10 Torr.

[0046] A silicon-containing precursor, such as bis(tert-butylamino)silane (BTBAS) or hexachlorosilane (HCDS), is selected and introduced into the cavity in the form of a short pulse (0.1-1 second). This causes the precursor molecules to undergo chemical adsorption on the first insulating dielectric layer 110 on the sidewall of the through hole 101 and the exposed surface of the nano-floating gate storage structure, forming a saturated silicon precursor monolayer.

[0047] Next, the first purging step is performed, in which a large flow of nitrogen is introduced for 10-30 seconds to completely remove the unadsorbed excess precursors and gaseous byproducts from the reaction chamber, ensuring that only self-limiting monolayer adsorption is retained on the channel sidewall.

[0048] Then, an oxygen source reactant pulse, such as ozone (O3) or water vapor (H2O), is introduced. The reactant molecules undergo hydrolysis or oxidation reactions with the silicon precursors adsorbed on the surface to generate a hydroxylated silicon dioxide monolayer and release organic ligands or hydrogen halide byproducts.

[0049] The second purging step is then performed, similarly purging with inert gas for 10-30 seconds to remove excess oxidant and reaction byproducts, thus completing one ALD growth cycle. This cycle precisely controls the growth of approximately 0.1 nm of SiO2 film per cycle.

[0050] By repeating this pulse-purge-pulse-purge cycle, setting the total number of cycles to 40-80, a high-quality tunneling silicon oxide layer with a thickness of 4-8 nm and an equivalent oxide layer thickness of less than 8 nm can be uniformly deposited on the sidewall of via 101. Its thickness accuracy can be controlled within ±1 Å by ellipsometer or TEM verification.

[0051] After deposition, rapid thermal annealing can be performed for 1-5 minutes in a nitrogen atmosphere at 400-600℃ to improve film density and repair interface defects.

[0052] This ALD process, with its self-limiting surface saturation reaction characteristics, exhibits excellent step coverage and thickness uniformity on the inner wall of the via 101 with an ultra-high aspect ratio (>50:1). Furthermore, by using optimized purging and temperature parameters, it effectively suppresses the low-k interface transition layer. The resulting silicon dioxide film is free of pinholes, has low leakage current, and forms a steep, high-quality interface with the subsequent central channel layer 220, providing a reliable charge tunneling path for the device.

[0053] Step 4: Growth of central channel layer 220: Polycrystalline silicon, monocrystalline silicon, oxide semiconductor (such as IGZO), silicon-germanium alloy, and two-dimensional materials (such as molybdenum disulfide, tungsten diselenide, tungsten disulfide, molybdenum diselenide, etc.) channel materials are grown by chemical vapor deposition, epitaxial growth, physical vapor deposition, spin coating, etc., to form central channel layer 220.

[0054] Taking metal-organic chemical vapor deposition (MOCVD) epitaxial growth as an example, the specific steps are as follows: Precursor transport: The organometallic source (such as trimethylgallium for Ga) and hydrides (such as arsine and phosphine) are precisely transported to the reaction chamber via a carrier gas; Surface reaction and growth: The precursor undergoes thermal decomposition and chemical reaction on the heated surface of the tunneling dielectric layer 210, and high-quality single-crystal thin films (such as GaAs and GaN) are epitaxially grown. Thickness and doping control: By precisely controlling the growth time, temperature and gas flow rate, the thickness, composition and electrical doping of the channel material can be precisely controlled.

[0055] Step 5, Center Insulating Dielectric Filling and Planarization: Insulating dielectrics such as silicon oxide, silicon oxynitride, silicon oxynitride, silicon carbide, hafnium oxide, aluminum oxide, zirconium oxide, hafnium zirconium oxide, titanium oxide, low-k dielectrics (such as SiCOH), high-k dielectrics, and spin-coated dielectric materials (such as spin-coated glass and spin-coated carbon) are filled using chemical vapor deposition (high conformal filling), plasma-enhanced chemical vapor deposition, spin coating, and atomic layer deposition, and then CMP (chemical mechanical polishing) is performed for planarization.

[0056] The detailed operating steps for filling with chemical vapor deposition silicon oxide as the central insulating dielectric are as follows: The wafer with the central trench layer 220 deposited is placed in a low-pressure CVD reaction chamber. After the chamber is evacuated to a base vacuum, it is heated to 350-500℃ and then argon or nitrogen is introduced to stabilize the pressure to 0.5-5 Torr.

[0057] Tetraethyl orthosilicate and ozone are used as silicon and oxygen sources, respectively, and are introduced into the cavity through independent pipelines. TEOS is carried in by carrier gas through a heated bubbler and is fully mixed with O3 at the top and inside of the through hole 101.

[0058] Gas molecules are transported to the sidewalls and bottom of the deep hole through diffusion and convection. Surface adsorption and thermal decomposition reactions occur on the inner wall of the through hole 101, which is covered by the tunneling medium layer 210 and the central channel layer 220. The decomposition products nucleate on the surface of the central channel layer 220 and gradually grow into a continuous silicon oxide film. At the same time, byproducts such as ethanol and water are released and discharged with the carrier gas.

[0059] By adjusting the TEOS to O3 flow ratio, cavity pressure and deposition time, the internal cavity of the via 101 is continuously filled at a low deposition rate (<10 nm / min) until silicon oxide completely fills the central cavity to form the central insulating dielectric layer 230.

[0060] After deposition, chemical mechanical polishing is used to remove excess silicon oxide from the wafer surface, and planarization is achieved by using the interface layer as a stop layer.

[0061] Annealing at 400-600℃ in a nitrogen atmosphere can be used to enhance the film density. The silicon oxide obtained by this process is densely filled, free of voids or gap defects, and forms a good insulating interface with the central channel layer 220, effectively isolating the channel layer and suppressing parasitic capacitance and leakage current, thus ensuring the reliability and yield of 3D NAND devices.

[0062] The simple steps for chemical mechanical polishing (CMP) surface planarization are as follows: Fixing and Pressuring: Fix the wafer face down on the polishing head and press it onto the rotating polishing pad, applying precise pressure; Chemical and mechanical action: A polishing slurry containing nano-abrasives and chemical reagents is simultaneously delivered to the polishing pad. The chemical action softens the thin film material; the mechanical action removes it through the abrasive particles. Selective removal: Utilizing the selectivity of the process for different materials, the raised parts are removed first to achieve global flattening; Cleaning and drying: After polishing, thoroughly clean the wafer to remove all abrasive and impurities, and then dry it.

[0063] Step 6: Etching back the second insulating dielectric layer 130 and the nano-floating gate layer 120: Selective etching processes include dry plasma etching and / or wet chemical etching. For silicon dioxide (SiO2), silicon oxynitride (SiON), and low-k dielectrics (carbon-doped oxide SiCOH, porous silicon dioxide), CHF3 / O2 plasma dry etching can be used, but is not limited to. Precise etching is achieved by controlling the gas ratio of CHF3 to O2, the cavity pressure, and the etching power. For silicon nitride (SiN), hot phosphoric acid (H3PO4) wet etching can be used, but is not limited to. The etching temperature and time are controlled to ensure the etching selectivity. During the etching process, the etching endpoint is precisely controlled so that etching stops at a distance of 5 nm to 50 nm from the tunneling dielectric layer 210, forming a first cavity 102 to avoid damage to the tunneling dielectric layer 210. Wherein: Dry plasma etching: Taking the etch-back of the silicon dioxide second insulating dielectric layer 130 as an example, the wafer with the nano-floating gate layer 120 already formed is sent into the reactive ion etching chamber. After the chamber is evacuated to a base vacuum, a mixture of CHF3 and O2 gas is introduced, with a CHF3 flow rate of 20-80 sccm and an O2 flow rate of 2-15 sccm. By adjusting the ratio of the two gases, the dynamic balance between polymer deposition and chemical etching is optimized, and the chamber pressure is maintained at 10-100 mTorr. A radio frequency power of 200-800 W is applied to excite the plasma, CF... xUnder a bias electric field, active free radicals directionally bombard the exposed surface of the second insulating dielectric layer 130, reacting with SiO2 to generate volatile SiF4 and byproducts such as CO and CO2, which are continuously removed by a turbomolecular pump. This process utilizes anisotropic etching characteristics to vertically remove the second insulating dielectric layer 130, while simultaneously achieving high selectivity by leveraging the etching rate difference between the second insulating dielectric layer 110 and the nano-floating gate layer 120. The intensity changes of characteristic spectral lines of the etching products are monitored in real time using optical emission spectroscopy. When a characteristic signal of the nano-floating gate layer 120 is detected, a low-bias over-etching step is initiated, stopping the etching at the surface of the nano-floating gate layer 120. Subsequently, the etching gas formulation is changed to specifically remove the nano-floating gate layer 120. Combined with preset time control and endpoint detection, the etching is precisely terminated at a distance of 5-50 nm from the tunneling dielectric layer 210, forming a first cavity 102, thus preventing plasma damage from penetrating into the tunneling dielectric layer 210 throughout the process.

[0064] Wet chemical etching: Taking the etching back of the silicon nitride second insulating dielectric layer 130 as an example, the wafer surface is first pretreated with oxygen plasma to improve surface wettability. Then, the wafer is immersed in an 85% hot phosphoric acid solution. The solution temperature is stabilized at 140-160℃ using a precisely controlled hot stage. This temperature window allows for high selectivity etching of silicon nitride relative to silicon oxide and the nano-floating gate layer 120. Under the synergistic effect of phosphoric acid and water molecules, the Si-N bonds on the SiN surface gradually hydrolyze and break, generating soluble silicate and ammonium ions that enter the solution. Magnetic stirring continuously renews the interface reaction layer to ensure uniform etching rate. The etching rate is precisely controlled by temperature and concentration, typically 3-6 nm / min. When approaching the interface of the nano-floating gate layer 120, the erosion rate of the etchant on the oxides on the surface of the metal nitride nano-floating gate layer 120 significantly decreases, forming a natural etching termination effect. In actual operation, through preset time control and in-situ ellipsometer monitoring, after the nano-floating gate layer 120 is exposed, the wafer is quickly transferred to a deionized water overflow cleaning tank for quenching and rinsing, followed by isopropanol drying. Subsequently, based on the material of the nano-floating gate layer 120, a mild formula such as dilute hydrofluoric acid or SC-1 cleaning solution is selected, and time-limited peeling is performed at an extremely low etching rate, precisely terminating at a distance of 50-110 nm from the tunneling dielectric layer 210 to form the first cavity 102, ensuring that the tunneling dielectric layer 210 remains intact.

[0065] Step 7, Selective etching back of the second insulating dielectric layer 130: The selective etching process can be, but is not limited to, CHF3 / O2 plasma dry etching or hot phosphoric acid (H3PO4) wet etching. Dry etching is suitable for silicon dioxide (SiO2), silicon oxynitride (SiON) and low-k dielectrics, while wet etching is suitable for silicon nitride (SiN). A single etching process or a composite etching process can be selected according to the specific material combination of the insulating layer. The etching terminates at a distance of 2 nm to 30 nm from the tunneling dielectric layer 210 to form a second cavity 103, ensuring the etching accuracy and the integrity of the tunneling dielectric layer 210.

[0066] Step 8, Deposition of barrier dielectric layer 140: Alumina, hafnium oxide, zirconium oxide, yttrium oxide, tantalum oxide, lanthanum oxide, titanium oxide and their silicates, nitrides or stacked structures (such as Al2O3 / HfO2) are prepared as barrier layers with a thickness of 5-20 nanometers by atomic layer deposition or chemical vapor deposition.

[0067] The specific steps for using atomic layer deposition of alumina as the barrier dielectric layer 140 are as follows: The wafer with the first cavity 102 etched back is placed in the ALD reaction chamber, which is heated to 200-300°C and nitrogen gas is introduced to stabilize the pressure at 0.1-5 Torr. Trimethylaluminum (TMA) is selected as the aluminum precursor and introduced into the chamber with a short pulse of 0.1-0.5 seconds. TMA molecules undergo self-limiting chemisorption on the exposed nano-floating gate layer 120, the second insulating dielectric layer 130, and the tunneling dielectric layer 210 to form a saturated Al-CH3 monolayer.

[0068] Then, a high flow rate of nitrogen is introduced to purge for 15-30 seconds to remove excess unadsorbed TMA and gaseous byproducts. Next, water vapor is pulsed for 0.1-1 seconds, and H2O molecules undergo a hydrolysis reaction with surface methyl groups to generate hydroxylated aluminum oxide and release methane gas.

[0069] The residual H2O and byproducts were removed by purging with nitrogen for 15-30 seconds, completing an ALD cycle that grows approximately 0.1 nm of alumina.

[0070] Repeating this pulse-purge-pulse-purge cycle 50-200 times will uniformly deposit a high-conformity alumina barrier layer with a thickness of 5-20 nm on the inner wall and bottom of the first cavity 102.

[0071] This process, leveraging its self-limiting surface reaction characteristics, achieves excellent step coverage and film thickness uniformity in complex three-dimensional cavity morphologies. The resulting film is dense and pinhole-free, with a steep interface with adjacent dielectric layers, effectively blocking charge injection and diffusion from the gate line metal 150 to the tunneling dielectric layer 210. After deposition, annealing at 400-500℃ in a nitrogen atmosphere can be performed to improve the film's density and insulation properties.

[0072] Step 9, Filling the gate line metal 150: Using atomic layer deposition (ALD) or physical vapor deposition (PVD) techniques, fill the formed cavity with a metal gate material (such as W, Ti / TiN, polycrystalline silicon or its alloys) to form the gate line metal 150, and then perform CMP planarization again.

[0073] In this embodiment, atomic layer deposition (ALD) is selected as it is the most reliable method for filling complex cavity structures, enabling pore-free, uniform, and continuous filling. The specific steps are as follows: Pretreatment: Clean the surface of the cavity structure to enhance film adhesion; Cyclic deposition: The wafer is placed in the ALD reaction chamber and a metal precursor (such as WF6 for tungsten) and a reactive gas (such as H2 or Si2H6) are alternately pulsed through it. Self-limiting reaction: Each precursor undergoes a self-limiting reaction with the surface, and only one atomic thin film is deposited per cycle; Thorough purging: After each pulse, thoroughly purge with inert gas to remove residues and prevent gas-phase reactions; Repeated cycle: This cycle is repeated continuously, growing evenly from the cavity sidewalls and bottom towards the center until the cavity is completely filled, forming a seamless grid line metal 150.

[0074] This method combines high-precision thin-film deposition techniques such as atomic layer deposition (ALD) and plasma-enhanced chemical vapor deposition (PECVD) with anisotropic etching processes to achieve precise control over the thickness and morphology of the nanofloating gate layer, ensuring its interface quality and electrical performance. Simultaneously, by introducing multi-step etching and selective filling processes, the interfacial characteristics of multilayer functional materials in the three-dimensional structure are effectively optimized, significantly reducing performance fluctuations between different memory cells. This not only directly improves chip yield and reliability but also provides a solid and reliable process guarantee for its large-scale, high-density integration in ultra-large arrays.

[0075] The entire technical solution is designed with high compatibility with existing 3D NAND flash memory manufacturing platforms in mind. The core fabrication steps do not require specialized or expensive dedicated equipment, allowing for rapid implementation and large-scale mass production. This feature significantly reduces the difficulty and cost of technology iteration and production line implementation, making it an efficient and feasible technical path to resolve the current contradiction between energy consumption and density, with broad market application prospects.

[0076] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments according to this application. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0077] It should be noted that the terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such terms can be used interchangeably where appropriate so that the embodiments of this application described herein can be implemented in sequences other than those illustrated or described herein.

[0078] Furthermore, the terms “comprising” and “having”, and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not necessarily limited to those steps or units that are explicitly listed, but may include other steps or units that are not explicitly listed or that are inherent to such process, method, product, or apparatus.

[0079] For ease of description, spatial relative terms such as "above," "on top of," "on the upper surface of," "above," etc., are used herein to describe the spatial positional relationship of a device or feature as shown in the figures to other devices or features. It should be understood that spatial relative terms are intended to encompass different orientations in use or operation beyond the orientation of the device as described in the figures. For example, if the device in the figures were inverted, a device described as "above" or "on top of" other devices or structures would subsequently be positioned as "below" or "under" other devices or structures. Thus, the exemplary term "above" can include both "above" and "below." The device may also be positioned in other different ways, such as rotated 90 degrees or in other orientations, and the spatial relative descriptions used herein will be interpreted accordingly.

[0080] In the detailed description above, reference has been made to the accompanying drawings, which form part of this document. In the drawings, similar symbols typically identify similar parts unless the context otherwise indicates otherwise. The illustrated embodiments described in the detailed specification, drawings, and claims are not intended to be limiting. Other embodiments may be used and other changes may be made without departing from the spirit or scope of the subject matter presented herein.

[0081] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. An ultra-low power nano-floating gate 3D NAND structure, characterized in that, Includes a substrate, A stacked structure is disposed on the substrate, the stacked structure comprising a plurality of interleaved first insulating dielectric layers and a nano-floating gate storage structure; A plurality of through holes penetrating the stacked structure are provided, and a tunneling dielectric layer and a central channel layer are sequentially disposed on the sidewall of each through hole, wherein a central insulating dielectric layer is filled in the central channel layer; The nano-floating gate storage structure is perpendicular to the tunneling dielectric layer on the sidewall of the via. A second insulating dielectric layer and a barrier dielectric layer are sequentially arranged along the tunneling dielectric layer toward the outside of the via. A gate wire metal is embedded on the outside of the barrier dielectric layer. A nano-floating gate layer is arranged below the second insulating dielectric layer and part of the barrier dielectric layer.

2. The ultra-low power nano-floating gate 3D NAND structure according to claim 1, characterized in that, The nano-floating grid layer is selected from graphene, ALD metal layer, or a composite layer of graphene and ALD metal, with a thickness of 1-5 nanometers.

3. The ultra-low power nano-floating gate 3D NAND structure according to claim 1, characterized in that, The tunneling dielectric layer is selected from one or more composite structures of silicon dioxide, silicon nitride, silicon oxynitride, and high-k dielectric materials.

4. The ultra-low power nano-floating gate 3D NAND structure according to claim 3, characterized in that, The grid line metal is made of tungsten, titanium, titanium nitride, polycrystalline silicon, or an alloy of the above materials.

5. A method for fabricating an ultra-low power nano-floating gate 3D NAND structure as described in claim 1, characterized in that, Includes the following steps: Step 1: Vertically deposit several periodic stacked structures on the substrate, wherein the periodic stacked structures, from bottom to top, include a first insulating dielectric layer, a nano-floating gate layer, and a second insulating dielectric layer. Step 2: Etch through holes, the through holes penetrating the plurality of periodic stacked structures; Step 3: After depositing the tunneling dielectric layer and the central channel layer sequentially on the sidewall of the through hole, the through hole is filled with an insulating dielectric to form a central insulating dielectric layer; Step 4: Use selective etching to etch back the second insulating dielectric layer and the nano-floating gate layer to form the first cavity; Step 5: Continue selectively etching the second insulating dielectric layer in the first cavity, and terminate the etching at a distance of 2nm to 30nm from the tunneling dielectric layer to form the second cavity; Step 6: Deposit a barrier dielectric layer on the inner wall of the first cavity and the second cavity, the thickness of the barrier dielectric layer being 5nm to 20nm; Step 7: Fill the space enclosed by the barrier dielectric layer with metal grid material to form grid line metal.

6. The method for fabricating the ultra-low power nano-floating gate 3D NAND structure according to claim 5, characterized in that, The material of the first insulating dielectric layer is different from that of the second insulating dielectric layer.

7. The method for fabricating the ultra-low power nano-floating gate 3D NAND structure according to claim 5, characterized in that, In step 2, the via pattern is defined by photolithography, and then a high aspect ratio via is formed by reactive ion etching based on Cl2 / HBr gas.

8. The method for fabricating the ultra-low power nano-floating gate 3D NAND structure according to claim 5, characterized in that, In step 3, a tunneling medium layer is deposited using atomic layer deposition or chemical vapor deposition, wherein the equivalent oxide layer thickness EOT of the tunneling medium layer is < 8 nm.

9. The method for fabricating the ultra-low power nano-floating gate 3D NAND structure according to claim 5, characterized in that, In step 4, dry plasma etching and / or wet chemical etching are used to selectively etch the second insulating dielectric layer and the nano-floating gate layer, so that the etching stops at a distance of 5nm to 50nm from the tunneling dielectric layer.

10. The method for fabricating the ultra-low power nano-floating gate 3D NAND structure according to claim 5, characterized in that, In step 7, the metal gate material is filled using atomic layer deposition or physical vapor deposition techniques, and then CMP planarization is performed to form the gate line metal.

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