Thin film transistor and display device including the same

Abstract

The invention relates to a thin film transistor and a display device including the same. The thin film transistor includes: an active layer; and a gate electrode spaced apart from the active layer and partially overlapping the active layer; the active layer includes: a channel region partially overlapping the gate electrode; a source region connected to one side of the channel region; and a drain region connected to the other side of the channel region. The active layer defines an active hole in which the active layer is absent, at least a portion of the active hole overlaps the gate electrode in a plan view, and at least another portion of the active hole extends beyond an edge of the gate electrode. The gate electrode includes a body portion and a protruding portion protruding in a first direction, which is a direction parallel to a shortest line connecting the source region and the drain region.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of priority to Korean Patent Application No. 10-2023-0120081, filed on September 11, 2023, which is hereby incorporated by reference as if fully set forth herein. Technical Field

[0003] The present invention relates to a thin film transistor and a display device including the thin film transistor. Background Art

[0004] Transistors are widely used as switching devices or driving devices in the field of electronic devices. In particular, since thin film transistors can be manufactured on glass substrates or plastic substrates, thin film transistors are widely used as switching devices of display devices such as liquid crystal display devices or organic light emitting devices.

[0005] Based on the material constituting the active layer, the thin film transistor can be divided into an amorphous silicon thin film transistor using amorphous silicon as an active layer, a polycrystalline silicon thin film transistor using polycrystalline silicon as an active layer, and an oxide semiconductor thin film transistor using an oxide semiconductor as an active layer.

[0006] Amorphous silicon thin film transistors (a-Si TFTs) have the advantages of short manufacturing process time and low production cost because amorphous silicon can be deposited in a short time to form an active layer, but have the disadvantage of limited use in active matrix organic light-emitting devices (AMOLEDs) due to low mobility and poor current driving capability and variation in threshold voltage.

[0007] Polycrystalline silicon thin film transistors (poly-Si TFTs) are made by crystallizing amorphous silicon after depositing it. Since a process of crystallizing amorphous silicon is required in the manufacturing process of polycrystalline silicon thin film transistors, the manufacturing cost increases as the number of processes increases, and since the crystallization process is performed at a high process temperature, it is difficult to apply polycrystalline silicon thin film transistors to large-area devices. In addition, due to its polycrystalline characteristics, it is difficult to ensure the uniformity of polycrystalline silicon thin film transistors.

[0008] In an oxide semiconductor thin film transistor (TFT), since the oxide constituting the active layer can be formed at a relatively low temperature, has high mobility, and has a large resistance change according to the oxygen content, it is easy to obtain the desired physical properties. In addition, due to the properties of the oxide, since the oxide semiconductor is transparent, it is also advantageous for realizing a transparent display.

[0009] In oxide semiconductors, when the width of an active layer increases, the penetration depth of conduction increases and the length of an effective channel decreases, so that the driving stability of a thin film device may be deteriorated. Therefore, technology for controlling the penetration depth of conduction is being continuously studied. Summary of the invention

[0010] Accordingly, embodiments of the present disclosure are directed to a thin film transistor and a display device including the same that substantially obviate one or more of the problems due to limitations and disadvantages of the related art.

[0011] An embodiment of the present invention is directed to providing a thin film transistor including a protruding portion and an active hole which can prevent or suppress a threshold voltage Vth from shifting in a negative (-) direction even if a channel region has a short channel.

[0012] An embodiment of the present invention is directed to providing a thin film transistor in which the conduction penetration depth can be controlled by including a protruding portion and an active hole even if the thin film transistor has a short channel.

[0013] Embodiments of the present invention are directed to providing a thin film transistor including a protruding portion and an active hole having improved reliability.

[0014] Another configuration of the present invention is directed to providing a display device including such a thin film transistor.

[0015] Additional features and aspects will be set forth in the following description, and in part will become apparent from the description, or may be learned through practice of the inventive concepts provided herein. Other features and aspects of the inventive concepts may be realized and obtained through structures specifically pointed out in the written description, or structures that can be derived from the written description and its claims and drawings.

[0016] In addition to the objects of the present disclosure as mentioned above, those skilled in the art will clearly understand additional objects and features of the present disclosure from the following description of the present disclosure.

[0017] To achieve these and other aspects of the inventive concept, as embodied and broadly described herein, a thin film transistor includes: an active layer; and a gate electrode, which is spaced apart from and partially overlaps with the active layer, wherein the active layer includes: a channel region, which partially overlaps with the gate electrode in a plan view; a source region, which is connected to one side of the channel region in a plan view; and a drain region, which is connected to the other side of the channel region in a plan view, wherein the active layer defines an active hole in which no active layer is present, at least a portion of the active hole overlaps with the gate electrode in a plan view, and at least another portion of the active hole extends beyond an edge of the gate electrode in a plan view, and wherein the gate electrode includes a body portion and a protruding portion protruding in a first direction, the first direction being a direction parallel to the shortest line connecting the source region and the drain region.

[0018] A straight line passing through at least a portion of the active hole among the straight lines parallel to the first direction may pass through the protruding portion.

[0019] The protruding portion may not overlap the active hole.

[0020] The protruding portion may overlap at least a portion of the active hole.

[0021] The protrusion portion may include a first protrusion portion and a second protrusion portion spaced apart from each other, and the active hole may include a first active hole and a second active hole spaced apart from each other.

[0022] The first active hole and the second active hole may not overlap with the protrusion portion.

[0023] The first protrusion and the second protrusion may be arranged in a plane toward the source region, the first active hole and the second active hole may be arranged in a plane in a first direction from the gate electrode toward the drain region, and a straight line parallel to the first direction passing through at least a portion of the active hole may pass through the protrusion.

[0024] The first protrusion and the second protrusion may be arranged in a plane toward the drain region, the first active hole and the second active hole may be arranged in a plane in a first direction from the gate electrode toward the source region, and a straight line parallel to the first direction passing through at least a portion of the active hole may pass through the protrusion.

[0025] Any one of the first protrusion and the second protrusion may be disposed in a plane toward the source region, and the other may be disposed toward the drain region, any one of the first active hole and the second active hole may be disposed in a plane in a first direction from the gate electrode toward the source region, and the other may be disposed toward the drain region, and a straight line among straight lines parallel to the first direction that passes through at least a portion of the active hole may pass through the protrusion.

[0026] A straight line passing through at least a portion of the first protruding portion among straight lines parallel to the first direction may not pass through the second protruding portion.

[0027] The protrusion portion may include a first protrusion portion and a second protrusion portion spaced apart from each other, the active hole may include a third active hole and a fourth active hole spaced apart from each other, the third active hole may overlap the first protrusion portion, and the fourth active hole may overlap the second protrusion portion.

[0028] The active hole may include a first active hole and a second active hole spaced apart from each other, and the first active hole and the second active hole do not overlap with the protrusion portion, and at least a portion of the first protrusion portion, at least a portion of the first active hole, and at least a portion of the third active hole are arranged on a straight line extending in a plane along a first direction, and at least a portion of the second protrusion portion, at least a portion of the second active hole, and at least a portion of the fourth active hole may be arranged on a straight line extending in a plane along the first direction.

[0029] The first protrusion portion and the second protrusion portion may be disposed toward the source region, and the first active hole and the second active hole may be disposed in a first direction from the gate electrode toward the drain region when viewed in a plan view.

[0030] The first protrusion portion and the second protrusion portion may be disposed toward the drain region, and the first active hole and the second active hole may be disposed in a plane along a first direction from the gate electrode toward the source region.

[0031] Any one of the first protrusion and the second protrusion may be disposed toward the source region in a plane, the other may be disposed toward the drain region, and a straight line parallel to the first direction passing through at least a portion of the first protrusion does not pass through the second protrusion.

[0032] Any one of the first and second protrusions may be disposed toward the source region in a plane, the other may be disposed toward the drain region, and a straight line parallel to the first direction passing through at least a portion of the first protrusion may pass through the second protrusion.

[0033] When the length of a region where an arbitrary straight line parallel to the second direction overlaps the protrusion portion is referred to as L1, and the length of a region where an arbitrary straight line parallel to the second direction overlaps the active hole is referred to as L2, L1 may be greater than or equal to L2.

[0034] When the length of an area where any straight line parallel to the first direction that passes through the protruding portion and overlaps with the gate electrode is L3, and the length of an area where any straight line parallel to the first direction that does not pass through the protruding portion and overlaps with the gate electrode is L4, L3 may be greater than L4.

[0035] A length of an area where a straight line passing through the protruding portion among any straight lines parallel to the first direction in a plan view overlaps with the source region and the drain region may be shorter than a length of an area where a straight line not passing through the protruding portion among any straight lines parallel to the first direction in a plan view overlaps with the source region and the drain region.

[0036] Among the straight lines parallel to the first direction, a portion of the straight lines passing through at least a portion of the active hole may pass through the protruding portion, and another portion may not pass through the protruding portion.

[0037] In a plan view, an area of ​​a region occupied by the protrusion may be larger than an area of ​​a region occupied by the active hole.

[0038] Another configuration of the present invention provides a display device including a thin film transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] The above and other objects, features and other advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0040] Figure 1 is a plan view of a thin film transistor according to an embodiment of the present invention.

[0041] Figure 2 is along Figure 1 A cross-sectional view taken along line II'.

[0042] Figure 3 is along Figure 1 A cross-sectional view taken along line II-II'.

[0043] Figure 4 is a plan view of a thin film transistor according to another embodiment of the present invention.

[0044] Figure 5 is a plan view of a thin film transistor according to another embodiment of the present invention.

[0045] Figure 6 is a plan view of a thin film transistor according to another embodiment of the present invention.

[0046] Figure 7 is a plan view of a thin film transistor according to another embodiment of the present invention.

[0047] Figure 8 is a plan view of a thin film transistor according to another embodiment of the present invention.

[0048] Fig. 9 is a plan view of a thin film transistor according to another embodiment of the present invention.

[0049] Fig.10is a plan view of a thin film transistor according to another embodiment of the present invention.

[0050] Fig.11 is a plan view of a thin film transistor according to another embodiment of the present invention.

[0051] Fig.12 is a plan view of a thin film transistor according to another embodiment of the present invention.

[0052] Fig.13A is a plan view of a thin film transistor according to another embodiment of the present invention.

[0053] Fig. 13B is a plan view of a thin film transistor according to another embodiment of the present invention.

[0054] Fig.14A is a plan view of a thin film transistor according to a comparative example.

[0055] Fig. 14B is a plan view of a thin film transistor according to another embodiment of the present invention.

[0056] Fig.15 is a graph showing measurement of threshold voltage Vth of thin film transistors according to the embodiment and the comparative example.

[0057] Fig.16 is a plan view of a thin film transistor according to another embodiment of the present invention.

[0058] Fig.17 is a schematic diagram of a display device according to an embodiment of the present invention.

[0059] Fig.18 is a schematic diagram of a shift register.

[0060] Fig.19 yes Fig.17 The circuit diagram of any pixel.

[0061] Fig. 20 yes Fig.19 A floor plan of pixels.

[0062] Fig.21 It is along Fig. 20 A cross-sectional view taken along line III-III'.

[0063] Fig. 22 is a circuit diagram of any one pixel of a display device according to another embodiment of the present invention.

[0064] Fig.23 is a circuit diagram of any one pixel of a display device according to another embodiment of the present invention.

[0065] Fig.24 is a circuit diagram of any one pixel of a display device according to another embodiment of the present invention. DETAILED DESCRIPTION

[0066] The advantages and features of the present disclosure and the implementation methods of the present disclosure will be explained by the following embodiments described with reference to the accompanying drawings. However, the present disclosure can be embodied in different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art. In addition, the present disclosure is limited only by the scope of the claims.

[0067] The shapes, sizes, ratios, angles, and numbers disclosed in the drawings used to describe the embodiments of the present disclosure are examples only, and therefore the present disclosure is not limited to the details shown. Throughout the specification, similar reference numerals refer to similar elements. In the following description, when it is determined that the detailed description of related known functions or configurations unnecessarily obscures the main points of the present disclosure, the detailed description will be omitted.

[0068] In the case where “including,” “having,” and “comprising” described in the present disclosure are used, another part may be added unless “only to” is used. Terms in the singular form may include plural forms unless noted otherwise.

[0069] When constituting an element, although there is no explicit description, the element is interpreted as including an error range.

[0070] When describing a positional relationship, for example, when the positional relationship is described as "on", "above", "below", and "adjacent to", one or more other parts may be set between the two parts, unless "immediately" or "directly" is used.

[0071] Spatially related terms such as "below," "beneath," "below," "above," and "above" may be used herein to easily describe the relationship of one element or elements to another element or elements as shown in the accompanying drawings. It will be understood that these terms are intended to cover different orientations of the device in addition to the orientation depicted in the accompanying drawings. For example, if the device shown in the figure is inverted, a device described as being arranged "below" or "below" another device may be arranged "above" the other device. Thus, the exemplary terms "below or below" may include a "below or below" orientation and an "above" orientation. Similarly, the exemplary terms "above" or "above" may include an "above" orientation and a "below or below" orientation.

[0072] When describing a time relationship, for example, when a time sequence is described as “after,” “subsequently,” “next,” and “before,” discontinuous cases may be included unless “immediately” or “directly” is used.

[0073] It will be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited to these terms. These terms are only used to distinguish one element from another element. For example, without departing from the scope of the present disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0074] It should be understood that the term "at least one" includes all combinations related to any one item. For example, "at least one of a first element, a second element, and a third element" may include all combinations of two or more elements selected from the first element, the second element, and the third element, and each element of the first element, the second element, and the third element.

[0075] The features of the various embodiments of the present disclosure may be coupled or combined with each other in part or in whole, and may interoperate and be technically driven with each other in various ways, as can be fully understood by those skilled in the art. The embodiments of the present disclosure may be implemented independently of each other, or may be implemented together in a mutually dependent relationship.

[0076] When adding reference numerals to components of each of the drawings describing embodiments of the present disclosure, the same components may have the same numerals as may be displayed on other drawings.

[0077] In the embodiments of the present disclosure, the source electrode and the drain electrode are distinguished for ease of description, and the source electrode and the drain electrode can be interchanged. The source electrode can be a drain electrode, and the drain electrode can be a source electrode. In addition, the source electrode of any embodiment can be a drain electrode in another embodiment, and the drain electrode of any embodiment can be a source electrode in another embodiment.

[0078] In some embodiments of the present disclosure, for ease of description, the source region is distinguished from the source electrode, and the drain region is distinguished from the drain electrode, but the embodiments of the present disclosure are not limited thereto. The source region may be the source electrode, and the drain region may be the drain electrode. In addition, the source region may be the drain electrode, and the drain region may be the source electrode.

[0079] Figure 1 is a plan view of a thin film transistor 100 according to an embodiment of the present invention. Figure 2 is along Figure 1 A cross-sectional view taken along line II′. Figure 3 is along Figure 1 A cross-sectional view taken along line II-II′.

[0080] Specifically, refer to Figure 1 , Figure 2 and Figure 3 , may include: an active layer 130 on a base substrate 110 ; and a gate electrode 150 spaced apart from the active layer 130 and partially overlapping the active layer 130 .

[0081] According to an embodiment of the present invention, the thin film transistor 100 may further include a base substrate 110. Figure 2 and Figure 3 , an active layer 130 is disposed on the base substrate 110 .

[0082] According to an embodiment of the present invention, the thin film transistor 100 may further include a buffer layer 120. Figure 2 and Figure 3 , the active layer 130 is disposed on the buffer layer 120. Specifically, the buffer layer 120 is disposed between the base substrate 110 and the active layer 130.

[0083] According to an embodiment of the present invention, the thin film transistor 100 may further include a gate insulating layer 140. Figure 2 and Figure 3 , the gate insulating layer 140 is disposed on the active layer 130 . Specifically, the gate insulating layer 140 is disposed between the active layer 130 and the gate electrode 150 .

[0084] According to an embodiment of the present invention, the thin film transistor 100 may further include another layer disposed on the gate electrode 150. In detail, the thin film transistor 100 may further include an interlayer insulating layer 180. Figure 3 , the interlayer insulating layer 180 is disposed on the gate electrode 150. In detail, the gate electrode 150 is disposed between the gate insulating layer 140 and the interlayer insulating layer 180.

[0085] According to an embodiment of the present invention, the thin film transistor 100 may further include a source electrode 160 and a drain electrode 170. Figure 1 , Figure 2 and Figure 3 , a source electrode 160 and a drain electrode 170 are disposed on the gate insulating layer 140 .

[0086] Hereinafter, components of the thin film transistor 100 according to an embodiment of the present invention will be described in more detail.

[0087] Glass or plastic may be used as the base substrate 110. As the plastic, transparent plastic having flexible properties such as polyimide may be used.

[0088] When polyimide is used as the base substrate 110, heat-resistant polyimide that can withstand high temperatures may be used in consideration of performing a high-temperature deposition process on the base substrate 110. In this case, in order to form a thin film transistor, processes such as deposition, etching, etc. may be performed in a state where a polyimide substrate is disposed on a carrier substrate made of a highly durable material such as glass.

[0089] Reference Figure 2 and Figure 3 , the buffer layer 120 may be disposed on the base substrate 110 .

[0090] The buffer layer 120 may be formed on the base substrate 110 and may be formed of an inorganic material or an organic material, and may include, for example, an insulating oxide such as silicon oxide (SiOx), aluminum oxide (Al2O3), or the like.

[0091] The buffer layer 120 blocks impurities such as moisture and oxygen from flowing out of the base substrate 110 to protect the active layer 130, and planarizes an upper portion of the base substrate 110. The buffer layer 120 may be formed as a single layer or a multi-layer.

[0092] Reference Figure 2 and Figure 3 , the active layer 130 may be disposed on the buffer layer 120 .

[0093] The active layer 130 may include a channel region 130 n , a source region 130 a , and a drain region 130 b .

[0094] The channel region 130n overlaps the gate electrode 150. The channel region 130n serves as a channel of the thin film transistor 100.

[0095] Specifically, the active layer 130 may include: a channel region 130n partially overlapping with the gate electrode 150 in a plane; a source region 130a connected to one side of the channel region 130n in a plane and not overlapping with the gate electrode 150; and a drain region 130b connected to the other side of the channel region 130n in a plane and not overlapping with the gate electrode 150.

[0096] According to an embodiment of the present invention, the source region 130 a and the drain region 130 b are spaced apart from each other, wherein the channel region 130 n is interposed between the source region 130 a and the drain region 130 b .

[0097] According to the configuration of the present invention, the active layer 130 may be formed of a semiconductor material. The active layer 130 may include an oxide semiconductor material.

[0098] The oxide semiconductor material may include at least one of an oxide semiconductor material based on IZO (InZnO), an oxide semiconductor material based on IGO (InGaO), an oxide semiconductor material based on ITO (InSnO), an oxide semiconductor material based on IGZO (InGaZnO), an oxide semiconductor material based on IGZTO (InGaZnSnO), an oxide semiconductor material based on GZTO (GaZnSnO), an oxide semiconductor material based on GZO (GaZnO), an oxide semiconductor material based on ITZO (InSnZnO), and an oxide semiconductor material based on FIZO (FeInZnO). However, the embodiments of the present invention are not limited thereto, and the active layer 130 may be made of another oxide semiconductor material known in the art.

[0099] The source region 130a and the drain region 130b may be formed by selectively conducting with respect to the active layer 130 made of a semiconductor material. According to an embodiment of the present invention, imparting conductivity to a specific portion of the active layer 130 so that it can be used as a conductor is called selective conduction. The portion imparted with conductivity by selective conduction is converted into a conductor, while the portion not imparted with conductivity is not converted into a conductor.

[0100] Figure 1 , Figure 2 and Figure 3 The source region 130 a and the drain region 130 b shown are portions rendered conductive by selective conductivity.

[0101] According to an embodiment of the present invention, selective conductivity may be formed by doping with a dopant. In addition, selective conductivity may be formed by plasma treatment.

[0102] The selective conduction of the active layer 130 may be performed by doping with a dopant using the gate electrode 150 or a photoresist as a mask. For example, the dopant may include at least one of boron (B), phosphorus (P), fluorine (F), and hydrogen (H).

[0103] When the active layer 130 is selectively conductive by doping the dopant, the region of the active layer 130 doped with the dopant is selectively conductive to become the source region 130a or the drain region 130b. The region of the active layer 130 not doped with the dopant may not be conductive and may become the channel region 130n.

[0104] Alternatively, the active layer 130 may be selectively conductive by a plasma treatment applied to the process of patterning the gate insulating layer 140. For example, plasma may be used in the process of patterning the gate insulating layer 140, and a portion of the active layer 130 in contact with the plasma may be selectively conductive to become a source region 130a or a drain region 130b of the active layer 130. A portion of the active layer 130 that is protected by the gate insulating layer 140 and not in contact with the plasma may be a channel region 130n that is not conductive.

[0105] exist Figure 1 , Figure 2 and Figure 3 , a configuration in which the active layer 130 is formed of one layer is disclosed, but the configuration of the present invention is not limited thereto. The active layer 130 may have a single layer structure or a multi-layer structure.

[0106] Reference Figure 1 , Figure 2 and Figure 3 , the active hole 135 where the active layer 130 is not provided is provided in a region whose edge is defined by the active layer 130. According to an embodiment of the present invention, the active hole 135 is provided in a region defined by the active layer 130 on a plane. Specifically, the active hole 135 may be a region formed by removing a portion of the active layer 130.

[0107] Reference Figure 1 and Figure 2 , the active hole 135 may be a region formed by removing a portion of the active layer 130. Since the active hole 135 may be referred to as a hole formed in the active layer 130 by removing a portion of the active layer 130, the hole is referred to as an "active hole" according to an embodiment of the present invention.

[0108] According to an embodiment of the present invention, at least a portion of the active hole 135 may overlap with the gate electrode 150 . Figure 1 , Figure 2 and Figure 3 A configuration is shown in which a portion of the active hole 135 overlaps the gate electrode 150 . However, embodiments of the present invention are not limited thereto, and the entire active hole 135 may overlap the gate electrode 150 .

[0109] The gate insulating layer 140 is disposed on the active layer 130. The gate insulating layer 140 protects the channel region 130n.

[0110] The gate insulating layer 140 has insulating properties. The gate insulating layer 140 may include, for example, at least one of silicon oxide, silicon nitride, and metal oxide. The gate insulating layer 140 may have a single-layer structure or a multi-layer structure.

[0111] Reference Figure 2 and Figure 3 , the gate insulating layer 140 is not patterned, and may be disposed on the entire surface of the base substrate 110. However, the embodiments of the present invention are not limited thereto, and the gate insulating layer 140 may have a patterned structure.

[0112] The gate electrode 150 is disposed on the gate insulating layer 140. The gate electrode 150 overlaps the channel region 130n of the active layer 130.

[0113] The gate electrode 150 may include at least one of the following: aluminum-based metals such as aluminum (Al) or aluminum alloys, silver-based metals such as silver (Ag) or silver alloys, copper-based metals such as copper (Cu) or copper alloys, molybdenum-based metals such as molybdenum (Mo) or molybdenum alloys, and chromium (Cr), tantalum (Ta), neodymium (Nd), and titanium (Ti). The gate electrode 150 may have a multilayer structure including at least two conductive layers, each conductive layer having different physical properties. For example, the gate electrode 150 may include at least one of molybdenum (Mo) and titanium (Ti).

[0114] According to an embodiment of the present invention, the gate insulating layer 140 may be patterned by etching using the gate electrode 150 as a mask, and in this process, the active layer 130 may be selectively conductive to form the source region 130a and the drain region 130b. Specifically, according to an embodiment of the present invention, the region of the active layer 130 overlapping with the gate electrode 150 is not conductive to form the channel region 130n having semiconductor characteristics, while the region not overlapping with the gate electrode 150 may be conductive to form the source region 130a and the drain region 130b.

[0115] Reference Figure 1 , when a direction parallel to the shortest line connecting the source region 130a and the drain region 130b is referred to as a first direction X and a direction perpendicular to the first direction X is referred to as a second direction Y, the gate electrode 150 may include a body portion 150a and a protrusion portion 150b protruding in the first direction X. Specifically, the protrusion portion 150b protrudes from the body portion 150a in the first direction X. More specifically, the protrusion portion 150b protrudes from the body portion 150a and overlaps the active layer 130.

[0116] Reference Figure 1 , wherein the length of an area where a straight line passing through the protruding portion 150b among any straight lines parallel to the first direction X in a plan view overlaps with the source region 130a and the drain region 130b may be shorter than the length of an area where a straight line not passing through the protruding portion 150b among any straight lines parallel to the first direction in a plan view overlaps with the source region 130a and the drain region 130b.

[0117] Specifically, refer to Figure 1 When the lengths of the source region 130a and the drain region 130b based on the first direction X are respectively the “width of the source region” and the “width of the drain region”, the width of the source region 130a based on the first direction X that is arranged on the same line as the protruding portion 150b may be smaller than the width of the source region 130a that is not arranged on the same line as the protruding portion 150b.

[0118] exist Figure 1 , a configuration is shown in which the protruding portion 150b is disposed toward the source region 130a in the first direction X. However, the embodiments of the present invention are not limited thereto, and the protruding portion 150b may be disposed toward the drain region 130b in the first direction X (see Figure 6 ).

[0119] Reference Figure 2 and Figure 3 , an interlayer insulating layer 180 may be disposed on the gate electrode 150. The interlayer insulating layer 180 may be formed of an organic insulating material or an inorganic insulating material. The interlayer insulating layer 180 may be formed of a composite layer of an organic layer and an inorganic layer.

[0120] According to an embodiment of the present invention, the thin film transistor 100 may include a source electrode 160 and a drain electrode 170 disposed on the interlayer insulating layer 180. The position of the source electrode 160 and the position of the drain electrode 170 may be inverted. However, the embodiment of the present invention is not limited thereto, and the source region 130a and the drain region 130b may be used as the source electrode and the drain electrode, respectively.

[0121] Reference Figure 1 , Figure 2 and Figure 3 , the source electrode 160 and the drain electrode 170 may be connected to the active layer 130 through the contact holes CH2 and CH3, respectively. Specifically, the source electrode 160 may contact the source region 130a through the contact hole. The drain electrode 170 may be spaced apart from the source electrode 160 and may contact the drain region 130b through the contact hole.

[0122] Reference Figure 1 , Figure 2 and Figure 3 , a light blocking layer 111 may be disposed on the base substrate 110. Specifically, the light blocking layer 111 may be disposed between the base substrate 110 and the active layer 130. The light blocking layer 111 overlaps the channel region 130n. The light blocking layer 111 blocks light incident from the outside, thereby protecting the channel region 130n.

[0123] The light blocking layer 111 may be formed of a material having a light blocking property. The light blocking layer 111 may include at least one of an aluminum-based metal such as aluminum (Al) or an aluminum alloy, a molybdenum-based metal such as molybdenum (Mo) or a molybdenum alloy, chromium (Cr), tantalum (Ta), neodymium (Nd), titanium (Ti), and iron (Fe). According to an embodiment of the present invention, the light blocking layer 111 may have electrical conductivity.

[0124] The light blocking layer 111 may be omitted. Figure 1 , Figure 2 and Figure 3 Although not shown in the drawings, a buffer layer may be additionally disposed between the base substrate 110 and the light blocking layer 111. The light blocking layer 111 may be electrically connected to one of the source electrode 160 and the drain electrode 170. Figure 2 A configuration is shown in which the light blocking layer 111 is electrically connected to the source electrode 160 through the contact hole CH1 .

[0125] According to an embodiment of the present invention, a portion of the active hole 135 may not overlap with the gate electrode 150 . Figure 1 A configuration is shown in which a portion of the active hole 135 overlaps a portion of the gate electrode 150 , and another portion of the active hole 135 is disposed from the gate electrode 150 toward the drain region 130 b in a first direction X in a plan view.

[0126] According to an embodiment of the present invention, if a direction parallel to the shortest line connecting the source region 130a and the drain region 130b is defined as a first direction X, the length of the channel region 130n in the first direction X can be defined as the length of the channel region, and if a direction perpendicular to the first direction X is defined as a second direction Y, the width of the channel region 130n in the second direction Y can be defined as the width of the channel region.

[0127] In the case where the channel region 130n has a large width, when the conduction is performed with respect to the source region 130a and the drain region 130b, the interface between the channel region 130n and the conduction portion increases, and thus the conduction diffusion toward the channel region 130n may be greatly performed. When the conduction diffusion toward the channel region 130n is greatly performed, the threshold voltage Vth of the thin film transistor 100 may move in the negative (-) direction, and the driving stability of the thin film transistor 100 may be deteriorated.

[0128] On the other hand, in the case where the channel region 130n has a small width, when conducting with respect to the source region 130a and the drain region 130b is performed, the interface between the channel region 130n and the conducting portion can be reduced, and thus conducting diffusion toward the channel region 130n can be suppressed.

[0129] According to an embodiment of the present invention, Figure 1 As shown, an active hole 135 is formed in a boundary region between the channel region 130n and the drain region 130b. Therefore, a boundary surface between the channel region 130n and the drain region 130b is reduced, and thus conductive diffusion toward the channel region 130n can be suppressed.

[0130] Therefore, it is possible to prevent or suppress the threshold voltage Vth of the thin film transistor 100 from shifting in the negative (−) direction.

[0131] Reference Figure 1 , a straight line LN passing through at least a portion of the active hole 135 among straight lines parallel to the first direction X may pass through the protrusion 150b. Specifically, at least a portion of the protrusion 150b and at least a portion of the active hole 135 may be disposed on any straight line extending along the first direction in a plane.

[0132] The active hole 135 is a region where the active layer 130 is not disposed in a region whose edge is defined by the active layer 130. Therefore, in the channel region 130n, compared with a region where the active hole 135 is not disposed based on the first direction X, the length of the channel region 130n may be narrowed.

[0133] On the other hand, when a straight line LN passing through at least a portion of the active hole 135 among the straight lines parallel to the first direction X passes through the protrusion 150b, that is, when the active hole 135 and the protrusion 150b are arranged on a straight line based on the first direction X, the length of the channel region 130n can be ensured by the protrusion 150b, and the conductive penetration can be very small.

[0134] Therefore, the thin film transistor can be driven even by a short channel having the length of the short channel region 130n, the short channel can be realized, the design accuracy of the channel region 130n can be improved, and the design of the channel region 130n can be facilitated.

[0135] In addition, when a straight line (LN) passing through at least a portion of the active hole (135) among the straight lines parallel to the first direction (X) passes through the protrusion (150b), that is, when the active hole (135) and the protrusion (150b) are arranged on a straight line based on the first direction (X), the threshold voltage (Vth) can be prevented from shifting in the negative (-) direction even through a short channel having the length of the short channel region (130n).

[0136] According to an embodiment of the present invention, the area of ​​region A1 occupied by protruding portion 150b on a plane may be larger than the area of ​​region A2 occupied by active hole 135. Therefore, the length of channel region 130n may be ensured, and conductive penetration may hardly occur or may be very small. Therefore, a thin film transistor may be driven even by a short channel having the length of short channel region 130n, and a short channel may be realized.

[0137] Figure 4 is a plan view of a thin film transistor 200 according to another embodiment of the present invention.

[0138] According to an embodiment of the present invention, the protrusion portion 150b may overlap at least a portion of the active hole 135. However, the embodiment of the present invention is not limited thereto, and the protrusion portion 150b may not overlap the active hole 135 (see Figure 1 ). Figure 4 A configuration is shown in which the protruding portion 150 b overlaps a portion of the active hole 135 .

[0139] Reference Figure 4 , even when the protrusion 150b overlaps at least a portion of the active hole 135, the length of the channel region 130n can be ensured by the protrusion 150b, and the conductive penetration may hardly occur or may be very small. Therefore, the thin film transistor can be driven even by a short channel having the length of the short channel region 130n, and a short channel can be realized.

[0140] Figure 5 is a plan view of a thin film transistor 300 according to another embodiment of the present invention.

[0141] Reference Figure 5 , the protruding portion 150b may include a first protruding portion 151b and a second protruding portion 152b spaced apart from each other, and the active hole 135 may include a first active hole 135a and a second active hole 135b spaced apart from each other. In this case, each of the first protruding portion 151b and the second protruding portion 152b may be disposed toward the source region 130a in a plane, or may be disposed toward the drain region 130b.

[0142] Although Figure 5 The configuration in which the protruding portion 150b includes the first protruding portion 151b and the second protruding portion 152b spaced apart from each other is shown, but the embodiments of the present invention are not limited thereto and may also include the third protruding portion and the fourth protruding portion or five or more protruding portions. In this case, the respective protruding portions 150b are spaced apart from each other.

[0143] In addition, although Figure 5A configuration is shown in which the active holes 135 include the first active holes 135a and the second active holes 135b spaced apart from each other, but the embodiments of the present invention are not limited thereto and may also include or may be five or more third active holes 135c and fourth active holes 135d. In this case, the respective active holes 135 are spaced apart from each other.

[0144] exist Figure 5 In the embodiment, the first protrusion 151b and the second protrusion 152b are arranged in a plane toward the source region 130a, the first active hole 135a and the second active hole 135b are arranged in a plane in a first direction X from the gate electrode 150 toward the drain region 130b, the first active hole 135a and the second active hole 135b do not overlap with the protrusion 150b, and a straight line passing through at least a portion of the active hole 135 in a straight line parallel to the first direction X passes through the protrusion 150b.

[0145] Specifically, a straight line passing through at least a portion of the first active hole 135a among the straight lines parallel to the first direction X may pass through the first protrusion 151b, and a straight line passing through at least a portion of the second active hole 135b among the straight lines parallel to the first direction X may pass through the second protrusion 152b.

[0146] In accordance with Figure 5 In the case of the thin film transistor 300, the length of the channel region 130n can be ensured by the protruding portion 150b and the active hole 135, and the conductive penetration may hardly occur or may be very small. Therefore, the thin film transistor 300 can be driven even by a short channel having the length of the short channel region 130n, and a short channel can be realized.

[0147] Figure 6 is a plan view of a thin film transistor 400 according to another embodiment of the present invention.

[0148] exist Figure 6 In the embodiment, the first protrusion 151b and the second protrusion 152b are arranged in a plane toward the drain region 130b, the first active hole 135a and the second active hole 135b are arranged in a plane from the gate electrode 150 toward the source region 130a in the first direction X, the first active hole 135a and the second active hole 135b do not overlap with the protrusion 150b, and a straight line passing through at least a portion of the active hole 135 in a straight line parallel to the first direction X passes through the protrusion 150b.

[0149] Specifically, a straight line passing through at least a portion of the first active hole 135a among the straight lines parallel to the first direction X may pass through the first protrusion 151b, and a straight line passing through at least a portion of the second active hole 135b among the straight lines parallel to the first direction X may pass through the second protrusion 152b.

[0150] In accordance with Figure 6 In the case of the thin film transistor 400, the length of the channel region 130n can be ensured by the protruding portion 150b and the active hole 135, and the conductive penetration may hardly occur or may be very small. Therefore, the thin film transistor 400 can be driven even by a short channel having the length of the short channel region 130n, and a short channel can be realized.

[0151] Figure 7 is a plan view of a thin film transistor 500 according to another embodiment of the present invention.

[0152] exist Figure 7 In the embodiment, any one of the first protrusion 151b and the second protrusion 152b is arranged toward the source region 130a in the plane, and the other is arranged toward the drain region 130b, any one of the first active hole 135a and the second active hole 135b is arranged from the gate electrode 150 toward the source region 130a in the plane along the first direction X, and the other is arranged toward the drain region 130b, the first active hole 135a and the second active hole 135b do not overlap with the protrusion 150b, and a straight line passing through at least a portion of the active hole 135 among the straight lines parallel to the first direction X passes through the protrusion 150b.

[0153] More specifically, in Figure 7 In the embodiment, a straight line parallel to the first direction X that passes through at least a portion of the first protruding portion 151b does not pass through the second protruding portion 152b. Figure 7 In the embodiment, a straight line parallel to the first direction X that passes through at least a portion of the first active hole 135 a does not pass through the second active hole 135 b.

[0154] In accordance with Figure 7 In the case of the thin film transistor 500, the length of the channel region 130n can be ensured by the protruding portion 150b and the active hole 135, and the conductive penetration may hardly occur or may be very small. Therefore, the thin film transistor 500 can be driven even by a short channel having the length of the short channel region 130n, and a short channel can be realized.

[0155] Figure 8 is a plan view of a thin film transistor 600 according to another embodiment of the present invention.

[0156] According to an embodiment of the present invention, the active hole 135 may include a third active hole 135c and a fourth active hole 135d spaced apart from each other. Each of the third active hole 135c and the fourth active hole 135d may overlap the protrusion portion 150b.

[0157] exist Figure 8 , the first protrusion 151b and the second protrusion 152b are disposed to be spaced apart from each other, the third active hole 135c and the fourth active hole 135d are disposed to be spaced apart from each other, the third active hole 135c overlaps the first protrusion 151b, and the fourth active hole 135d overlaps the second protrusion 152b. However, the embodiments of the present invention are not limited thereto, and the third active hole 135c may overlap the second protrusion 152b, and the fourth active hole 135d may overlap the first protrusion 151b.

[0158] In accordance with Figure 8 In the case of the thin film transistor 600, the length of the channel region 130n can be ensured by the protruding portion 150b and the active hole 135, and the conductive penetration may hardly occur or may be very small. Therefore, the thin film transistor 600 can be driven even by a short channel having the length of the short channel region 130n, and a short channel can be realized.

[0159] Fig. 9 is a plan view of a thin film transistor 700 according to another embodiment of the present invention.

[0160] and Figure 8 compared to, Fig. 9 A first active hole 135 a and a second active hole 135 b spaced apart from each other may further be included.

[0161] Specifically, in Fig. 9 , the first protrusion 151b and the second protrusion 152b are disposed to be spaced apart from each other, the third active hole 135c and the fourth active hole 135d are disposed to be spaced apart from each other, the third active hole 135c overlaps with the first protrusion 151b, the fourth active hole 135d overlaps with the second protrusion 152b, the first active hole 135a and the second active hole 135b do not overlap with the protrusion 150b, at least a portion of the first protrusion 151b, at least a portion of the first active hole 135a, and at least a portion of the third active hole 135c are disposed on a straight line extending in the first direction X in a plane, and at least a portion of the second protrusion 152b, at least a portion of the second active hole 135b, and at least a portion of the fourth active hole 135d are disposed on a straight line extending in the first direction X in a plane.

[0162] More specifically, Fig. 9A configuration is shown in which the first and second protruding portions 151 b and 152 b are disposed toward the source region 130 a , and the first and second active holes 135 a and 135 b are disposed from the gate electrode 150 toward the drain region 130 b in a plan view along the first direction X.

[0163] However, the embodiments of the present invention are not limited thereto, and the position of the first protrusion 151b and the second protrusion 152b may be changed, the position of the first active hole 135a and the second active hole 135b may be changed, and the position of the third active hole 135c and the fourth active hole 135d may be changed.

[0164] In accordance with Fig. 9 In the case of the thin film transistor 700, the length of the channel region 130n can be ensured by the protruding portion 150b and the active hole 135, and the conductive penetration may hardly occur or may be very small. Therefore, the thin film transistor 700 can be driven even by a short channel having the length of the short channel region 130n, and a short channel can be realized.

[0165] Fig.10 is a plan view of a thin film transistor 800 according to another embodiment of the present invention.

[0166] and Fig. 9 compared to, Fig.10 A configuration is shown in which the first and second protruding portions 151b and 152b are disposed toward the drain region 130b, and the first and second active holes 135a and 135b are disposed from the gate electrode 150 toward the source region 130a in a plan view along the first direction X.

[0167] In accordance with Fig.10 In the case of the thin film transistor 800, the length of the channel region 130n can be ensured by the protruding portion 150b and the active hole 135, and the conductive penetration can hardly occur or can be very small. Therefore, the thin film transistor 800 can be driven even by a short channel having the length of the short channel region 130n, and a short channel can be realized.

[0168] Fig.11 is a plan view of a thin film transistor 900 according to another embodiment of the present invention.

[0169] and Fig.10 In comparison, Fig.11In the embodiment, one of the first protrusion 151b and the second protrusion 152b is arranged toward the source region 130a in the plane, and the other is arranged toward the drain region 130b, and a straight line parallel to the first direction X that passes through at least a portion of the first protrusion 151b may not pass through the second protrusion 152b.

[0170] Specifically, Fig.11 A configuration is shown in which the first protrusion 151b is disposed toward the source region 130a and the second protrusion 152b is disposed toward the drain region 130b. However, embodiments of the present invention are not limited thereto, and the first protrusion 151b may be disposed toward the drain region 130b, while the second protrusion 152b may be disposed toward the source region 130a.

[0171] In accordance with Fig.11 In the case of the thin film transistor 900, the length of the channel region 130n can be ensured by the protruding portion 150b and the active hole 135, and the conductive penetration can hardly occur or can be very small. Therefore, the thin film transistor 900 can be driven even by a short channel having the length of the short channel region 130n, and a short channel can be realized.

[0172] Fig.12 is a plan view of a thin film transistor 1000 according to another embodiment of the present invention.

[0173] and Figure 8 In comparison, Fig.12 In the embodiment, one of the first protrusion 151b and the second protrusion 152b is arranged toward the source region 130a in the plane, and the other is arranged toward the drain region 130b, and a straight line parallel to the first direction X that passes through at least a portion of the first protrusion 151b can pass through the second protrusion 152b.

[0174] Specifically, Fig.12 A configuration is shown in which the first protrusion 151b is disposed toward the source region 130a and the second protrusion 152b is disposed toward the drain region 130b. However, embodiments of the present invention are not limited thereto, and the first protrusion 151b may be disposed toward the drain region 130b, while the second protrusion 152b may be disposed toward the source region 130a.

[0175] In accordance with Fig.12 In the case of the thin film transistor 1000, the length of the channel region 130n can be ensured by the protruding portion 150b and the active hole 135, and the conductive penetration can hardly occur or can be very small. Therefore, the thin film transistor 1000 can be driven even by a short channel having the length of the short channel region 130n, and a short channel can be realized.

[0176] Fig.13A is a plan view of a thin film transistor 1000 according to another embodiment of the present invention. Fig. 13B is a plan view of a thin film transistor 1000 according to another embodiment of the present invention.

[0177] According to an embodiment of the present invention, when the length of an area or line where an arbitrary straight line parallel to the second direction Y overlaps with the protrusion 150b is referred to as L1, and the length of an area or line where an arbitrary straight line parallel to the second direction Y overlaps with the active hole 135 is referred to as L2, L1 may be greater than or equal to L2.

[0178] Reference Fig.13A , when the length of the protrusion 150b and the length of the active hole 135 are regarded as thickness based on the second direction Y, the thickness of the protrusion 150b may be greater than or equal to the thickness of the active hole 135. Therefore, the driving stability of the thin film transistor can be ensured even by a short channel having the length of the short channel region 130n.

[0179] On the other hand, when the thickness of the protrusion 150 b is smaller than the thickness of the active hole 135 , even if a short channel having the length of the short channel region 130 n is ensured by the protrusion 150 b and the active hole 135 , it may be difficult to ensure driving stability of the thin film transistor.

[0180] According to an embodiment of the present invention, when the length of an area or line in which a straight line passing through the protruding portion 150b among any straight lines parallel to the first direction X overlaps with the gate electrode 150 is L3, and the length of an area or line in which a straight line not passing through the protruding portion 150b among any straight lines parallel to the first direction X overlaps with the gate electrode 150 is L4, L3 may be greater than L4.

[0181] Reference Fig. 13B , when the length of the gate electrode 150 is defined as the width based on the first direction X, the width of the gate electrode 150 passing through the protruding portion 150b based on the first direction X may be greater than the width of the gate electrode 150 not passing through the protruding portion 150b based on the first direction X. Therefore, the length of the channel region 130n may be ensured, and the conductive penetration may hardly occur or may be very small. Therefore, the thin film transistor may be driven even by a short channel having the length of the short channel region 130n, and the short channel may be realized.

[0182] Fig.14A is a plan view of a thin film transistor according to a comparative example. Fig. 14B is a plan view of a thin film transistor according to another embodiment of the present invention. Fig.15: is a graph showing measurement of threshold voltage Vth of thin film transistors according to the embodiment and the comparative example.

[0183] Reference Fig.15 , graph A represents a threshold voltage Vth measurement result of the thin film transistor according to the embodiment, and graph B represents a threshold voltage Vth measurement result of the thin film transistor according to the comparative example.

[0184] exist Fig.15 , the horizontal axis represents the length of the channel region 130n, and the vertical axis represents the threshold voltage (Vth) of the thin film transistor.

[0185] Reference Fig.14A , the thin film transistor according to the comparative example does not include the active hole 135 and the protruding portion 150b. Fig. 14B , the thin film transistor according to the embodiment includes the active hole 135 and the protrusion 150b. The thin film transistor according to the embodiment may be Figure 1 and Figures 4 to 12 Any one of the thin film transistors 100, 200, 300, 400, 500, 600, 700, 800, 900 and 1000.

[0186] Reference Fig.15 In the case of the embodiment A including the active hole 135 and the protruding portion 150b, the length of the channel region 130n can be ensured, and the conductive penetration can hardly occur or can be very small. Therefore, it can be confirmed that the threshold voltage (Vth) of the thin film transistor is suppressed from moving in the negative (-) direction even by a short channel having the length of the short channel region 130n.

[0187] On the other hand, in the case of Comparative Example B which does not include the active hole 135 and the protruding portion 150b, the source region 130a and the drain region 130b can be made conductive, and thus the conductive diffusion toward the channel region 130n can be significantly performed. Therefore, it can be confirmed that the threshold voltage Vth of the thin film transistor moves in the negative (-) direction.

[0188] Fig.16 is a plan view of a thin film transistor 1100 according to another embodiment of the present invention.

[0189] Reference Fig.16 , a portion of the straight line passing through at least a portion of the active hole 135 among the straight lines parallel to the first direction X may pass through the protrusion 150 b , and another portion may not pass through the protrusion 150 b .

[0190] More specifically, a portion of the active hole 135 may overlap the protrusion 150b with respect to the first direction, and another portion of the active hole 135 may not overlap the protrusion 150b. More specifically, the active hole 135 may be disposed to be spaced apart from the protrusion 150b in a plane with respect to the first direction X. Even when there are a plurality of protrusions 150b and active holes 135, a portion of the active hole 135 may be disposed to be spaced apart from the protrusion 150b with respect to the first direction X.

[0191] Fig.17 is a schematic diagram illustrating a display device 2000 according to still another embodiment of the present disclosure.

[0192] like Fig.17 As shown, a display device 2000 according to still another embodiment of the present disclosure may include a display panel 310 , a gate driver 320 , a data driver 330 , and a controller 340 .

[0193] The display panel 310 includes gate lines GL and data lines DL, and pixels P are disposed in intersection regions of the gate lines GL and the data lines DL. An image is displayed by driving the pixels P. The gate lines GL, the data lines DL, and the pixels P may be disposed on a base substrate 110 .

[0194] The controller 340 controls the gate driver 320 and the data driver 330 .

[0195] The controller 340 outputs a gate control signal GCS for controlling the gate driver 320 and a data control signal DCS for controlling the data driver 330 by using a signal supplied from an external system (not shown). In addition, the controller 340 samples input image data input from the external system, realigns the sampled data, and supplies the realigned digital image data RGB to the data driver 330.

[0196] The gate control signal GCS includes a gate start pulse GSP, a gate shift clock GSC, a gate output enable signal GOE, a start signal Vst, and a gate clock GCLK. In addition, a control signal for controlling a shift register may be included in the gate control signal GCS.

[0197] The data control signal DCS includes a source start pulse SSP, a source shift clock signal SSC, a source output enable signal SOE, and a polarity control signal POL.

[0198] The data driver 330 supplies data voltages to the data lines DL of the display panel 310. In detail, the data driver 330 converts the image data RGB input from the controller 340 into analog data voltages and supplies the data voltages to the data lines DL.

[0199] According to one embodiment of the present disclosure, the gate driver 320 may be packaged on the display panel 310. In this manner, a structure in which the gate driver 320 is directly packaged on the display panel 310 will be referred to as a gate-in-panel (GIP) structure. In detail, in the gate-in-panel (GIP) structure, the gate driver 320 may be disposed on the base substrate 110.

[0200] The display device 2000 according to one embodiment of the present disclosure may include the above-mentioned thin film transistors 100, 200, 300, 400, 500, 600, 700, 800, 900, 1000 and 1100. According to one embodiment of the present disclosure, the gate driver 320 may include the above-mentioned thin film transistors 100, 200, 300, 400, 500, 600, 700, 800, 900, 1000 and 1100.

[0201] The gate driver 320 may include a shift register 350 .

[0202] The shift register 350 sequentially supplies gate pulses to the gate lines GL within one frame by using a start signal and a gate clock transmitted from the controller 340. In this case, one frame means a period of time during which one image is output through the display panel 310. The gate pulse has a turn-on voltage capable of turning on a switching device (thin film transistor) provided in the pixel P.

[0203] In addition, the shift register 350 supplies a gate-off signal capable of turning off the switching device to the gate line GL during another frame period during which no gate pulse is supplied. Hereinafter, the gate pulse and the gate-off signal will be collectively referred to as a scan signal SS or Scan.

[0204] The shift register 350 may include the thin film transistors 100 , 200 , 300 , 400 , 500 , 600 , 700 , 800 , 900 , 1000 , and 1100 described above.

[0205] Fig.18 is a schematic diagram showing the shift register 350 .

[0206] Reference Fig.18 , the shift register 350 may include g number of stages 351 (ST1 to STg).

[0207] The shift register 350 transmits one scan signal SS to the pixel P connected to one gate line GL through one gate line GL. Each of the stages 351 may be connected to one gate line GL. When g number of gate lines GL are formed in the display panel 110, the shift register 350 may include g number of stages 351 (ST1 to STg), and may generate g number of scan signals SS1 to SSg.

[0208] Generally, each stage 351 outputs the gate pulse GP once during one frame, and the gate pulse GP is sequentially output from each stage 351 .

[0209] Fig.19 It is shown Fig.17 A circuit diagram of any pixel P.

[0210] Fig.19 The circuit diagram of FIG. 7 is an equivalent circuit diagram of a pixel P of a display device 2000 including an organic light emitting diode (OLED) as a display element 710 .

[0211] Reference Fig.19 , the pixel P includes a display element 710 and a pixel driving circuit PDC for driving the display element 710. In detail, the display device 2000 according to one embodiment of the present disclosure may include a pixel driving circuit PDC on a base substrate 110.

[0212] Fig.19 The pixel driving circuit PDC includes a first thin film transistor TR1 as a switching transistor and a second thin film transistor TR2 as a driving transistor. A display device 2000 according to another embodiment of the present disclosure may include at least one of the above-mentioned thin film transistors 100, 200, 300, 400, 500, 600, 700, 800, 900, 1000 and 1100.

[0213] The first thin film transistor TR1 is connected to the gate line GL and the data line DL, and is turned on or off by a scan signal SS supplied through the gate line GL.

[0214] The data line DL supplies a data voltage Vdata to the pixel driving circuit PDC, and the first thin film transistor TR1 controls application of the data voltage Vdata.

[0215] The driving power line PL supplies a driving voltage Vdd to the display element 710 , and the first thin film transistor TR1 controls the driving voltage Vdd. The driving voltage Vdd is a pixel driving voltage for driving an organic light emitting diode (OLED) as the display element 710 .

[0216] When the first thin film transistor TR1 is turned on by the scan signal SS applied from the gate driver 320 through the gate line GL, the data voltage Vdata supplied through the data line DL is supplied to the gate electrode of the second thin film transistor TR2 connected to the display element 710. The data voltage Vdata is charged in the storage capacitor Cst formed between the gate electrode and the source electrode of the second thin film transistor TR2.

[0217] The amount of current supplied to the organic light emitting diode (OLED) as the display element 710 through the second thin film transistor TR2 is controlled according to the data voltage Vdata, whereby the gray scale of light output from the display element 710 may be controlled.

[0218] Fig. 20 yes Fig.19 The pixel plane diagram, and Fig.21 is along Fig. 20 A cross-sectional view taken along line III-III'.

[0219] Reference Fig. 20 and Fig.21 , a first thin film transistor TR1 and a second thin film transistor TR2 are disposed on a base substrate 110 .

[0220] The base substrate 110 may be made of glass or plastic. As the base substrate 110, plastic having flexible properties such as polyimide (PI) may be used.

[0221] The light blocking layer 111 is disposed on the base substrate 110. The light blocking layer 111 may have a light blocking property. The light blocking layer 111 may block light incident from the outside to protect the active layers A1 and A2.

[0222] The buffer layer 120 is disposed on the light blocking layer 111. The buffer layer 120 is made of an insulating material, and protects the active layers A1 and A2 from moisture or oxygen introduced from the outside.

[0223] A first active layer A1 of the first thin film transistor TR1 and a second active layer A2 of the second thin film transistor TR2 are disposed on the buffer layer 120 .

[0224] The first active layer A1 and the second active layer A2 may include, for example, an oxide semiconductor material. The first active layer A1 and the second active layer A2 may be formed of an oxide semiconductor layer made of an oxide semiconductor material.

[0225] In the first thin film transistor TR1, the first active layer A1 may include a channel region, a source region, and a drain region. The channel region of the first active layer A1 overlaps the gate electrode G1. According to another embodiment of the present invention, the source region may be referred to as a source electrode S1, and the drain region may be referred to as a drain electrode D1.

[0226] In the second thin film transistor TR2, the second active layer A2 may include a channel region, a source region and a drain region. The channel region of the second active layer A2 overlaps the gate electrode G2. According to another embodiment of the present invention, the source region may be referred to as a source electrode S2, and the drain region may be referred to as a drain electrode D2.

[0227] In the first thin film transistor TR1, an active hole 135 in which the first active layer A1 is not disposed is disposed in a region in which an edge thereof is defined by the first active layer A1. The active hole 135 may be a region formed by removing the active layers A1 and A2.

[0228] At least a portion of the active hole 135 may overlap the gate electrodes G1 and G2 .

[0229] A gate insulating layer 140 is disposed on the active layers A1 and A2. The gate insulating layer 140 covers upper surfaces of the active layers A1 and A2.

[0230] The gate electrode G1 of the first thin film transistor TR1 and the gate electrode G2 of the second thin film transistor TR2 are disposed on the gate insulating layer 140 .

[0231] Although not shown in the drawings, a gate line GL may be disposed on the gate insulating layer 140. The gate electrode G1 of the first thin film transistor TR1 may extend from the gate line GL or may be a part of the gate line GL.

[0232] Reference Fig. 20 and Fig.21 , a first capacitor electrode CE1 of the storage capacitor Cst is formed on the gate insulating layer 140. The first capacitor electrode CE1 may be formed of the same material as the gate electrodes G1 and G2 through the same process.

[0233] An interlayer insulating layer 180 is disposed on the gate electrodes G1 and G2 and the first capacitor electrode CE1 .

[0234] The data line DL and the driving power line PL are disposed on the interlayer insulating layer 180. In addition, the source electrode S1 and the drain electrode D1 of the first thin film transistor TR1 and the source electrode S2 and the drain electrode D2 of the second thin film transistor TR2 are disposed on the interlayer insulating layer 180.

[0235] The source electrode S1 of the first thin film transistor TR1 may be integrally formed with the data line DL, and may have a structure extending from the data line DL.

[0236] The source electrode S1 of the first thin film transistor TR1 may make contact with a side surface of the active layer A1 of the first thin film transistor TR1 through the first contact hole H1 .

[0237] The drain electrode D1 of the first thin film transistor TR1 contacts the other side surface of the active layer A1 of the first thin film transistor TR1 through the second contact hole H2. In addition, the drain electrode D1 of the first thin film transistor TR1 is connected to the first capacitor electrode CE1 through the third contact hole H3. Therefore, the first capacitor electrode CE1 can be connected to the first thin film transistor TR1.

[0238] The drain electrode D2 of the second thin film transistor TR2 may be integrally formed with the driving power line PL, and may have a structure extending from the driving power line PL.

[0239] The drain electrode D2 of the second thin film transistor TR2 may make contact with the side surface of the active layer A2 of the second thin film transistor TR2 through the sixth contact hole H6.

[0240] The source electrode S2 of the second thin film transistor TR2 contacts the other side surface of the active layer A2 of the second thin film transistor TR2 through the fifth contact hole H5. In addition, the source electrode S2 of the second thin film transistor TR2 is connected to the light blocking layer 111 through the fourth contact hole H4. The same voltage as the source electrode S2 of the second thin film transistor TR2 may be applied to the light blocking layer 111 overlapping the second thin film transistor TR2.

[0241] The source electrode S2 of the second thin film transistor TR2 may extend onto the interlayer insulating layer 180 to form a second capacitor electrode CE2 of the storage capacitor Cst.

[0242] According to an embodiment of the present invention, the first capacitor electrode CE1 and the second capacitor electrode CE2 may overlap to form a storage capacitor Cst.

[0243] Reference Fig. 20 and Fig.21 A planarization layer 190 is disposed on the data line DL, the driving power line PL, the source electrodes S1 and S2, the drain electrodes D1 and D2, and the second capacitor electrode CE2. The planarization layer 190 planarizes the upper portion of the first thin film transistor TR1 and the upper portion of the second thin film transistor TR2 and protects the first thin film transistor TR1 and the second thin film transistor TR2. The planarization layer 190 serves as a protective layer.

[0244] The first electrode 711 of the display element 710 is disposed on the planarization layer 190. The first electrode 711 of the display element 710 contacts the second capacitor electrode CE2 through the seventh contact hole H7 formed in the planarization layer 190. Therefore, the first electrode 711 of the display element 710 may be connected to the source electrode S2 of the second thin film transistor TR2.

[0245] A bank layer 750 is provided at an edge of the first electrode 711. The bank layer 750 defines a light emitting region of the display element 710.

[0246] An organic light emitting layer 712 is provided on the first electrode 711, and a second electrode 713 is provided on the organic light emitting layer 712. Thus, the display element 710 is completed. Fig.21 The display element 710 shown is an organic light emitting diode (OLED). Therefore, the display device 2000 according to the embodiment of the present invention is an organic light emitting display device.

[0247] Fig. 22 is a circuit diagram of any one pixel of a display device 2100 according to another embodiment of the present invention.

[0248] Fig. 22 is an equivalent circuit diagram of a pixel P of an organic light emitting display device.

[0249] Fig. 22 The pixel P of the illustrated display device 2100 includes an organic light emitting diode OLED as a display element 710, and a pixel driving circuit PDC for driving the display element 710. The display element 710 is connected to the pixel driving circuit PDC.

[0250] In the pixel P, signal lines DL, GL, PL, RL, and SCL for supplying signals to the pixel driving circuit PDC are arranged.

[0251] The data voltage Vdata is supplied to the data line DL, the scan signal SS is supplied to the gate line GL, the driving voltage Vdd for driving pixels is supplied to the driving power line PL, the reference voltage Vref is supplied to the reference line RL, and the sensing control signal SCS is supplied to the sensing control line SCL.

[0252] The pixel driving circuit PDC, for example, includes: a first thin film transistor TR1 (switching transistor), which is connected to the gate line GL and the data line DL; a second thin film transistor TR2 (driving transistor), which controls the magnitude of the current output to the display element 710 according to the data voltage Vdata transmitted through the first thin film transistor TR1; and a third thin film transistor TR3 (sensing transistor), which is used to sense the characteristics of the second thin film transistor TR2.

[0253] The first thin film transistor TR1 is turned on by the scan signal SS supplied to the gate line GL, and transmits the data voltage Vdata supplied to the data line DL to the gate electrode of the second thin film transistor TR2 .

[0254] The third thin film transistor TR3 is connected to the first node n1 and the reference line RL between the second thin film transistor TR2 and the display element 710, is turned on or off by the sensing control signal SCS, and detects characteristics of the second thin film transistor TR2 as a driving transistor during a sensing period.

[0255] The second node n2 connected to the gate electrode of the second thin film transistor TR2 is connected to the first thin film transistor TR1. The storage capacitor Cst is formed between the second node n2 and the first node n1.

[0256] When the first thin film transistor TR1 is turned on, the data voltage Vdata supplied through the data line DL is supplied to the gate electrode of the second thin film transistor TR2. The data voltage Vdata is charged in the storage capacitor Cst formed between the gate electrode and the source electrode of the second thin film transistor TR2.

[0257] When the second thin film transistor TR2 is turned on, current is supplied to the display element 710 through the second thin film transistor TR2 by the driving voltage Vdd that drives the pixel, and light is output from the display element 710 .

[0258] A display device 2100 according to another embodiment of the present invention may include at least one of the thin film transistors 100 , 200 , 300 , 400 , 500 , 600 , 700 , 800 , 900 , 1000 , and 1100 .

[0259] Fig.23 is a circuit diagram of any one pixel P of a display device 2200 according to another embodiment of the present invention.

[0260] Fig.23 The pixel P of the illustrated display device 2200 includes an organic light emitting diode OLED as a display element 710, and a pixel driving circuit PDC for driving the display element 710. The display element 710 is connected to the pixel driving circuit PDC.

[0261] The pixel driving circuit PDC includes thin film transistors TR1 , TR2 , TR3 , and TR4 .

[0262] In the pixel P, signal lines DL, EL, GL, PL, SCL, and RL that supply drive signals to the pixel drive circuit PDC are arranged.

[0263] and Fig. 22 Compared with the pixel P, Fig.23 The pixel P further includes an emission control line EL. An emission control signal EM is supplied to the emission control line EL. Fig. 22 Compared with the pixel driving circuit PDC, Fig.23The pixel driving circuit PDC further includes a fourth thin film transistor TR4, which is a light emission control transistor for controlling a light emission timing point of the second thin film transistor TR2.

[0264] The first thin film transistor TR1 is turned on by the scan signal SS supplied to the gate line GL, and transmits the data voltage Vdata supplied to the data line DL to the gate electrode of the second thin film transistor TR2 .

[0265] The storage capacitor Cst is located between the gate electrode of the second thin film transistor TR2 and the display element 710 .

[0266] The third thin film transistor TR3 is connected to the reference line RL, is turned on or off by the sensing control signal SCS, and detects characteristics of the second thin film transistor TR2 as a driving transistor during a sensing period.

[0267] The fourth thin film transistor TR4 transmits the driving voltage Vdd to the second thin film transistor TR2 or blocks the driving voltage Vdd according to the emission control signal EM. When the fourth thin film transistor TR4 is turned on, current is supplied to the second thin film transistor TR2 to output light from the display element 710 .

[0268] A pixel driving circuit PDC according to another exemplary configuration of the present invention may be formed in various structures other than the above-described structure. The pixel driving circuit PDC may include, for example, five or more thin film transistors.

[0269] Fig.24 is a circuit diagram of any one pixel of a display device 2300 according to another embodiment of the present invention.

[0270] Fig.24 The pixel P of the illustrated display device 2300 includes a pixel driving circuit PDC and a liquid crystal capacitor Clc connected to the pixel driving circuit PDC. The liquid crystal capacitor Clc corresponds to a display device. Fig.24 The display device 2300 is a liquid crystal display device.

[0271] The pixel driving circuit PDC includes: a thin film transistor TR connected to the gate line GL and the data line DL; a pixel electrode 371 connected to the thin film transistor TR; a common electrode 372 opposite to the pixel electrode 371; and a storage capacitor Cst connected between the thin film transistor TR and the common electrode 372. The liquid crystal capacitor Clc is connected in parallel with the storage capacitor Cst between the thin film transistor TR and the common electrode 372.

[0272] The liquid crystal capacitor Clc is charged with a difference voltage between a data signal supplied to the pixel electrode through the thin film transistor TR and a common voltage Vcom supplied to the common electrode 372, and drives the liquid crystal according to the charged voltage to control the amount of light transmission. The storage capacitor Cst stably maintains the voltage charged in the liquid crystal capacitor Clc.

[0273] A display device 2300 according to another embodiment of the present invention may include at least one of the above-described thin film transistors 100 , 200 , 300 , 400 , 500 , 600 , 700 , 800 , 900 , 1000 , and 1100 .

[0274] According to the present disclosure, the following advantageous effects can be obtained.

[0275] The thin film transistor including the protruding portion and the active hole according to the embodiment of the present invention can prevent or suppress the threshold voltage Vth from shifting in the negative (−) direction even in the case where the thin film transistor has a short channel.

[0276] The thin film transistor including the protruding portion and the active hole according to the embodiment of the present invention can control the conduction penetration depth even in the case where the thin film transistor has a short channel.

[0277] A thin film transistor including a protruding portion and an active hole according to a configuration of the present invention may have excellent reliability.

[0278] In addition to the above-mentioned effects, other features and advantages of the present invention will be described below or will be clearly understood by a person of ordinary skill in the art to which the present invention pertains based on such technology and description.

[0279] It will be apparent to those skilled in the art that the above disclosure is not limited to the above embodiments and drawings, and that various substitutions, modifications and variations may be made in the present disclosure without departing from the spirit or scope of the present disclosure. Therefore, the scope of the present disclosure is defined by the appended claims, and it is intended that all changes or modifications derived from the meaning, scope and equivalent concepts of the claims fall within the scope of the present disclosure.

Claims

1. A thin film transistor, comprising: Active layer; as well as a gate electrode spaced apart from the active layer and partially overlapping the active layer, Wherein, the active layer comprises: a channel region which partially overlaps with the gate electrode in a plan view; a source region connected to one side of the channel region in the plan view; and a drain region connected to the other side of the channel region in the plan view, wherein the active layer defines an active hole in which the active layer does not exist, at least a portion of the active hole in the plan view overlaps the gate electrode, and at least another portion of the active hole in the plan view extends beyond an edge of the gate electrode, and The gate electrode includes a main body portion and a protruding portion protruding in a first direction, and the first direction is a direction parallel to the shortest line connecting the source region and the drain region.

2. The thin film transistor according to claim 1, wherein: In the plan view, a straight line that passes through at least a portion of the active hole among straight lines parallel to the first direction passes through the protruding portion.

3. The thin film transistor according to claim 1, wherein: In the plan view, the protruding portion does not overlap the active hole.

4. The thin film transistor according to claim 1, wherein: The protruding portion overlaps at least a portion of the active hole in the plan view.

5. The thin film transistor according to claim 1, wherein: The protruding portion includes a first protruding portion and a second protruding portion that are spaced apart from each other, and The active holes include a first active hole and a second active hole which are spaced apart from each other.

6. The thin film transistor according to claim 5, wherein: In the plan view, the first active hole and the second active hole do not overlap with either the first protruding portion or the second protruding portion.

7. The thin film transistor according to claim 6, wherein: In the plan view, the first protruding portion and the second protruding portion protrude from a side of the body portion toward the source region in the first direction, Wherein, in the plan view, the first active hole and the second active hole are arranged on a side of the gate electrode facing the drain region in the first direction, and Wherein, in the plan view, a straight line passing through at least a portion of one of the first active hole and the second active hole in the first direction passes through one of the first protruding portion and the second protruding portion.

8. The thin film transistor according to claim 6, wherein: In the plan view, the first protruding portion and the second protruding portion protrude from a side of the body portion toward the drain region in the first direction, Wherein, in the plan view, the first active hole and the second active hole are arranged on a side of the gate electrode facing the source region in the first direction, and Wherein, in the plan view, a straight line passing through at least a portion of one of the first active hole and the second active hole in the first direction passes through one of the first protruding portion and the second protruding portion.

9. The thin film transistor according to claim 6, wherein: In the plan view, one of the first protruding portion and the second protruding portion protrudes from one side of the body portion toward the source region in the first direction, and the other of the first protruding portion and the second protruding portion protrudes from the other side of the body portion toward the drain region in the first direction. wherein, in the plan view, one of the first active hole and the second active hole is disposed on one side of the gate electrode facing the source region in the first direction, and the other of the first active hole and the second active hole is disposed on the other side of the gate electrode facing the drain region in the first direction, and Wherein, in the plan view, a straight line passing through at least a portion of one of the first active hole and the second active hole in the first direction passes through at least one of the first protruding portion and the second protruding portion.

10. The thin film transistor according to claim 9, wherein: In the plan view, a straight line passing through at least a portion of the first protruding portion in the first direction does not pass over the second protruding portion.

11. The thin film transistor according to claim 1, wherein: The protruding portion includes a first protruding portion and a second protruding portion that are spaced apart from each other, The active holes include a third active hole and a fourth active hole spaced apart from each other. wherein the third active hole overlaps with the first protruding portion, and Wherein, the fourth active hole overlaps with the second protrusion.

12. The thin film transistor according to claim 11, wherein: The active holes further include a first active hole and a second active hole spaced apart from each other, wherein the first active hole and the second active hole do not overlap with any one of the first protruding portion and the second protruding portion, wherein, in the plan view, at least a portion of the first protruding portion, at least a portion of the first active hole, and at least a portion of the third active hole are disposed on a first straight line extending along the first direction, and Wherein, in the plan view, at least a portion of the second protrusion portion, at least a portion of the second active hole, and at least a portion of the fourth active hole are disposed on a second straight line extending along the first direction.

13. The thin film transistor according to claim 12, wherein: In the plan view, the first protruding portion and the second protruding portion are arranged on a side of the body portion facing the source region in the first direction, and Wherein, in the plan view, the first active hole and the second active hole are arranged on the other side of the body portion facing the drain region in the first direction.

14. The thin film transistor according to claim 12, wherein: In the plan view, the first protruding portion and the second protruding portion are arranged on a side of the body portion facing the drain region in the first direction, and Wherein, in the plan view, the first active hole and the second active hole are arranged on the other side of the body portion facing the source region in the first direction.

15. The thin film transistor according to claim 12, wherein: In the plan view, one of the first protruding portion and the second protruding portion is disposed on one side of the body portion facing the source region, and the other of the first protruding portion and the second protruding portion is disposed on the other side of the body portion facing the drain region, and Wherein, a straight line passing through at least a portion of the first protruding portion in the first direction does not pass through the second protruding portion.

16. The thin film transistor according to claim 11, wherein: In the plan view, one of the first protruding portion and the second protruding portion is disposed on one side of the body portion facing the source region, and the other of the first protruding portion and the second protruding portion is disposed on the other side of the body portion facing the drain region, and Wherein, a straight line passing through at least a portion of the first protruding portion in the first direction passes through the second protruding portion.

17. The thin film transistor according to claim 1, wherein: The second direction is a direction perpendicular to the first direction, and Wherein, the width of the protruding portion in the second direction is greater than or equal to the width of the active hole in the second direction.

18. The thin film transistor according to claim 1, wherein: A length of the gate electrode in the first direction at a portion including the body portion and the protruding portion is greater than a length of the gate electrode in the first direction at a portion including the body portion where the protruding portion does not exist.

19. The thin film transistor according to claim 1, wherein: The protruding portion protrudes to overlap a portion of one of the source region and the drain region of the active layer.

20. The thin film transistor according to claim 1, wherein: In the plan view, a first straight line passing through at least a portion of the active hole in the first direction passes through the protruding portion, and a second straight line passing through at least a portion of the active hole in the first direction does not pass through the protruding portion.

21. The thin film transistor according to claim 1, wherein: The area of ​​a region occupied by the protruding portion in the plan view is larger than the area of ​​a region occupied by the active hole.

22. A display device comprising the thin film transistor according to any one of claims 1 to 21.

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