Array substrate and display panel

Abstract

The invention discloses an array substrate and a display panel, a first thin film transistor located in a pixel area in the array substrate comprises a first electrode, a first insulating layer, a second electrode, a first active part, a second insulating layer and a first grid electrode which are arranged on a substrate, one end of the first active part is connected with the second electrode, and the other end of the first active part is connected with the second insulating layer. The other end of the first active part extends along the side wall of a first via hole in the first insulating layer and is connected with a first electrode corresponding to the first via hole; the first electrode and the second electrode which are connected with the first active part are vertically arranged, that is, the longitudinal distance between the first electrode and the second electrode is the channel length of the first active part, so that the channel length of a transistor in a pixel region is reduced, the size of the transistor is further reduced, and the resolution of the small-size display device is improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to an array substrate and a display panel. Background Art

[0002] As the size of thin film transistors decreases, their channels also become smaller, which in turn makes the stability of thin film transistors worse and the leakage current increases. The channel length of current ultra-short channel thin film transistors is about 2 to 3 microns, and the channel size of thin film transistors is mainly limited by the accuracy of the exposure machine, which makes it impossible to further reduce the channel of thin film transistors and cannot meet the high resolution requirements of small-sized display devices. Summary of the invention

[0003] The present application provides an array substrate and a display panel to improve the problem that the channel size of the existing thin film transistor cannot be reduced.

[0004] To solve the above-mentioned problems, the technical solutions provided by this application are as follows:

[0005] The present application provides an array substrate, the array substrate comprising a pixel area and a non-pixel area, the pixel area is provided with a substrate and a first thin film transistor provided on the substrate; wherein the first thin film transistor comprises:

[0006] A first electrode, disposed on one side of the substrate;

[0007] A first insulating layer, disposed on one side of the substrate and covering the first electrode, wherein the first insulating layer is provided with a first via hole corresponding to a portion of the first electrode;

[0008] A second electrode is provided on a side of the first insulating layer away from the substrate;

[0009] a first active portion, one end of the first active portion being connected to the second electrode, and the other end of the first active portion extending along the side wall of the first via hole and being connected to the first electrode corresponding to the first via hole;

[0010] a second insulating layer, disposed on a side of the first insulating layer away from the substrate, and the second insulating layer covers the second active portion;

[0011] The first gate is arranged on a side of the second insulating layer away from the substrate.

[0012] Optionally, the substrate and a second thin film transistor disposed on the substrate are disposed in the non-pixel area;

[0013] The second thin film transistor includes a second active portion, and a material of the second active portion is different from a material of the first active portion.

[0014] Optionally, a material of the second active portion is the same as a material of the first electrode, and the second active portion and the first electrode are both located on a surface of a same film layer.

[0015] Optionally, a channel length of the first active portion is smaller than a channel length of the second active portion.

[0016] Optionally, the second thin film transistor further includes:

[0017] The first insulating layer covers the second active portion;

[0018] a second gate, disposed on a side of the first insulating layer away from the substrate, the second gate corresponding to the second active portion;

[0019] The material of the second gate is the same as that of the second electrode, and both the second gate and the second electrode are arranged on a surface of the first insulating layer away from the substrate.

[0020] Optionally, the second thin film transistor further includes:

[0021] The second insulating layer covers the second gate;

[0022] A third electrode is provided on a side of the second insulating layer away from the substrate, and the third electrode passes through a second via hole and is connected to the conductor portion of the second active portion;

[0023] The material of the third electrode is the same as that of the first gate, and both the third electrode and the first gate are arranged on a surface of the second insulating layer away from the substrate.

[0024] Optionally, the first thin film transistor further includes an extension segment connected to the first electrode, the material of the extension segment is the same as that of the first electrode, and the extension segment is a semiconductor;

[0025] The orthographic projection of the extension section on the substrate is located within the orthographic projection of the second electrode on the substrate.

[0026] Optionally, a third via hole corresponding to the first via hole is formed on the second insulating layer, and a depth of the third via hole is less than a thickness of the second insulating layer;

[0027] One end of the first gate is overlapped on a surface of the second insulating layer away from the substrate layer, and the other end of the first gate extends along the side wall of the third via hole to the bottom surface of the third via hole.

[0028] Optionally, the orthographic projection of the third via hole on the substrate is located within the orthographic projection of the first via hole on the substrate, and the orthographic projection area of ​​the third via hole on the substrate is smaller than the orthographic projection area of ​​the first via hole on the substrate.

[0029] Optionally, the first thin film transistor further includes:

[0030] A third insulating layer is provided on a side of the second insulating layer away from the substrate, and the third insulating line covers the first gate;

[0031] a fourth electrode, disposed on a side of the third insulating layer away from the substrate, the fourth electrode being electrically connected to the first electrode through a fourth via hole;

[0032] A fourth insulating layer is provided on a side of the third insulating layer away from the substrate, and the fourth insulating line covers the fourth electrode;

[0033] The first pixel electrode is disposed on a side of the fourth insulating layer away from the substrate, and the first pixel electrode is electrically connected to the second electrode through a fifth via hole.

[0034] The present application also proposes a display panel, which includes the above array substrate.

[0035] Other features and advantages of the present application will be described in detail in the subsequent detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application, and those skilled in the art can obtain other drawings based on these drawings without creative work.

[0037] In order to more completely understand the present application and its beneficial effects, the following description will be given in conjunction with the accompanying drawings, wherein the same figure numbers represent the same parts in the following description.

[0038] Figure 1 A top view of the array substrate provided in an embodiment of the present application;

[0039] Figure 2 A structural diagram of a display panel provided in an embodiment of the present application;

[0040] Figure 3 A first film layer diagram of an array substrate provided in an embodiment of the present application;

[0041] Figure 4 A second film layer diagram of the array substrate provided in an embodiment of the present application;

[0042] Figure 5 A process step diagram of an array substrate provided in an embodiment of the present application;

[0043] FIG. 6A to FIG. 6J A process flow chart of an array substrate provided in an embodiment of the present application. DETAILED DESCRIPTION

[0044] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0045] See also Figures 1 to 4 The present application proposes a display panel 100. The display panel 100 of the present application includes an array substrate 100a and a light-emitting component 100b arranged on one side of the array substrate 100a. The array substrate 100a includes a pixel area AA and a non-pixel area NA. A substrate 110 and a first thin film transistor T1 arranged on the substrate 110 are provided in the pixel area AA; wherein the first thin film transistor T1 includes a first electrode 141, a first insulating layer IL1, a second electrode 151, a first active portion 144, a second insulating layer IL2 and a first gate 161.

[0046] In this embodiment, the first electrode 141 is arranged on one side of the substrate 110; the first insulating layer IL1 is arranged on one side of the substrate 110 and covers the first electrode 141, and a first via hole HL1 corresponding to a portion of the first electrode 141 is opened on the first insulating layer IL1; the second electrode 151 is arranged on the side of the first insulating layer IL1 away from the substrate 110; one end of the first active portion 144 is connected to the second electrode 151, and the other end of the first active portion 144 extends along the side wall of the first via hole HL1 and is connected to the first electrode 141 corresponding to the first via hole HL1; the second insulating layer IL2 is arranged on the side of the first insulating layer IL1 away from the substrate 110, and the second insulating layer IL2 covers the second active portion 142; the first gate 161 is arranged on the side of the second insulating layer IL2 away from the substrate 110.

[0047] In the present application, the first electrode 141 and the second electrode 151 connecting the first active portion 144 are vertically arranged, that is, the longitudinal spacing between the first electrode 141 and the second electrode 151 is equal to the channel length of the first active portion 144. The channel length of the first active portion 144 is changed from horizontal to vertical, thereby reducing the channel length of the transistor in the pixel area AA, which is equivalent to reducing the size of the transistor, so that more transistors can be arranged in the same area of ​​the product, thereby improving the resolution of small-size display devices.

[0048] The technical solution of the present application is now described in conjunction with specific embodiments.

[0049] See also Figure 1 The non-pixel area NA surrounds the pixel area AA, and the area of ​​the display panel 100 corresponding to the pixel area AA is used for performing the display function, and a plurality of display units for realizing the display function are arranged inside the area. The area of ​​the display panel 100 corresponding to the non-pixel area NA may be a frame area of ​​the display panel 100, and a functional component for displaying the display unit in the auxiliary pixel area AA may be arranged inside the area.

[0050] In this embodiment, a plurality of pixel driving circuits may be provided in the pixel area AA, and the pixel driving circuit may include at least one first thin film transistor T1. A gate driving circuit is provided in the non-pixel area NA for outputting control signals to the pixel driving circuits in the pixel area AA, and the gate driving circuit may include at least one second thin film transistor T2.

[0051] In this embodiment, the second thin film transistor T2 includes a second active portion 142, and the material of the second active portion 142 is different from the material of the first active portion 144; for example, the material of the first active portion 144 of the present application may be an oxide semiconductor, and the material of the second active portion 142 may be a polycrystalline silicon semiconductor.

[0052] See also Figure 2 When the display panel 100 is a liquid crystal display panel, the light-emitting component 100b can be a backlight module, and the side of the display panel 100 away from the light-emitting component 100b is the light-emitting side; when the display panel 100 is an organic light-emitting diode display panel, the light-emitting component 100b can be an organic light-emitting diode; when the display panel 100 is a direct display panel, the light-emitting component 100b can be MiniLED, MicroLED, etc.

[0053] See also Figure 3 , the array substrate 100a may include a substrate 110 and an array layer 120 disposed on the substrate 110. The substrate 110 is laid as a whole layer, and the substrate 110 is disposed in both the pixel area AA and the non-pixel area NA; the material of the substrate 110 may be a rigid substrate, such as glass, quartz and other rigid materials; the material of the substrate 110 may be a flexible substrate, such as polyimide and other flexible materials.

[0054] See also Figure 3The array substrate 100a includes a light-shielding layer (not shown) disposed on one side of the substrate 110, and the orthographic projection of the first active portion 144 on the substrate 110 is located within the orthographic projection of the light-shielding layer on the substrate 110, so as to avoid the device effect of the transistor being reduced due to the light entering the channel portion; at the same time, the orthographic projection of the second active portion 142 on the substrate 110 can also be located within the orthographic projection of the light-shielding layer on the substrate 110.

[0055] See also Figure 3 The light-shielding layer may be a light-shielding metal or other material with light-shielding properties, such as molybdenum, aluminum, copper, titanium, or alloys of the above materials or stacked layers of the above materials.

[0056] See also Figure 3 The array substrate 100a also includes a buffer layer 130 disposed on the side of the light shielding layer away from the substrate 110. The buffer layer 130 covers the light shielding layer and is laid on the entire array substrate 100a. The material of the buffer layer 130 may include a compound composed of nitrogen, silicon and oxygen. For example, the material of the buffer layer 130 may include a single layer of silicon oxide, a silicon oxide film layer, or a stacked structure of silicon oxide, silicon nitride, aluminum oxide, etc. For example, the buffer layer 130 of the present application may be a stacked structure of silicon oxide, silicon nitride and silicon oxide.

[0057] See also Figure 3 The array substrate 100a further includes a first active layer 140 disposed on a side of the buffer layer 130 away from the substrate 110. The material of the first active layer 140 may be polycrystalline silicon, which may be formed by amorphous silicon laser annealing crystallization or other crystallization processes.

[0058] In this embodiment, the first active layer 140 may include a first electrode 141 located in the pixel area AA and a second active portion 142 located in the non-pixel area NA, which is equivalent to forming the first electrode 141 of the first thin film transistor T1 at the same time in the process of forming the second active portion 142 of the second thin film transistor T2, that is, the material of the second active portion 142 is the same as that of the first electrode 141, and the second active portion 142 and the first electrode 141 are both located on the surface of the same film layer, that is, both are located on the surface of the buffer layer 130.

[0059] In this embodiment, the second active portion 142 includes a second channel 142 a and conductor portions 142 b disposed on both sides of the second channel 142 a . The conductor portion 142 b and the first electrode 141 are formed of polysilicon by ion doping or plasma treatment.

[0060] See also Figure 3The array substrate 100a further includes a first insulating layer IL1 disposed on a side of the buffer layer 130 away from the substrate 110. The first insulating layer IL1 is laid as a whole layer and covers both the second active portion 142 and the first electrode 141. Meanwhile, a first via hole HL1 is opened on the first insulating layer IL1, and the first via hole HL1 exposes a portion of the first electrode 141.

[0061] In this embodiment, the material of the first insulating layer IL1 may include a compound composed of nitrogen, silicon and oxygen. For example, the material of the first insulating layer IL1 may include a single layer of silicon oxide, a silicon oxide film layer, or a stacked structure of silicon oxide, silicon nitride, aluminum oxide, etc.

[0062] See also Figure 3 The array substrate 100a also includes a first metal layer 150 arranged on the side of the first insulating layer IL1 away from the substrate 110. The material of the first metal layer 150 may include metals such as Cr, W, Ti, Ta, Mo, Al, Cu, or a single-layer or multi-layer metal structure composed of at least two of the above metals; for example, the material of the first metal layer 150 may be Mo, Mo / Al, Mo / Cu, MoTi / Cu, MoTi / Cu / MoTi, Ti / Al / Ti, Ti / Cu / Ti, Mo / Cu / IZO, IZO / Cu / IZO, Mo / Cu / ITO, etc.

[0063] In this embodiment, the first metal layer 150 includes a second electrode 151 located in the pixel area AA and a second gate 152 located in the non-pixel area NA, which is equivalent to forming the second electrode 151 of the first thin film transistor T1 and the second gate 152 of the second thin film transistor T2 at the same time when the patterning process of the first metal layer 150 is performed. The material of the second gate 152 is the same as that of the second electrode 151, and the second gate 152 and the second electrode 151 are both arranged on the surface of the first insulating layer IL1 away from the substrate 110.

[0064] In this embodiment, the second gate 152 corresponds to the channel of the second active portion 142 , that is, the second gate 152 can be used as a mask to perform a conductor processing on the second active portion 142 .

[0065] In this embodiment, the first electrode 141 may be a drain electrode of the first thin film transistor T1 , and the second electrode 151 may be a source electrode of the first thin film transistor T1 .

[0066] See also Figure 3 The array substrate 100a further includes a first active portion 144 located in the pixel area AA, one end of the first active portion 144 is connected to the second electrode 151, and the other end of the first active portion 144 extends along the side wall of the first via hole HL1 and is connected to the first electrode 141 corresponding to the first via hole HL1.

[0067] In this embodiment, the first active portion 144 can be formed by physical vapor deposition and a pattern is formed by a yellow light process and an etching process; the material of the first active portion 144 can be an oxide semiconductor, such as IGZO, IGTO, Ln-IZO, ITZO, ITGZO, HIZO, IZO (InZnO), ZnO:F, In2O3:Sn, In2O3:Mo, Cd2SnO4, ZnO:Al, TiO2:Nb, Cd-Sn-O or other oxides.

[0068] In this embodiment, the first active portion 144 can fill the first via hole HL1 so that the first active portion 144 covers the first electrode 141 corresponding to the first via hole HL1, thereby increasing the contact area between the first active portion 144 and the first electrode 141; at the same time, the first active portion 144 of the present application can also contact the surface of the first insulating layer IL1 on the side of the first via hole HL1 away from the second electrode 151.

[0069] In the present embodiment, since the second active portion 142 of the second thin film transistor T2 of the present application is a conventional channel structure, and the first electrode 141, the first active portion 144 and the second active portion 142 of the first thin film transistor T1 of the present application are vertical structures, that is, the channel length of the first active portion 144 is changed from horizontal to vertical, the channel length of the first active portion 144 is reduced, so that the channel length of the first active portion 144 is smaller than the channel length of the second active portion 142, which is equivalent to reducing the size of the transistor in the pixel area AA, so that more transistors can be arranged in the same area of ​​the product, thereby improving the resolution of the small-size display device.

[0070] In the present embodiment, the channel length of the first active portion 144 may be 0.3 micrometers to 0.5 micrometers.

[0071] See also Figure 3 The first thin film transistor T1 further includes an extension segment 143 connected to the first electrode 141 . The material of the extension segment 143 is the same as that of the first electrode 141 , and the extension segment 143 is a semiconductor. The orthographic projection of the extension segment 143 on the substrate 110 is located within the orthographic projection of the second electrode 151 on the substrate 110 .

[0072] In the present embodiment, since the channel length of the first active portion 144 is the distance between the first electrode 141 and the second electrode 151, in order to reduce the channel length of the first active portion 144, the present application increases the non-conductorized semiconductor material as much as possible when preparing the first electrode 141, that is, the non-conductorized semiconductor material can partially overlap with the second electrode 151, and after forming the first via hole HL1, it is necessary to conduct the non-conductorized semiconductor material using the second electrode 151 as a mask, so that the non-conductorized semiconductor material forms the first electrode 141 and the extension section 143 overlapping with the second electrode 151.

[0073] The provision of the extension section 143 of the present application reduces the distance between the second electrode 151 and the first electrode 141 , thereby reducing the channel length of the first active portion 144 and improving the device performance of the first thin film transistor T1 .

[0074] See also Figure 3 The array substrate 100 a further includes a second insulating layer IL2 disposed on a side of the first insulating layer IL1 away from the substrate 110 . The second insulating layer IL2 is entirely laid out and covers the second gate 152 and the first active portion 144 .

[0075] In this embodiment, the material of the second insulating layer IL2 may include a compound composed of nitrogen, silicon and oxygen. For example, the material of the second insulating layer IL2 may include a single layer of silicon oxide, a silicon oxide film layer, or a stacked structure of silicon oxide, silicon nitride, aluminum oxide, etc.

[0076] See also Figure 3 The array substrate 100a also includes a second metal layer 160 arranged on the side of the second insulating layer IL2 away from the substrate 110. The material of the second metal layer 160 may include metals such as Cr, W, Ti, Ta, Mo, Al, Cu, or a single-layer or multi-layer metal structure composed of at least two of the above metals; for example, the material of the second metal layer 160 may be Mo, Mo / Al, Mo / Cu, MoTi / Cu, MoTi / Cu / MoTi, Ti / Al / Ti, Ti / Cu / Ti, Mo / Cu / IZO, IZO / Cu / IZO, Mo / Cu / ITO, etc.

[0077] In this embodiment, the second metal layer 160 includes a third electrode 162 located in the non-pixel area NA and a first gate 161 located in the pixel area AA, which is equivalent to simultaneously forming the third electrode 162 of the second thin film transistor T2 and the first gate 161 of the first thin film transistor T1 when the patterning process of the second metal layer 160 is performed. The material of the third electrode 162 is the same as that of the first gate 161, and the third electrode 162 and the first gate 161 are both arranged on the surface of the second insulating layer IL2 away from the substrate 110.

[0078] In the present embodiment, the third electrode 162 is connected to the conductor portion 142 b of the second active portion 142 through the second via hole HL2 , and the second via hole HL2 penetrates the second insulating layer IL2 and a portion of the first insulating layer IL1 .

[0079] See also Figure 3 In order to reduce the distance between the first gate 161 and the first active portion 144 and improve the conduction rate of the first active portion 144, the present application can open a third via hole HL3 corresponding to the first via hole HL1 on the second insulating layer IL2, and the depth of the third via hole HL3 is less than the thickness of the second insulating layer IL2; one end of the first gate 161 overlaps the surface of the second insulating layer IL2 away from the substrate 110, and the other end of the first gate 161 extends along the side wall of the third via hole HL3 to the bottom surface of the third via hole HL3.

[0080] In this embodiment, the third via hole HL3 is disposed so that the first gate 161 can extend along the side wall of the third via hole HL3 and extend to the bottom surface of the third via hole HL3 close to the first active portion 144. The first gate 161 located on the side wall of the third via hole HL3 corresponds to the side wall of the first active portion 144, thereby reducing the distance between the first gate 161 and the first active portion 144, increasing the turn-on voltage applied by the first gate 161 to the first active portion 144, and improving the conduction rate of the first active portion 144.

[0081] See also Figure 3 , the orthographic projection of the third via HL3 on the substrate 110 may be located within the orthographic projection of the first via HL1 on the substrate 110, and the orthographic projection area of ​​the third via HL3 on the substrate 110 is smaller than the orthographic projection area of ​​the first via HL1 on the substrate 110. That is, the area of ​​the third via HL3 is smaller than the area of ​​the first via HL1, so that the side wall of the third via HL3 may correspond to the side wall of the first via HL1, that is, the first active portion 144 on the side wall of the first via HL1 may correspond to the first gate 161 on the side wall of the third via HL3, further improving the turn-on voltage applied by the first gate 161 to the first active portion 144, and improving the conduction rate of the first active portion 144.

[0082] See also Figure 3 The array substrate 100 a further includes a third insulating layer IL3 disposed on a side of the second insulating layer IL2 away from the substrate 110 . The third insulating layer IL3 is entirely laid, and the third insulating layer IL3 covers the first gate 161 and the third electrode 162 .

[0083] In this embodiment, the material of the third insulating layer IL3 may include a compound composed of nitrogen, silicon and oxygen. For example, the material of the third insulating layer IL3 may include a single layer of silicon oxide, a silicon oxide film layer, or a stacked structure of silicon oxide, silicon nitride, aluminum oxide, etc.

[0084] See also Figure 3 The array substrate 100 a further includes a third metal layer 170 disposed on a side of the third insulating layer IL3 away from the substrate 110 . The material of the third metal layer 170 may be the same as that of the second electrode 151 .

[0085] In this embodiment, the third metal layer 170 includes a fourth electrode 171 located in the pixel area AA, and the fourth electrode 171 can be electrically connected to the first electrode 141 through the fourth via hole HL4, and the fourth via hole HL4 passes through the third insulating layer IL3, the second insulating layer IL2 and a portion of the first insulating layer IL1; the fourth via hole HL4 can be located on the side of the third via hole HL3 away from the second electrode 151, that is, the fourth via hole HL4 does not overlap with the first via hole HL1.

[0086] See also Figure 3 The array substrate 100 a further includes a fourth insulating layer IL4 disposed on a side of the third insulating layer IL3 away from the substrate 110 . The fourth insulating layer IL4 is entirely laid, and the fourth insulating layer IL4 covers the fourth electrode 171 .

[0087] In this embodiment, the material of the fourth insulating layer IL4 may include a compound composed of nitrogen, silicon and oxygen. For example, the material of the fourth insulating layer IL4 may include a single layer of silicon oxide, a silicon oxide film layer, or a stacked structure of silicon oxide, silicon nitride, aluminum oxide, etc.

[0088] See also Figure 3 The array substrate 100a also includes a first pixel electrode PE1 disposed on a side of the fourth insulating layer IL4 away from the substrate 110. The first pixel electrode PE1 is located in the pixel area AA, and the first pixel electrode PE1 is electrically connected to the second electrode 151 through a fifth via hole HL5. The fifth via hole HL5 penetrates the fourth insulating layer IL4, the third insulating layer IL3 and a portion of the second insulating layer IL2.

[0089] In the present embodiment, the material of the first pixel electrode PE1 may include ITO, IZO, ITO / Ag / ITO, IZO / Ag / IZO, Mo / Cu, MoTi / Cu / MoTi, etc.

[0090] In this embodiment, the first electrode 141 may be a drain electrode of the first thin film transistor T1 , and the second electrode 151 may be a source electrode of the first thin film transistor T1 .

[0091] In this embodiment, the third metal layer 170 may also include at least one transmission line for transmitting a voltage signal, such as a high potential line, a low potential line, a clock signal line, a start signal line, a data signal line, etc.; for example, the data line located in the third metal layer 170 is connected to the fourth electrode 171 to introduce the data signal in the data line into the first electrode 141, and at the same time the first active part 144 is turned on, the data signal is transmitted to the second electrode 151, and is introduced into the first pixel electrode PE1 through the second electrode 151.

[0092] exist Figure 3 Based on Figure 4 The array substrate 100a further includes a planar layer PLN disposed on a side of the fourth insulating layer IL4 away from the substrate 110, the planar layer PLN covers the first pixel electrode PE1, and the material of the planar layer PLN includes a flexible material such as polytetrafluoroethylene.

[0093] See also Figure 4 The array substrate 100a further includes a second pixel electrode PE2 disposed on a side of the planar layer PLN away from the substrate 110, and the second pixel electrode PE2 is electrically connected to the first pixel electrode PE1 through a sixth via hole HL6 on the planar layer PLN.

[0094] In the present embodiment, the material of the second pixel electrode PE2 may include ITO, IZO, ITO / Ag / ITO, IZO / Ag / IZO, Mo / Cu, MoTi / Cu / MoTi, etc.

[0095] Also, see Figure 4 The array substrate 100 a further includes a common electrode AE ​​which is in the same layer as the first pixel electrode PE1 and is manufactured in the same process. The common electrode AE ​​and the second pixel electrode PE2 form a driving electric field to drive the liquid crystal in the display panel 100 to deflect.

[0096] It should be noted that Figure 4 The structures in the figure are only applicable to liquid crystal display panels. Figure 3 The structure in the invention can be applicable to direct display panels such as liquid crystal display panels, organic light emitting diode display panels, MiniLED or MicroLED.

[0097] See also Figure 5 The present application also proposes a method for manufacturing an array substrate. Figure 3 Taking the structure of as an example, the method for manufacturing the array substrate includes:

[0098] S10, providing a substrate 110, and forming a buffer layer 130 on the substrate 110;

[0099] See also Fig. 6AThe material of the substrate 110 may be a rigid substrate 110, such as glass, quartz or other rigid materials; the material of the substrate 110 may be a flexible substrate 110, such as polyimide or other flexible materials.

[0100] In this embodiment, a light shielding layer may be further provided between the substrate 110 and the buffer layer 130, and the first active portion 144 of the first thin film transistor T1 in the pixel area AA may have an orthographic projection on the substrate 110 located within the orthographic projection of the light shielding layer on the substrate 110, thereby preventing the device effect of the transistor from being reduced due to light entering the channel portion.

[0101] In this embodiment, the buffer layer 130 is laid on the entire layer of the array substrate 100a and covers the light-shielding layer. For example, the material of the buffer layer 130 may include a single layer of silicon oxide, a silicon oxide film layer, or a stacked structure of silicon oxide, silicon nitride, aluminum oxide, etc. For example, the buffer layer 130 of the present application may be a stacked structure of silicon oxide, silicon nitride, and silicon oxide.

[0102] S20, forming a semiconductor material layer ACT on the surface of the buffer layer 130 away from the substrate 110, and forming a first semiconductor pattern ACT1 located in the pixel area AA and a second semiconductor pattern ACT2 located in the non-pixel area NA through patterning;

[0103] See also Figure 6B The material of the semiconductor material layer ACT may be polycrystalline silicon, and the polycrystalline silicon may be formed by crystallizing amorphous silicon through laser annealing or other crystallization processes.

[0104] S30, forming a first insulating layer IL1 and a first metal layer 150 on a side of the semiconductor material layer ACT away from the substrate 110, forming a first metal pattern 150a located in the pixel area AA and a second metal pattern 150b located in the non-pixel area NA through patterning, and performing a conductorization process on the first semiconductor pattern ACT1 using the first metal pattern 150a as a mask so that the first semiconductor pattern ACT1 forms a second active portion 142, and performing a conductorization process on the second semiconductor pattern ACT2 using the second metal pattern 150b as a mask so that the second semiconductor pattern ACT2 not blocked by the second metal pattern 150b forms a first electrode 141, and the second semiconductor pattern ACT2 blocked by the second metal pattern 150b forms an extension section 143;

[0105] See also Figure 6C The second active portion 142 includes a second channel 142a and conductor portions 142b disposed on both sides of the second channel 142a. The conductor portion 142b and the second electrode 151 are formed of polysilicon by ion doping or plasma treatment; and the first metal pattern 150a is a second gate 152 corresponding to the second channel 142a.

[0106] In the present embodiment, the material of the first insulating layer IL1 may include a single layer of silicon oxide, a silicon oxide film layer, or a stacked structure of silicon oxide, silicon nitride, aluminum oxide, etc.

[0107] In this embodiment, the material of the first metal layer 150 can be Mo, Mo / Al, Mo / Cu, MoTi / Cu, MoTi / Cu / MoTi, Ti / Al / Ti, Ti / Cu / Ti, Mo / Cu / IZO, IZO / Cu / IZO, Mo / Cu / ITO, etc.

[0108] S40, patterning the second metal pattern 150b and the first insulating layer IL1 so that the second metal pattern 150b forms a second electrode 151, and forming a first via hole HL1 on the first insulating layer IL1, and then using the second electrode 151 as a mask to conduct the second semiconductor pattern ACT2 that is not blocked by the second electrode 151, so that the part of the extension section 143 is conducted and forms the first electrode 141, for example Fig.6D structure.

[0109] S50 , forming a first active portion 144 on a side of the first insulating layer IL1 away from the substrate 110 ;

[0110] See also Fig. 6E One end of the first active portion 144 is connected to the second electrode 151 , and the other end of the first active portion 144 extends along the sidewall of the first via hole HL1 and is connected to the first electrode 141 corresponding to the first via hole HL1 .

[0111] In this embodiment, the first active portion 144 can be formed by physical vapor deposition and a pattern is formed by a yellow light process and an etching process; the material of the first active portion 144 can be an oxide semiconductor, such as IGZO, IGTO, Ln-IZO, ITZO, ITGZO, HIZO, IZO (InZnO), ZnO:F, In2O3:Sn, In2O3:Mo, Cd2SnO4, ZnO:Al, TiO2:Nb, Cd-Sn-O or other oxides.

[0112] In this embodiment, the first active portion 144 can fill the first via hole HL1 so that the first active portion 144 covers the first electrode 141 corresponding to the first via hole HL1, thereby increasing the contact area between the first active portion 144 and the first electrode 141; at the same time, the first active portion 144 of the present application can also contact the surface of the first insulating layer IL1 on the side of the first via hole HL1 away from the second electrode 151.

[0113] S60, forming a second insulating layer IL2 on a side of the first insulating layer IL1 away from the substrate 110, and forming a second via hole HL2 and a third via hole HL3 through patterning of the second insulating layer IL2;

[0114] See also Fig. 6F The second via hole HL2 penetrates the second insulating layer IL2 and a portion of the first insulating layer IL1 and exposes a portion of the conductor portion 142 b . The third via hole HL3 penetrates a portion of the second insulating layer IL2 .

[0115] S70, forming a second metal layer 160 on a side of the second insulating layer IL2 away from the substrate 110, and forming a first gate electrode 161 located in the pixel area AA and a third electrode 162 located in the non-pixel area NA through patterning;

[0116] See also Figure 6G The material of the second metal layer 160 can be Mo, Mo / Al, Mo / Cu, MoTi / Cu, MoTi / Cu / MoTi, Ti / Al / Ti, Ti / Cu / Ti, Mo / Cu / IZO, IZO / Cu / IZO, Mo / Cu / ITO, etc.

[0117] In this embodiment, the third electrode 162 passes through the second via hole HL2 and is connected to the conductor portion 142b of the second active portion 142, one end of the first gate 161 overlaps the surface of the second insulating layer IL2 one layer away from the substrate 110, and the other end of the first gate 161 extends along the side wall of the third via hole HL3 to the bottom surface of the third via hole HL3.

[0118] In the present embodiment, the material of the second insulating layer IL2 may include a single layer of silicon oxide, a silicon oxide film layer, or a stacked structure of silicon oxide, silicon nitride, aluminum oxide, etc.

[0119] S80 , forming a third insulating layer IL3 and a fourth electrode 171 on a surface of the second insulating layer IL2 away from the substrate 110 .

[0120] See also Figure 6H The fourth electrode 171 can be electrically connected to the first electrode 141 through the fourth via hole HL4, and the fourth via hole HL4 penetrates the third insulating layer IL3, the second insulating layer IL2 and a portion of the first insulating layer IL1; the fourth via hole HL4 can be located on a side of the third via hole HL3 away from the second electrode 151, that is, the fourth via hole HL4 does not overlap with the first via hole HL1.

[0121] In this embodiment, the material of the third insulating layer IL3 may include a single layer of silicon oxide, a silicon oxide film layer, or a stacked structure of silicon oxide, silicon nitride, aluminum oxide, etc.; the material of the third metal layer 170 may be the same as that of the second metal layer 160 .

[0122] S90, forming a fourth insulating layer IL4 and a first pixel electrode PE1 layer on a surface of the third insulating layer IL3 away from the substrate 110;

[0123] See also Fig.6I The first pixel electrode PE1 layer includes a first pixel electrode PE1 and a common electrode. The first pixel electrode PE1 is electrically connected to the second electrode 151 through a fifth via hole HL5. The fifth via hole HL5 penetrates the fourth insulating layer IL4, the third insulating layer IL3 and a portion of the second insulating layer IL2.

[0124] In the present embodiment, the material of the fourth insulating layer IL4 may include a single layer of silicon oxide, a silicon oxide film layer, or a stacked structure of silicon oxide, silicon nitride, aluminum oxide, etc.

[0125] In this embodiment, the material of the first pixel electrode PE1 layer may include ITO, IZO, ITO / Ag / ITO, IZO / Ag / IZO, Mo / Cu, MoTi / Cu / MoTi, etc.

[0126] On the basis of step S90, the method for manufacturing the array substrate includes:

[0127] S100 , forming a planar layer PLN and a second pixel electrode PE2 on a surface of the fourth insulating layer IL4 away from the substrate 110 .

[0128] See also Figure 6J A sixth via hole HL6 is formed on the planar layer PLN, and the first pixel electrode PE1 passes through the sixth via hole HL6 and is electrically connected to the first pixel electrode PE1.

[0129] In this embodiment, the array substrate 100 a further includes a common electrode AE ​​which is in the same layer as the first pixel electrode PE1 and is manufactured in the same process. The common electrode AE ​​and the second pixel electrode PE2 form a driving electric field to drive the liquid crystal in the display panel 100 to deflect.

[0130] In this embodiment, the material of the planar layer PLN includes flexible materials such as polytetrafluoroethylene.

[0131] In the present embodiment, the material of the second pixel electrode PE2 may include ITO, IZO, ITO / Ag / ITO, IZO / Ag / IZO, Mo / Cu, MoTi / Cu / MoTi, etc.

[0132] It should be noted that Figure 6J The structures in the figure are only applicable to liquid crystal display panels. Fig.6I The structure in the invention can be applicable to direct display panels such as liquid crystal display panels, organic light emitting diode display panels, MiniLED or MicroLED.

[0133] The second active portion 142 of the second thin film transistor T2 of the present application is a conventional channel structure, while the first electrode 141, the first active portion 144 and the second active portion 142 of the first thin film transistor T1 of the present application are vertical structures, that is, the channel length of the first active portion 144 is changed from horizontal to vertical, which reduces the channel length of the first active portion 144, making the channel length of the first active portion 144 smaller than the channel length of the second active portion 142, which is equivalent to reducing the size of the transistor in the pixel area AA, so that more transistors can be arranged in the same area of ​​the product, thereby improving the resolution of small-size display devices.

[0134] In the present embodiment, the channel length of the first active portion 144 may be 0.3 micrometers to 0.5 micrometers.

[0135] At the same time, when preparing the second active portion of the second thin film transistor, the present application simultaneously prepares the first electrode of the first thin film transistor; when preparing the second gate of the second thin film transistor, the second electrode of the first thin film transistor is simultaneously prepared; when preparing the third electrode of the second thin film transistor, the first gate of the first thin film transistor is simultaneously prepared; that is, the present application can utilize three layers of insulation to simultaneously realize the preparation of transistors in the pixel area and the non-pixel area, reduce the number of masks, simplify the preparation process of the array substrate, and reduce the preparation cost of the display panel.

[0136] The present application also proposes a mobile terminal, which includes a terminal body and the above-mentioned display panel, and the terminal body and the display panel are combined into one. The terminal body can be a device such as a circuit board bound to the display panel and a cover plate set on the display panel. The mobile terminal can include electronic devices such as mobile phones, televisions, and laptops.

[0137] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0138] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0139] The embodiments, implementation methods and related technical features of the present application can be combined and replaced with each other without conflict.

[0140] The above are only preferred embodiments of the present application and do not constitute any form of limitation to the present application. However, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are still within the scope of the technical solution of the present application.

Claims

1. An array substrate, characterized in that: The array substrate comprises a pixel region and a non-pixel region, wherein a substrate and a first thin film transistor arranged on the substrate are arranged in the pixel region; wherein the first thin film transistor comprises: A first electrode, disposed on one side of the substrate; A first insulating layer, disposed on one side of the substrate and covering the first electrode, wherein the first insulating layer is provided with a first via hole corresponding to a portion of the first electrode; A second electrode is provided on a side of the first insulating layer away from the substrate; a first active portion, one end of the first active portion being connected to the second electrode, and the other end of the first active portion extending along the side wall of the first via hole and being connected to the first electrode corresponding to the first via hole; a second insulating layer, disposed on a side of the first insulating layer away from the substrate, and the second insulating layer covers the second active portion; The first gate is arranged on a side of the second insulating layer away from the substrate.

2. The array substrate according to claim 1, characterized in that: The substrate and a second thin film transistor disposed on the substrate are disposed in the non-pixel area; The second thin film transistor includes a second active portion, and a material of the second active portion is different from a material of the first active portion.

3. The array substrate according to claim 2, characterized in that: The material of the second active portion is the same as that of the first electrode, and the second active portion and the first electrode are both located on the surface of the same film layer.

4. The array substrate according to claim 2, characterized in that: A channel length of the first active portion is smaller than a channel length of the second active portion.

5. The array substrate according to claim 2, characterized in that: The second thin film transistor further includes: The first insulating layer covers the second active portion; a second gate, disposed on a side of the first insulating layer away from the substrate, the second gate corresponding to the second active portion; The material of the second gate is the same as that of the second electrode, and both the second gate and the second electrode are arranged on a surface of the first insulating layer away from the substrate.

6. The array substrate according to claim 5, characterized in that: The second thin film transistor further includes: The second insulating layer covers the second gate; A third electrode is provided on a side of the second insulating layer away from the substrate, and the third electrode passes through a second via hole and is connected to the conductor portion of the second active portion; The material of the third electrode is the same as that of the first gate, and both the third electrode and the first gate are arranged on a surface of the second insulating layer away from the substrate.

7. The array substrate according to any one of claims 1 to 6, characterized in that: The first thin film transistor further includes an extension segment connected to the first electrode, the material of the extension segment is the same as that of the first electrode, and the extension segment is a semiconductor; The orthographic projection of the extension section on the substrate is located within the orthographic projection of the second electrode on the substrate.

8. The array substrate according to any one of claims 1 to 6, characterized in that: A third via hole corresponding to the first via hole is formed on the second insulating layer, and a depth of the third via hole is less than a thickness of the second insulating layer; One end of the first gate is overlapped on a surface of the second insulating layer away from the substrate layer, and the other end of the first gate extends along the side wall of the third via hole to the bottom surface of the third via hole.

9. The array substrate according to claim 8, characterized in that: The orthographic projection of the third via hole on the substrate is located within the orthographic projection of the first via hole on the substrate, and the orthographic projection area of ​​the third via hole on the substrate is smaller than the orthographic projection area of ​​the first via hole on the substrate.

10. The array substrate according to any one of claims 1 to 6, characterized in that: The first thin film transistor further comprises: A third insulating layer is provided on a side of the second insulating layer away from the substrate, and the third insulating line covers the first gate; a fourth electrode, disposed on a side of the third insulating layer away from the substrate, the fourth electrode being electrically connected to the first electrode through a fourth via hole; A fourth insulating layer is provided on a side of the third insulating layer away from the substrate, and the fourth insulating line covers the fourth electrode; The first pixel electrode is disposed on a side of the fourth insulating layer away from the substrate, and the first pixel electrode is electrically connected to the second electrode through a fifth via hole.

11. A display panel, characterized in that: It comprises the array substrate as claimed in any one of claims 1 to 10.

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